12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 357644d581SMichael Ellerman #include <asm/debugfs.h> 36262af557SGuo Chao #include <asm/firmware.h> 3780c49c7eSIan Munsie #include <asm/pnv-pci.h> 38aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 3980c49c7eSIan Munsie 40ec249dd8SMichael Neuling #include <misc/cxl-base.h> 41184cd4a3SBenjamin Herrenschmidt 42184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 43184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4444bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 45184cd4a3SBenjamin Herrenschmidt 4699451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4799451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 48acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 49781a868fSWei Yang 507f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 517f2c39e9SFrederic Barrat "NPU_OCAPI" }; 52aca6913fSAlexey Kardashevskiy 53c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus); 55c498a4f9SChristoph Hellwig 567d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 576d31c2faSJoe Perches const char *fmt, ...) 586d31c2faSJoe Perches { 596d31c2faSJoe Perches struct va_format vaf; 606d31c2faSJoe Perches va_list args; 616d31c2faSJoe Perches char pfix[32]; 62184cd4a3SBenjamin Herrenschmidt 636d31c2faSJoe Perches va_start(args, fmt); 646d31c2faSJoe Perches 656d31c2faSJoe Perches vaf.fmt = fmt; 666d31c2faSJoe Perches vaf.va = &args; 676d31c2faSJoe Perches 68781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 696d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 70781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 716d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 726d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 73781a868fSWei Yang #ifdef CONFIG_PCI_IOV 74781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 75781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 76781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 77781a868fSWei Yang (pe->rid & 0xff00) >> 8, 78781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 79781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 806d31c2faSJoe Perches 811f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 826d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 836d31c2faSJoe Perches 846d31c2faSJoe Perches va_end(args); 856d31c2faSJoe Perches } 866d31c2faSJoe Perches 874e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8845baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 894e287840SThadeu Lima de Souza Cascardo 904e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 914e287840SThadeu Lima de Souza Cascardo { 924e287840SThadeu Lima de Souza Cascardo if (!str) 934e287840SThadeu Lima de Souza Cascardo return -EINVAL; 944e287840SThadeu Lima de Souza Cascardo 954e287840SThadeu Lima de Souza Cascardo while (*str) { 964e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 974e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 984e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 994e287840SThadeu Lima de Souza Cascardo break; 1004e287840SThadeu Lima de Souza Cascardo } 1014e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1024e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1034e287840SThadeu Lima de Souza Cascardo str++; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo 1064e287840SThadeu Lima de Souza Cascardo return 0; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1094e287840SThadeu Lima de Souza Cascardo 11045baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11145baee14SGuilherme G. Piccoli { 11245baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11345baee14SGuilherme G. Piccoli return 0; 11445baee14SGuilherme G. Piccoli } 11545baee14SGuilherme G. Piccoli 11645baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11745baee14SGuilherme G. Piccoli 1185958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 119262af557SGuo Chao { 1205958d19aSBenjamin Herrenschmidt /* 1215958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1225958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1235958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1245958d19aSBenjamin Herrenschmidt * 1255958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1265958d19aSBenjamin Herrenschmidt */ 1275958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1285958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 129262af557SGuo Chao } 130262af557SGuo Chao 131b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 132b79331a5SRussell Currey { 133b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 134b79331a5SRussell Currey 135b79331a5SRussell Currey return (resource_flags & flags) == flags; 136b79331a5SRussell Currey } 137b79331a5SRussell Currey 1381e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1391e916772SGavin Shan { 140313483ddSGavin Shan s64 rc; 141313483ddSGavin Shan 1421e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1431e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1441e916772SGavin Shan 145313483ddSGavin Shan /* 146313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 147313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 148313483ddSGavin Shan * PE is already in unfrozen state. 149313483ddSGavin Shan */ 150313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 151313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 152d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1531f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 154313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 155313483ddSGavin Shan 1561e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1571e916772SGavin Shan } 1581e916772SGavin Shan 1594b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1604b82ab18SGavin Shan { 16192b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1621f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1634b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1644b82ab18SGavin Shan return; 1654b82ab18SGavin Shan } 1664b82ab18SGavin Shan 167e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1681f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1694b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1704b82ab18SGavin Shan 1711e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1724b82ab18SGavin Shan } 1734b82ab18SGavin Shan 1741e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 175184cd4a3SBenjamin Herrenschmidt { 17660964816SAndrzej Hajda long pe; 177184cd4a3SBenjamin Herrenschmidt 1789fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1799fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1801e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 181184cd4a3SBenjamin Herrenschmidt } 182184cd4a3SBenjamin Herrenschmidt 1839fcd6f4aSGavin Shan return NULL; 1849fcd6f4aSGavin Shan } 1859fcd6f4aSGavin Shan 1861e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 187184cd4a3SBenjamin Herrenschmidt { 1881e916772SGavin Shan struct pnv_phb *phb = pe->phb; 189caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 190184cd4a3SBenjamin Herrenschmidt 1911e916772SGavin Shan WARN_ON(pe->pdev); 192f724385fSFrederic Barrat WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */ 1930bd97167SAlexey Kardashevskiy kfree(pe->npucomp); 1941e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 195caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 196184cd4a3SBenjamin Herrenschmidt } 197184cd4a3SBenjamin Herrenschmidt 198262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 199262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 200262af557SGuo Chao { 201262af557SGuo Chao const char *desc; 202262af557SGuo Chao struct resource *r; 203262af557SGuo Chao s64 rc; 204262af557SGuo Chao 205262af557SGuo Chao /* Configure the default M64 BAR */ 206262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 207262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 208262af557SGuo Chao phb->ioda.m64_bar_idx, 209262af557SGuo Chao phb->ioda.m64_base, 210262af557SGuo Chao 0, /* unused */ 211262af557SGuo Chao phb->ioda.m64_size); 212262af557SGuo Chao if (rc != OPAL_SUCCESS) { 213262af557SGuo Chao desc = "configuring"; 214262af557SGuo Chao goto fail; 215262af557SGuo Chao } 216262af557SGuo Chao 217262af557SGuo Chao /* Enable the default M64 BAR */ 218262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 219262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 220262af557SGuo Chao phb->ioda.m64_bar_idx, 221262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 222262af557SGuo Chao if (rc != OPAL_SUCCESS) { 223262af557SGuo Chao desc = "enabling"; 224262af557SGuo Chao goto fail; 225262af557SGuo Chao } 226262af557SGuo Chao 227262af557SGuo Chao /* 22863803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22963803c39SGavin Shan * are first or last two PEs. 230262af557SGuo Chao */ 231262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23292b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23363803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23492b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23563803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 236262af557SGuo Chao else 2371f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23892b8f137SGavin Shan phb->ioda.reserved_pe_idx); 239262af557SGuo Chao 240262af557SGuo Chao return 0; 241262af557SGuo Chao 242262af557SGuo Chao fail: 243262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 244262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 245262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 246262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 247262af557SGuo Chao phb->ioda.m64_bar_idx, 248262af557SGuo Chao OPAL_DISABLE_M64); 249262af557SGuo Chao return -EIO; 250262af557SGuo Chao } 251262af557SGuo Chao 252c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25396a2f92bSGavin Shan unsigned long *pe_bitmap) 254262af557SGuo Chao { 2555609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 256262af557SGuo Chao struct resource *r; 25796a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25896a2f92bSGavin Shan int segno, i; 259262af557SGuo Chao 26096a2f92bSGavin Shan base = phb->ioda.m64_base; 26196a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26296a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26396a2f92bSGavin Shan r = &pdev->resource[i]; 2645958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 265262af557SGuo Chao continue; 266262af557SGuo Chao 267e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 268b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 26996a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27096a2f92bSGavin Shan if (pe_bitmap) 27196a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27296a2f92bSGavin Shan else 27396a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 274262af557SGuo Chao } 275262af557SGuo Chao } 276262af557SGuo Chao } 277262af557SGuo Chao 27899451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 27999451551SGavin Shan { 28099451551SGavin Shan struct resource *r; 28199451551SGavin Shan int index; 28299451551SGavin Shan 28399451551SGavin Shan /* 28499451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28599451551SGavin Shan * there are as many M64 segments as the maximum number of 28699451551SGavin Shan * PEs, which is 128. 28799451551SGavin Shan */ 28899451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 28999451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29099451551SGavin Shan int64_t rc; 29199451551SGavin Shan 29299451551SGavin Shan base = phb->ioda.m64_base + 29399451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29499451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29699451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29799451551SGavin Shan if (rc != OPAL_SUCCESS) { 2981f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 29999451551SGavin Shan rc, phb->hose->global_number, index); 30099451551SGavin Shan goto fail; 30199451551SGavin Shan } 30299451551SGavin Shan 30399451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30499451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30599451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30699451551SGavin Shan if (rc != OPAL_SUCCESS) { 3071f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30899451551SGavin Shan rc, phb->hose->global_number, index); 30999451551SGavin Shan goto fail; 31099451551SGavin Shan } 31199451551SGavin Shan } 31299451551SGavin Shan 31399451551SGavin Shan /* 31463803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31563803c39SGavin Shan * are first or last two PEs. 31699451551SGavin Shan */ 31799451551SGavin Shan r = &phb->hose->mem_resources[1]; 31899451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 31963803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32099451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32163803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32299451551SGavin Shan else 3231f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32499451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32599451551SGavin Shan 32699451551SGavin Shan return 0; 32799451551SGavin Shan 32899451551SGavin Shan fail: 32999451551SGavin Shan for ( ; index >= 0; index--) 33099451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33199451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33299451551SGavin Shan 33399451551SGavin Shan return -EIO; 33499451551SGavin Shan } 33599451551SGavin Shan 336c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33796a2f92bSGavin Shan unsigned long *pe_bitmap, 33896a2f92bSGavin Shan bool all) 339262af557SGuo Chao { 340262af557SGuo Chao struct pci_dev *pdev; 34196a2f92bSGavin Shan 34296a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 343c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34496a2f92bSGavin Shan 34596a2f92bSGavin Shan if (all && pdev->subordinate) 346c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34796a2f92bSGavin Shan pe_bitmap, all); 34896a2f92bSGavin Shan } 34996a2f92bSGavin Shan } 35096a2f92bSGavin Shan 3511e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 352262af557SGuo Chao { 3535609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 354262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 355262af557SGuo Chao unsigned long size, *pe_alloc; 35626ba248dSGavin Shan int i; 357262af557SGuo Chao 358262af557SGuo Chao /* Root bus shouldn't use M64 */ 359262af557SGuo Chao if (pci_is_root_bus(bus)) 3601e916772SGavin Shan return NULL; 361262af557SGuo Chao 362262af557SGuo Chao /* Allocate bitmap */ 363b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 364262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 365262af557SGuo Chao if (!pe_alloc) { 366262af557SGuo Chao pr_warn("%s: Out of memory !\n", 367262af557SGuo Chao __func__); 3681e916772SGavin Shan return NULL; 369262af557SGuo Chao } 370262af557SGuo Chao 37126ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 372c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 373262af557SGuo Chao 374262af557SGuo Chao /* 375262af557SGuo Chao * the current bus might not own M64 window and that's all 376262af557SGuo Chao * contributed by its child buses. For the case, we needn't 377262af557SGuo Chao * pick M64 dependent PE#. 378262af557SGuo Chao */ 37992b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 380262af557SGuo Chao kfree(pe_alloc); 3811e916772SGavin Shan return NULL; 382262af557SGuo Chao } 383262af557SGuo Chao 384262af557SGuo Chao /* 385262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 386262af557SGuo Chao * PE's list to form compound PE. 387262af557SGuo Chao */ 388262af557SGuo Chao master_pe = NULL; 389262af557SGuo Chao i = -1; 39092b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39192b8f137SGavin Shan phb->ioda.total_pe_num) { 392262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 393262af557SGuo Chao 39493289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 395262af557SGuo Chao if (!master_pe) { 396262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 397262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 398262af557SGuo Chao master_pe = pe; 399262af557SGuo Chao } else { 400262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 401262af557SGuo Chao pe->master = master_pe; 402262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 403262af557SGuo Chao } 40499451551SGavin Shan 40599451551SGavin Shan /* 40699451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40799451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 40899451551SGavin Shan * between M64 segment and PE#. In order to have same logic 40999451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41099451551SGavin Shan * segment and PE# on P7IOC. 41199451551SGavin Shan */ 41299451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41399451551SGavin Shan int64_t rc; 41499451551SGavin Shan 41599451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41699451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41799451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 41899451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 41999451551SGavin Shan if (rc != OPAL_SUCCESS) 4201f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42199451551SGavin Shan __func__, rc, phb->hose->global_number, 42299451551SGavin Shan pe->pe_number); 42399451551SGavin Shan } 424262af557SGuo Chao } 425262af557SGuo Chao 426262af557SGuo Chao kfree(pe_alloc); 4271e916772SGavin Shan return master_pe; 428262af557SGuo Chao } 429262af557SGuo Chao 430262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 431262af557SGuo Chao { 432262af557SGuo Chao struct pci_controller *hose = phb->hose; 433262af557SGuo Chao struct device_node *dn = hose->dn; 434262af557SGuo Chao struct resource *res; 435a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4360e7736c6SGavin Shan const __be32 *r; 437262af557SGuo Chao u64 pci_addr; 438262af557SGuo Chao 43999451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4401665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4411665c4a8SGavin Shan return; 4421665c4a8SGavin Shan } 4431665c4a8SGavin Shan 444e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 445262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 446262af557SGuo Chao return; 447262af557SGuo Chao } 448262af557SGuo Chao 449262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 450262af557SGuo Chao if (!r) { 451b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 452b7c670d6SRob Herring dn); 453262af557SGuo Chao return; 454262af557SGuo Chao } 455262af557SGuo Chao 456a1339fafSBenjamin Herrenschmidt /* 457a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 458a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 459a1339fafSBenjamin Herrenschmidt */ 460a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 461a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 462a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 463a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 464a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 465a1339fafSBenjamin Herrenschmidt } 466a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 467a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 468a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 469a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 470a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 471a1339fafSBenjamin Herrenschmidt } 472a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 473a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 474a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 475a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 476a1339fafSBenjamin Herrenschmidt return; 477a1339fafSBenjamin Herrenschmidt } 478a1339fafSBenjamin Herrenschmidt 479a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 480262af557SGuo Chao res = &hose->mem_resources[1]; 481e80c4e7cSGavin Shan res->name = dn->full_name; 482262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 483262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 484262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 485262af557SGuo Chao pci_addr = of_read_number(r, 2); 486262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 487262af557SGuo Chao 488262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 48992b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 490262af557SGuo Chao phb->ioda.m64_base = pci_addr; 491262af557SGuo Chao 492a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 493a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 494a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 495a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 496a1339fafSBenjamin Herrenschmidt 497a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 498a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 499e9863e68SWei Yang 500262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 501a1339fafSBenjamin Herrenschmidt m64_range[1]--; 502a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 503a1339fafSBenjamin Herrenschmidt 504a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 505a1339fafSBenjamin Herrenschmidt 506a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 507a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 508a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 509a1339fafSBenjamin Herrenschmidt 510a1339fafSBenjamin Herrenschmidt /* 511a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 512a1339fafSBenjamin Herrenschmidt * the IODA2 code. 513a1339fafSBenjamin Herrenschmidt */ 51499451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51599451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51699451551SGavin Shan else 517262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 518262af557SGuo Chao } 519262af557SGuo Chao 52049dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52149dec922SGavin Shan { 52249dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52349dec922SGavin Shan struct pnv_ioda_pe *slave; 52449dec922SGavin Shan s64 rc; 52549dec922SGavin Shan 52649dec922SGavin Shan /* Fetch master PE */ 52749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 52849dec922SGavin Shan pe = pe->master; 529ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 530ec8e4e9dSGavin Shan return; 531ec8e4e9dSGavin Shan 53249dec922SGavin Shan pe_no = pe->pe_number; 53349dec922SGavin Shan } 53449dec922SGavin Shan 53549dec922SGavin Shan /* Freeze master PE */ 53649dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53749dec922SGavin Shan pe_no, 53849dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 53949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54049dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54149dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54249dec922SGavin Shan return; 54349dec922SGavin Shan } 54449dec922SGavin Shan 54549dec922SGavin Shan /* Freeze slave PEs */ 54649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54749dec922SGavin Shan return; 54849dec922SGavin Shan 54949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55049dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55149dec922SGavin Shan slave->pe_number, 55249dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55349dec922SGavin Shan if (rc != OPAL_SUCCESS) 55449dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55549dec922SGavin Shan __func__, rc, phb->hose->global_number, 55649dec922SGavin Shan slave->pe_number); 55749dec922SGavin Shan } 55849dec922SGavin Shan } 55949dec922SGavin Shan 560e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56149dec922SGavin Shan { 56249dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56349dec922SGavin Shan s64 rc; 56449dec922SGavin Shan 56549dec922SGavin Shan /* Find master PE */ 56649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 56849dec922SGavin Shan pe = pe->master; 56949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57049dec922SGavin Shan pe_no = pe->pe_number; 57149dec922SGavin Shan } 57249dec922SGavin Shan 57349dec922SGavin Shan /* Clear frozen state for master PE */ 57449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57649dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57749dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 57849dec922SGavin Shan return -EIO; 57949dec922SGavin Shan } 58049dec922SGavin Shan 58149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58249dec922SGavin Shan return 0; 58349dec922SGavin Shan 58449dec922SGavin Shan /* Clear frozen state for slave PEs */ 58549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58749dec922SGavin Shan slave->pe_number, 58849dec922SGavin Shan opt); 58949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59049dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59149dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59249dec922SGavin Shan slave->pe_number); 59349dec922SGavin Shan return -EIO; 59449dec922SGavin Shan } 59549dec922SGavin Shan } 59649dec922SGavin Shan 59749dec922SGavin Shan return 0; 59849dec922SGavin Shan } 59949dec922SGavin Shan 60049dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60149dec922SGavin Shan { 60249dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 603c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 604c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 60549dec922SGavin Shan s64 rc; 60649dec922SGavin Shan 60749dec922SGavin Shan /* Sanity check on PE number */ 60892b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 60949dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61049dec922SGavin Shan 61149dec922SGavin Shan /* 61249dec922SGavin Shan * Fetch the master PE and the PE instance might be 61349dec922SGavin Shan * not initialized yet. 61449dec922SGavin Shan */ 61549dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61749dec922SGavin Shan pe = pe->master; 61849dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 61949dec922SGavin Shan pe_no = pe->pe_number; 62049dec922SGavin Shan } 62149dec922SGavin Shan 62249dec922SGavin Shan /* Check the master PE */ 62349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62449dec922SGavin Shan &state, &pcierr, NULL); 62549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62749dec922SGavin Shan "PHB#%x-PE#%x state\n", 62849dec922SGavin Shan __func__, rc, 62949dec922SGavin Shan phb->hose->global_number, pe_no); 63049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63149dec922SGavin Shan } 63249dec922SGavin Shan 63349dec922SGavin Shan /* Check the slave PE */ 63449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63549dec922SGavin Shan return state; 63649dec922SGavin Shan 63749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 63849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 63949dec922SGavin Shan slave->pe_number, 64049dec922SGavin Shan &fstate, 64149dec922SGavin Shan &pcierr, 64249dec922SGavin Shan NULL); 64349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64549dec922SGavin Shan "PHB#%x-PE#%x state\n", 64649dec922SGavin Shan __func__, rc, 64749dec922SGavin Shan phb->hose->global_number, slave->pe_number); 64849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 64949dec922SGavin Shan } 65049dec922SGavin Shan 65149dec922SGavin Shan /* 65249dec922SGavin Shan * Override the result based on the ascending 65349dec922SGavin Shan * priority. 65449dec922SGavin Shan */ 65549dec922SGavin Shan if (fstate > state) 65649dec922SGavin Shan state = fstate; 65749dec922SGavin Shan } 65849dec922SGavin Shan 65949dec922SGavin Shan return state; 66049dec922SGavin Shan } 66149dec922SGavin Shan 662a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 663a8d7d5fcSOliver O'Halloran { 664a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn]; 665a8d7d5fcSOliver O'Halloran 666a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE) 667a8d7d5fcSOliver O'Halloran return NULL; 668a8d7d5fcSOliver O'Halloran 669a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number]; 670a8d7d5fcSOliver O'Halloran } 671a8d7d5fcSOliver O'Halloran 672f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 673184cd4a3SBenjamin Herrenschmidt { 6745609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 675b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 676184cd4a3SBenjamin Herrenschmidt 677184cd4a3SBenjamin Herrenschmidt if (!pdn) 678184cd4a3SBenjamin Herrenschmidt return NULL; 679184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 680184cd4a3SBenjamin Herrenschmidt return NULL; 681184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 682184cd4a3SBenjamin Herrenschmidt } 683184cd4a3SBenjamin Herrenschmidt 684b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 685b131a842SGavin Shan struct pnv_ioda_pe *parent, 686b131a842SGavin Shan struct pnv_ioda_pe *child, 687b131a842SGavin Shan bool is_add) 688b131a842SGavin Shan { 689b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 690b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 691b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 692b131a842SGavin Shan struct pnv_ioda_pe *slave; 693b131a842SGavin Shan long rc; 694b131a842SGavin Shan 695b131a842SGavin Shan /* Parent PE affects child PE */ 696b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 697b131a842SGavin Shan child->pe_number, op); 698b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 699b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 700b131a842SGavin Shan rc, desc); 701b131a842SGavin Shan return -ENXIO; 702b131a842SGavin Shan } 703b131a842SGavin Shan 704b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 705b131a842SGavin Shan return 0; 706b131a842SGavin Shan 707b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 708b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 709b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 710b131a842SGavin Shan slave->pe_number, op); 711b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 712b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 713b131a842SGavin Shan rc, desc); 714b131a842SGavin Shan return -ENXIO; 715b131a842SGavin Shan } 716b131a842SGavin Shan } 717b131a842SGavin Shan 718b131a842SGavin Shan return 0; 719b131a842SGavin Shan } 720b131a842SGavin Shan 721b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 722b131a842SGavin Shan struct pnv_ioda_pe *pe, 723b131a842SGavin Shan bool is_add) 724b131a842SGavin Shan { 725b131a842SGavin Shan struct pnv_ioda_pe *slave; 726781a868fSWei Yang struct pci_dev *pdev = NULL; 727b131a842SGavin Shan int ret; 728b131a842SGavin Shan 729b131a842SGavin Shan /* 730b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 731b131a842SGavin Shan * clear slave PE frozen state as well. 732b131a842SGavin Shan */ 733b131a842SGavin Shan if (is_add) { 734b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 735b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 736b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 737b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 738b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 739b131a842SGavin Shan slave->pe_number, 740b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 741b131a842SGavin Shan } 742b131a842SGavin Shan } 743b131a842SGavin Shan 744b131a842SGavin Shan /* 745b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 746b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 747b131a842SGavin Shan * originated from the PE might contribute to other 748b131a842SGavin Shan * PEs. 749b131a842SGavin Shan */ 750b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 751b131a842SGavin Shan if (ret) 752b131a842SGavin Shan return ret; 753b131a842SGavin Shan 754b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 755b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 756b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 757b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 758b131a842SGavin Shan if (ret) 759b131a842SGavin Shan return ret; 760b131a842SGavin Shan } 761b131a842SGavin Shan } 762b131a842SGavin Shan 763b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 764b131a842SGavin Shan pdev = pe->pbus->self; 765781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 766b131a842SGavin Shan pdev = pe->pdev->bus->self; 767781a868fSWei Yang #ifdef CONFIG_PCI_IOV 768781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 769283e2d8aSGavin Shan pdev = pe->parent_dev; 770781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 771b131a842SGavin Shan while (pdev) { 772b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 773b131a842SGavin Shan struct pnv_ioda_pe *parent; 774b131a842SGavin Shan 775b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 776b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 777b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 778b131a842SGavin Shan if (ret) 779b131a842SGavin Shan return ret; 780b131a842SGavin Shan } 781b131a842SGavin Shan 782b131a842SGavin Shan pdev = pdev->bus->self; 783b131a842SGavin Shan } 784b131a842SGavin Shan 785b131a842SGavin Shan return 0; 786b131a842SGavin Shan } 787b131a842SGavin Shan 788f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 789f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 790f724385fSFrederic Barrat struct pci_dev *parent) 791f724385fSFrederic Barrat { 792f724385fSFrederic Barrat int64_t rc; 793f724385fSFrederic Barrat 794f724385fSFrederic Barrat while (parent) { 795f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 796f724385fSFrederic Barrat 797f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 798f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 799f724385fSFrederic Barrat pe->pe_number, 800f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 801f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 802f724385fSFrederic Barrat } 803f724385fSFrederic Barrat parent = parent->bus->self; 804f724385fSFrederic Barrat } 805f724385fSFrederic Barrat 806f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 807f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 808f724385fSFrederic Barrat 809f724385fSFrederic Barrat /* Disassociate PE in PELT */ 810f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 811f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 812f724385fSFrederic Barrat if (rc) 813f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 814f724385fSFrederic Barrat } 815f724385fSFrederic Barrat 816781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 817781a868fSWei Yang { 818781a868fSWei Yang struct pci_dev *parent; 819781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 820781a868fSWei Yang int64_t rc; 821781a868fSWei Yang long rid_end, rid; 822781a868fSWei Yang 823781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 824781a868fSWei Yang if (pe->pbus) { 825781a868fSWei Yang int count; 826781a868fSWei Yang 827781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 828781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 829781a868fSWei Yang parent = pe->pbus->self; 830781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 831552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 832781a868fSWei Yang else 833781a868fSWei Yang count = 1; 834781a868fSWei Yang 835781a868fSWei Yang switch(count) { 836781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 837781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 838781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 839781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 840781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 841781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 842781a868fSWei Yang default: 843781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 844781a868fSWei Yang count); 845781a868fSWei Yang /* Do an exact match only */ 846781a868fSWei Yang bcomp = OpalPciBusAll; 847781a868fSWei Yang } 848781a868fSWei Yang rid_end = pe->rid + (count << 8); 849781a868fSWei Yang } else { 85093e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 851781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 852781a868fSWei Yang parent = pe->parent_dev; 853781a868fSWei Yang else 85493e01a50SGavin Shan #endif 855781a868fSWei Yang parent = pe->pdev->bus->self; 856781a868fSWei Yang bcomp = OpalPciBusAll; 857781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 858781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 859781a868fSWei Yang rid_end = pe->rid + 1; 860781a868fSWei Yang } 861781a868fSWei Yang 862781a868fSWei Yang /* Clear the reverse map */ 863781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 864c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 865781a868fSWei Yang 866f724385fSFrederic Barrat /* 867f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 868f724385fSFrederic Barrat * table 869f724385fSFrederic Barrat */ 870f724385fSFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 871f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 872781a868fSWei Yang 873781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 874781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 875781a868fSWei Yang if (rc) 8761e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 877781a868fSWei Yang 878781a868fSWei Yang pe->pbus = NULL; 879781a868fSWei Yang pe->pdev = NULL; 88093e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 881781a868fSWei Yang pe->parent_dev = NULL; 88293e01a50SGavin Shan #endif 883781a868fSWei Yang 884781a868fSWei Yang return 0; 885781a868fSWei Yang } 886781a868fSWei Yang 887cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 888184cd4a3SBenjamin Herrenschmidt { 889184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 890184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 891184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 892184cd4a3SBenjamin Herrenschmidt 893184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 894184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 895184cd4a3SBenjamin Herrenschmidt int count; 896184cd4a3SBenjamin Herrenschmidt 897184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 898184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 899184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 900fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 901552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 902fb446ad0SGavin Shan else 903fb446ad0SGavin Shan count = 1; 904fb446ad0SGavin Shan 905184cd4a3SBenjamin Herrenschmidt switch(count) { 906184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 907184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 908184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 909184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 910184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 911184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 912184cd4a3SBenjamin Herrenschmidt default: 913781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 914781a868fSWei Yang count); 915184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 916184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 917184cd4a3SBenjamin Herrenschmidt } 918184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 919184cd4a3SBenjamin Herrenschmidt } else { 920781a868fSWei Yang #ifdef CONFIG_PCI_IOV 921781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 922781a868fSWei Yang parent = pe->parent_dev; 923781a868fSWei Yang else 924781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 925184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 926184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 927184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 928184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 929184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 930184cd4a3SBenjamin Herrenschmidt } 931184cd4a3SBenjamin Herrenschmidt 932631ad691SGavin Shan /* 933631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 934631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 935631ad691SGavin Shan * originated from the PE might contribute to other 936631ad691SGavin Shan * PEs. 937631ad691SGavin Shan */ 938184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 939184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 940184cd4a3SBenjamin Herrenschmidt if (rc) { 941184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 942184cd4a3SBenjamin Herrenschmidt return -ENXIO; 943184cd4a3SBenjamin Herrenschmidt } 944631ad691SGavin Shan 9455d2aa710SAlistair Popple /* 9465d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9475d2aa710SAlistair Popple * configuration on them. 9485d2aa710SAlistair Popple */ 9497f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 950b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 951184cd4a3SBenjamin Herrenschmidt 952184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 953184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 954184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 955184cd4a3SBenjamin Herrenschmidt 956184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9574773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9584773f76bSGavin Shan pe->mve_number = 0; 9594773f76bSGavin Shan goto out; 9604773f76bSGavin Shan } 9614773f76bSGavin Shan 962184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9634773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9644773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9651f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 966184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 967184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 968184cd4a3SBenjamin Herrenschmidt } else { 969184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 970cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 971184cd4a3SBenjamin Herrenschmidt if (rc) { 9721f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 973184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 974184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 975184cd4a3SBenjamin Herrenschmidt } 976184cd4a3SBenjamin Herrenschmidt } 977184cd4a3SBenjamin Herrenschmidt 9784773f76bSGavin Shan out: 979184cd4a3SBenjamin Herrenschmidt return 0; 980184cd4a3SBenjamin Herrenschmidt } 981184cd4a3SBenjamin Herrenschmidt 982781a868fSWei Yang #ifdef CONFIG_PCI_IOV 983781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 984781a868fSWei Yang { 985781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 986781a868fSWei Yang int i; 987781a868fSWei Yang struct resource *res, res2; 988781a868fSWei Yang resource_size_t size; 989781a868fSWei Yang u16 num_vfs; 990781a868fSWei Yang 991781a868fSWei Yang if (!dev->is_physfn) 992781a868fSWei Yang return -EINVAL; 993781a868fSWei Yang 994781a868fSWei Yang /* 995781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 996781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 997781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 998781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 999781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 1000781a868fSWei Yang * range of PEs the VFs are in. 1001781a868fSWei Yang */ 1002781a868fSWei Yang num_vfs = pdn->num_vfs; 1003781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1004781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1005781a868fSWei Yang if (!res->flags || !res->parent) 1006781a868fSWei Yang continue; 1007781a868fSWei Yang 1008781a868fSWei Yang /* 1009781a868fSWei Yang * The actual IOV BAR range is determined by the start address 1010781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 1011781a868fSWei Yang * make sure that after shifting, the range will not overlap 1012781a868fSWei Yang * with another device. 1013781a868fSWei Yang */ 1014781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1015781a868fSWei Yang res2.flags = res->flags; 1016781a868fSWei Yang res2.start = res->start + (size * offset); 1017781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 1018781a868fSWei Yang 1019781a868fSWei Yang if (res2.end > res->end) { 1020781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1021781a868fSWei Yang i, &res2, res, num_vfs, offset); 1022781a868fSWei Yang return -EBUSY; 1023781a868fSWei Yang } 1024781a868fSWei Yang } 1025781a868fSWei Yang 1026781a868fSWei Yang /* 1027d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1028d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1029d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1030d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1031d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1032d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1033781a868fSWei Yang */ 1034781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1035781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1036781a868fSWei Yang if (!res->flags || !res->parent) 1037781a868fSWei Yang continue; 1038781a868fSWei Yang 1039781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1040781a868fSWei Yang res2 = *res; 1041781a868fSWei Yang res->start += size * offset; 1042781a868fSWei Yang 104374703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 104474703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 104574703cc4SWei Yang num_vfs, offset); 1046d6f934fdSAlexey Kardashevskiy 1047d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1048d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1049d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1050d6f934fdSAlexey Kardashevskiy } 1051d6f934fdSAlexey Kardashevskiy 1052781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1053d6f934fdSAlexey Kardashevskiy 1054d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1055d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1056d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1057d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1058d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1059d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1060d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1061d6f934fdSAlexey Kardashevskiy } 1062781a868fSWei Yang } 1063781a868fSWei Yang return 0; 1064781a868fSWei Yang } 1065781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1066781a868fSWei Yang 1067cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1068184cd4a3SBenjamin Herrenschmidt { 10695609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 1070b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1071184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1072184cd4a3SBenjamin Herrenschmidt 1073184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1074184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1075184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1076184cd4a3SBenjamin Herrenschmidt return NULL; 1077184cd4a3SBenjamin Herrenschmidt } 1078184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1079184cd4a3SBenjamin Herrenschmidt return NULL; 1080184cd4a3SBenjamin Herrenschmidt 10811e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10821e916772SGavin Shan if (!pe) { 1083f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1084184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1085184cd4a3SBenjamin Herrenschmidt return NULL; 1086184cd4a3SBenjamin Herrenschmidt } 1087184cd4a3SBenjamin Herrenschmidt 108805dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 108905dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 109005dd7da7SFrederic Barrat * destroyed at the same time. However, removing nvlink 109105dd7da7SFrederic Barrat * devices will need some work. 1092184cd4a3SBenjamin Herrenschmidt * 1093184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1094184cd4a3SBenjamin Herrenschmidt */ 10951e916772SGavin Shan pdn->pe_number = pe->pe_number; 10965d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1097184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1098184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1099184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1100184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1101f724385fSFrederic Barrat pe->device_count++; 1102184cd4a3SBenjamin Herrenschmidt 1103184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1104184cd4a3SBenjamin Herrenschmidt 1105184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1106184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11071e916772SGavin Shan pnv_ioda_free_pe(pe); 1108184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1109184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1110184cd4a3SBenjamin Herrenschmidt return NULL; 1111184cd4a3SBenjamin Herrenschmidt } 1112184cd4a3SBenjamin Herrenschmidt 11131d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 111480f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 11151d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 111680f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 1117184cd4a3SBenjamin Herrenschmidt return pe; 1118184cd4a3SBenjamin Herrenschmidt } 1119184cd4a3SBenjamin Herrenschmidt 1120fb446ad0SGavin Shan /* 1121fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1122fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1123fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1124fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1125fb446ad0SGavin Shan */ 11261e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1127184cd4a3SBenjamin Herrenschmidt { 11285609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 11291e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1130ccd1c191SGavin Shan unsigned int pe_num; 1131ccd1c191SGavin Shan 1132ccd1c191SGavin Shan /* 1133ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1134ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1135ccd1c191SGavin Shan */ 1136ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 11376ae8aedfSOliver O'Halloran if (WARN_ON(pe_num != IODA_INVALID_PE)) { 1138ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1139ccd1c191SGavin Shan return NULL; 1140ccd1c191SGavin Shan } 1141184cd4a3SBenjamin Herrenschmidt 114263803c39SGavin Shan /* PE number for root bus should have been reserved */ 1143718d249aSOliver O'Halloran if (pci_is_root_bus(bus)) 114463803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 114563803c39SGavin Shan 1146262af557SGuo Chao /* Check if PE is determined by M64 */ 1147a25de7afSAlexey Kardashevskiy if (!pe) 1148a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1149262af557SGuo Chao 1150262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11511e916772SGavin Shan if (!pe) 11521e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1153262af557SGuo Chao 11541e916772SGavin Shan if (!pe) { 1155f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1156fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11571e916772SGavin Shan return NULL; 1158184cd4a3SBenjamin Herrenschmidt } 1159184cd4a3SBenjamin Herrenschmidt 1160262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1161184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1162184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1163184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1164b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1165184cd4a3SBenjamin Herrenschmidt 1166fb446ad0SGavin Shan if (all) 11671e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 11681e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 11691e496391SJoe Perches pe->pe_number); 1170fb446ad0SGavin Shan else 11711e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 11721e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1173184cd4a3SBenjamin Herrenschmidt 1174184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1175184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11761e916772SGavin Shan pnv_ioda_free_pe(pe); 1177184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11781e916772SGavin Shan return NULL; 1179184cd4a3SBenjamin Herrenschmidt } 1180184cd4a3SBenjamin Herrenschmidt 11817ebdf956SGavin Shan /* Put PE to the list */ 11827ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11831e916772SGavin Shan 11841e916772SGavin Shan return pe; 1185184cd4a3SBenjamin Herrenschmidt } 1186184cd4a3SBenjamin Herrenschmidt 1187b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11885d2aa710SAlistair Popple { 1189b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1190b521549aSAlistair Popple long rid; 1191b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1192b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1193b521549aSAlistair Popple struct pci_dn *npu_pdn; 11945609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(npu_pdev->bus); 1195b521549aSAlistair Popple 1196b521549aSAlistair Popple /* 119705dd7da7SFrederic Barrat * Intentionally leak a reference on the npu device (for 119805dd7da7SFrederic Barrat * nvlink only; this is not an opencapi path) to make sure it 119905dd7da7SFrederic Barrat * never goes away, as it's been the case all along and some 120005dd7da7SFrederic Barrat * work is needed otherwise. 120105dd7da7SFrederic Barrat */ 120205dd7da7SFrederic Barrat pci_dev_get(npu_pdev); 120305dd7da7SFrederic Barrat 120405dd7da7SFrederic Barrat /* 1205b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1206b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1207b521549aSAlistair Popple * which need to be assigned to four links, implying some 1208b521549aSAlistair Popple * links must share PEs. 1209b521549aSAlistair Popple * 1210b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1211b521549aSAlistair Popple * same GPU get assigned the same PE. 1212b521549aSAlistair Popple */ 1213b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 121492b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1215b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1216b521549aSAlistair Popple if (!pe->pdev) 1217b521549aSAlistair Popple continue; 1218b521549aSAlistair Popple 1219b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1220b521549aSAlistair Popple /* 1221b521549aSAlistair Popple * This device has the same peer GPU so should 1222b521549aSAlistair Popple * be assigned the same PE as the existing 1223b521549aSAlistair Popple * peer NPU. 1224b521549aSAlistair Popple */ 1225b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12261f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1227b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1228b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1229b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1230b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1231f724385fSFrederic Barrat pe->device_count++; 1232b521549aSAlistair Popple 1233b521549aSAlistair Popple /* Map the PE to this link */ 1234b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1235b521549aSAlistair Popple OpalPciBusAll, 1236b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1237b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1238b521549aSAlistair Popple OPAL_MAP_PE); 1239b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1240b521549aSAlistair Popple found_pe = true; 1241b521549aSAlistair Popple break; 1242b521549aSAlistair Popple } 1243b521549aSAlistair Popple } 1244b521549aSAlistair Popple 1245b521549aSAlistair Popple if (!found_pe) 1246b521549aSAlistair Popple /* 1247b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1248b521549aSAlistair Popple * one. 1249b521549aSAlistair Popple */ 1250b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1251b521549aSAlistair Popple else 1252b521549aSAlistair Popple return pe; 1253b521549aSAlistair Popple } 1254b521549aSAlistair Popple 1255b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1256b521549aSAlistair Popple { 12575d2aa710SAlistair Popple struct pci_dev *pdev; 12585d2aa710SAlistair Popple 12595d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1260b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12615d2aa710SAlistair Popple } 12625d2aa710SAlistair Popple 126303b7bf34SOliver O'Halloran static void pnv_pci_ioda_setup_nvlink(void) 1264fb446ad0SGavin Shan { 12650e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1266262af557SGuo Chao struct pnv_phb *phb; 12670e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1268fb446ad0SGavin Shan 12690e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1270262af557SGuo Chao phb = hose->private_data; 12717f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 127208f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 127308f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1274b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12751ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12760e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1277ccd1c191SGavin Shan } 1278fb446ad0SGavin Shan } 12790e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 12800e759bd7SAlexey Kardashevskiy phb = hose->private_data; 12810e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 12820e759bd7SAlexey Kardashevskiy continue; 12830e759bd7SAlexey Kardashevskiy 12840e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 12850e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 12860e759bd7SAlexey Kardashevskiy } 128703b7bf34SOliver O'Halloran 128803b7bf34SOliver O'Halloran #ifdef CONFIG_IOMMU_API 128903b7bf34SOliver O'Halloran /* setup iommu groups so we can do nvlink pass-thru */ 129003b7bf34SOliver O'Halloran pnv_pci_npu_setup_iommu_groups(); 129103b7bf34SOliver O'Halloran #endif 1292fb446ad0SGavin Shan } 1293184cd4a3SBenjamin Herrenschmidt 1294a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1295ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1296781a868fSWei Yang { 1297781a868fSWei Yang struct pnv_phb *phb; 1298781a868fSWei Yang struct pci_dn *pdn; 129902639b0eSWei Yang int i, j; 1300ee8222feSWei Yang int m64_bars; 1301781a868fSWei Yang 13025609ffddSOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 1303781a868fSWei Yang pdn = pci_get_pdn(pdev); 1304781a868fSWei Yang 1305ee8222feSWei Yang if (pdn->m64_single_mode) 1306ee8222feSWei Yang m64_bars = num_vfs; 1307ee8222feSWei Yang else 1308ee8222feSWei Yang m64_bars = 1; 1309ee8222feSWei Yang 131002639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1311ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1312ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1313781a868fSWei Yang continue; 1314781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1315ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1316ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1317ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1318781a868fSWei Yang } 1319781a868fSWei Yang 1320ee8222feSWei Yang kfree(pdn->m64_map); 1321781a868fSWei Yang return 0; 1322781a868fSWei Yang } 1323781a868fSWei Yang 132402639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1325781a868fSWei Yang { 1326781a868fSWei Yang struct pnv_phb *phb; 1327781a868fSWei Yang struct pci_dn *pdn; 1328781a868fSWei Yang unsigned int win; 1329781a868fSWei Yang struct resource *res; 133002639b0eSWei Yang int i, j; 1331781a868fSWei Yang int64_t rc; 133202639b0eSWei Yang int total_vfs; 133302639b0eSWei Yang resource_size_t size, start; 133402639b0eSWei Yang int pe_num; 1335ee8222feSWei Yang int m64_bars; 1336781a868fSWei Yang 13375609ffddSOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 1338781a868fSWei Yang pdn = pci_get_pdn(pdev); 133902639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1340781a868fSWei Yang 1341ee8222feSWei Yang if (pdn->m64_single_mode) 1342ee8222feSWei Yang m64_bars = num_vfs; 1343ee8222feSWei Yang else 1344ee8222feSWei Yang m64_bars = 1; 134502639b0eSWei Yang 1346fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1347fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1348fb37e128SMarkus Elfring GFP_KERNEL); 1349ee8222feSWei Yang if (!pdn->m64_map) 1350ee8222feSWei Yang return -ENOMEM; 1351ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1352ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1353ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1354ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1355ee8222feSWei Yang 1356781a868fSWei Yang 1357781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1358781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1359781a868fSWei Yang if (!res->flags || !res->parent) 1360781a868fSWei Yang continue; 1361781a868fSWei Yang 1362ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1363781a868fSWei Yang do { 1364781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1365781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1366781a868fSWei Yang 1367781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1368781a868fSWei Yang goto m64_failed; 1369781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1370781a868fSWei Yang 1371ee8222feSWei Yang pdn->m64_map[j][i] = win; 137202639b0eSWei Yang 1373ee8222feSWei Yang if (pdn->m64_single_mode) { 137402639b0eSWei Yang size = pci_iov_resource_size(pdev, 137502639b0eSWei Yang PCI_IOV_RESOURCES + i); 137602639b0eSWei Yang start = res->start + size * j; 137702639b0eSWei Yang } else { 137802639b0eSWei Yang size = resource_size(res); 137902639b0eSWei Yang start = res->start; 138002639b0eSWei Yang } 1381781a868fSWei Yang 1382781a868fSWei Yang /* Map the M64 here */ 1383ee8222feSWei Yang if (pdn->m64_single_mode) { 1384be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 138502639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 138602639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1387ee8222feSWei Yang pdn->m64_map[j][i], 0); 138802639b0eSWei Yang } 138902639b0eSWei Yang 1390781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1391781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1392ee8222feSWei Yang pdn->m64_map[j][i], 139302639b0eSWei Yang start, 1394781a868fSWei Yang 0, /* unused */ 139502639b0eSWei Yang size); 139602639b0eSWei Yang 139702639b0eSWei Yang 1398781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1399781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1400781a868fSWei Yang win, rc); 1401781a868fSWei Yang goto m64_failed; 1402781a868fSWei Yang } 1403781a868fSWei Yang 1404ee8222feSWei Yang if (pdn->m64_single_mode) 1405781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1406ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 140702639b0eSWei Yang else 140802639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1409ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 141002639b0eSWei Yang 1411781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1412781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1413781a868fSWei Yang win, rc); 1414781a868fSWei Yang goto m64_failed; 1415781a868fSWei Yang } 1416781a868fSWei Yang } 141702639b0eSWei Yang } 1418781a868fSWei Yang return 0; 1419781a868fSWei Yang 1420781a868fSWei Yang m64_failed: 1421ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1422781a868fSWei Yang return -EBUSY; 1423781a868fSWei Yang } 1424781a868fSWei Yang 14257a52ffabSOliver O'Halloran static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe); 1426781a868fSWei Yang 1427ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1428781a868fSWei Yang { 1429781a868fSWei Yang struct pnv_phb *phb; 1430781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1431781a868fSWei Yang struct pci_dn *pdn; 1432781a868fSWei Yang 14335609ffddSOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 143402639b0eSWei Yang pdn = pci_get_pdn(pdev); 1435781a868fSWei Yang 1436781a868fSWei Yang if (!pdev->is_physfn) 1437781a868fSWei Yang return; 1438781a868fSWei Yang 14397a52ffabSOliver O'Halloran /* FIXME: Use pnv_ioda_release_pe()? */ 1440781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1441781a868fSWei Yang if (pe->parent_dev != pdev) 1442781a868fSWei Yang continue; 1443781a868fSWei Yang 14447a52ffabSOliver O'Halloran pnv_pci_ioda2_release_pe_dma(pe); 1445781a868fSWei Yang 1446781a868fSWei Yang /* Remove from list */ 1447781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1448781a868fSWei Yang list_del(&pe->list); 1449781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1450781a868fSWei Yang 1451781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1452781a868fSWei Yang 14531e916772SGavin Shan pnv_ioda_free_pe(pe); 1454781a868fSWei Yang } 1455781a868fSWei Yang } 1456781a868fSWei Yang 145793eacd94SOliver O'Halloran static void pnv_pci_sriov_disable(struct pci_dev *pdev) 1458781a868fSWei Yang { 1459781a868fSWei Yang struct pnv_phb *phb; 14601e916772SGavin Shan struct pnv_ioda_pe *pe; 1461781a868fSWei Yang struct pci_dn *pdn; 1462be283eebSWei Yang u16 num_vfs, i; 1463781a868fSWei Yang 14645609ffddSOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 1465781a868fSWei Yang pdn = pci_get_pdn(pdev); 1466781a868fSWei Yang num_vfs = pdn->num_vfs; 1467781a868fSWei Yang 1468781a868fSWei Yang /* Release VF PEs */ 1469ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1470781a868fSWei Yang 1471781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1472ee8222feSWei Yang if (!pdn->m64_single_mode) 1473be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1474781a868fSWei Yang 1475781a868fSWei Yang /* Release M64 windows */ 1476ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1477781a868fSWei Yang 1478781a868fSWei Yang /* Release PE numbers */ 1479be283eebSWei Yang if (pdn->m64_single_mode) { 1480be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 14811e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 14821e916772SGavin Shan continue; 14831e916772SGavin Shan 14841e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 14851e916772SGavin Shan pnv_ioda_free_pe(pe); 1486be283eebSWei Yang } 1487be283eebSWei Yang } else 1488be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1489be283eebSWei Yang /* Releasing pe_num_map */ 1490be283eebSWei Yang kfree(pdn->pe_num_map); 1491781a868fSWei Yang } 1492781a868fSWei Yang } 1493781a868fSWei Yang 1494781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1495781a868fSWei Yang struct pnv_ioda_pe *pe); 1496781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1497781a868fSWei Yang { 1498781a868fSWei Yang struct pnv_phb *phb; 1499781a868fSWei Yang struct pnv_ioda_pe *pe; 1500781a868fSWei Yang int pe_num; 1501781a868fSWei Yang u16 vf_index; 1502781a868fSWei Yang struct pci_dn *pdn; 1503781a868fSWei Yang 15045609ffddSOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 1505781a868fSWei Yang pdn = pci_get_pdn(pdev); 1506781a868fSWei Yang 1507781a868fSWei Yang if (!pdev->is_physfn) 1508781a868fSWei Yang return; 1509781a868fSWei Yang 1510781a868fSWei Yang /* Reserve PE for each VF */ 1511781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 15123b5b9997SOliver O'Halloran int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 15133b5b9997SOliver O'Halloran int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 15143b5b9997SOliver O'Halloran struct pci_dn *vf_pdn; 15153b5b9997SOliver O'Halloran 1516be283eebSWei Yang if (pdn->m64_single_mode) 1517be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1518be283eebSWei Yang else 1519be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1520781a868fSWei Yang 1521781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1522781a868fSWei Yang pe->pe_number = pe_num; 1523781a868fSWei Yang pe->phb = phb; 1524781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1525781a868fSWei Yang pe->pbus = NULL; 1526781a868fSWei Yang pe->parent_dev = pdev; 1527781a868fSWei Yang pe->mve_number = -1; 15283b5b9997SOliver O'Halloran pe->rid = (vf_bus << 8) | vf_devfn; 1529781a868fSWei Yang 15301f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 15315609ffddSOliver O'Halloran pci_domain_nr(pdev->bus), pdev->bus->number, 15323b5b9997SOliver O'Halloran PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 1533781a868fSWei Yang 1534781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1535781a868fSWei Yang /* XXX What do we do here ? */ 15361e916772SGavin Shan pnv_ioda_free_pe(pe); 1537781a868fSWei Yang pe->pdev = NULL; 1538781a868fSWei Yang continue; 1539781a868fSWei Yang } 1540781a868fSWei Yang 1541781a868fSWei Yang /* Put PE to the list */ 1542781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1543781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1544781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1545781a868fSWei Yang 15463b5b9997SOliver O'Halloran /* associate this pe to it's pdn */ 15473b5b9997SOliver O'Halloran list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 15483b5b9997SOliver O'Halloran if (vf_pdn->busno == vf_bus && 15493b5b9997SOliver O'Halloran vf_pdn->devfn == vf_devfn) { 15503b5b9997SOliver O'Halloran vf_pdn->pe_number = pe_num; 15513b5b9997SOliver O'Halloran break; 15523b5b9997SOliver O'Halloran } 15533b5b9997SOliver O'Halloran } 15543b5b9997SOliver O'Halloran 1555781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1556781a868fSWei Yang } 1557781a868fSWei Yang } 1558781a868fSWei Yang 155993eacd94SOliver O'Halloran static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1560781a868fSWei Yang { 1561781a868fSWei Yang struct pnv_phb *phb; 15621e916772SGavin Shan struct pnv_ioda_pe *pe; 1563781a868fSWei Yang struct pci_dn *pdn; 1564781a868fSWei Yang int ret; 1565be283eebSWei Yang u16 i; 1566781a868fSWei Yang 15675609ffddSOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 1568781a868fSWei Yang pdn = pci_get_pdn(pdev); 1569781a868fSWei Yang 1570781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1571b0331854SWei Yang if (!pdn->vfs_expanded) { 1572b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1573b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1574b0331854SWei Yang return -ENOSPC; 1575b0331854SWei Yang } 1576b0331854SWei Yang 1577ee8222feSWei Yang /* 1578ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1579ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1580ee8222feSWei Yang */ 1581ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1582ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1583ee8222feSWei Yang return -EBUSY; 1584ee8222feSWei Yang } 1585ee8222feSWei Yang 1586be283eebSWei Yang /* Allocating pe_num_map */ 1587be283eebSWei Yang if (pdn->m64_single_mode) 1588fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1589fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1590be283eebSWei Yang GFP_KERNEL); 1591be283eebSWei Yang else 1592be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1593be283eebSWei Yang 1594be283eebSWei Yang if (!pdn->pe_num_map) 1595be283eebSWei Yang return -ENOMEM; 1596be283eebSWei Yang 1597be283eebSWei Yang if (pdn->m64_single_mode) 1598be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1599be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1600be283eebSWei Yang 1601781a868fSWei Yang /* Calculate available PE for required VFs */ 1602be283eebSWei Yang if (pdn->m64_single_mode) { 1603be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16041e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16051e916772SGavin Shan if (!pe) { 1606be283eebSWei Yang ret = -EBUSY; 1607be283eebSWei Yang goto m64_failed; 1608be283eebSWei Yang } 16091e916772SGavin Shan 16101e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1611be283eebSWei Yang } 1612be283eebSWei Yang } else { 1613781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1614be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 161592b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1616781a868fSWei Yang 0, num_vfs, 0); 161792b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1618781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1619781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1620be283eebSWei Yang kfree(pdn->pe_num_map); 1621781a868fSWei Yang return -EBUSY; 1622781a868fSWei Yang } 1623be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1624781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1625be283eebSWei Yang } 1626be283eebSWei Yang pdn->num_vfs = num_vfs; 1627781a868fSWei Yang 1628781a868fSWei Yang /* Assign M64 window accordingly */ 162902639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1630781a868fSWei Yang if (ret) { 1631781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1632781a868fSWei Yang goto m64_failed; 1633781a868fSWei Yang } 1634781a868fSWei Yang 1635781a868fSWei Yang /* 1636781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1637781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1638781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1639781a868fSWei Yang */ 1640ee8222feSWei Yang if (!pdn->m64_single_mode) { 1641be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1642781a868fSWei Yang if (ret) 1643781a868fSWei Yang goto m64_failed; 1644781a868fSWei Yang } 164502639b0eSWei Yang } 1646781a868fSWei Yang 1647781a868fSWei Yang /* Setup VF PEs */ 1648781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1649781a868fSWei Yang 1650781a868fSWei Yang return 0; 1651781a868fSWei Yang 1652781a868fSWei Yang m64_failed: 1653be283eebSWei Yang if (pdn->m64_single_mode) { 1654be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16551e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16561e916772SGavin Shan continue; 16571e916772SGavin Shan 16581e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16591e916772SGavin Shan pnv_ioda_free_pe(pe); 1660be283eebSWei Yang } 1661be283eebSWei Yang } else 1662be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1663be283eebSWei Yang 1664be283eebSWei Yang /* Releasing pe_num_map */ 1665be283eebSWei Yang kfree(pdn->pe_num_map); 1666781a868fSWei Yang 1667781a868fSWei Yang return ret; 1668781a868fSWei Yang } 1669781a868fSWei Yang 167093eacd94SOliver O'Halloran static int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1671a8b2f828SGavin Shan { 1672781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1673781a868fSWei Yang 1674a8b2f828SGavin Shan /* Release PCI data */ 16758cd6aaccSOliver O'Halloran remove_sriov_vf_pdns(pdev); 1676a8b2f828SGavin Shan return 0; 1677a8b2f828SGavin Shan } 1678a8b2f828SGavin Shan 167993eacd94SOliver O'Halloran static int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1680a8b2f828SGavin Shan { 1681a8b2f828SGavin Shan /* Allocate PCI data */ 16828cd6aaccSOliver O'Halloran add_sriov_vf_pdns(pdev); 1683781a868fSWei Yang 1684ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1685a8b2f828SGavin Shan } 1686a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1687a8b2f828SGavin Shan 16880a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1689184cd4a3SBenjamin Herrenschmidt { 16905609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1691b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1692959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1693184cd4a3SBenjamin Herrenschmidt 1694dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */ 1695dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1696dc3d8f85SOliver O'Halloran if (!pe) { 1697dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1698dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn)) 1699959c9bddSGavin Shan return; 1700184cd4a3SBenjamin Herrenschmidt 1701dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus); 1702dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1703dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1704dc3d8f85SOliver O'Halloran 1705dc3d8f85SOliver O'Halloran 1706dc3d8f85SOliver O'Halloran /* 1707dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly 1708dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device. 1709dc3d8f85SOliver O'Halloran */ 1710dc3d8f85SOliver O'Halloran if (WARN_ON(!pe)) 1711dc3d8f85SOliver O'Halloran return; 1712dc3d8f85SOliver O'Halloran } else { 1713dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1714dc3d8f85SOliver O'Halloran } 1715dc3d8f85SOliver O'Halloran 1716dc3d8f85SOliver O'Halloran if (pdn) 1717dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number; 1718dc3d8f85SOliver O'Halloran pe->device_count++; 1719dc3d8f85SOliver O'Halloran 1720cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17210617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1722b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 172384d8cc07SOliver O'Halloran 172484d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */ 172584d8cc07SOliver O'Halloran if (pe->table_group.group) 172684d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev); 1727184cd4a3SBenjamin Herrenschmidt } 1728184cd4a3SBenjamin Herrenschmidt 17298e3f1b1dSRussell Currey /* 17308e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17318e3f1b1dSRussell Currey * 17328e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17338e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17348e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17358e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17368e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17378e3f1b1dSRussell Currey * devices in TVE#0. 17388e3f1b1dSRussell Currey * 17398e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17408e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17418e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17428e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17438e3f1b1dSRussell Currey * 17448e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17458e3f1b1dSRussell Currey */ 17468e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17478e3f1b1dSRussell Currey { 17488e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17498e3f1b1dSRussell Currey struct page *table_pages; 17508e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 17518e3f1b1dSRussell Currey __be64 *tces; 17528e3f1b1dSRussell Currey s64 rc; 17538e3f1b1dSRussell Currey 17548e3f1b1dSRussell Currey /* 17558e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 17568e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 17578e3f1b1dSRussell Currey */ 17588e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 17598e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 17608e3f1b1dSRussell Currey table_size = tce_count << 3; 17618e3f1b1dSRussell Currey 17628e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 17638e3f1b1dSRussell Currey table_size = PAGE_SIZE; 17648e3f1b1dSRussell Currey 17658e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 17668e3f1b1dSRussell Currey get_order(table_size)); 17678e3f1b1dSRussell Currey if (!table_pages) 17688e3f1b1dSRussell Currey goto err; 17698e3f1b1dSRussell Currey 17708e3f1b1dSRussell Currey tces = page_address(table_pages); 17718e3f1b1dSRussell Currey if (!tces) 17728e3f1b1dSRussell Currey goto err; 17738e3f1b1dSRussell Currey 17748e3f1b1dSRussell Currey memset(tces, 0, table_size); 17758e3f1b1dSRussell Currey 17768e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 17778e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 17788e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 17798e3f1b1dSRussell Currey } 17808e3f1b1dSRussell Currey 17818e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 17828e3f1b1dSRussell Currey pe->pe_number, 17838e3f1b1dSRussell Currey /* reconfigure window 0 */ 17848e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 17858e3f1b1dSRussell Currey 1, 17868e3f1b1dSRussell Currey __pa(tces), 17878e3f1b1dSRussell Currey table_size, 17888e3f1b1dSRussell Currey 1 << tce_order); 17898e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 17908e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 17918e3f1b1dSRussell Currey return 0; 17928e3f1b1dSRussell Currey } 17938e3f1b1dSRussell Currey err: 17948e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 17958e3f1b1dSRussell Currey return -EIO; 17968e3f1b1dSRussell Currey } 17978e3f1b1dSRussell Currey 17982d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 17992d6ad41bSChristoph Hellwig u64 dma_mask) 1800cd15b048SBenjamin Herrenschmidt { 18015609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1802cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1803cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1804cd15b048SBenjamin Herrenschmidt 1805cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1806b511cdd1SAlexey Kardashevskiy return false; 1807cd15b048SBenjamin Herrenschmidt 1808cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1809cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 18102d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 18112d6ad41bSChristoph Hellwig if (dma_mask >= top) 18122d6ad41bSChristoph Hellwig return true; 1813cd15b048SBenjamin Herrenschmidt } 1814cd15b048SBenjamin Herrenschmidt 18158e3f1b1dSRussell Currey /* 18168e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18178e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18188e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18198e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18208e3f1b1dSRussell Currey */ 18218e3f1b1dSRussell Currey if (dma_mask >> 32 && 18228e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1823661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1824661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 18258e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18268e3f1b1dSRussell Currey /* Configure the bypass mode */ 18272d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18288e3f1b1dSRussell Currey if (rc) 1829b511cdd1SAlexey Kardashevskiy return false; 18308e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18310617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 18322d6ad41bSChristoph Hellwig return true; 1833cd15b048SBenjamin Herrenschmidt } 1834cd15b048SBenjamin Herrenschmidt 18352d6ad41bSChristoph Hellwig return false; 1836fe7e85c6SGavin Shan } 1837fe7e85c6SGavin Shan 1838fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1839fd141d1aSBenjamin Herrenschmidt bool real_mode) 1840fd141d1aSBenjamin Herrenschmidt { 1841fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1842fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1843fd141d1aSBenjamin Herrenschmidt } 1844fd141d1aSBenjamin Herrenschmidt 1845a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1846decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 18474cce9550SGavin Shan { 18480eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 18490eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 18500eaf4defSAlexey Kardashevskiy next); 18510eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1852b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1853fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 18544cce9550SGavin Shan unsigned long start, end, inc; 18554cce9550SGavin Shan 1856decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1857decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1858decbda25SAlexey Kardashevskiy npages - 1); 18594cce9550SGavin Shan 18604cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 18614cce9550SGavin Shan start |= (1ull << 63); 18624cce9550SGavin Shan end |= (1ull << 63); 18634cce9550SGavin Shan inc = 16; 18644cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 18654cce9550SGavin Shan 18664cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 18674cce9550SGavin Shan while (start <= end) { 18688e0a1611SAlexey Kardashevskiy if (rm) 1869001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 18708e0a1611SAlexey Kardashevskiy else 1871001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1872001ff2eeSMichael Ellerman 18734cce9550SGavin Shan start += inc; 18744cce9550SGavin Shan } 18754cce9550SGavin Shan 18764cce9550SGavin Shan /* 18774cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 18784cce9550SGavin Shan * and we don't care on free() 18794cce9550SGavin Shan */ 18804cce9550SGavin Shan } 18814cce9550SGavin Shan 1882decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1883decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1884decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 188500085f1eSKrzysztof Kozlowski unsigned long attrs) 1886decbda25SAlexey Kardashevskiy { 1887decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1888decbda25SAlexey Kardashevskiy attrs); 1889decbda25SAlexey Kardashevskiy 189008acce1cSBenjamin Herrenschmidt if (!ret) 1891a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1892decbda25SAlexey Kardashevskiy 1893decbda25SAlexey Kardashevskiy return ret; 1894decbda25SAlexey Kardashevskiy } 1895decbda25SAlexey Kardashevskiy 189605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 189735872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 189835872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 189935872480SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 190035872480SAlexey Kardashevskiy bool realmode) 190105c6cfb9SAlexey Kardashevskiy { 190235872480SAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1903a540aa56SAlexey Kardashevskiy } 190405c6cfb9SAlexey Kardashevskiy #endif 190505c6cfb9SAlexey Kardashevskiy 1906decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1907decbda25SAlexey Kardashevskiy long npages) 1908decbda25SAlexey Kardashevskiy { 1909decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1910decbda25SAlexey Kardashevskiy 1911a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1912decbda25SAlexey Kardashevskiy } 1913decbda25SAlexey Kardashevskiy 1914da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1915decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 191605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 191735872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 191835872480SAlexey Kardashevskiy .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1919090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 192005c6cfb9SAlexey Kardashevskiy #endif 1921decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1922da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1923da004c36SAlexey Kardashevskiy }; 1924da004c36SAlexey Kardashevskiy 1925a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1926a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1927a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1928bef9253fSAlexey Kardashevskiy 19296b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 19300bbcdb43SAlexey Kardashevskiy { 1931fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1932a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 19330bbcdb43SAlexey Kardashevskiy 19340bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 19350bbcdb43SAlexey Kardashevskiy if (rm) 1936001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 19370bbcdb43SAlexey Kardashevskiy else 1938001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 19390bbcdb43SAlexey Kardashevskiy } 19400bbcdb43SAlexey Kardashevskiy 1941a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 19425780fb04SAlexey Kardashevskiy { 19435780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1944fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1945a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 19465780fb04SAlexey Kardashevskiy 19475780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1948001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 19495780fb04SAlexey Kardashevskiy } 19505780fb04SAlexey Kardashevskiy 1951fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1952fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1953fd141d1aSBenjamin Herrenschmidt unsigned long npages) 19544cce9550SGavin Shan { 19554d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19564cce9550SGavin Shan unsigned long start, end, inc; 19574cce9550SGavin Shan 19584cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1959a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1960fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 19614cce9550SGavin Shan end = start; 19624cce9550SGavin Shan 19634cce9550SGavin Shan /* Figure out the start, end and step */ 1964decbda25SAlexey Kardashevskiy start |= (index << shift); 1965decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1966b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 19674cce9550SGavin Shan mb(); 19684cce9550SGavin Shan 19694cce9550SGavin Shan while (start <= end) { 19708e0a1611SAlexey Kardashevskiy if (rm) 1971001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19728e0a1611SAlexey Kardashevskiy else 1973001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 19744cce9550SGavin Shan start += inc; 19754cce9550SGavin Shan } 19764cce9550SGavin Shan } 19774cce9550SGavin Shan 1978f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1979f0228c41SBenjamin Herrenschmidt { 1980f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1981f0228c41SBenjamin Herrenschmidt 1982f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1983f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1984f0228c41SBenjamin Herrenschmidt else 1985f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1986f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1987f0228c41SBenjamin Herrenschmidt } 1988f0228c41SBenjamin Herrenschmidt 1989e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1990e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1991e57080f1SAlexey Kardashevskiy { 1992e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1993e57080f1SAlexey Kardashevskiy 1994a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1995e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1996e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1997f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1998f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1999f0228c41SBenjamin Herrenschmidt 2000616badd2SAlistair Popple /* 2001616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2002616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2003616badd2SAlistair Popple * should go via the OPAL call. 2004616badd2SAlistair Popple */ 2005616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 20060bbcdb43SAlexey Kardashevskiy /* 20070bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 20080bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 20090bbcdb43SAlexey Kardashevskiy * the entire cache for it. 20100bbcdb43SAlexey Kardashevskiy */ 2011f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20125d2aa710SAlistair Popple continue; 20135d2aa710SAlistair Popple } 2014f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2015f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 201685674868SAlexey Kardashevskiy index, npages); 2017f0228c41SBenjamin Herrenschmidt else 2018f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2019f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2020f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2021f0228c41SBenjamin Herrenschmidt index << shift, npages); 2022e57080f1SAlexey Kardashevskiy } 2023e57080f1SAlexey Kardashevskiy } 2024e57080f1SAlexey Kardashevskiy 20256b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20266b3d12a9SAlistair Popple { 20276b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 20286b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20296b3d12a9SAlistair Popple else 20306b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 20316b3d12a9SAlistair Popple } 20326b3d12a9SAlistair Popple 2033decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2034decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2035decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 203600085f1eSKrzysztof Kozlowski unsigned long attrs) 20374cce9550SGavin Shan { 2038decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2039decbda25SAlexey Kardashevskiy attrs); 20404cce9550SGavin Shan 204108acce1cSBenjamin Herrenschmidt if (!ret) 2042decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2043decbda25SAlexey Kardashevskiy 2044decbda25SAlexey Kardashevskiy return ret; 2045decbda25SAlexey Kardashevskiy } 2046decbda25SAlexey Kardashevskiy 2047decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2048decbda25SAlexey Kardashevskiy long npages) 2049decbda25SAlexey Kardashevskiy { 2050decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2051decbda25SAlexey Kardashevskiy 2052decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 20534cce9550SGavin Shan } 20544cce9550SGavin Shan 2055da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2056decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 205705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 205835872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 205935872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 2060090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 206105c6cfb9SAlexey Kardashevskiy #endif 2062decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2063da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2064da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 2065da004c36SAlexey Kardashevskiy }; 2066da004c36SAlexey Kardashevskiy 2067801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2068801846d1SGavin Shan { 2069801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2070801846d1SGavin Shan 2071801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2072801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2073801846d1SGavin Shan */ 2074801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2075801846d1SGavin Shan return 0; 2076801846d1SGavin Shan 2077801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2078801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2079801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2080801846d1SGavin Shan *weight += 3; 2081801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2082801846d1SGavin Shan *weight += 15; 2083801846d1SGavin Shan else 2084801846d1SGavin Shan *weight += 10; 2085801846d1SGavin Shan 2086801846d1SGavin Shan return 0; 2087801846d1SGavin Shan } 2088801846d1SGavin Shan 2089801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2090801846d1SGavin Shan { 2091801846d1SGavin Shan unsigned int weight = 0; 2092801846d1SGavin Shan 2093801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2094801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2095801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2096801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2097801846d1SGavin Shan return weight; 2098801846d1SGavin Shan } 2099801846d1SGavin Shan #endif 2100801846d1SGavin Shan 2101801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2102801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2103801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2104801846d1SGavin Shan struct pci_dev *pdev; 2105801846d1SGavin Shan 2106801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2107801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2108801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2109801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2110801846d1SGavin Shan } 2111801846d1SGavin Shan 2112801846d1SGavin Shan return weight; 2113801846d1SGavin Shan } 2114801846d1SGavin Shan 2115b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 21162b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2117184cd4a3SBenjamin Herrenschmidt { 2118184cd4a3SBenjamin Herrenschmidt 2119184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2120184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 21212b923ed1SGavin Shan unsigned int weight, total_weight = 0; 21222b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2123184cd4a3SBenjamin Herrenschmidt int64_t rc; 2124184cd4a3SBenjamin Herrenschmidt void *addr; 2125184cd4a3SBenjamin Herrenschmidt 2126184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2127184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2128184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 21292b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 21302b923ed1SGavin Shan if (!weight) 21312b923ed1SGavin Shan return; 2132184cd4a3SBenjamin Herrenschmidt 21332b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 21342b923ed1SGavin Shan &total_weight); 21352b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 21362b923ed1SGavin Shan if (!segs) 21372b923ed1SGavin Shan segs = 1; 21382b923ed1SGavin Shan 21392b923ed1SGavin Shan /* 21402b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 21412b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 21422b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 21432b923ed1SGavin Shan * is allocated successfully. 21442b923ed1SGavin Shan */ 21452b923ed1SGavin Shan do { 21462b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 21472b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 21482b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 21492b923ed1SGavin Shan IODA_INVALID_PE) 21502b923ed1SGavin Shan avail++; 21512b923ed1SGavin Shan } 21522b923ed1SGavin Shan 21532b923ed1SGavin Shan if (avail == segs) 21542b923ed1SGavin Shan goto found; 21552b923ed1SGavin Shan } 21562b923ed1SGavin Shan } while (--segs); 21572b923ed1SGavin Shan 21582b923ed1SGavin Shan if (!segs) { 21592b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 21602b923ed1SGavin Shan return; 21612b923ed1SGavin Shan } 21622b923ed1SGavin Shan 21632b923ed1SGavin Shan found: 21640eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 216582eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 216682eae1afSAlexey Kardashevskiy return; 216782eae1afSAlexey Kardashevskiy 2168b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2169b348aa65SAlexey Kardashevskiy pe->pe_number); 21700eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2171c5773822SAlexey Kardashevskiy 2172184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 21732b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 21742b923ed1SGavin Shan weight, total_weight, base, segs); 2175184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2176acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2177acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2178184cd4a3SBenjamin Herrenschmidt 2179184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2180184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2181184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2182184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2183acce971cSGavin Shan * 2184acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2185acce971cSGavin Shan * bytes 2186184cd4a3SBenjamin Herrenschmidt */ 2187acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2188184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2189acce971cSGavin Shan get_order(tce32_segsz * segs)); 2190184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2191184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2192184cd4a3SBenjamin Herrenschmidt goto fail; 2193184cd4a3SBenjamin Herrenschmidt } 2194184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2195acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2196184cd4a3SBenjamin Herrenschmidt 2197184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2198184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2199184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2200184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2201184cd4a3SBenjamin Herrenschmidt base + i, 1, 2202acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2203acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2204184cd4a3SBenjamin Herrenschmidt if (rc) { 22051e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 22061e496391SJoe Perches rc); 2207184cd4a3SBenjamin Herrenschmidt goto fail; 2208184cd4a3SBenjamin Herrenschmidt } 2209184cd4a3SBenjamin Herrenschmidt } 2210184cd4a3SBenjamin Herrenschmidt 22112b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 22122b923ed1SGavin Shan for (i = base; i < base + segs; i++) 22132b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 22142b923ed1SGavin Shan 2215184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2216acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2217acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2218acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2219184cd4a3SBenjamin Herrenschmidt 2220da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 22214793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 22224793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2223201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, phb->hose->node, 0, 0); 2224184cd4a3SBenjamin Herrenschmidt 2225184cd4a3SBenjamin Herrenschmidt return; 2226184cd4a3SBenjamin Herrenschmidt fail: 2227184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2228184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2229acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 22300eaf4defSAlexey Kardashevskiy if (tbl) { 22310eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2232e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 22330eaf4defSAlexey Kardashevskiy } 2234184cd4a3SBenjamin Herrenschmidt } 2235184cd4a3SBenjamin Herrenschmidt 223643cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 223743cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 223843cb60abSAlexey Kardashevskiy { 223943cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 224043cb60abSAlexey Kardashevskiy table_group); 224143cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 224243cb60abSAlexey Kardashevskiy int64_t rc; 2243bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2244bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 224543cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 224643cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 224743cb60abSAlexey Kardashevskiy 22481e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 22491e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 225043cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 225143cb60abSAlexey Kardashevskiy 225243cb60abSAlexey Kardashevskiy /* 225343cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 225443cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 225543cb60abSAlexey Kardashevskiy */ 225643cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 225743cb60abSAlexey Kardashevskiy pe->pe_number, 22584793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2259bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 226043cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2261bbb845c4SAlexey Kardashevskiy size << 3, 226243cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 226343cb60abSAlexey Kardashevskiy if (rc) { 22641e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 226543cb60abSAlexey Kardashevskiy return rc; 226643cb60abSAlexey Kardashevskiy } 226743cb60abSAlexey Kardashevskiy 226843cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 226943cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2270ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 227143cb60abSAlexey Kardashevskiy 227243cb60abSAlexey Kardashevskiy return 0; 227343cb60abSAlexey Kardashevskiy } 227443cb60abSAlexey Kardashevskiy 2275c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2276cd15b048SBenjamin Herrenschmidt { 2277cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2278cd15b048SBenjamin Herrenschmidt int64_t rc; 2279cd15b048SBenjamin Herrenschmidt 2280cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2281cd15b048SBenjamin Herrenschmidt if (enable) { 2282cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2283cd15b048SBenjamin Herrenschmidt 2284cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2285cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2286cd15b048SBenjamin Herrenschmidt pe->pe_number, 2287cd15b048SBenjamin Herrenschmidt window_id, 2288cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2289cd15b048SBenjamin Herrenschmidt top); 2290cd15b048SBenjamin Herrenschmidt } else { 2291cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2292cd15b048SBenjamin Herrenschmidt pe->pe_number, 2293cd15b048SBenjamin Herrenschmidt window_id, 2294cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2295cd15b048SBenjamin Herrenschmidt 0); 2296cd15b048SBenjamin Herrenschmidt } 2297cd15b048SBenjamin Herrenschmidt if (rc) 2298cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2299cd15b048SBenjamin Herrenschmidt else 2300cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2301cd15b048SBenjamin Herrenschmidt } 2302cd15b048SBenjamin Herrenschmidt 23034793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 23044793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2305090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 23064793d65dSAlexey Kardashevskiy { 23074793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 23084793d65dSAlexey Kardashevskiy table_group); 23094793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 23104793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 23114793d65dSAlexey Kardashevskiy long ret; 23124793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 23134793d65dSAlexey Kardashevskiy 23144793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 23154793d65dSAlexey Kardashevskiy if (!tbl) 23164793d65dSAlexey Kardashevskiy return -ENOMEM; 23174793d65dSAlexey Kardashevskiy 231811edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 231911edf116SAlexey Kardashevskiy 23204793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 23214793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 2322090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 23234793d65dSAlexey Kardashevskiy if (ret) { 2324e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23254793d65dSAlexey Kardashevskiy return ret; 23264793d65dSAlexey Kardashevskiy } 23274793d65dSAlexey Kardashevskiy 23284793d65dSAlexey Kardashevskiy *ptbl = tbl; 23294793d65dSAlexey Kardashevskiy 23304793d65dSAlexey Kardashevskiy return 0; 23314793d65dSAlexey Kardashevskiy } 23324793d65dSAlexey Kardashevskiy 233346d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 233446d3e1e1SAlexey Kardashevskiy { 233546d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 233646d3e1e1SAlexey Kardashevskiy long rc; 2337201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 233846d3e1e1SAlexey Kardashevskiy 2339bb005455SNishanth Aravamudan /* 2340fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2341fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2342fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2343fa144869SNishanth Aravamudan */ 2344fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2345fa144869SNishanth Aravamudan 2346fa144869SNishanth Aravamudan /* 2347bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2348bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2349bb005455SNishanth Aravamudan * cause errors later. 2350bb005455SNishanth Aravamudan */ 2351201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 2352bb005455SNishanth Aravamudan 2353201ed7f3SAlexey Kardashevskiy /* 2354201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 2355201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 2356201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 2357201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 2358201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 2359201ed7f3SAlexey Kardashevskiy */ 2360201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 2361201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 2362201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 2363201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 2364201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 2365201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 2366201ed7f3SAlexey Kardashevskiy 2367201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 2368201ed7f3SAlexey Kardashevskiy levels += 1; 2369201ed7f3SAlexey Kardashevskiy /* 2370201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 2371201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 2372201ed7f3SAlexey Kardashevskiy */ 2373201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 2374201ed7f3SAlexey Kardashevskiy 2375201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 2376201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 237746d3e1e1SAlexey Kardashevskiy if (rc) { 237846d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 237946d3e1e1SAlexey Kardashevskiy rc); 238046d3e1e1SAlexey Kardashevskiy return rc; 238146d3e1e1SAlexey Kardashevskiy } 238246d3e1e1SAlexey Kardashevskiy 2383201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 2384201ed7f3SAlexey Kardashevskiy res_start = 0; 2385201ed7f3SAlexey Kardashevskiy res_end = 0; 2386201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 2387201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 2388201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 2389201ed7f3SAlexey Kardashevskiy } 2390201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end); 239146d3e1e1SAlexey Kardashevskiy 239246d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 239346d3e1e1SAlexey Kardashevskiy if (rc) { 239446d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 239546d3e1e1SAlexey Kardashevskiy rc); 2396e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 239746d3e1e1SAlexey Kardashevskiy return rc; 239846d3e1e1SAlexey Kardashevskiy } 239946d3e1e1SAlexey Kardashevskiy 240046d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 240146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 240246d3e1e1SAlexey Kardashevskiy 24035636427dSAlexey Kardashevskiy /* 24045636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 24055636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 24065636427dSAlexey Kardashevskiy * from VFIO so do it here. 24075636427dSAlexey Kardashevskiy */ 24085636427dSAlexey Kardashevskiy if (pe->pdev) 24095636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 24105636427dSAlexey Kardashevskiy 241146d3e1e1SAlexey Kardashevskiy return 0; 241246d3e1e1SAlexey Kardashevskiy } 241346d3e1e1SAlexey Kardashevskiy 2414b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2415b5926430SAlexey Kardashevskiy int num) 2416b5926430SAlexey Kardashevskiy { 2417b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2418b5926430SAlexey Kardashevskiy table_group); 2419b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2420b5926430SAlexey Kardashevskiy long ret; 2421b5926430SAlexey Kardashevskiy 2422b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2423b5926430SAlexey Kardashevskiy 2424b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2425b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2426b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2427b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2428b5926430SAlexey Kardashevskiy if (ret) 2429b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2430b5926430SAlexey Kardashevskiy else 2431ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2432b5926430SAlexey Kardashevskiy 2433b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2434b5926430SAlexey Kardashevskiy 2435b5926430SAlexey Kardashevskiy return ret; 2436b5926430SAlexey Kardashevskiy } 2437b5926430SAlexey Kardashevskiy 2438f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 24390bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 244000547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 244100547193SAlexey Kardashevskiy { 244200547193SAlexey Kardashevskiy unsigned long bytes = 0; 244300547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 244400547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 244500547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 244600547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 244700547193SAlexey Kardashevskiy unsigned long direct_table_size; 244800547193SAlexey Kardashevskiy 244900547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 245000547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 245100547193SAlexey Kardashevskiy return 0; 245200547193SAlexey Kardashevskiy 245300547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 245400547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 245500547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 245600547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 245700547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 245800547193SAlexey Kardashevskiy 245900547193SAlexey Kardashevskiy for ( ; levels; --levels) { 2460b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 246100547193SAlexey Kardashevskiy 246200547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 246300547193SAlexey Kardashevskiy tce_table_size <<= 3; 2464e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2465e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 246600547193SAlexey Kardashevskiy } 246700547193SAlexey Kardashevskiy 2468090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2469090bad39SAlexey Kardashevskiy } 2470090bad39SAlexey Kardashevskiy 2471090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2472090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2473090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2474090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2475090bad39SAlexey Kardashevskiy { 247611f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 2477090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 247811f5acceSAlexey Kardashevskiy 247911f5acceSAlexey Kardashevskiy if (!ret) 248011f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 248111f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 248211f5acceSAlexey Kardashevskiy return ret; 248300547193SAlexey Kardashevskiy } 248400547193SAlexey Kardashevskiy 2485e3417faeSOliver O'Halloran static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 2486e3417faeSOliver O'Halloran { 2487e3417faeSOliver O'Halloran struct pci_dev *dev; 2488e3417faeSOliver O'Halloran 2489e3417faeSOliver O'Halloran list_for_each_entry(dev, &bus->devices, bus_list) { 2490e3417faeSOliver O'Halloran set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 2491e3417faeSOliver O'Halloran dev->dev.archdata.dma_offset = pe->tce_bypass_base; 2492e3417faeSOliver O'Halloran 2493e3417faeSOliver O'Halloran if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 2494e3417faeSOliver O'Halloran pnv_ioda_setup_bus_dma(pe, dev->subordinate); 2495e3417faeSOliver O'Halloran } 2496e3417faeSOliver O'Halloran } 2497e3417faeSOliver O'Halloran 2498f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2499cd15b048SBenjamin Herrenschmidt { 2500f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2501f87a8864SAlexey Kardashevskiy table_group); 250246d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 250346d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2504cd15b048SBenjamin Herrenschmidt 2505f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 250646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2507db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25085eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 25095636427dSAlexey Kardashevskiy else if (pe->pdev) 25105636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 2511e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2512cd15b048SBenjamin Herrenschmidt } 2513cd15b048SBenjamin Herrenschmidt 2514f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2515f87a8864SAlexey Kardashevskiy { 2516f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2517f87a8864SAlexey Kardashevskiy table_group); 2518f87a8864SAlexey Kardashevskiy 251946d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2520db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25215eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2522f87a8864SAlexey Kardashevskiy } 2523f87a8864SAlexey Kardashevskiy 2524f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 252500547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2526090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 25274793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 25284793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2529f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2530f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2531f87a8864SAlexey Kardashevskiy }; 2532f87a8864SAlexey Kardashevskiy #endif 2533f87a8864SAlexey Kardashevskiy 2534373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2535373f5657SGavin Shan struct pnv_ioda_pe *pe) 2536373f5657SGavin Shan { 2537373f5657SGavin Shan int64_t rc; 2538373f5657SGavin Shan 2539ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2540ccd1c191SGavin Shan return; 2541ccd1c191SGavin Shan 2542f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2543f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2544f87a8864SAlexey Kardashevskiy 2545373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2546373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2547aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2548373f5657SGavin Shan 2549e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 25504793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 25514793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 25524793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 25534793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 25544793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 25557ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2556e5aad1e6SAlexey Kardashevskiy 255746d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2558801846d1SGavin Shan if (rc) 255946d3e1e1SAlexey Kardashevskiy return; 256046d3e1e1SAlexey Kardashevskiy 25619b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 25629b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 25639b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 25649b9408c5SOliver O'Halloran pe->pe_number); 25659b9408c5SOliver O'Halloran #endif 2566373f5657SGavin Shan } 2567373f5657SGavin Shan 25684ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2569137436c9SGavin Shan { 2570137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2571137436c9SGavin Shan ioda.irq_chip); 2572137436c9SGavin Shan 25734ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 25744ee11c1aSSuresh Warrier } 25754ee11c1aSSuresh Warrier 25764ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 25774ee11c1aSSuresh Warrier { 25784ee11c1aSSuresh Warrier int64_t rc; 25794ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 25804ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 25814ee11c1aSSuresh Warrier 25824ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2583137436c9SGavin Shan WARN_ON_ONCE(rc); 2584137436c9SGavin Shan 2585137436c9SGavin Shan icp_native_eoi(d); 2586137436c9SGavin Shan } 2587137436c9SGavin Shan 2588fd9a1c26SIan Munsie 2589f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2590fd9a1c26SIan Munsie { 2591fd9a1c26SIan Munsie struct irq_data *idata; 2592fd9a1c26SIan Munsie struct irq_chip *ichip; 2593fd9a1c26SIan Munsie 2594fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2595fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2596fd9a1c26SIan Munsie return; 2597fd9a1c26SIan Munsie 2598fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2599fd9a1c26SIan Munsie /* 2600fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2601fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2602fd9a1c26SIan Munsie */ 2603fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2604fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2605fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2606fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2607fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2608fd9a1c26SIan Munsie } 2609fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2610fd9a1c26SIan Munsie } 2611fd9a1c26SIan Munsie 26124ee11c1aSSuresh Warrier /* 26134ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 26144ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 26154ee11c1aSSuresh Warrier */ 26164ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 26174ee11c1aSSuresh Warrier { 26184ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 26194ee11c1aSSuresh Warrier } 26204ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 26214ee11c1aSSuresh Warrier 2622184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2623137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2624137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2625184cd4a3SBenjamin Herrenschmidt { 2626184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2627184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 26283a1a4661SBenjamin Herrenschmidt __be32 data; 2629184cd4a3SBenjamin Herrenschmidt int rc; 2630184cd4a3SBenjamin Herrenschmidt 2631184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2632184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2633184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2634184cd4a3SBenjamin Herrenschmidt 2635184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2636184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2637184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2638184cd4a3SBenjamin Herrenschmidt 2639b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 264036074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2641b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2642b72c1f65SBenjamin Herrenschmidt 2643184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2644184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2645184cd4a3SBenjamin Herrenschmidt if (rc) { 2646184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2647184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2648184cd4a3SBenjamin Herrenschmidt return -EIO; 2649184cd4a3SBenjamin Herrenschmidt } 2650184cd4a3SBenjamin Herrenschmidt 2651184cd4a3SBenjamin Herrenschmidt if (is_64) { 26523a1a4661SBenjamin Herrenschmidt __be64 addr64; 26533a1a4661SBenjamin Herrenschmidt 2654184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2655184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2656184cd4a3SBenjamin Herrenschmidt if (rc) { 2657184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2658184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2659184cd4a3SBenjamin Herrenschmidt return -EIO; 2660184cd4a3SBenjamin Herrenschmidt } 26613a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 26623a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2663184cd4a3SBenjamin Herrenschmidt } else { 26643a1a4661SBenjamin Herrenschmidt __be32 addr32; 26653a1a4661SBenjamin Herrenschmidt 2666184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2667184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2668184cd4a3SBenjamin Herrenschmidt if (rc) { 2669184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2670184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2671184cd4a3SBenjamin Herrenschmidt return -EIO; 2672184cd4a3SBenjamin Herrenschmidt } 2673184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 26743a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2675184cd4a3SBenjamin Herrenschmidt } 26763a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2677184cd4a3SBenjamin Herrenschmidt 2678f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2679137436c9SGavin Shan 2680184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 26811f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2682184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2683184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2684184cd4a3SBenjamin Herrenschmidt 2685184cd4a3SBenjamin Herrenschmidt return 0; 2686184cd4a3SBenjamin Herrenschmidt } 2687184cd4a3SBenjamin Herrenschmidt 2688184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2689184cd4a3SBenjamin Herrenschmidt { 2690fb1b55d6SGavin Shan unsigned int count; 2691184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2692184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2693184cd4a3SBenjamin Herrenschmidt if (!prop) { 2694184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2695184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2696184cd4a3SBenjamin Herrenschmidt } 2697184cd4a3SBenjamin Herrenschmidt if (!prop) 2698184cd4a3SBenjamin Herrenschmidt return; 2699184cd4a3SBenjamin Herrenschmidt 2700184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2701fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2702fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2703184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2704184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2705184cd4a3SBenjamin Herrenschmidt return; 2706184cd4a3SBenjamin Herrenschmidt } 2707fb1b55d6SGavin Shan 2708184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2709184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2710184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2711fb1b55d6SGavin Shan count, phb->msi_base); 2712184cd4a3SBenjamin Herrenschmidt } 2713184cd4a3SBenjamin Herrenschmidt 27146e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 27156e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 27166e628c7dSWei Yang { 27175609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2718f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 27196e628c7dSWei Yang struct resource *res; 27206e628c7dSWei Yang int i; 2721dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 27226e628c7dSWei Yang struct pci_dn *pdn; 27235b88ec22SWei Yang int mul, total_vfs; 27246e628c7dSWei Yang 27256e628c7dSWei Yang pdn = pci_get_pdn(pdev); 27266e628c7dSWei Yang pdn->vfs_expanded = 0; 2727ee8222feSWei Yang pdn->m64_single_mode = false; 27286e628c7dSWei Yang 27295b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 273092b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2731dfcc8d45SWei Yang total_vf_bar_sz = 0; 27325b88ec22SWei Yang 27335b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27345b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 27355b88ec22SWei Yang if (!res->flags || res->parent) 27365b88ec22SWei Yang continue; 2737b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 2738b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2739b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 27405b88ec22SWei Yang i, res); 2741b0331854SWei Yang goto truncate_iov; 27425b88ec22SWei Yang } 27435b88ec22SWei Yang 2744dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2745dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 27465b88ec22SWei Yang 2747f2dd0afeSWei Yang /* 2748f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2749f2dd0afeSWei Yang * power of two. 2750f2dd0afeSWei Yang * 2751f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2752f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2753f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2754f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2755f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2756f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2757f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2758f2dd0afeSWei Yang */ 2759dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 27605b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2761dfcc8d45SWei Yang dev_info(&pdev->dev, 2762dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2763dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2764ee8222feSWei Yang pdn->m64_single_mode = true; 27655b88ec22SWei Yang break; 27665b88ec22SWei Yang } 27675b88ec22SWei Yang } 27685b88ec22SWei Yang 27696e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27706e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 27716e628c7dSWei Yang if (!res->flags || res->parent) 27726e628c7dSWei Yang continue; 27736e628c7dSWei Yang 27746e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2775ee8222feSWei Yang /* 2776ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2777ee8222feSWei Yang * mode is 32MB. 2778ee8222feSWei Yang */ 2779ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2780ee8222feSWei Yang goto truncate_iov; 2781ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 27825b88ec22SWei Yang res->end = res->start + size * mul - 1; 27836e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 27846e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 27855b88ec22SWei Yang i, res, mul); 27866e628c7dSWei Yang } 27875b88ec22SWei Yang pdn->vfs_expanded = mul; 2788b0331854SWei Yang 2789b0331854SWei Yang return; 2790b0331854SWei Yang 2791b0331854SWei Yang truncate_iov: 2792b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2793b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2794b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2795b0331854SWei Yang res->flags = 0; 2796b0331854SWei Yang res->end = res->start - 1; 2797b0331854SWei Yang } 27986e628c7dSWei Yang } 2799965c94f3SOliver O'Halloran 2800965c94f3SOliver O'Halloran static void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) 2801965c94f3SOliver O'Halloran { 2802965c94f3SOliver O'Halloran if (WARN_ON(pci_dev_is_added(pdev))) 2803965c94f3SOliver O'Halloran return; 2804965c94f3SOliver O'Halloran 2805965c94f3SOliver O'Halloran if (pdev->is_virtfn) { 2806965c94f3SOliver O'Halloran struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev); 2807965c94f3SOliver O'Halloran 2808965c94f3SOliver O'Halloran /* 2809965c94f3SOliver O'Halloran * VF PEs are single-device PEs so their pdev pointer needs to 2810965c94f3SOliver O'Halloran * be set. The pdev doesn't exist when the PE is allocated (in 2811965c94f3SOliver O'Halloran * (pcibios_sriov_enable()) so we fix it up here. 2812965c94f3SOliver O'Halloran */ 2813965c94f3SOliver O'Halloran pe->pdev = pdev; 2814965c94f3SOliver O'Halloran WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); 2815965c94f3SOliver O'Halloran } else if (pdev->is_physfn) { 2816965c94f3SOliver O'Halloran /* 2817965c94f3SOliver O'Halloran * For PFs adjust their allocated IOV resources to match what 2818965c94f3SOliver O'Halloran * the PHB can support using it's M64 BAR table. 2819965c94f3SOliver O'Halloran */ 2820965c94f3SOliver O'Halloran pnv_pci_ioda_fixup_iov_resources(pdev); 2821965c94f3SOliver O'Halloran } 2822965c94f3SOliver O'Halloran } 28236e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 28246e628c7dSWei Yang 282523e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 282623e79425SGavin Shan struct resource *res) 282711685becSGavin Shan { 282823e79425SGavin Shan struct pnv_phb *phb = pe->phb; 282911685becSGavin Shan struct pci_bus_region region; 283023e79425SGavin Shan int index; 283123e79425SGavin Shan int64_t rc; 283211685becSGavin Shan 283323e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 283423e79425SGavin Shan return; 283511685becSGavin Shan 283611685becSGavin Shan if (res->flags & IORESOURCE_IO) { 283711685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 283811685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 283911685becSGavin Shan index = region.start / phb->ioda.io_segsize; 284011685becSGavin Shan 284192b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 284211685becSGavin Shan region.start <= region.end) { 284311685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 284411685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 284511685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 284611685becSGavin Shan if (rc != OPAL_SUCCESS) { 28471f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 284811685becSGavin Shan __func__, rc, index, pe->pe_number); 284911685becSGavin Shan break; 285011685becSGavin Shan } 285111685becSGavin Shan 285211685becSGavin Shan region.start += phb->ioda.io_segsize; 285311685becSGavin Shan index++; 285411685becSGavin Shan } 2855027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 28565958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 285711685becSGavin Shan region.start = res->start - 285823e79425SGavin Shan phb->hose->mem_offset[0] - 285911685becSGavin Shan phb->ioda.m32_pci_base; 286011685becSGavin Shan region.end = res->end - 286123e79425SGavin Shan phb->hose->mem_offset[0] - 286211685becSGavin Shan phb->ioda.m32_pci_base; 286311685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 286411685becSGavin Shan 286592b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 286611685becSGavin Shan region.start <= region.end) { 286711685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 286811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 286911685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 287011685becSGavin Shan if (rc != OPAL_SUCCESS) { 28711f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 287211685becSGavin Shan __func__, rc, index, pe->pe_number); 287311685becSGavin Shan break; 287411685becSGavin Shan } 287511685becSGavin Shan 287611685becSGavin Shan region.start += phb->ioda.m32_segsize; 287711685becSGavin Shan index++; 287811685becSGavin Shan } 287911685becSGavin Shan } 288011685becSGavin Shan } 288123e79425SGavin Shan 288223e79425SGavin Shan /* 288323e79425SGavin Shan * This function is supposed to be called on basis of PE from top 288423e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 288503671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 288623e79425SGavin Shan */ 288723e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 288823e79425SGavin Shan { 288969d733e7SGavin Shan struct pci_dev *pdev; 289023e79425SGavin Shan int i; 289123e79425SGavin Shan 289223e79425SGavin Shan /* 289323e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 289423e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 289523e79425SGavin Shan * be figured out later. 289623e79425SGavin Shan */ 289723e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 289823e79425SGavin Shan 289969d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 290069d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 290169d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 290269d733e7SGavin Shan 290369d733e7SGavin Shan /* 290469d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 290569d733e7SGavin Shan * windows of the child bridges should be mapped to 290669d733e7SGavin Shan * the PE as well. 290769d733e7SGavin Shan */ 290869d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 290969d733e7SGavin Shan continue; 291069d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 291169d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 291269d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 291369d733e7SGavin Shan } 291411685becSGavin Shan } 291511685becSGavin Shan 291698b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 291798b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 291898b665daSRussell Currey { 291922ba7289SOliver O'Halloran struct pnv_phb *phb = data; 292098b665daSRussell Currey s64 ret; 292198b665daSRussell Currey 292298b665daSRussell Currey /* Retrieve the diag data from firmware */ 29235cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 29245cb1f8fdSRussell Currey phb->diag_data_size); 292598b665daSRussell Currey if (ret != OPAL_SUCCESS) 292698b665daSRussell Currey return -EIO; 292798b665daSRussell Currey 292898b665daSRussell Currey /* Print the diag data to the kernel log */ 29295cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 293098b665daSRussell Currey return 0; 293198b665daSRussell Currey } 293298b665daSRussell Currey 2933bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2934bfa2325eSYueHaibing "%llu\n"); 293598b665daSRussell Currey 293618697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 293718697d2bSOliver O'Halloran { 293818697d2bSOliver O'Halloran struct pnv_phb *phb = data; 293918697d2bSOliver O'Halloran int pe_num; 294018697d2bSOliver O'Halloran 294118697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 294218697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 294318697d2bSOliver O'Halloran 294418697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 294518697d2bSOliver O'Halloran continue; 294618697d2bSOliver O'Halloran 294718697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 294818697d2bSOliver O'Halloran pe->rid, pe->device_count, 294918697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 295018697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 295118697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 295218697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 295318697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 295418697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 295518697d2bSOliver O'Halloran } 295618697d2bSOliver O'Halloran 295718697d2bSOliver O'Halloran return 0; 295818697d2bSOliver O'Halloran } 295918697d2bSOliver O'Halloran 296018697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 296118697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 296218697d2bSOliver O'Halloran 296398b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 296498b665daSRussell Currey 296537c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 296637c367f2SGavin Shan { 296737c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 296837c367f2SGavin Shan struct pci_controller *hose, *tmp; 296937c367f2SGavin Shan struct pnv_phb *phb; 297037c367f2SGavin Shan char name[16]; 297137c367f2SGavin Shan 297237c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 297337c367f2SGavin Shan phb = hose->private_data; 297437c367f2SGavin Shan 2975ccd1c191SGavin Shan /* Notify initialization of PHB done */ 2976ccd1c191SGavin Shan phb->initialized = 1; 2977ccd1c191SGavin Shan 297837c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 297937c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 298098b665daSRussell Currey 2981bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 298222ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 298318697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 298418697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 298537c367f2SGavin Shan } 298637c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 298737c367f2SGavin Shan } 298837c367f2SGavin Shan 2989db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 2990db217319SBenjamin Herrenschmidt { 2991db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 2992db217319SBenjamin Herrenschmidt struct pci_bus *child; 2993db217319SBenjamin Herrenschmidt 2994db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 2995db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 2996db217319SBenjamin Herrenschmidt return; 2997db217319SBenjamin Herrenschmidt 2998db217319SBenjamin Herrenschmidt /* 2999db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 3000db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 3001db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 3002db217319SBenjamin Herrenschmidt * fixed. 3003db217319SBenjamin Herrenschmidt */ 3004db217319SBenjamin Herrenschmidt if (dev) { 3005db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 3006db217319SBenjamin Herrenschmidt if (rc) 3007db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 3008db217319SBenjamin Herrenschmidt pci_set_master(dev); 3009db217319SBenjamin Herrenschmidt } 3010db217319SBenjamin Herrenschmidt 3011db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 3012db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 3013db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 3014db217319SBenjamin Herrenschmidt } 3015db217319SBenjamin Herrenschmidt 3016db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 3017db217319SBenjamin Herrenschmidt { 3018db217319SBenjamin Herrenschmidt struct pci_controller *hose; 3019db217319SBenjamin Herrenschmidt 3020db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 3021db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 3022db217319SBenjamin Herrenschmidt } 3023db217319SBenjamin Herrenschmidt 3024cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3025fb446ad0SGavin Shan { 302603b7bf34SOliver O'Halloran pnv_pci_ioda_setup_nvlink(); 302737c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 302837c367f2SGavin Shan 3029db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 3030db217319SBenjamin Herrenschmidt 3031e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3032b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3033e9cc17d4SGavin Shan #endif 3034fb446ad0SGavin Shan } 3035fb446ad0SGavin Shan 3036271fd03aSGavin Shan /* 3037271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3038271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3039271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3040271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3041271fd03aSGavin Shan * 1MiB for memory) will be returned. 3042271fd03aSGavin Shan * 3043271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3044271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3045271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3046271fd03aSGavin Shan * resources. 3047271fd03aSGavin Shan */ 3048271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3049271fd03aSGavin Shan unsigned long type) 3050271fd03aSGavin Shan { 30515609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 3052271fd03aSGavin Shan int num_pci_bridges = 0; 30535609ffddSOliver O'Halloran struct pci_dev *bridge; 3054271fd03aSGavin Shan 3055271fd03aSGavin Shan bridge = bus->self; 3056271fd03aSGavin Shan while (bridge) { 3057271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3058271fd03aSGavin Shan num_pci_bridges++; 3059271fd03aSGavin Shan if (num_pci_bridges >= 2) 3060271fd03aSGavin Shan return 1; 3061271fd03aSGavin Shan } 3062271fd03aSGavin Shan 3063271fd03aSGavin Shan bridge = bridge->bus->self; 3064271fd03aSGavin Shan } 3065271fd03aSGavin Shan 30665958d19aSBenjamin Herrenschmidt /* 30675958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 30685958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 30695958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 30705958d19aSBenjamin Herrenschmidt */ 3071b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3072262af557SGuo Chao return phb->ioda.m64_segsize; 3073271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3074271fd03aSGavin Shan return phb->ioda.m32_segsize; 3075271fd03aSGavin Shan 3076271fd03aSGavin Shan return phb->ioda.io_segsize; 3077271fd03aSGavin Shan } 3078271fd03aSGavin Shan 307940e2a47eSGavin Shan /* 308040e2a47eSGavin Shan * We are updating root port or the upstream port of the 308140e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 308240e2a47eSGavin Shan * to accommodate the changes on required resources during 308340e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 308440e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 308540e2a47eSGavin Shan * root port. 308640e2a47eSGavin Shan */ 308740e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 308840e2a47eSGavin Shan unsigned long type) 308940e2a47eSGavin Shan { 309040e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 309140e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 309240e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 309340e2a47eSGavin Shan struct resource *r, *w; 309440e2a47eSGavin Shan bool msi_region = false; 309540e2a47eSGavin Shan int i; 309640e2a47eSGavin Shan 309740e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 309840e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 309940e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 310040e2a47eSGavin Shan return; 310140e2a47eSGavin Shan 310240e2a47eSGavin Shan /* Fixup the resources */ 310340e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 310440e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 310540e2a47eSGavin Shan if (!r->flags || !r->parent) 310640e2a47eSGavin Shan continue; 310740e2a47eSGavin Shan 310840e2a47eSGavin Shan w = NULL; 310940e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 311040e2a47eSGavin Shan w = &hose->io_resource; 31115958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 311240e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 311340e2a47eSGavin Shan phb->ioda.m64_segsize) 311440e2a47eSGavin Shan w = &hose->mem_resources[1]; 311540e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 311640e2a47eSGavin Shan w = &hose->mem_resources[0]; 311740e2a47eSGavin Shan msi_region = true; 311840e2a47eSGavin Shan } 311940e2a47eSGavin Shan 312040e2a47eSGavin Shan r->start = w->start; 312140e2a47eSGavin Shan r->end = w->end; 312240e2a47eSGavin Shan 312340e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 312440e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 312540e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 312640e2a47eSGavin Shan * 312740e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 312840e2a47eSGavin Shan * 32-bits bridge window. 312940e2a47eSGavin Shan */ 313040e2a47eSGavin Shan if (msi_region) { 313140e2a47eSGavin Shan r->end += 0x10000; 313240e2a47eSGavin Shan r->end -= 0x100000; 313340e2a47eSGavin Shan } 313440e2a47eSGavin Shan } 313540e2a47eSGavin Shan } 313640e2a47eSGavin Shan 3137dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus) 3138ccd1c191SGavin Shan { 31395609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 3140ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3141ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3142dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3143ccd1c191SGavin Shan 3144dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n"); 314540e2a47eSGavin Shan 3146ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 31476ae8aedfSOliver O'Halloran if (WARN_ON(list_empty(&bus->devices))) 3148ccd1c191SGavin Shan return; 3149ccd1c191SGavin Shan 3150ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3151a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 3152ccd1c191SGavin Shan 3153ccd1c191SGavin Shan /* 3154ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3155ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3156ccd1c191SGavin Shan * not allocate resources again. 3157ccd1c191SGavin Shan */ 3158ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3159ccd1c191SGavin Shan if (!pe) 3160ccd1c191SGavin Shan return; 3161ccd1c191SGavin Shan 3162ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3163ccd1c191SGavin Shan switch (phb->type) { 3164ccd1c191SGavin Shan case PNV_PHB_IODA1: 3165ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3166ccd1c191SGavin Shan break; 3167ccd1c191SGavin Shan case PNV_PHB_IODA2: 3168ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3169ccd1c191SGavin Shan break; 3170ccd1c191SGavin Shan default: 31711f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3172ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3173ccd1c191SGavin Shan } 3174ccd1c191SGavin Shan } 3175ccd1c191SGavin Shan 317638274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 317738274637SYongji Xie { 317838274637SYongji Xie return PAGE_SIZE; 317938274637SYongji Xie } 318038274637SYongji Xie 31815350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 31825350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 31835350ab3fSWei Yang int resno) 31845350ab3fSWei Yang { 31855609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 31865350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 31877fbe7a93SWei Yang resource_size_t align; 31885350ab3fSWei Yang 31897fbe7a93SWei Yang /* 31907fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 31917fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 31927fbe7a93SWei Yang * BAR should be size aligned. 31937fbe7a93SWei Yang * 3194ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3195ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3196ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3197ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3198ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3199ee8222feSWei Yang * m64_segsize. 3200ee8222feSWei Yang * 32017fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 32027fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3203ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3204ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 32057fbe7a93SWei Yang */ 32065350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 32077fbe7a93SWei Yang if (!pdn->vfs_expanded) 32085350ab3fSWei Yang return align; 3209ee8222feSWei Yang if (pdn->m64_single_mode) 3210ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 32117fbe7a93SWei Yang 32127fbe7a93SWei Yang return pdn->vfs_expanded * align; 32135350ab3fSWei Yang } 32145350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 32155350ab3fSWei Yang 3216184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3217184cd4a3SBenjamin Herrenschmidt * assign a PE 3218184cd4a3SBenjamin Herrenschmidt */ 32198bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3220184cd4a3SBenjamin Herrenschmidt { 32215609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3222db1266c8SGavin Shan struct pci_dn *pdn; 3223184cd4a3SBenjamin Herrenschmidt 3224db1266c8SGavin Shan /* The function is probably called while the PEs have 3225db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3226db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3227db1266c8SGavin Shan * PEs isn't ready. 3228db1266c8SGavin Shan */ 3229db1266c8SGavin Shan if (!phb->initialized) 3230c88c2a18SDaniel Axtens return true; 3231db1266c8SGavin Shan 3232b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3233184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3234c88c2a18SDaniel Axtens return false; 3235db1266c8SGavin Shan 3236c88c2a18SDaniel Axtens return true; 3237184cd4a3SBenjamin Herrenschmidt } 3238184cd4a3SBenjamin Herrenschmidt 3239c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 3240c1a2feadSFrederic Barrat { 3241c1a2feadSFrederic Barrat struct pci_controller *hose = pci_bus_to_host(dev->bus); 3242c1a2feadSFrederic Barrat struct pnv_phb *phb = hose->private_data; 3243c1a2feadSFrederic Barrat struct pci_dn *pdn; 3244c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 3245c1a2feadSFrederic Barrat 3246c1a2feadSFrederic Barrat if (!phb->initialized) 3247c1a2feadSFrederic Barrat return true; 3248c1a2feadSFrederic Barrat 3249c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 3250c1a2feadSFrederic Barrat if (!pdn) 3251c1a2feadSFrederic Barrat return false; 3252c1a2feadSFrederic Barrat 3253c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 3254c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 3255c1a2feadSFrederic Barrat if (!pe) 3256c1a2feadSFrederic Barrat return false; 3257c1a2feadSFrederic Barrat } 3258c1a2feadSFrederic Barrat return true; 3259c1a2feadSFrederic Barrat } 3260c1a2feadSFrederic Barrat 3261c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3262c5f7700bSGavin Shan int num) 3263c5f7700bSGavin Shan { 3264c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3265c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3266c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3267c5f7700bSGavin Shan unsigned int idx; 3268c5f7700bSGavin Shan long rc; 3269c5f7700bSGavin Shan 3270c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3271c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3272c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3273c5f7700bSGavin Shan continue; 3274c5f7700bSGavin Shan 3275c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3276c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3277c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3278c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3279c5f7700bSGavin Shan rc, idx); 3280c5f7700bSGavin Shan return rc; 3281c5f7700bSGavin Shan } 3282c5f7700bSGavin Shan 3283c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3284c5f7700bSGavin Shan } 3285c5f7700bSGavin Shan 3286c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3287c5f7700bSGavin Shan return OPAL_SUCCESS; 3288c5f7700bSGavin Shan } 3289c5f7700bSGavin Shan 3290c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3291c5f7700bSGavin Shan { 3292c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3293c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3294c5f7700bSGavin Shan int64_t rc; 3295c5f7700bSGavin Shan 3296c5f7700bSGavin Shan if (!weight) 3297c5f7700bSGavin Shan return; 3298c5f7700bSGavin Shan 3299c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3300c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3301c5f7700bSGavin Shan return; 3302c5f7700bSGavin Shan 3303a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3304c5f7700bSGavin Shan if (pe->table_group.group) { 3305c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3306c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3307c5f7700bSGavin Shan } 3308c5f7700bSGavin Shan 3309c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3310e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3311c5f7700bSGavin Shan } 3312c5f7700bSGavin Shan 3313c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3314c5f7700bSGavin Shan { 3315c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3316c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3317c5f7700bSGavin Shan int64_t rc; 3318c5f7700bSGavin Shan 3319c5f7700bSGavin Shan if (!weight) 3320c5f7700bSGavin Shan return; 3321c5f7700bSGavin Shan 3322c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3323c5f7700bSGavin Shan if (rc) 33241e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 3325c5f7700bSGavin Shan 3326c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3327c5f7700bSGavin Shan if (pe->table_group.group) { 3328c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3329c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3330c5f7700bSGavin Shan } 3331c5f7700bSGavin Shan 3332e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3333c5f7700bSGavin Shan } 3334c5f7700bSGavin Shan 3335c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3336c5f7700bSGavin Shan unsigned short win, 3337c5f7700bSGavin Shan unsigned int *map) 3338c5f7700bSGavin Shan { 3339c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3340c5f7700bSGavin Shan int idx; 3341c5f7700bSGavin Shan int64_t rc; 3342c5f7700bSGavin Shan 3343c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3344c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3345c5f7700bSGavin Shan continue; 3346c5f7700bSGavin Shan 3347c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3348c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3349c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3350c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3351c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3352c5f7700bSGavin Shan else 3353c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3354c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3355c5f7700bSGavin Shan 3356c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 33571e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 3358c5f7700bSGavin Shan rc, win, idx); 3359c5f7700bSGavin Shan 3360c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3361c5f7700bSGavin Shan } 3362c5f7700bSGavin Shan } 3363c5f7700bSGavin Shan 3364c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3365c5f7700bSGavin Shan { 3366c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3367c5f7700bSGavin Shan 3368c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3369c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3370c5f7700bSGavin Shan phb->ioda.io_segmap); 3371c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3372c5f7700bSGavin Shan phb->ioda.m32_segmap); 3373c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3374c5f7700bSGavin Shan phb->ioda.m64_segmap); 3375c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3376c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3377c5f7700bSGavin Shan phb->ioda.m32_segmap); 3378c5f7700bSGavin Shan } 3379c5f7700bSGavin Shan } 3380c5f7700bSGavin Shan 3381c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3382c5f7700bSGavin Shan { 3383c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3384c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3385c5f7700bSGavin Shan 3386e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n"); 3387e5500ab6SOliver O'Halloran 338880f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 3389c5f7700bSGavin Shan list_del(&pe->list); 339080f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 339180f1ff83SFrederic Barrat 3392c5f7700bSGavin Shan switch (phb->type) { 3393c5f7700bSGavin Shan case PNV_PHB_IODA1: 3394c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3395c5f7700bSGavin Shan break; 3396c5f7700bSGavin Shan case PNV_PHB_IODA2: 3397c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3398c5f7700bSGavin Shan break; 3399f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 3400f724385fSFrederic Barrat break; 3401c5f7700bSGavin Shan default: 3402c5f7700bSGavin Shan WARN_ON(1); 3403c5f7700bSGavin Shan } 3404c5f7700bSGavin Shan 3405c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3406c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3407b314427aSGavin Shan 3408b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3409b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3410b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3411b314427aSGavin Shan list_del(&slave->list); 3412b314427aSGavin Shan pnv_ioda_free_pe(slave); 3413b314427aSGavin Shan } 3414b314427aSGavin Shan } 3415b314427aSGavin Shan 34166eaed166SGavin Shan /* 34176eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 34186eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 34196eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 34206eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 34216eaed166SGavin Shan */ 3422718d249aSOliver O'Halloran if (phb->ioda.root_pe_idx == pe->pe_number) 3423718d249aSOliver O'Halloran return; 3424718d249aSOliver O'Halloran 3425c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3426c5f7700bSGavin Shan } 3427c5f7700bSGavin Shan 3428c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3429c5f7700bSGavin Shan { 34305609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 3431c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3432c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3433c5f7700bSGavin Shan 3434c5f7700bSGavin Shan if (pdev->is_virtfn) 3435c5f7700bSGavin Shan return; 3436c5f7700bSGavin Shan 3437c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3438c5f7700bSGavin Shan return; 3439c5f7700bSGavin Shan 344029bf282dSGavin Shan /* 344129bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 344229bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 344329bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 344429bf282dSGavin Shan * device count is decreased on removing devices while failing to 344529bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 344629bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 344729bf282dSGavin Shan */ 3448c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 344929bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 345029bf282dSGavin Shan 3451c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3452c5f7700bSGavin Shan if (pe->device_count == 0) 3453c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3454c5f7700bSGavin Shan } 3455c5f7700bSGavin Shan 3456ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 3457ab7032e7SAlexey Kardashevskiy { 3458ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 3459ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 3460ab7032e7SAlexey Kardashevskiy 3461ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 3462ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 3463ab7032e7SAlexey Kardashevskiy } 3464ab7032e7SAlexey Kardashevskiy 34657a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 346673ed148aSBenjamin Herrenschmidt { 34677a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 34687a8e6bbfSMichael Neuling 3469d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 347073ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 347173ed148aSBenjamin Herrenschmidt } 347273ed148aSBenjamin Herrenschmidt 3473946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 3474946743d0SOliver O'Halloran { 34755609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 3476946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 3477946743d0SOliver O'Halloran 3478946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3479946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 3480946743d0SOliver O'Halloran continue; 3481946743d0SOliver O'Halloran 3482946743d0SOliver O'Halloran if (!pe->pbus) 3483946743d0SOliver O'Halloran continue; 3484946743d0SOliver O'Halloran 3485946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 3486946743d0SOliver O'Halloran pe->pbus = bus; 3487946743d0SOliver O'Halloran break; 3488946743d0SOliver O'Halloran } 3489946743d0SOliver O'Halloran } 3490946743d0SOliver O'Halloran } 3491946743d0SOliver O'Halloran 349292ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 34930a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 3494946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 34952d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 349692ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 349792ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 349892ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3499c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 350092ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3501dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources, 350292ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35037a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 350492ae0353SDaniel Axtens }; 350592ae0353SDaniel Axtens 35065d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 35075d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 35085d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 35095d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 35105d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 35115d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35125d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 3513ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 35145d2aa710SAlistair Popple }; 35155d2aa710SAlistair Popple 35167f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 3517c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 3518f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 35197f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 35207f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35217f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 35227f2c39e9SFrederic Barrat }; 35237f2c39e9SFrederic Barrat 3524e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3525e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3526184cd4a3SBenjamin Herrenschmidt { 3527184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3528184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 35292b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 35302b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3531718d249aSOliver O'Halloran struct pnv_ioda_pe *root_pe; 3532fd141d1aSBenjamin Herrenschmidt struct resource r; 3533c681b93cSAlistair Popple const __be64 *prop64; 35343a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3535f1b7cc3eSGavin Shan int len; 35363fa23ff8SGavin Shan unsigned int segno; 3537184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3538184cd4a3SBenjamin Herrenschmidt void *aux; 3539184cd4a3SBenjamin Herrenschmidt long rc; 3540184cd4a3SBenjamin Herrenschmidt 354108a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 354208a45b32SBenjamin Herrenschmidt return; 354308a45b32SBenjamin Herrenschmidt 3544b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3545184cd4a3SBenjamin Herrenschmidt 3546184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3547184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3548184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3549184cd4a3SBenjamin Herrenschmidt return; 3550184cd4a3SBenjamin Herrenschmidt } 3551184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3552184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3553184cd4a3SBenjamin Herrenschmidt 35547e1c4e27SMike Rapoport phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 35558a7f97b9SMike Rapoport if (!phb) 35568a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 35578a7f97b9SMike Rapoport sizeof(*phb)); 355858d714ecSGavin Shan 355958d714ecSGavin Shan /* Allocate PCI controller */ 3560184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 356158d714ecSGavin Shan if (!phb->hose) { 3562b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3563b7c670d6SRob Herring np); 3564e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3565184cd4a3SBenjamin Herrenschmidt return; 3566184cd4a3SBenjamin Herrenschmidt } 3567184cd4a3SBenjamin Herrenschmidt 3568184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3569f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3570f1b7cc3eSGavin Shan if (prop32 && len == 8) { 35713a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 35723a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3573f1b7cc3eSGavin Shan } else { 3574b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3575184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3576184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3577f1b7cc3eSGavin Shan } 3578184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3579e9cc17d4SGavin Shan phb->hub_id = hub_id; 3580184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3581aa0c033fSGavin Shan phb->type = ioda_type; 3582781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3583184cd4a3SBenjamin Herrenschmidt 3584cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3585cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3586cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3587f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3588aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 35895d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 35905d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3591616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3592616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3593cee72d5bSBenjamin Herrenschmidt else 3594cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3595cee72d5bSBenjamin Herrenschmidt 35965cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 35975cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 35985cb1f8fdSRussell Currey if (prop32) 35995cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 36005cb1f8fdSRussell Currey else 36015cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 36025cb1f8fdSRussell Currey 36037e1c4e27SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 36048a7f97b9SMike Rapoport if (!phb->diag_data) 36058a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 36068a7f97b9SMike Rapoport phb->diag_data_size); 36075cb1f8fdSRussell Currey 3608aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 36092f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3610184cd4a3SBenjamin Herrenschmidt 3611aa0c033fSGavin Shan /* Get registers */ 3612fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3613fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3614fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3615184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3616184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3617fd141d1aSBenjamin Herrenschmidt } 3618577c8c88SGavin Shan 3619184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 362092b8f137SGavin Shan phb->ioda.total_pe_num = 1; 362136954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 362236954dc7SGavin Shan if (prop32) 362392b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 362436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 362536954dc7SGavin Shan if (prop32) 362692b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3627262af557SGuo Chao 3628c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3629c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3630c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3631c127562aSGavin Shan 3632262af557SGuo Chao /* Parse 64-bit MMIO range */ 3633262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3634262af557SGuo Chao 3635184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3636aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3637184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3638184cd4a3SBenjamin Herrenschmidt 363992b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 36403fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3641184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 364292b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3643184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3644184cd4a3SBenjamin Herrenschmidt 36452b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 36462b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 36472b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 36482b923ed1SGavin Shan 3649c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3650b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 365192a86756SAlexey Kardashevskiy sizeof(unsigned long)); 365293289d8cSGavin Shan m64map_off = size; 365393289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3654184cd4a3SBenjamin Herrenschmidt m32map_off = size; 365592b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3656c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3657c35d2a8cSGavin Shan iomap_off = size; 365892b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 36592b923ed1SGavin Shan dma32map_off = size; 36602b923ed1SGavin Shan size += phb->ioda.dma32_count * 36612b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3662c35d2a8cSGavin Shan } 3663184cd4a3SBenjamin Herrenschmidt pemap_off = size; 366492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 36657e1c4e27SMike Rapoport aux = memblock_alloc(size, SMP_CACHE_BYTES); 36668a7f97b9SMike Rapoport if (!aux) 36678a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3668184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 366993289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3670184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 367193289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 367293289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 36733fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 367493289d8cSGavin Shan } 36753fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3676184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 36773fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 36783fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 36792b923ed1SGavin Shan 36802b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 36812b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 36822b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 36833fa23ff8SGavin Shan } 3684184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 368563803c39SGavin Shan 368663803c39SGavin Shan /* 368763803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 368863803c39SGavin Shan * M64 resources consumed by its child devices. To pick 368963803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 369063803c39SGavin Shan */ 369163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 369263803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 369363803c39SGavin Shan phb->ioda.root_pe_idx = 1; 369463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 369563803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 369663803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 369763803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 369863803c39SGavin Shan } else { 3699718d249aSOliver O'Halloran /* otherwise just allocate one */ 3700718d249aSOliver O'Halloran root_pe = pnv_ioda_alloc_pe(phb); 3701718d249aSOliver O'Halloran phb->ioda.root_pe_idx = root_pe->pe_number; 370263803c39SGavin Shan } 3703184cd4a3SBenjamin Herrenschmidt 3704184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3705781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3706184cd4a3SBenjamin Herrenschmidt 3707184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 37082b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3709acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3710184cd4a3SBenjamin Herrenschmidt 3711aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3712184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3713184cd4a3SBenjamin Herrenschmidt window_type, 3714184cd4a3SBenjamin Herrenschmidt window_num, 3715184cd4a3SBenjamin Herrenschmidt starting_real_address, 3716184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3717184cd4a3SBenjamin Herrenschmidt segment_size); 3718184cd4a3SBenjamin Herrenschmidt #endif 3719184cd4a3SBenjamin Herrenschmidt 3720262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 372192b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3722262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3723262af557SGuo Chao if (phb->ioda.m64_size) 3724262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3725262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3726262af557SGuo Chao if (phb->ioda.io_size) 3727262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3728184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3729184cd4a3SBenjamin Herrenschmidt 3730262af557SGuo Chao 3731184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 373249dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 373349dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 373449dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3735184cd4a3SBenjamin Herrenschmidt 3736184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3737184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3738184cd4a3SBenjamin Herrenschmidt 3739c40a4210SGavin Shan /* 3740c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3741c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3742c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3743c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3744c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3745184cd4a3SBenjamin Herrenschmidt */ 3746fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 37475d2aa710SAlistair Popple 37487f2c39e9SFrederic Barrat switch (phb->type) { 37497f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 37505d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 37517f2c39e9SFrederic Barrat break; 37527f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 37537f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 37547f2c39e9SFrederic Barrat break; 37557f2c39e9SFrederic Barrat default: 375692ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3757f9f83456SAlexey Kardashevskiy } 3758ad30cb99SMichael Ellerman 375938274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 376038274637SYongji Xie 37616e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 3762965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 37635350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3764988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3765988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3766ad30cb99SMichael Ellerman #endif 3767ad30cb99SMichael Ellerman 3768c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3769184cd4a3SBenjamin Herrenschmidt 3770184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3771d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3772184cd4a3SBenjamin Herrenschmidt if (rc) 3773f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3774361f2a2aSGavin Shan 37756060e9eaSAndrew Donnellan /* 37766060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3777361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3778361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 377945baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3780b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3781b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3782b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3783b174b4fbSOliver O'Halloran * boot. 3784361f2a2aSGavin Shan */ 3785b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3786361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3787cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3788cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3789361f2a2aSGavin Shan } 3790262af557SGuo Chao 37919e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 37929e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3793262af557SGuo Chao hose->mem_resources[1].flags = 0; 3794184cd4a3SBenjamin Herrenschmidt } 3795184cd4a3SBenjamin Herrenschmidt 379667975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3797aa0c033fSGavin Shan { 3798e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3799aa0c033fSGavin Shan } 3800aa0c033fSGavin Shan 38015d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 38025d2aa710SAlistair Popple { 38037f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 38045d2aa710SAlistair Popple } 38055d2aa710SAlistair Popple 38067f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 38077f2c39e9SFrederic Barrat { 38087f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3809184cd4a3SBenjamin Herrenschmidt } 3810184cd4a3SBenjamin Herrenschmidt 3811228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3812228c2f41SAndrew Donnellan { 38135609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3814228c2f41SAndrew Donnellan 3815228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3816228c2f41SAndrew Donnellan return; 3817228c2f41SAndrew Donnellan 3818228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3819228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3820228c2f41SAndrew Donnellan } 3821228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3822228c2f41SAndrew Donnellan 3823184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3824184cd4a3SBenjamin Herrenschmidt { 3825184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3826184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 3827184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3828184cd4a3SBenjamin Herrenschmidt 3829b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3830184cd4a3SBenjamin Herrenschmidt 3831184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3832184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3833184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3834184cd4a3SBenjamin Herrenschmidt return; 3835184cd4a3SBenjamin Herrenschmidt } 3836184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3837184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3838184cd4a3SBenjamin Herrenschmidt 3839184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3840184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3841184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3842184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3843184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3844184cd4a3SBenjamin Herrenschmidt } 3845184cd4a3SBenjamin Herrenschmidt } 3846