1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 2057c8a661SMike Rapoport #include <linux/memblock.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 25e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 264793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 27184cd4a3SBenjamin Herrenschmidt 28184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 33fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 38137436c9SGavin Shan #include <asm/xics.h> 397644d581SMichael Ellerman #include <asm/debugfs.h> 40262af557SGuo Chao #include <asm/firmware.h> 4180c49c7eSIan Munsie #include <asm/pnv-pci.h> 42aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4380c49c7eSIan Munsie 44ec249dd8SMichael Neuling #include <misc/cxl-base.h> 45184cd4a3SBenjamin Herrenschmidt 46184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 47184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4844bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 49184cd4a3SBenjamin Herrenschmidt 5099451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5199451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53781a868fSWei Yang 547f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 557f2c39e9SFrederic Barrat "NPU_OCAPI" }; 56aca6913fSAlexey Kardashevskiy 577d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 586d31c2faSJoe Perches const char *fmt, ...) 596d31c2faSJoe Perches { 606d31c2faSJoe Perches struct va_format vaf; 616d31c2faSJoe Perches va_list args; 626d31c2faSJoe Perches char pfix[32]; 63184cd4a3SBenjamin Herrenschmidt 646d31c2faSJoe Perches va_start(args, fmt); 656d31c2faSJoe Perches 666d31c2faSJoe Perches vaf.fmt = fmt; 676d31c2faSJoe Perches vaf.va = &args; 686d31c2faSJoe Perches 69781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 706d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 71781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 726d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 736d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 74781a868fSWei Yang #ifdef CONFIG_PCI_IOV 75781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 76781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 77781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 78781a868fSWei Yang (pe->rid & 0xff00) >> 8, 79781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 80781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 816d31c2faSJoe Perches 821f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 836d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 846d31c2faSJoe Perches 856d31c2faSJoe Perches va_end(args); 866d31c2faSJoe Perches } 876d31c2faSJoe Perches 884e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8945baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 904e287840SThadeu Lima de Souza Cascardo 914e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 924e287840SThadeu Lima de Souza Cascardo { 934e287840SThadeu Lima de Souza Cascardo if (!str) 944e287840SThadeu Lima de Souza Cascardo return -EINVAL; 954e287840SThadeu Lima de Souza Cascardo 964e287840SThadeu Lima de Souza Cascardo while (*str) { 974e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 984e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 994e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1004e287840SThadeu Lima de Souza Cascardo break; 1014e287840SThadeu Lima de Souza Cascardo } 1024e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1034e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1044e287840SThadeu Lima de Souza Cascardo str++; 1054e287840SThadeu Lima de Souza Cascardo } 1064e287840SThadeu Lima de Souza Cascardo 1074e287840SThadeu Lima de Souza Cascardo return 0; 1084e287840SThadeu Lima de Souza Cascardo } 1094e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1104e287840SThadeu Lima de Souza Cascardo 11145baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11245baee14SGuilherme G. Piccoli { 11345baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11445baee14SGuilherme G. Piccoli return 0; 11545baee14SGuilherme G. Piccoli } 11645baee14SGuilherme G. Piccoli 11745baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11845baee14SGuilherme G. Piccoli 1195958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 120262af557SGuo Chao { 1215958d19aSBenjamin Herrenschmidt /* 1225958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1235958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1245958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1255958d19aSBenjamin Herrenschmidt * 1265958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1275958d19aSBenjamin Herrenschmidt */ 1285958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1295958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 130262af557SGuo Chao } 131262af557SGuo Chao 132b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 133b79331a5SRussell Currey { 134b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 135b79331a5SRussell Currey 136b79331a5SRussell Currey return (resource_flags & flags) == flags; 137b79331a5SRussell Currey } 138b79331a5SRussell Currey 1391e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1401e916772SGavin Shan { 141313483ddSGavin Shan s64 rc; 142313483ddSGavin Shan 1431e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1441e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1451e916772SGavin Shan 146313483ddSGavin Shan /* 147313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 148313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 149313483ddSGavin Shan * PE is already in unfrozen state. 150313483ddSGavin Shan */ 151313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 152313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 153d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1541f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 155313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 156313483ddSGavin Shan 1571e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1581e916772SGavin Shan } 1591e916772SGavin Shan 1604b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1614b82ab18SGavin Shan { 16292b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1631f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1644b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1654b82ab18SGavin Shan return; 1664b82ab18SGavin Shan } 1674b82ab18SGavin Shan 168e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1691f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1704b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1714b82ab18SGavin Shan 1721e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1734b82ab18SGavin Shan } 1744b82ab18SGavin Shan 1751e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 176184cd4a3SBenjamin Herrenschmidt { 17760964816SAndrzej Hajda long pe; 178184cd4a3SBenjamin Herrenschmidt 1799fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1809fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1811e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 182184cd4a3SBenjamin Herrenschmidt } 183184cd4a3SBenjamin Herrenschmidt 1849fcd6f4aSGavin Shan return NULL; 1859fcd6f4aSGavin Shan } 1869fcd6f4aSGavin Shan 1871e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 188184cd4a3SBenjamin Herrenschmidt { 1891e916772SGavin Shan struct pnv_phb *phb = pe->phb; 190caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 191184cd4a3SBenjamin Herrenschmidt 1921e916772SGavin Shan WARN_ON(pe->pdev); 1930bd97167SAlexey Kardashevskiy WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */ 1940bd97167SAlexey Kardashevskiy kfree(pe->npucomp); 1951e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 196caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 197184cd4a3SBenjamin Herrenschmidt } 198184cd4a3SBenjamin Herrenschmidt 199262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 200262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 201262af557SGuo Chao { 202262af557SGuo Chao const char *desc; 203262af557SGuo Chao struct resource *r; 204262af557SGuo Chao s64 rc; 205262af557SGuo Chao 206262af557SGuo Chao /* Configure the default M64 BAR */ 207262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 208262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 209262af557SGuo Chao phb->ioda.m64_bar_idx, 210262af557SGuo Chao phb->ioda.m64_base, 211262af557SGuo Chao 0, /* unused */ 212262af557SGuo Chao phb->ioda.m64_size); 213262af557SGuo Chao if (rc != OPAL_SUCCESS) { 214262af557SGuo Chao desc = "configuring"; 215262af557SGuo Chao goto fail; 216262af557SGuo Chao } 217262af557SGuo Chao 218262af557SGuo Chao /* Enable the default M64 BAR */ 219262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 220262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 221262af557SGuo Chao phb->ioda.m64_bar_idx, 222262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 223262af557SGuo Chao if (rc != OPAL_SUCCESS) { 224262af557SGuo Chao desc = "enabling"; 225262af557SGuo Chao goto fail; 226262af557SGuo Chao } 227262af557SGuo Chao 228262af557SGuo Chao /* 22963803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23063803c39SGavin Shan * are first or last two PEs. 231262af557SGuo Chao */ 232262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23392b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23463803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23592b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23663803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 237262af557SGuo Chao else 2381f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23992b8f137SGavin Shan phb->ioda.reserved_pe_idx); 240262af557SGuo Chao 241262af557SGuo Chao return 0; 242262af557SGuo Chao 243262af557SGuo Chao fail: 244262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 245262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 246262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 247262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 248262af557SGuo Chao phb->ioda.m64_bar_idx, 249262af557SGuo Chao OPAL_DISABLE_M64); 250262af557SGuo Chao return -EIO; 251262af557SGuo Chao } 252262af557SGuo Chao 253c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25496a2f92bSGavin Shan unsigned long *pe_bitmap) 255262af557SGuo Chao { 25696a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25796a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 258262af557SGuo Chao struct resource *r; 25996a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26096a2f92bSGavin Shan int segno, i; 261262af557SGuo Chao 26296a2f92bSGavin Shan base = phb->ioda.m64_base; 26396a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26496a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26596a2f92bSGavin Shan r = &pdev->resource[i]; 2665958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 267262af557SGuo Chao continue; 268262af557SGuo Chao 26996a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 27096a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 27196a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27296a2f92bSGavin Shan if (pe_bitmap) 27396a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27496a2f92bSGavin Shan else 27596a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 276262af557SGuo Chao } 277262af557SGuo Chao } 278262af557SGuo Chao } 279262af557SGuo Chao 28099451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28199451551SGavin Shan { 28299451551SGavin Shan struct resource *r; 28399451551SGavin Shan int index; 28499451551SGavin Shan 28599451551SGavin Shan /* 28699451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28799451551SGavin Shan * there are as many M64 segments as the maximum number of 28899451551SGavin Shan * PEs, which is 128. 28999451551SGavin Shan */ 29099451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29199451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29299451551SGavin Shan int64_t rc; 29399451551SGavin Shan 29499451551SGavin Shan base = phb->ioda.m64_base + 29599451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29699451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29799451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29899451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29999451551SGavin Shan if (rc != OPAL_SUCCESS) { 3001f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30199451551SGavin Shan rc, phb->hose->global_number, index); 30299451551SGavin Shan goto fail; 30399451551SGavin Shan } 30499451551SGavin Shan 30599451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30799451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30899451551SGavin Shan if (rc != OPAL_SUCCESS) { 3091f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31099451551SGavin Shan rc, phb->hose->global_number, index); 31199451551SGavin Shan goto fail; 31299451551SGavin Shan } 31399451551SGavin Shan } 31499451551SGavin Shan 31599451551SGavin Shan /* 31663803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31763803c39SGavin Shan * are first or last two PEs. 31899451551SGavin Shan */ 31999451551SGavin Shan r = &phb->hose->mem_resources[1]; 32099451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 32163803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32299451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32363803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32499451551SGavin Shan else 3251f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32699451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32799451551SGavin Shan 32899451551SGavin Shan return 0; 32999451551SGavin Shan 33099451551SGavin Shan fail: 33199451551SGavin Shan for ( ; index >= 0; index--) 33299451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33399451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33499451551SGavin Shan 33599451551SGavin Shan return -EIO; 33699451551SGavin Shan } 33799451551SGavin Shan 338c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33996a2f92bSGavin Shan unsigned long *pe_bitmap, 34096a2f92bSGavin Shan bool all) 341262af557SGuo Chao { 342262af557SGuo Chao struct pci_dev *pdev; 34396a2f92bSGavin Shan 34496a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 345c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34696a2f92bSGavin Shan 34796a2f92bSGavin Shan if (all && pdev->subordinate) 348c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34996a2f92bSGavin Shan pe_bitmap, all); 35096a2f92bSGavin Shan } 35196a2f92bSGavin Shan } 35296a2f92bSGavin Shan 3531e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 354262af557SGuo Chao { 35526ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35626ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 357262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 358262af557SGuo Chao unsigned long size, *pe_alloc; 35926ba248dSGavin Shan int i; 360262af557SGuo Chao 361262af557SGuo Chao /* Root bus shouldn't use M64 */ 362262af557SGuo Chao if (pci_is_root_bus(bus)) 3631e916772SGavin Shan return NULL; 364262af557SGuo Chao 365262af557SGuo Chao /* Allocate bitmap */ 36692b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 367262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 368262af557SGuo Chao if (!pe_alloc) { 369262af557SGuo Chao pr_warn("%s: Out of memory !\n", 370262af557SGuo Chao __func__); 3711e916772SGavin Shan return NULL; 372262af557SGuo Chao } 373262af557SGuo Chao 37426ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 375c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 376262af557SGuo Chao 377262af557SGuo Chao /* 378262af557SGuo Chao * the current bus might not own M64 window and that's all 379262af557SGuo Chao * contributed by its child buses. For the case, we needn't 380262af557SGuo Chao * pick M64 dependent PE#. 381262af557SGuo Chao */ 38292b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 383262af557SGuo Chao kfree(pe_alloc); 3841e916772SGavin Shan return NULL; 385262af557SGuo Chao } 386262af557SGuo Chao 387262af557SGuo Chao /* 388262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 389262af557SGuo Chao * PE's list to form compound PE. 390262af557SGuo Chao */ 391262af557SGuo Chao master_pe = NULL; 392262af557SGuo Chao i = -1; 39392b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39492b8f137SGavin Shan phb->ioda.total_pe_num) { 395262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 396262af557SGuo Chao 39793289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 398262af557SGuo Chao if (!master_pe) { 399262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 400262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 401262af557SGuo Chao master_pe = pe; 402262af557SGuo Chao } else { 403262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 404262af557SGuo Chao pe->master = master_pe; 405262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 406262af557SGuo Chao } 40799451551SGavin Shan 40899451551SGavin Shan /* 40999451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 41099451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 41199451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41299451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41399451551SGavin Shan * segment and PE# on P7IOC. 41499451551SGavin Shan */ 41599451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41699451551SGavin Shan int64_t rc; 41799451551SGavin Shan 41899451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41999451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 42099451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 42199451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42299451551SGavin Shan if (rc != OPAL_SUCCESS) 4231f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42499451551SGavin Shan __func__, rc, phb->hose->global_number, 42599451551SGavin Shan pe->pe_number); 42699451551SGavin Shan } 427262af557SGuo Chao } 428262af557SGuo Chao 429262af557SGuo Chao kfree(pe_alloc); 4301e916772SGavin Shan return master_pe; 431262af557SGuo Chao } 432262af557SGuo Chao 433262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 434262af557SGuo Chao { 435262af557SGuo Chao struct pci_controller *hose = phb->hose; 436262af557SGuo Chao struct device_node *dn = hose->dn; 437262af557SGuo Chao struct resource *res; 438a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4390e7736c6SGavin Shan const __be32 *r; 440262af557SGuo Chao u64 pci_addr; 441262af557SGuo Chao 44299451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4431665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4441665c4a8SGavin Shan return; 4451665c4a8SGavin Shan } 4461665c4a8SGavin Shan 447e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 448262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 449262af557SGuo Chao return; 450262af557SGuo Chao } 451262af557SGuo Chao 452262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 453262af557SGuo Chao if (!r) { 454b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 455b7c670d6SRob Herring dn); 456262af557SGuo Chao return; 457262af557SGuo Chao } 458262af557SGuo Chao 459a1339fafSBenjamin Herrenschmidt /* 460a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 461a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 462a1339fafSBenjamin Herrenschmidt */ 463a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 464a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 465a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 466a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 467a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 468a1339fafSBenjamin Herrenschmidt } 469a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 470a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 471a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 472a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 473a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 474a1339fafSBenjamin Herrenschmidt } 475a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 476a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 477a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 478a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 479a1339fafSBenjamin Herrenschmidt return; 480a1339fafSBenjamin Herrenschmidt } 481a1339fafSBenjamin Herrenschmidt 482a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 483262af557SGuo Chao res = &hose->mem_resources[1]; 484e80c4e7cSGavin Shan res->name = dn->full_name; 485262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 486262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 487262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 488262af557SGuo Chao pci_addr = of_read_number(r, 2); 489262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 490262af557SGuo Chao 491262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49292b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 493262af557SGuo Chao phb->ioda.m64_base = pci_addr; 494262af557SGuo Chao 495a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 496a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 497a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 498a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 499a1339fafSBenjamin Herrenschmidt 500a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 501a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 502e9863e68SWei Yang 503262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 504a1339fafSBenjamin Herrenschmidt m64_range[1]--; 505a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 506a1339fafSBenjamin Herrenschmidt 507a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 508a1339fafSBenjamin Herrenschmidt 509a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 510a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 511a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 512a1339fafSBenjamin Herrenschmidt 513a1339fafSBenjamin Herrenschmidt /* 514a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 515a1339fafSBenjamin Herrenschmidt * the IODA2 code. 516a1339fafSBenjamin Herrenschmidt */ 51799451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51899451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51999451551SGavin Shan else 520262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 521262af557SGuo Chao } 522262af557SGuo Chao 52349dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52449dec922SGavin Shan { 52549dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52649dec922SGavin Shan struct pnv_ioda_pe *slave; 52749dec922SGavin Shan s64 rc; 52849dec922SGavin Shan 52949dec922SGavin Shan /* Fetch master PE */ 53049dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53149dec922SGavin Shan pe = pe->master; 532ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 533ec8e4e9dSGavin Shan return; 534ec8e4e9dSGavin Shan 53549dec922SGavin Shan pe_no = pe->pe_number; 53649dec922SGavin Shan } 53749dec922SGavin Shan 53849dec922SGavin Shan /* Freeze master PE */ 53949dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54049dec922SGavin Shan pe_no, 54149dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54349dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54449dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54549dec922SGavin Shan return; 54649dec922SGavin Shan } 54749dec922SGavin Shan 54849dec922SGavin Shan /* Freeze slave PEs */ 54949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55049dec922SGavin Shan return; 55149dec922SGavin Shan 55249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55349dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55449dec922SGavin Shan slave->pe_number, 55549dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55649dec922SGavin Shan if (rc != OPAL_SUCCESS) 55749dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55849dec922SGavin Shan __func__, rc, phb->hose->global_number, 55949dec922SGavin Shan slave->pe_number); 56049dec922SGavin Shan } 56149dec922SGavin Shan } 56249dec922SGavin Shan 563e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56449dec922SGavin Shan { 56549dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56649dec922SGavin Shan s64 rc; 56749dec922SGavin Shan 56849dec922SGavin Shan /* Find master PE */ 56949dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57049dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57149dec922SGavin Shan pe = pe->master; 57249dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57349dec922SGavin Shan pe_no = pe->pe_number; 57449dec922SGavin Shan } 57549dec922SGavin Shan 57649dec922SGavin Shan /* Clear frozen state for master PE */ 57749dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57949dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58049dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58149dec922SGavin Shan return -EIO; 58249dec922SGavin Shan } 58349dec922SGavin Shan 58449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58549dec922SGavin Shan return 0; 58649dec922SGavin Shan 58749dec922SGavin Shan /* Clear frozen state for slave PEs */ 58849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58949dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59049dec922SGavin Shan slave->pe_number, 59149dec922SGavin Shan opt); 59249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59349dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59449dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59549dec922SGavin Shan slave->pe_number); 59649dec922SGavin Shan return -EIO; 59749dec922SGavin Shan } 59849dec922SGavin Shan } 59949dec922SGavin Shan 60049dec922SGavin Shan return 0; 60149dec922SGavin Shan } 60249dec922SGavin Shan 60349dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60449dec922SGavin Shan { 60549dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 606c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 607c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 60849dec922SGavin Shan s64 rc; 60949dec922SGavin Shan 61049dec922SGavin Shan /* Sanity check on PE number */ 61192b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61249dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61349dec922SGavin Shan 61449dec922SGavin Shan /* 61549dec922SGavin Shan * Fetch the master PE and the PE instance might be 61649dec922SGavin Shan * not initialized yet. 61749dec922SGavin Shan */ 61849dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62049dec922SGavin Shan pe = pe->master; 62149dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62249dec922SGavin Shan pe_no = pe->pe_number; 62349dec922SGavin Shan } 62449dec922SGavin Shan 62549dec922SGavin Shan /* Check the master PE */ 62649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62749dec922SGavin Shan &state, &pcierr, NULL); 62849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62949dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63049dec922SGavin Shan "PHB#%x-PE#%x state\n", 63149dec922SGavin Shan __func__, rc, 63249dec922SGavin Shan phb->hose->global_number, pe_no); 63349dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63449dec922SGavin Shan } 63549dec922SGavin Shan 63649dec922SGavin Shan /* Check the slave PE */ 63749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63849dec922SGavin Shan return state; 63949dec922SGavin Shan 64049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64249dec922SGavin Shan slave->pe_number, 64349dec922SGavin Shan &fstate, 64449dec922SGavin Shan &pcierr, 64549dec922SGavin Shan NULL); 64649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64749dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64849dec922SGavin Shan "PHB#%x-PE#%x state\n", 64949dec922SGavin Shan __func__, rc, 65049dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65149dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65249dec922SGavin Shan } 65349dec922SGavin Shan 65449dec922SGavin Shan /* 65549dec922SGavin Shan * Override the result based on the ascending 65649dec922SGavin Shan * priority. 65749dec922SGavin Shan */ 65849dec922SGavin Shan if (fstate > state) 65949dec922SGavin Shan state = fstate; 66049dec922SGavin Shan } 66149dec922SGavin Shan 66249dec922SGavin Shan return state; 66349dec922SGavin Shan } 66449dec922SGavin Shan 665f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 666184cd4a3SBenjamin Herrenschmidt { 667184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 668184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 669b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 670184cd4a3SBenjamin Herrenschmidt 671184cd4a3SBenjamin Herrenschmidt if (!pdn) 672184cd4a3SBenjamin Herrenschmidt return NULL; 673184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 674184cd4a3SBenjamin Herrenschmidt return NULL; 675184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 676184cd4a3SBenjamin Herrenschmidt } 677184cd4a3SBenjamin Herrenschmidt 678b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 679b131a842SGavin Shan struct pnv_ioda_pe *parent, 680b131a842SGavin Shan struct pnv_ioda_pe *child, 681b131a842SGavin Shan bool is_add) 682b131a842SGavin Shan { 683b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 684b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 685b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 686b131a842SGavin Shan struct pnv_ioda_pe *slave; 687b131a842SGavin Shan long rc; 688b131a842SGavin Shan 689b131a842SGavin Shan /* Parent PE affects child PE */ 690b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 691b131a842SGavin Shan child->pe_number, op); 692b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 693b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 694b131a842SGavin Shan rc, desc); 695b131a842SGavin Shan return -ENXIO; 696b131a842SGavin Shan } 697b131a842SGavin Shan 698b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 699b131a842SGavin Shan return 0; 700b131a842SGavin Shan 701b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 702b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 703b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 704b131a842SGavin Shan slave->pe_number, op); 705b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 706b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 707b131a842SGavin Shan rc, desc); 708b131a842SGavin Shan return -ENXIO; 709b131a842SGavin Shan } 710b131a842SGavin Shan } 711b131a842SGavin Shan 712b131a842SGavin Shan return 0; 713b131a842SGavin Shan } 714b131a842SGavin Shan 715b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 716b131a842SGavin Shan struct pnv_ioda_pe *pe, 717b131a842SGavin Shan bool is_add) 718b131a842SGavin Shan { 719b131a842SGavin Shan struct pnv_ioda_pe *slave; 720781a868fSWei Yang struct pci_dev *pdev = NULL; 721b131a842SGavin Shan int ret; 722b131a842SGavin Shan 723b131a842SGavin Shan /* 724b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 725b131a842SGavin Shan * clear slave PE frozen state as well. 726b131a842SGavin Shan */ 727b131a842SGavin Shan if (is_add) { 728b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 729b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 730b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 731b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 732b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 733b131a842SGavin Shan slave->pe_number, 734b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 735b131a842SGavin Shan } 736b131a842SGavin Shan } 737b131a842SGavin Shan 738b131a842SGavin Shan /* 739b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 740b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 741b131a842SGavin Shan * originated from the PE might contribute to other 742b131a842SGavin Shan * PEs. 743b131a842SGavin Shan */ 744b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 745b131a842SGavin Shan if (ret) 746b131a842SGavin Shan return ret; 747b131a842SGavin Shan 748b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 749b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 750b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 751b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 752b131a842SGavin Shan if (ret) 753b131a842SGavin Shan return ret; 754b131a842SGavin Shan } 755b131a842SGavin Shan } 756b131a842SGavin Shan 757b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 758b131a842SGavin Shan pdev = pe->pbus->self; 759781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 760b131a842SGavin Shan pdev = pe->pdev->bus->self; 761781a868fSWei Yang #ifdef CONFIG_PCI_IOV 762781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 763283e2d8aSGavin Shan pdev = pe->parent_dev; 764781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 765b131a842SGavin Shan while (pdev) { 766b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 767b131a842SGavin Shan struct pnv_ioda_pe *parent; 768b131a842SGavin Shan 769b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 771b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 772b131a842SGavin Shan if (ret) 773b131a842SGavin Shan return ret; 774b131a842SGavin Shan } 775b131a842SGavin Shan 776b131a842SGavin Shan pdev = pdev->bus->self; 777b131a842SGavin Shan } 778b131a842SGavin Shan 779b131a842SGavin Shan return 0; 780b131a842SGavin Shan } 781b131a842SGavin Shan 782781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 783781a868fSWei Yang { 784781a868fSWei Yang struct pci_dev *parent; 785781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 786781a868fSWei Yang int64_t rc; 787781a868fSWei Yang long rid_end, rid; 788781a868fSWei Yang 789781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 790781a868fSWei Yang if (pe->pbus) { 791781a868fSWei Yang int count; 792781a868fSWei Yang 793781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 794781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 795781a868fSWei Yang parent = pe->pbus->self; 796781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 797781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 798781a868fSWei Yang else 799781a868fSWei Yang count = 1; 800781a868fSWei Yang 801781a868fSWei Yang switch(count) { 802781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 803781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 804781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 805781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 806781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 807781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 808781a868fSWei Yang default: 809781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 810781a868fSWei Yang count); 811781a868fSWei Yang /* Do an exact match only */ 812781a868fSWei Yang bcomp = OpalPciBusAll; 813781a868fSWei Yang } 814781a868fSWei Yang rid_end = pe->rid + (count << 8); 815781a868fSWei Yang } else { 81693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 817781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 818781a868fSWei Yang parent = pe->parent_dev; 819781a868fSWei Yang else 82093e01a50SGavin Shan #endif 821781a868fSWei Yang parent = pe->pdev->bus->self; 822781a868fSWei Yang bcomp = OpalPciBusAll; 823781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 824781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 825781a868fSWei Yang rid_end = pe->rid + 1; 826781a868fSWei Yang } 827781a868fSWei Yang 828781a868fSWei Yang /* Clear the reverse map */ 829781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 830c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 831781a868fSWei Yang 832781a868fSWei Yang /* Release from all parents PELT-V */ 833781a868fSWei Yang while (parent) { 834781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 835781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 836781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 837781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 838781a868fSWei Yang /* XXX What to do in case of error ? */ 839781a868fSWei Yang } 840781a868fSWei Yang parent = parent->bus->self; 841781a868fSWei Yang } 842781a868fSWei Yang 843f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 844781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 845781a868fSWei Yang 846781a868fSWei Yang /* Disassociate PE in PELT */ 847781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 848781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 849781a868fSWei Yang if (rc) 850781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 851781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 852781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 853781a868fSWei Yang if (rc) 854781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 855781a868fSWei Yang 856781a868fSWei Yang pe->pbus = NULL; 857781a868fSWei Yang pe->pdev = NULL; 85893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 859781a868fSWei Yang pe->parent_dev = NULL; 86093e01a50SGavin Shan #endif 861781a868fSWei Yang 862781a868fSWei Yang return 0; 863781a868fSWei Yang } 864781a868fSWei Yang 865cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 866184cd4a3SBenjamin Herrenschmidt { 867184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 868184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 869184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 870184cd4a3SBenjamin Herrenschmidt 871184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 872184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 873184cd4a3SBenjamin Herrenschmidt int count; 874184cd4a3SBenjamin Herrenschmidt 875184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 876184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 877184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 878fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 879b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 880fb446ad0SGavin Shan else 881fb446ad0SGavin Shan count = 1; 882fb446ad0SGavin Shan 883184cd4a3SBenjamin Herrenschmidt switch(count) { 884184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 885184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 886184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 887184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 888184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 889184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 890184cd4a3SBenjamin Herrenschmidt default: 891781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 892781a868fSWei Yang count); 893184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 894184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 895184cd4a3SBenjamin Herrenschmidt } 896184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 897184cd4a3SBenjamin Herrenschmidt } else { 898781a868fSWei Yang #ifdef CONFIG_PCI_IOV 899781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 900781a868fSWei Yang parent = pe->parent_dev; 901781a868fSWei Yang else 902781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 903184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 904184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 905184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 906184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 907184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 908184cd4a3SBenjamin Herrenschmidt } 909184cd4a3SBenjamin Herrenschmidt 910631ad691SGavin Shan /* 911631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 912631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 913631ad691SGavin Shan * originated from the PE might contribute to other 914631ad691SGavin Shan * PEs. 915631ad691SGavin Shan */ 916184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 917184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 918184cd4a3SBenjamin Herrenschmidt if (rc) { 919184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 920184cd4a3SBenjamin Herrenschmidt return -ENXIO; 921184cd4a3SBenjamin Herrenschmidt } 922631ad691SGavin Shan 9235d2aa710SAlistair Popple /* 9245d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9255d2aa710SAlistair Popple * configuration on them. 9265d2aa710SAlistair Popple */ 9277f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 928b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 929184cd4a3SBenjamin Herrenschmidt 930184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 931184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 932184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 933184cd4a3SBenjamin Herrenschmidt 934184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9354773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9364773f76bSGavin Shan pe->mve_number = 0; 9374773f76bSGavin Shan goto out; 9384773f76bSGavin Shan } 9394773f76bSGavin Shan 940184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9414773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9424773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9431f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 944184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 945184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 946184cd4a3SBenjamin Herrenschmidt } else { 947184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 948cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 949184cd4a3SBenjamin Herrenschmidt if (rc) { 9501f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 951184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 952184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 953184cd4a3SBenjamin Herrenschmidt } 954184cd4a3SBenjamin Herrenschmidt } 955184cd4a3SBenjamin Herrenschmidt 9564773f76bSGavin Shan out: 957184cd4a3SBenjamin Herrenschmidt return 0; 958184cd4a3SBenjamin Herrenschmidt } 959184cd4a3SBenjamin Herrenschmidt 960781a868fSWei Yang #ifdef CONFIG_PCI_IOV 961781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 962781a868fSWei Yang { 963781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 964781a868fSWei Yang int i; 965781a868fSWei Yang struct resource *res, res2; 966781a868fSWei Yang resource_size_t size; 967781a868fSWei Yang u16 num_vfs; 968781a868fSWei Yang 969781a868fSWei Yang if (!dev->is_physfn) 970781a868fSWei Yang return -EINVAL; 971781a868fSWei Yang 972781a868fSWei Yang /* 973781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 974781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 975781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 976781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 977781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 978781a868fSWei Yang * range of PEs the VFs are in. 979781a868fSWei Yang */ 980781a868fSWei Yang num_vfs = pdn->num_vfs; 981781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 982781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 983781a868fSWei Yang if (!res->flags || !res->parent) 984781a868fSWei Yang continue; 985781a868fSWei Yang 986781a868fSWei Yang /* 987781a868fSWei Yang * The actual IOV BAR range is determined by the start address 988781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 989781a868fSWei Yang * make sure that after shifting, the range will not overlap 990781a868fSWei Yang * with another device. 991781a868fSWei Yang */ 992781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 993781a868fSWei Yang res2.flags = res->flags; 994781a868fSWei Yang res2.start = res->start + (size * offset); 995781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 996781a868fSWei Yang 997781a868fSWei Yang if (res2.end > res->end) { 998781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 999781a868fSWei Yang i, &res2, res, num_vfs, offset); 1000781a868fSWei Yang return -EBUSY; 1001781a868fSWei Yang } 1002781a868fSWei Yang } 1003781a868fSWei Yang 1004781a868fSWei Yang /* 1005d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1006d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1007d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1008d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1009d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1010d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1011781a868fSWei Yang */ 1012781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1013781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1014781a868fSWei Yang if (!res->flags || !res->parent) 1015781a868fSWei Yang continue; 1016781a868fSWei Yang 1017781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1018781a868fSWei Yang res2 = *res; 1019781a868fSWei Yang res->start += size * offset; 1020781a868fSWei Yang 102174703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 102274703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102374703cc4SWei Yang num_vfs, offset); 1024d6f934fdSAlexey Kardashevskiy 1025d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1026d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1027d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1028d6f934fdSAlexey Kardashevskiy } 1029d6f934fdSAlexey Kardashevskiy 1030781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1031d6f934fdSAlexey Kardashevskiy 1032d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1033d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1034d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1035d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1036d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1037d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1038d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1039d6f934fdSAlexey Kardashevskiy } 1040781a868fSWei Yang } 1041781a868fSWei Yang return 0; 1042781a868fSWei Yang } 1043781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1044781a868fSWei Yang 1045cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1046184cd4a3SBenjamin Herrenschmidt { 1047184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1048184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1049b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1050184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1051184cd4a3SBenjamin Herrenschmidt 1052184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1053184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1054184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1055184cd4a3SBenjamin Herrenschmidt return NULL; 1056184cd4a3SBenjamin Herrenschmidt } 1057184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1058184cd4a3SBenjamin Herrenschmidt return NULL; 1059184cd4a3SBenjamin Herrenschmidt 10601e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10611e916772SGavin Shan if (!pe) { 1062f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1063184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1064184cd4a3SBenjamin Herrenschmidt return NULL; 1065184cd4a3SBenjamin Herrenschmidt } 1066184cd4a3SBenjamin Herrenschmidt 1067184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1068184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1069184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1070184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1071184cd4a3SBenjamin Herrenschmidt * 1072184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1073184cd4a3SBenjamin Herrenschmidt */ 1074184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 10751e916772SGavin Shan pdn->pe_number = pe->pe_number; 10765d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1077184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1078184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1079184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1080184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1081184cd4a3SBenjamin Herrenschmidt 1082184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1083184cd4a3SBenjamin Herrenschmidt 1084184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1085184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10861e916772SGavin Shan pnv_ioda_free_pe(pe); 1087184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1088184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1089184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1090184cd4a3SBenjamin Herrenschmidt return NULL; 1091184cd4a3SBenjamin Herrenschmidt } 1092184cd4a3SBenjamin Herrenschmidt 10931d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10941d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10951d4e89cfSAlexey Kardashevskiy 1096184cd4a3SBenjamin Herrenschmidt return pe; 1097184cd4a3SBenjamin Herrenschmidt } 1098184cd4a3SBenjamin Herrenschmidt 1099184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1100184cd4a3SBenjamin Herrenschmidt { 1101184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1102184cd4a3SBenjamin Herrenschmidt 1103184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1104b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1105184cd4a3SBenjamin Herrenschmidt 1106184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1107184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1108184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1109184cd4a3SBenjamin Herrenschmidt continue; 1110184cd4a3SBenjamin Herrenschmidt } 1111ccd1c191SGavin Shan 1112ccd1c191SGavin Shan /* 1113ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1114ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1115ccd1c191SGavin Shan * again. 1116ccd1c191SGavin Shan */ 1117ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1118ccd1c191SGavin Shan continue; 1119ccd1c191SGavin Shan 1120c5f7700bSGavin Shan pe->device_count++; 1121184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1122fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1123184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1124184cd4a3SBenjamin Herrenschmidt } 1125184cd4a3SBenjamin Herrenschmidt } 1126184cd4a3SBenjamin Herrenschmidt 1127fb446ad0SGavin Shan /* 1128fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1129fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1130fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1131fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1132fb446ad0SGavin Shan */ 11331e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1134184cd4a3SBenjamin Herrenschmidt { 1135fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1136184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11371e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1138ccd1c191SGavin Shan unsigned int pe_num; 1139ccd1c191SGavin Shan 1140ccd1c191SGavin Shan /* 1141ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1142ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1143ccd1c191SGavin Shan */ 1144ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1145ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1146ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1147ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1148ccd1c191SGavin Shan return NULL; 1149ccd1c191SGavin Shan } 1150184cd4a3SBenjamin Herrenschmidt 115163803c39SGavin Shan /* PE number for root bus should have been reserved */ 115263803c39SGavin Shan if (pci_is_root_bus(bus) && 115363803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 115463803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 115563803c39SGavin Shan 1156262af557SGuo Chao /* Check if PE is determined by M64 */ 1157a25de7afSAlexey Kardashevskiy if (!pe) 1158a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1159262af557SGuo Chao 1160262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11611e916772SGavin Shan if (!pe) 11621e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1163262af557SGuo Chao 11641e916772SGavin Shan if (!pe) { 1165f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1166fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11671e916772SGavin Shan return NULL; 1168184cd4a3SBenjamin Herrenschmidt } 1169184cd4a3SBenjamin Herrenschmidt 1170262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1171184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1172184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1173184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1174b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1175184cd4a3SBenjamin Herrenschmidt 1176fb446ad0SGavin Shan if (all) 11771f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11781e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1179fb446ad0SGavin Shan else 11801f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11811e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1182184cd4a3SBenjamin Herrenschmidt 1183184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1184184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11851e916772SGavin Shan pnv_ioda_free_pe(pe); 1186184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11871e916772SGavin Shan return NULL; 1188184cd4a3SBenjamin Herrenschmidt } 1189184cd4a3SBenjamin Herrenschmidt 1190184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1191184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1192184cd4a3SBenjamin Herrenschmidt 11937ebdf956SGavin Shan /* Put PE to the list */ 11947ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11951e916772SGavin Shan 11961e916772SGavin Shan return pe; 1197184cd4a3SBenjamin Herrenschmidt } 1198184cd4a3SBenjamin Herrenschmidt 1199b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 12005d2aa710SAlistair Popple { 1201b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1202b521549aSAlistair Popple long rid; 1203b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1204b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1205b521549aSAlistair Popple struct pci_dn *npu_pdn; 1206b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1207b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1208b521549aSAlistair Popple 1209b521549aSAlistair Popple /* 1210b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1211b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1212b521549aSAlistair Popple * which need to be assigned to four links, implying some 1213b521549aSAlistair Popple * links must share PEs. 1214b521549aSAlistair Popple * 1215b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1216b521549aSAlistair Popple * same GPU get assigned the same PE. 1217b521549aSAlistair Popple */ 1218b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 121992b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1220b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1221b521549aSAlistair Popple if (!pe->pdev) 1222b521549aSAlistair Popple continue; 1223b521549aSAlistair Popple 1224b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1225b521549aSAlistair Popple /* 1226b521549aSAlistair Popple * This device has the same peer GPU so should 1227b521549aSAlistair Popple * be assigned the same PE as the existing 1228b521549aSAlistair Popple * peer NPU. 1229b521549aSAlistair Popple */ 1230b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12311f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1232b521549aSAlistair Popple pci_dev_get(npu_pdev); 1233b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1234b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1235b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1236b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1237b521549aSAlistair Popple 1238b521549aSAlistair Popple /* Map the PE to this link */ 1239b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1240b521549aSAlistair Popple OpalPciBusAll, 1241b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1242b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1243b521549aSAlistair Popple OPAL_MAP_PE); 1244b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1245b521549aSAlistair Popple found_pe = true; 1246b521549aSAlistair Popple break; 1247b521549aSAlistair Popple } 1248b521549aSAlistair Popple } 1249b521549aSAlistair Popple 1250b521549aSAlistair Popple if (!found_pe) 1251b521549aSAlistair Popple /* 1252b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1253b521549aSAlistair Popple * one. 1254b521549aSAlistair Popple */ 1255b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1256b521549aSAlistair Popple else 1257b521549aSAlistair Popple return pe; 1258b521549aSAlistair Popple } 1259b521549aSAlistair Popple 1260b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1261b521549aSAlistair Popple { 12625d2aa710SAlistair Popple struct pci_dev *pdev; 12635d2aa710SAlistair Popple 12645d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1265b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12665d2aa710SAlistair Popple } 12675d2aa710SAlistair Popple 1268cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1269fb446ad0SGavin Shan { 12700e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1271262af557SGuo Chao struct pnv_phb *phb; 12727f2c39e9SFrederic Barrat struct pci_bus *bus; 12737f2c39e9SFrederic Barrat struct pci_dev *pdev; 12740e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1275fb446ad0SGavin Shan 12760e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1277262af557SGuo Chao phb = hose->private_data; 12787f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 127908f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 128008f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1281b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12821ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12830e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1284ccd1c191SGavin Shan } 12857f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_OCAPI) { 12867f2c39e9SFrederic Barrat bus = hose->bus; 12877f2c39e9SFrederic Barrat list_for_each_entry(pdev, &bus->devices, bus_list) 12887f2c39e9SFrederic Barrat pnv_ioda_setup_dev_PE(pdev); 12897f2c39e9SFrederic Barrat } 1290fb446ad0SGavin Shan } 12910e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 12920e759bd7SAlexey Kardashevskiy phb = hose->private_data; 12930e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 12940e759bd7SAlexey Kardashevskiy continue; 12950e759bd7SAlexey Kardashevskiy 12960e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 12970e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 12980e759bd7SAlexey Kardashevskiy } 1299fb446ad0SGavin Shan } 1300184cd4a3SBenjamin Herrenschmidt 1301a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1302ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1303781a868fSWei Yang { 1304781a868fSWei Yang struct pci_bus *bus; 1305781a868fSWei Yang struct pci_controller *hose; 1306781a868fSWei Yang struct pnv_phb *phb; 1307781a868fSWei Yang struct pci_dn *pdn; 130802639b0eSWei Yang int i, j; 1309ee8222feSWei Yang int m64_bars; 1310781a868fSWei Yang 1311781a868fSWei Yang bus = pdev->bus; 1312781a868fSWei Yang hose = pci_bus_to_host(bus); 1313781a868fSWei Yang phb = hose->private_data; 1314781a868fSWei Yang pdn = pci_get_pdn(pdev); 1315781a868fSWei Yang 1316ee8222feSWei Yang if (pdn->m64_single_mode) 1317ee8222feSWei Yang m64_bars = num_vfs; 1318ee8222feSWei Yang else 1319ee8222feSWei Yang m64_bars = 1; 1320ee8222feSWei Yang 132102639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1322ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1323ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1324781a868fSWei Yang continue; 1325781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1326ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1327ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1328ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1329781a868fSWei Yang } 1330781a868fSWei Yang 1331ee8222feSWei Yang kfree(pdn->m64_map); 1332781a868fSWei Yang return 0; 1333781a868fSWei Yang } 1334781a868fSWei Yang 133502639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1336781a868fSWei Yang { 1337781a868fSWei Yang struct pci_bus *bus; 1338781a868fSWei Yang struct pci_controller *hose; 1339781a868fSWei Yang struct pnv_phb *phb; 1340781a868fSWei Yang struct pci_dn *pdn; 1341781a868fSWei Yang unsigned int win; 1342781a868fSWei Yang struct resource *res; 134302639b0eSWei Yang int i, j; 1344781a868fSWei Yang int64_t rc; 134502639b0eSWei Yang int total_vfs; 134602639b0eSWei Yang resource_size_t size, start; 134702639b0eSWei Yang int pe_num; 1348ee8222feSWei Yang int m64_bars; 1349781a868fSWei Yang 1350781a868fSWei Yang bus = pdev->bus; 1351781a868fSWei Yang hose = pci_bus_to_host(bus); 1352781a868fSWei Yang phb = hose->private_data; 1353781a868fSWei Yang pdn = pci_get_pdn(pdev); 135402639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1355781a868fSWei Yang 1356ee8222feSWei Yang if (pdn->m64_single_mode) 1357ee8222feSWei Yang m64_bars = num_vfs; 1358ee8222feSWei Yang else 1359ee8222feSWei Yang m64_bars = 1; 136002639b0eSWei Yang 1361fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1362fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1363fb37e128SMarkus Elfring GFP_KERNEL); 1364ee8222feSWei Yang if (!pdn->m64_map) 1365ee8222feSWei Yang return -ENOMEM; 1366ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1367ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1368ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1369ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1370ee8222feSWei Yang 1371781a868fSWei Yang 1372781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1373781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1374781a868fSWei Yang if (!res->flags || !res->parent) 1375781a868fSWei Yang continue; 1376781a868fSWei Yang 1377ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1378781a868fSWei Yang do { 1379781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1380781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1381781a868fSWei Yang 1382781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1383781a868fSWei Yang goto m64_failed; 1384781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1385781a868fSWei Yang 1386ee8222feSWei Yang pdn->m64_map[j][i] = win; 138702639b0eSWei Yang 1388ee8222feSWei Yang if (pdn->m64_single_mode) { 138902639b0eSWei Yang size = pci_iov_resource_size(pdev, 139002639b0eSWei Yang PCI_IOV_RESOURCES + i); 139102639b0eSWei Yang start = res->start + size * j; 139202639b0eSWei Yang } else { 139302639b0eSWei Yang size = resource_size(res); 139402639b0eSWei Yang start = res->start; 139502639b0eSWei Yang } 1396781a868fSWei Yang 1397781a868fSWei Yang /* Map the M64 here */ 1398ee8222feSWei Yang if (pdn->m64_single_mode) { 1399be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 140002639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 140102639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1402ee8222feSWei Yang pdn->m64_map[j][i], 0); 140302639b0eSWei Yang } 140402639b0eSWei Yang 1405781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1406781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1407ee8222feSWei Yang pdn->m64_map[j][i], 140802639b0eSWei Yang start, 1409781a868fSWei Yang 0, /* unused */ 141002639b0eSWei Yang size); 141102639b0eSWei Yang 141202639b0eSWei Yang 1413781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1414781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1415781a868fSWei Yang win, rc); 1416781a868fSWei Yang goto m64_failed; 1417781a868fSWei Yang } 1418781a868fSWei Yang 1419ee8222feSWei Yang if (pdn->m64_single_mode) 1420781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1421ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 142202639b0eSWei Yang else 142302639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1424ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 142502639b0eSWei Yang 1426781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1427781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1428781a868fSWei Yang win, rc); 1429781a868fSWei Yang goto m64_failed; 1430781a868fSWei Yang } 1431781a868fSWei Yang } 143202639b0eSWei Yang } 1433781a868fSWei Yang return 0; 1434781a868fSWei Yang 1435781a868fSWei Yang m64_failed: 1436ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1437781a868fSWei Yang return -EBUSY; 1438781a868fSWei Yang } 1439781a868fSWei Yang 1440c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1441c035e37bSAlexey Kardashevskiy int num); 1442c035e37bSAlexey Kardashevskiy 1443781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1444781a868fSWei Yang { 1445781a868fSWei Yang struct iommu_table *tbl; 1446781a868fSWei Yang int64_t rc; 1447781a868fSWei Yang 1448b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1449c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1450781a868fSWei Yang if (rc) 1451781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1452781a868fSWei Yang 1453c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14540eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14550eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14560eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1457ac9a5889SAlexey Kardashevskiy } 1458e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1459781a868fSWei Yang } 1460781a868fSWei Yang 1461ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1462781a868fSWei Yang { 1463781a868fSWei Yang struct pci_bus *bus; 1464781a868fSWei Yang struct pci_controller *hose; 1465781a868fSWei Yang struct pnv_phb *phb; 1466781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1467781a868fSWei Yang struct pci_dn *pdn; 1468781a868fSWei Yang 1469781a868fSWei Yang bus = pdev->bus; 1470781a868fSWei Yang hose = pci_bus_to_host(bus); 1471781a868fSWei Yang phb = hose->private_data; 147202639b0eSWei Yang pdn = pci_get_pdn(pdev); 1473781a868fSWei Yang 1474781a868fSWei Yang if (!pdev->is_physfn) 1475781a868fSWei Yang return; 1476781a868fSWei Yang 1477781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1478781a868fSWei Yang if (pe->parent_dev != pdev) 1479781a868fSWei Yang continue; 1480781a868fSWei Yang 1481781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1482781a868fSWei Yang 1483781a868fSWei Yang /* Remove from list */ 1484781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1485781a868fSWei Yang list_del(&pe->list); 1486781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1487781a868fSWei Yang 1488781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1489781a868fSWei Yang 14901e916772SGavin Shan pnv_ioda_free_pe(pe); 1491781a868fSWei Yang } 1492781a868fSWei Yang } 1493781a868fSWei Yang 1494781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1495781a868fSWei Yang { 1496781a868fSWei Yang struct pci_bus *bus; 1497781a868fSWei Yang struct pci_controller *hose; 1498781a868fSWei Yang struct pnv_phb *phb; 14991e916772SGavin Shan struct pnv_ioda_pe *pe; 1500781a868fSWei Yang struct pci_dn *pdn; 1501be283eebSWei Yang u16 num_vfs, i; 1502781a868fSWei Yang 1503781a868fSWei Yang bus = pdev->bus; 1504781a868fSWei Yang hose = pci_bus_to_host(bus); 1505781a868fSWei Yang phb = hose->private_data; 1506781a868fSWei Yang pdn = pci_get_pdn(pdev); 1507781a868fSWei Yang num_vfs = pdn->num_vfs; 1508781a868fSWei Yang 1509781a868fSWei Yang /* Release VF PEs */ 1510ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1511781a868fSWei Yang 1512781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1513ee8222feSWei Yang if (!pdn->m64_single_mode) 1514be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1515781a868fSWei Yang 1516781a868fSWei Yang /* Release M64 windows */ 1517ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1518781a868fSWei Yang 1519781a868fSWei Yang /* Release PE numbers */ 1520be283eebSWei Yang if (pdn->m64_single_mode) { 1521be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15221e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15231e916772SGavin Shan continue; 15241e916772SGavin Shan 15251e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15261e916772SGavin Shan pnv_ioda_free_pe(pe); 1527be283eebSWei Yang } 1528be283eebSWei Yang } else 1529be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1530be283eebSWei Yang /* Releasing pe_num_map */ 1531be283eebSWei Yang kfree(pdn->pe_num_map); 1532781a868fSWei Yang } 1533781a868fSWei Yang } 1534781a868fSWei Yang 1535781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1536781a868fSWei Yang struct pnv_ioda_pe *pe); 15375eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15380bd97167SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 15390bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, struct pci_bus *bus); 15400bd97167SAlexey Kardashevskiy 15415eada8a3SAlexey Kardashevskiy #endif 1542781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1543781a868fSWei Yang { 1544781a868fSWei Yang struct pci_bus *bus; 1545781a868fSWei Yang struct pci_controller *hose; 1546781a868fSWei Yang struct pnv_phb *phb; 1547781a868fSWei Yang struct pnv_ioda_pe *pe; 1548781a868fSWei Yang int pe_num; 1549781a868fSWei Yang u16 vf_index; 1550781a868fSWei Yang struct pci_dn *pdn; 1551781a868fSWei Yang 1552781a868fSWei Yang bus = pdev->bus; 1553781a868fSWei Yang hose = pci_bus_to_host(bus); 1554781a868fSWei Yang phb = hose->private_data; 1555781a868fSWei Yang pdn = pci_get_pdn(pdev); 1556781a868fSWei Yang 1557781a868fSWei Yang if (!pdev->is_physfn) 1558781a868fSWei Yang return; 1559781a868fSWei Yang 1560781a868fSWei Yang /* Reserve PE for each VF */ 1561781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1562be283eebSWei Yang if (pdn->m64_single_mode) 1563be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1564be283eebSWei Yang else 1565be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1566781a868fSWei Yang 1567781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1568781a868fSWei Yang pe->pe_number = pe_num; 1569781a868fSWei Yang pe->phb = phb; 1570781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1571781a868fSWei Yang pe->pbus = NULL; 1572781a868fSWei Yang pe->parent_dev = pdev; 1573781a868fSWei Yang pe->mve_number = -1; 1574781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1575781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1576781a868fSWei Yang 15771f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1578781a868fSWei Yang hose->global_number, pdev->bus->number, 1579781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1580781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1581781a868fSWei Yang 1582781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1583781a868fSWei Yang /* XXX What do we do here ? */ 15841e916772SGavin Shan pnv_ioda_free_pe(pe); 1585781a868fSWei Yang pe->pdev = NULL; 1586781a868fSWei Yang continue; 1587781a868fSWei Yang } 1588781a868fSWei Yang 1589781a868fSWei Yang /* Put PE to the list */ 1590781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1591781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1592781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1593781a868fSWei Yang 1594781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 15955eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15960bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL); 15975eada8a3SAlexey Kardashevskiy #endif 1598781a868fSWei Yang } 1599781a868fSWei Yang } 1600781a868fSWei Yang 1601781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1602781a868fSWei Yang { 1603781a868fSWei Yang struct pci_bus *bus; 1604781a868fSWei Yang struct pci_controller *hose; 1605781a868fSWei Yang struct pnv_phb *phb; 16061e916772SGavin Shan struct pnv_ioda_pe *pe; 1607781a868fSWei Yang struct pci_dn *pdn; 1608781a868fSWei Yang int ret; 1609be283eebSWei Yang u16 i; 1610781a868fSWei Yang 1611781a868fSWei Yang bus = pdev->bus; 1612781a868fSWei Yang hose = pci_bus_to_host(bus); 1613781a868fSWei Yang phb = hose->private_data; 1614781a868fSWei Yang pdn = pci_get_pdn(pdev); 1615781a868fSWei Yang 1616781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1617b0331854SWei Yang if (!pdn->vfs_expanded) { 1618b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1619b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1620b0331854SWei Yang return -ENOSPC; 1621b0331854SWei Yang } 1622b0331854SWei Yang 1623ee8222feSWei Yang /* 1624ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1625ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1626ee8222feSWei Yang */ 1627ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1628ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1629ee8222feSWei Yang return -EBUSY; 1630ee8222feSWei Yang } 1631ee8222feSWei Yang 1632be283eebSWei Yang /* Allocating pe_num_map */ 1633be283eebSWei Yang if (pdn->m64_single_mode) 1634fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1635fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1636be283eebSWei Yang GFP_KERNEL); 1637be283eebSWei Yang else 1638be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1639be283eebSWei Yang 1640be283eebSWei Yang if (!pdn->pe_num_map) 1641be283eebSWei Yang return -ENOMEM; 1642be283eebSWei Yang 1643be283eebSWei Yang if (pdn->m64_single_mode) 1644be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1645be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1646be283eebSWei Yang 1647781a868fSWei Yang /* Calculate available PE for required VFs */ 1648be283eebSWei Yang if (pdn->m64_single_mode) { 1649be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16501e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16511e916772SGavin Shan if (!pe) { 1652be283eebSWei Yang ret = -EBUSY; 1653be283eebSWei Yang goto m64_failed; 1654be283eebSWei Yang } 16551e916772SGavin Shan 16561e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1657be283eebSWei Yang } 1658be283eebSWei Yang } else { 1659781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1660be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 166192b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1662781a868fSWei Yang 0, num_vfs, 0); 166392b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1664781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1665781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1666be283eebSWei Yang kfree(pdn->pe_num_map); 1667781a868fSWei Yang return -EBUSY; 1668781a868fSWei Yang } 1669be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1670781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1671be283eebSWei Yang } 1672be283eebSWei Yang pdn->num_vfs = num_vfs; 1673781a868fSWei Yang 1674781a868fSWei Yang /* Assign M64 window accordingly */ 167502639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1676781a868fSWei Yang if (ret) { 1677781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1678781a868fSWei Yang goto m64_failed; 1679781a868fSWei Yang } 1680781a868fSWei Yang 1681781a868fSWei Yang /* 1682781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1683781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1684781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1685781a868fSWei Yang */ 1686ee8222feSWei Yang if (!pdn->m64_single_mode) { 1687be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1688781a868fSWei Yang if (ret) 1689781a868fSWei Yang goto m64_failed; 1690781a868fSWei Yang } 169102639b0eSWei Yang } 1692781a868fSWei Yang 1693781a868fSWei Yang /* Setup VF PEs */ 1694781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1695781a868fSWei Yang 1696781a868fSWei Yang return 0; 1697781a868fSWei Yang 1698781a868fSWei Yang m64_failed: 1699be283eebSWei Yang if (pdn->m64_single_mode) { 1700be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 17011e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 17021e916772SGavin Shan continue; 17031e916772SGavin Shan 17041e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 17051e916772SGavin Shan pnv_ioda_free_pe(pe); 1706be283eebSWei Yang } 1707be283eebSWei Yang } else 1708be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1709be283eebSWei Yang 1710be283eebSWei Yang /* Releasing pe_num_map */ 1711be283eebSWei Yang kfree(pdn->pe_num_map); 1712781a868fSWei Yang 1713781a868fSWei Yang return ret; 1714781a868fSWei Yang } 1715781a868fSWei Yang 1716988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1717a8b2f828SGavin Shan { 1718781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1719781a868fSWei Yang 1720a8b2f828SGavin Shan /* Release PCI data */ 1721a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1722a8b2f828SGavin Shan return 0; 1723a8b2f828SGavin Shan } 1724a8b2f828SGavin Shan 1725988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1726a8b2f828SGavin Shan { 1727a8b2f828SGavin Shan /* Allocate PCI data */ 1728a8b2f828SGavin Shan add_dev_pci_data(pdev); 1729781a868fSWei Yang 1730ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1731a8b2f828SGavin Shan } 1732a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1733a8b2f828SGavin Shan 1734959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1735184cd4a3SBenjamin Herrenschmidt { 1736b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1737959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1738184cd4a3SBenjamin Herrenschmidt 1739959c9bddSGavin Shan /* 1740959c9bddSGavin Shan * The function can be called while the PE# 1741959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1742959c9bddSGavin Shan * case. 1743959c9bddSGavin Shan */ 1744959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1745959c9bddSGavin Shan return; 1746184cd4a3SBenjamin Herrenschmidt 1747959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1748cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17490e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1750b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17514617082eSAlexey Kardashevskiy /* 17524617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17534617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17544617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17554617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17564617082eSAlexey Kardashevskiy */ 1757184cd4a3SBenjamin Herrenschmidt } 1758184cd4a3SBenjamin Herrenschmidt 17598e3f1b1dSRussell Currey /* 17608e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17618e3f1b1dSRussell Currey * 17628e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17638e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17648e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17658e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17668e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17678e3f1b1dSRussell Currey * devices in TVE#0. 17688e3f1b1dSRussell Currey * 17698e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17708e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17718e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17728e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17738e3f1b1dSRussell Currey * 17748e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17758e3f1b1dSRussell Currey */ 17768e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17778e3f1b1dSRussell Currey { 17788e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17798e3f1b1dSRussell Currey struct page *table_pages; 17808e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 17818e3f1b1dSRussell Currey __be64 *tces; 17828e3f1b1dSRussell Currey s64 rc; 17838e3f1b1dSRussell Currey 17848e3f1b1dSRussell Currey /* 17858e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 17868e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 17878e3f1b1dSRussell Currey */ 17888e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 17898e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 17908e3f1b1dSRussell Currey table_size = tce_count << 3; 17918e3f1b1dSRussell Currey 17928e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 17938e3f1b1dSRussell Currey table_size = PAGE_SIZE; 17948e3f1b1dSRussell Currey 17958e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 17968e3f1b1dSRussell Currey get_order(table_size)); 17978e3f1b1dSRussell Currey if (!table_pages) 17988e3f1b1dSRussell Currey goto err; 17998e3f1b1dSRussell Currey 18008e3f1b1dSRussell Currey tces = page_address(table_pages); 18018e3f1b1dSRussell Currey if (!tces) 18028e3f1b1dSRussell Currey goto err; 18038e3f1b1dSRussell Currey 18048e3f1b1dSRussell Currey memset(tces, 0, table_size); 18058e3f1b1dSRussell Currey 18068e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18078e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18088e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18098e3f1b1dSRussell Currey } 18108e3f1b1dSRussell Currey 18118e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18128e3f1b1dSRussell Currey pe->pe_number, 18138e3f1b1dSRussell Currey /* reconfigure window 0 */ 18148e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18158e3f1b1dSRussell Currey 1, 18168e3f1b1dSRussell Currey __pa(tces), 18178e3f1b1dSRussell Currey table_size, 18188e3f1b1dSRussell Currey 1 << tce_order); 18198e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18208e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18218e3f1b1dSRussell Currey return 0; 18228e3f1b1dSRussell Currey } 18238e3f1b1dSRussell Currey err: 18248e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18258e3f1b1dSRussell Currey return -EIO; 18268e3f1b1dSRussell Currey } 18278e3f1b1dSRussell Currey 1828763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1829cd15b048SBenjamin Herrenschmidt { 1830763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1831763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1832cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1833cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1834cd15b048SBenjamin Herrenschmidt uint64_t top; 1835cd15b048SBenjamin Herrenschmidt bool bypass = false; 18368e3f1b1dSRussell Currey s64 rc; 1837cd15b048SBenjamin Herrenschmidt 1838cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1839ed7158baSIngo Molnar return -ENODEV; 1840cd15b048SBenjamin Herrenschmidt 1841cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1842cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1843cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1844cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1845cd15b048SBenjamin Herrenschmidt } 1846cd15b048SBenjamin Herrenschmidt 1847cd15b048SBenjamin Herrenschmidt if (bypass) { 1848cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 18492d9d6f6cSChristoph Hellwig set_dma_ops(&pdev->dev, &dma_nommu_ops); 1850cd15b048SBenjamin Herrenschmidt } else { 18518e3f1b1dSRussell Currey /* 18528e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18538e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18548e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18558e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18568e3f1b1dSRussell Currey */ 18578e3f1b1dSRussell Currey if (dma_mask >> 32 && 18588e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1859661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1860661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 18618e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18628e3f1b1dSRussell Currey /* Configure the bypass mode */ 18638e3f1b1dSRussell Currey rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18648e3f1b1dSRussell Currey if (rc) 18658e3f1b1dSRussell Currey return rc; 18668e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18678e3f1b1dSRussell Currey set_dma_offset(&pdev->dev, (1ULL << 32)); 18682d9d6f6cSChristoph Hellwig set_dma_ops(&pdev->dev, &dma_nommu_ops); 1869253fd51eSAlistair Popple } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1870253fd51eSAlistair Popple /* 1871253fd51eSAlistair Popple * Fail the request if a DMA mask between 32 and 64 bits 1872253fd51eSAlistair Popple * was requested but couldn't be fulfilled. Ideally we 1873253fd51eSAlistair Popple * would do this for 64-bits but historically we have 1874253fd51eSAlistair Popple * always fallen back to 32-bits. 1875253fd51eSAlistair Popple */ 1876253fd51eSAlistair Popple return -ENOMEM; 18778e3f1b1dSRussell Currey } else { 1878cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1879cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1880cd15b048SBenjamin Herrenschmidt } 18818e3f1b1dSRussell Currey } 1882a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 18835d2aa710SAlistair Popple 18845d2aa710SAlistair Popple /* Update peer npu devices */ 1885f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 18865d2aa710SAlistair Popple 1887cd15b048SBenjamin Herrenschmidt return 0; 1888cd15b048SBenjamin Herrenschmidt } 1889cd15b048SBenjamin Herrenschmidt 189053522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1891fe7e85c6SGavin Shan { 189253522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 189353522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1894fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1895fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1896fe7e85c6SGavin Shan u64 end, mask; 1897fe7e85c6SGavin Shan 1898fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1899fe7e85c6SGavin Shan return 0; 1900fe7e85c6SGavin Shan 1901fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1902fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1903fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1904fe7e85c6SGavin Shan 1905fe7e85c6SGavin Shan 1906fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1907fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1908fe7e85c6SGavin Shan mask += mask - 1; 1909fe7e85c6SGavin Shan 1910fe7e85c6SGavin Shan return mask; 1911fe7e85c6SGavin Shan } 1912fe7e85c6SGavin Shan 19135eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 191474251fe2SBenjamin Herrenschmidt { 191574251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 191674251fe2SBenjamin Herrenschmidt 191774251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1918b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1919e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 1920dff4a39eSGavin Shan 19215c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 19225eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 192374251fe2SBenjamin Herrenschmidt } 192474251fe2SBenjamin Herrenschmidt } 192574251fe2SBenjamin Herrenschmidt 1926fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1927fd141d1aSBenjamin Herrenschmidt bool real_mode) 1928fd141d1aSBenjamin Herrenschmidt { 1929fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1930fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1931fd141d1aSBenjamin Herrenschmidt } 1932fd141d1aSBenjamin Herrenschmidt 1933a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1934decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19354cce9550SGavin Shan { 19360eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19370eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19380eaf4defSAlexey Kardashevskiy next); 19390eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1940b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1941fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19424cce9550SGavin Shan unsigned long start, end, inc; 19434cce9550SGavin Shan 1944decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1945decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1946decbda25SAlexey Kardashevskiy npages - 1); 19474cce9550SGavin Shan 19484cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19494cce9550SGavin Shan start |= (1ull << 63); 19504cce9550SGavin Shan end |= (1ull << 63); 19514cce9550SGavin Shan inc = 16; 19524cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19534cce9550SGavin Shan 19544cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19554cce9550SGavin Shan while (start <= end) { 19568e0a1611SAlexey Kardashevskiy if (rm) 1957001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19588e0a1611SAlexey Kardashevskiy else 1959001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1960001ff2eeSMichael Ellerman 19614cce9550SGavin Shan start += inc; 19624cce9550SGavin Shan } 19634cce9550SGavin Shan 19644cce9550SGavin Shan /* 19654cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19664cce9550SGavin Shan * and we don't care on free() 19674cce9550SGavin Shan */ 19684cce9550SGavin Shan } 19694cce9550SGavin Shan 1970decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1971decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1972decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 197300085f1eSKrzysztof Kozlowski unsigned long attrs) 1974decbda25SAlexey Kardashevskiy { 1975decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1976decbda25SAlexey Kardashevskiy attrs); 1977decbda25SAlexey Kardashevskiy 197808acce1cSBenjamin Herrenschmidt if (!ret) 1979a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1980decbda25SAlexey Kardashevskiy 1981decbda25SAlexey Kardashevskiy return ret; 1982decbda25SAlexey Kardashevskiy } 1983decbda25SAlexey Kardashevskiy 198405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 198505c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 198605c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 198705c6cfb9SAlexey Kardashevskiy { 1988a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 198905c6cfb9SAlexey Kardashevskiy 199008acce1cSBenjamin Herrenschmidt if (!ret) 1991a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 199205c6cfb9SAlexey Kardashevskiy 199305c6cfb9SAlexey Kardashevskiy return ret; 199405c6cfb9SAlexey Kardashevskiy } 1995a540aa56SAlexey Kardashevskiy 1996a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 1997a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 1998a540aa56SAlexey Kardashevskiy { 1999a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 2000a540aa56SAlexey Kardashevskiy 2001a540aa56SAlexey Kardashevskiy if (!ret) 2002a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 2003a540aa56SAlexey Kardashevskiy 2004a540aa56SAlexey Kardashevskiy return ret; 2005a540aa56SAlexey Kardashevskiy } 200605c6cfb9SAlexey Kardashevskiy #endif 200705c6cfb9SAlexey Kardashevskiy 2008decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 2009decbda25SAlexey Kardashevskiy long npages) 2010decbda25SAlexey Kardashevskiy { 2011decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2012decbda25SAlexey Kardashevskiy 2013a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2014decbda25SAlexey Kardashevskiy } 2015decbda25SAlexey Kardashevskiy 2016da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2017decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 201805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 201905c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 2020a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 2021090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 202205c6cfb9SAlexey Kardashevskiy #endif 2023decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 2024da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2025da004c36SAlexey Kardashevskiy }; 2026da004c36SAlexey Kardashevskiy 2027a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2028a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2029a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2030bef9253fSAlexey Kardashevskiy 20316b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20320bbcdb43SAlexey Kardashevskiy { 2033fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2034a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 20350bbcdb43SAlexey Kardashevskiy 20360bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 20370bbcdb43SAlexey Kardashevskiy if (rm) 2038001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 20390bbcdb43SAlexey Kardashevskiy else 2040001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20410bbcdb43SAlexey Kardashevskiy } 20420bbcdb43SAlexey Kardashevskiy 2043a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20445780fb04SAlexey Kardashevskiy { 20455780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2046fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2047a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20485780fb04SAlexey Kardashevskiy 20495780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2050001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20515780fb04SAlexey Kardashevskiy } 20525780fb04SAlexey Kardashevskiy 2053fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2054fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2055fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20564cce9550SGavin Shan { 20574d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20584cce9550SGavin Shan unsigned long start, end, inc; 20594cce9550SGavin Shan 20604cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2061a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2062fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20634cce9550SGavin Shan end = start; 20644cce9550SGavin Shan 20654cce9550SGavin Shan /* Figure out the start, end and step */ 2066decbda25SAlexey Kardashevskiy start |= (index << shift); 2067decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2068b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20694cce9550SGavin Shan mb(); 20704cce9550SGavin Shan 20714cce9550SGavin Shan while (start <= end) { 20728e0a1611SAlexey Kardashevskiy if (rm) 2073001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 20748e0a1611SAlexey Kardashevskiy else 2075001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 20764cce9550SGavin Shan start += inc; 20774cce9550SGavin Shan } 20784cce9550SGavin Shan } 20794cce9550SGavin Shan 2080f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2081f0228c41SBenjamin Herrenschmidt { 2082f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2083f0228c41SBenjamin Herrenschmidt 2084f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2085f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2086f0228c41SBenjamin Herrenschmidt else 2087f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2088f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2089f0228c41SBenjamin Herrenschmidt } 2090f0228c41SBenjamin Herrenschmidt 2091e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2092e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2093e57080f1SAlexey Kardashevskiy { 2094e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2095e57080f1SAlexey Kardashevskiy 2096a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2097e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2098e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2099f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2100f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2101f0228c41SBenjamin Herrenschmidt 2102616badd2SAlistair Popple /* 2103616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2104616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2105616badd2SAlistair Popple * should go via the OPAL call. 2106616badd2SAlistair Popple */ 2107616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 21080bbcdb43SAlexey Kardashevskiy /* 21090bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 21100bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 21110bbcdb43SAlexey Kardashevskiy * the entire cache for it. 21120bbcdb43SAlexey Kardashevskiy */ 2113f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21145d2aa710SAlistair Popple continue; 21155d2aa710SAlistair Popple } 2116f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2117f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 211885674868SAlexey Kardashevskiy index, npages); 2119f0228c41SBenjamin Herrenschmidt else 2120f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2121f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2122f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2123f0228c41SBenjamin Herrenschmidt index << shift, npages); 2124e57080f1SAlexey Kardashevskiy } 2125e57080f1SAlexey Kardashevskiy } 2126e57080f1SAlexey Kardashevskiy 21276b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 21286b3d12a9SAlistair Popple { 21296b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 21306b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21316b3d12a9SAlistair Popple else 21326b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 21336b3d12a9SAlistair Popple } 21346b3d12a9SAlistair Popple 2135decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2136decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2137decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 213800085f1eSKrzysztof Kozlowski unsigned long attrs) 21394cce9550SGavin Shan { 2140decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2141decbda25SAlexey Kardashevskiy attrs); 21424cce9550SGavin Shan 214308acce1cSBenjamin Herrenschmidt if (!ret) 2144decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2145decbda25SAlexey Kardashevskiy 2146decbda25SAlexey Kardashevskiy return ret; 2147decbda25SAlexey Kardashevskiy } 2148decbda25SAlexey Kardashevskiy 214905c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 215005c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 215105c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 215205c6cfb9SAlexey Kardashevskiy { 2153a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 215405c6cfb9SAlexey Kardashevskiy 215508acce1cSBenjamin Herrenschmidt if (!ret) 215605c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 215705c6cfb9SAlexey Kardashevskiy 215805c6cfb9SAlexey Kardashevskiy return ret; 215905c6cfb9SAlexey Kardashevskiy } 2160a540aa56SAlexey Kardashevskiy 2161a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2162a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2163a540aa56SAlexey Kardashevskiy { 2164a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 2165a540aa56SAlexey Kardashevskiy 2166a540aa56SAlexey Kardashevskiy if (!ret) 2167a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2168a540aa56SAlexey Kardashevskiy 2169a540aa56SAlexey Kardashevskiy return ret; 2170a540aa56SAlexey Kardashevskiy } 217105c6cfb9SAlexey Kardashevskiy #endif 217205c6cfb9SAlexey Kardashevskiy 2173decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2174decbda25SAlexey Kardashevskiy long npages) 2175decbda25SAlexey Kardashevskiy { 2176decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2177decbda25SAlexey Kardashevskiy 2178decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 21794cce9550SGavin Shan } 21804cce9550SGavin Shan 2181da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2182decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 218305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 218405c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2185a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 2186090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 218705c6cfb9SAlexey Kardashevskiy #endif 2188decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2189da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2190da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 2191da004c36SAlexey Kardashevskiy }; 2192da004c36SAlexey Kardashevskiy 2193801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2194801846d1SGavin Shan { 2195801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2196801846d1SGavin Shan 2197801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2198801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2199801846d1SGavin Shan */ 2200801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2201801846d1SGavin Shan return 0; 2202801846d1SGavin Shan 2203801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2204801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2205801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2206801846d1SGavin Shan *weight += 3; 2207801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2208801846d1SGavin Shan *weight += 15; 2209801846d1SGavin Shan else 2210801846d1SGavin Shan *weight += 10; 2211801846d1SGavin Shan 2212801846d1SGavin Shan return 0; 2213801846d1SGavin Shan } 2214801846d1SGavin Shan 2215801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2216801846d1SGavin Shan { 2217801846d1SGavin Shan unsigned int weight = 0; 2218801846d1SGavin Shan 2219801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2220801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2221801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2222801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2223801846d1SGavin Shan return weight; 2224801846d1SGavin Shan } 2225801846d1SGavin Shan #endif 2226801846d1SGavin Shan 2227801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2228801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2229801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2230801846d1SGavin Shan struct pci_dev *pdev; 2231801846d1SGavin Shan 2232801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2233801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2234801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2235801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2236801846d1SGavin Shan } 2237801846d1SGavin Shan 2238801846d1SGavin Shan return weight; 2239801846d1SGavin Shan } 2240801846d1SGavin Shan 2241b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 22422b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2243184cd4a3SBenjamin Herrenschmidt { 2244184cd4a3SBenjamin Herrenschmidt 2245184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2246184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22472b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22482b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2249184cd4a3SBenjamin Herrenschmidt int64_t rc; 2250184cd4a3SBenjamin Herrenschmidt void *addr; 2251184cd4a3SBenjamin Herrenschmidt 2252184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2253184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2254184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22552b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22562b923ed1SGavin Shan if (!weight) 22572b923ed1SGavin Shan return; 2258184cd4a3SBenjamin Herrenschmidt 22592b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22602b923ed1SGavin Shan &total_weight); 22612b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22622b923ed1SGavin Shan if (!segs) 22632b923ed1SGavin Shan segs = 1; 22642b923ed1SGavin Shan 22652b923ed1SGavin Shan /* 22662b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22672b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22682b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22692b923ed1SGavin Shan * is allocated successfully. 22702b923ed1SGavin Shan */ 22712b923ed1SGavin Shan do { 22722b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22732b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22742b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22752b923ed1SGavin Shan IODA_INVALID_PE) 22762b923ed1SGavin Shan avail++; 22772b923ed1SGavin Shan } 22782b923ed1SGavin Shan 22792b923ed1SGavin Shan if (avail == segs) 22802b923ed1SGavin Shan goto found; 22812b923ed1SGavin Shan } 22822b923ed1SGavin Shan } while (--segs); 22832b923ed1SGavin Shan 22842b923ed1SGavin Shan if (!segs) { 22852b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 22862b923ed1SGavin Shan return; 22872b923ed1SGavin Shan } 22882b923ed1SGavin Shan 22892b923ed1SGavin Shan found: 22900eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 229182eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 229282eae1afSAlexey Kardashevskiy return; 229382eae1afSAlexey Kardashevskiy 2294b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2295b348aa65SAlexey Kardashevskiy pe->pe_number); 22960eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2297c5773822SAlexey Kardashevskiy 2298184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 22992b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 23002b923ed1SGavin Shan weight, total_weight, base, segs); 2301184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2302acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2303acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2304184cd4a3SBenjamin Herrenschmidt 2305184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2306184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2307184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2308184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2309acce971cSGavin Shan * 2310acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2311acce971cSGavin Shan * bytes 2312184cd4a3SBenjamin Herrenschmidt */ 2313acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2314184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2315acce971cSGavin Shan get_order(tce32_segsz * segs)); 2316184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2317184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2318184cd4a3SBenjamin Herrenschmidt goto fail; 2319184cd4a3SBenjamin Herrenschmidt } 2320184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2321acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2322184cd4a3SBenjamin Herrenschmidt 2323184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2324184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2325184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2326184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2327184cd4a3SBenjamin Herrenschmidt base + i, 1, 2328acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2329acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2330184cd4a3SBenjamin Herrenschmidt if (rc) { 2331184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2332184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2333184cd4a3SBenjamin Herrenschmidt goto fail; 2334184cd4a3SBenjamin Herrenschmidt } 2335184cd4a3SBenjamin Herrenschmidt } 2336184cd4a3SBenjamin Herrenschmidt 23372b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 23382b923ed1SGavin Shan for (i = base; i < base + segs; i++) 23392b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 23402b923ed1SGavin Shan 2341184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2342acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2343acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2344acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2345184cd4a3SBenjamin Herrenschmidt 2346da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23474793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23484793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2349184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2350184cd4a3SBenjamin Herrenschmidt 2351f21b0a45SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 23525eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 235374251fe2SBenjamin Herrenschmidt 2354184cd4a3SBenjamin Herrenschmidt return; 2355184cd4a3SBenjamin Herrenschmidt fail: 2356184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2357184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2358acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23590eaf4defSAlexey Kardashevskiy if (tbl) { 23600eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2361e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23620eaf4defSAlexey Kardashevskiy } 2363184cd4a3SBenjamin Herrenschmidt } 2364184cd4a3SBenjamin Herrenschmidt 236543cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 236643cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 236743cb60abSAlexey Kardashevskiy { 236843cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 236943cb60abSAlexey Kardashevskiy table_group); 237043cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 237143cb60abSAlexey Kardashevskiy int64_t rc; 2372bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2373bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 237443cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 237543cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 237643cb60abSAlexey Kardashevskiy 23774793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 237843cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 237943cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 238043cb60abSAlexey Kardashevskiy 238143cb60abSAlexey Kardashevskiy /* 238243cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 238343cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 238443cb60abSAlexey Kardashevskiy */ 238543cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 238643cb60abSAlexey Kardashevskiy pe->pe_number, 23874793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2388bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 238943cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2390bbb845c4SAlexey Kardashevskiy size << 3, 239143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 239243cb60abSAlexey Kardashevskiy if (rc) { 239343cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 239443cb60abSAlexey Kardashevskiy return rc; 239543cb60abSAlexey Kardashevskiy } 239643cb60abSAlexey Kardashevskiy 239743cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 239843cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2399ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 240043cb60abSAlexey Kardashevskiy 240143cb60abSAlexey Kardashevskiy return 0; 240243cb60abSAlexey Kardashevskiy } 240343cb60abSAlexey Kardashevskiy 240425529100SFrederic Barrat void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2405cd15b048SBenjamin Herrenschmidt { 2406cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2407cd15b048SBenjamin Herrenschmidt int64_t rc; 2408cd15b048SBenjamin Herrenschmidt 2409cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2410cd15b048SBenjamin Herrenschmidt if (enable) { 2411cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2412cd15b048SBenjamin Herrenschmidt 2413cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2414cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2415cd15b048SBenjamin Herrenschmidt pe->pe_number, 2416cd15b048SBenjamin Herrenschmidt window_id, 2417cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2418cd15b048SBenjamin Herrenschmidt top); 2419cd15b048SBenjamin Herrenschmidt } else { 2420cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2421cd15b048SBenjamin Herrenschmidt pe->pe_number, 2422cd15b048SBenjamin Herrenschmidt window_id, 2423cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2424cd15b048SBenjamin Herrenschmidt 0); 2425cd15b048SBenjamin Herrenschmidt } 2426cd15b048SBenjamin Herrenschmidt if (rc) 2427cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2428cd15b048SBenjamin Herrenschmidt else 2429cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2430cd15b048SBenjamin Herrenschmidt } 2431cd15b048SBenjamin Herrenschmidt 24324793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 24334793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2434090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 24354793d65dSAlexey Kardashevskiy { 24364793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 24374793d65dSAlexey Kardashevskiy table_group); 24384793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 24394793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 24404793d65dSAlexey Kardashevskiy long ret; 24414793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 24424793d65dSAlexey Kardashevskiy 24434793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24444793d65dSAlexey Kardashevskiy if (!tbl) 24454793d65dSAlexey Kardashevskiy return -ENOMEM; 24464793d65dSAlexey Kardashevskiy 244711edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 244811edf116SAlexey Kardashevskiy 24494793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24504793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 2451090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 24524793d65dSAlexey Kardashevskiy if (ret) { 2453e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24544793d65dSAlexey Kardashevskiy return ret; 24554793d65dSAlexey Kardashevskiy } 24564793d65dSAlexey Kardashevskiy 24574793d65dSAlexey Kardashevskiy *ptbl = tbl; 24584793d65dSAlexey Kardashevskiy 24594793d65dSAlexey Kardashevskiy return 0; 24604793d65dSAlexey Kardashevskiy } 24614793d65dSAlexey Kardashevskiy 246246d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 246346d3e1e1SAlexey Kardashevskiy { 246446d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 246546d3e1e1SAlexey Kardashevskiy long rc; 246646d3e1e1SAlexey Kardashevskiy 2467bb005455SNishanth Aravamudan /* 2468fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2469fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2470fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2471fa144869SNishanth Aravamudan */ 2472fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2473fa144869SNishanth Aravamudan 2474fa144869SNishanth Aravamudan /* 2475bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2476bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2477bb005455SNishanth Aravamudan * cause errors later. 2478bb005455SNishanth Aravamudan */ 2479fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2480bb005455SNishanth Aravamudan 248146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 248246d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2483bb005455SNishanth Aravamudan window_size, 2484090bad39SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl); 248546d3e1e1SAlexey Kardashevskiy if (rc) { 248646d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 248746d3e1e1SAlexey Kardashevskiy rc); 248846d3e1e1SAlexey Kardashevskiy return rc; 248946d3e1e1SAlexey Kardashevskiy } 249046d3e1e1SAlexey Kardashevskiy 249146d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 249246d3e1e1SAlexey Kardashevskiy 249346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 249446d3e1e1SAlexey Kardashevskiy if (rc) { 249546d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 249646d3e1e1SAlexey Kardashevskiy rc); 2497e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 249846d3e1e1SAlexey Kardashevskiy return rc; 249946d3e1e1SAlexey Kardashevskiy } 250046d3e1e1SAlexey Kardashevskiy 250146d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 250246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 250346d3e1e1SAlexey Kardashevskiy 250446d3e1e1SAlexey Kardashevskiy return 0; 250546d3e1e1SAlexey Kardashevskiy } 250646d3e1e1SAlexey Kardashevskiy 2507b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2508b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2509b5926430SAlexey Kardashevskiy int num) 2510b5926430SAlexey Kardashevskiy { 2511b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2512b5926430SAlexey Kardashevskiy table_group); 2513b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2514b5926430SAlexey Kardashevskiy long ret; 2515b5926430SAlexey Kardashevskiy 2516b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2517b5926430SAlexey Kardashevskiy 2518b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2519b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2520b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2521b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2522b5926430SAlexey Kardashevskiy if (ret) 2523b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2524b5926430SAlexey Kardashevskiy else 2525ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2526b5926430SAlexey Kardashevskiy 2527b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2528b5926430SAlexey Kardashevskiy 2529b5926430SAlexey Kardashevskiy return ret; 2530b5926430SAlexey Kardashevskiy } 2531b5926430SAlexey Kardashevskiy #endif 2532b5926430SAlexey Kardashevskiy 2533f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 25340bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 253500547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 253600547193SAlexey Kardashevskiy { 253700547193SAlexey Kardashevskiy unsigned long bytes = 0; 253800547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 253900547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 254000547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 254100547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 254200547193SAlexey Kardashevskiy unsigned long direct_table_size; 254300547193SAlexey Kardashevskiy 254400547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 254500547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 254600547193SAlexey Kardashevskiy return 0; 254700547193SAlexey Kardashevskiy 254800547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 254900547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 255000547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 255100547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 255200547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 255300547193SAlexey Kardashevskiy 255400547193SAlexey Kardashevskiy for ( ; levels; --levels) { 255500547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 255600547193SAlexey Kardashevskiy 255700547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 255800547193SAlexey Kardashevskiy tce_table_size <<= 3; 2559e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2560e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 256100547193SAlexey Kardashevskiy } 256200547193SAlexey Kardashevskiy 2563090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2564090bad39SAlexey Kardashevskiy } 2565090bad39SAlexey Kardashevskiy 2566090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2567090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2568090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2569090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2570090bad39SAlexey Kardashevskiy { 2571090bad39SAlexey Kardashevskiy return pnv_pci_ioda2_create_table(table_group, 2572090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 257300547193SAlexey Kardashevskiy } 257400547193SAlexey Kardashevskiy 2575f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2576cd15b048SBenjamin Herrenschmidt { 2577f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2578f87a8864SAlexey Kardashevskiy table_group); 257946d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 258046d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2581cd15b048SBenjamin Herrenschmidt 2582f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 258346d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2584db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25855eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2586e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2587cd15b048SBenjamin Herrenschmidt } 2588cd15b048SBenjamin Herrenschmidt 2589f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2590f87a8864SAlexey Kardashevskiy { 2591f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2592f87a8864SAlexey Kardashevskiy table_group); 2593f87a8864SAlexey Kardashevskiy 259446d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2595db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25965eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2597f87a8864SAlexey Kardashevskiy } 2598f87a8864SAlexey Kardashevskiy 2599f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 260000547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2601090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 26024793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 26034793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2604f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2605f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2606f87a8864SAlexey Kardashevskiy }; 2607b5cb9ab1SAlexey Kardashevskiy 26085eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe, 26090bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, 26105eada8a3SAlexey Kardashevskiy struct pci_bus *bus) 26115eada8a3SAlexey Kardashevskiy { 26125eada8a3SAlexey Kardashevskiy struct pci_dev *dev; 26135eada8a3SAlexey Kardashevskiy 26145eada8a3SAlexey Kardashevskiy list_for_each_entry(dev, &bus->devices, bus_list) { 26150bd97167SAlexey Kardashevskiy iommu_add_device(table_group, &dev->dev); 26165eada8a3SAlexey Kardashevskiy 26175eada8a3SAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 26185eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, 26190bd97167SAlexey Kardashevskiy table_group, dev->subordinate); 26205eada8a3SAlexey Kardashevskiy } 26215eada8a3SAlexey Kardashevskiy } 26225eada8a3SAlexey Kardashevskiy 26230bd97167SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 26240bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, struct pci_bus *bus) 26255eada8a3SAlexey Kardashevskiy { 26265eada8a3SAlexey Kardashevskiy 26275eada8a3SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 26280bd97167SAlexey Kardashevskiy iommu_add_device(table_group, &pe->pdev->dev); 26290bd97167SAlexey Kardashevskiy 26300bd97167SAlexey Kardashevskiy if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus) 26310bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group, 26320bd97167SAlexey Kardashevskiy bus); 26335eada8a3SAlexey Kardashevskiy } 26345eada8a3SAlexey Kardashevskiy 26350bd97167SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 26360bd97167SAlexey Kardashevskiy 2637b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2638b5cb9ab1SAlexey Kardashevskiy { 26390bd97167SAlexey Kardashevskiy struct pci_controller *hose; 2640b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 26410bd97167SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 2642b5cb9ab1SAlexey Kardashevskiy 2643b5cb9ab1SAlexey Kardashevskiy /* 26445eada8a3SAlexey Kardashevskiy * There are 4 types of PEs: 26455eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS: a downstream port with an adapter, 26465eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 26475eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it, 26485eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 26495eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_VF: a SRIOV virtual function, 26505eada8a3SAlexey Kardashevskiy * created from pnv_pcibios_sriov_enable(); 26515eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_DEV: an NPU or OCAPI device, 26525eada8a3SAlexey Kardashevskiy * created from pnv_pci_ioda_fixup(). 26535eada8a3SAlexey Kardashevskiy * 26545eada8a3SAlexey Kardashevskiy * Normally a PE is represented by an IOMMU group, however for 26555eada8a3SAlexey Kardashevskiy * devices with side channels the groups need to be more strict. 26565eada8a3SAlexey Kardashevskiy */ 26575eada8a3SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 26585eada8a3SAlexey Kardashevskiy phb = hose->private_data; 26595eada8a3SAlexey Kardashevskiy 26605eada8a3SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU_NVLINK) 26615eada8a3SAlexey Kardashevskiy continue; 26625eada8a3SAlexey Kardashevskiy 26630bd97167SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 26640bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group; 26650bd97167SAlexey Kardashevskiy 26660bd97167SAlexey Kardashevskiy table_group = pnv_try_setup_npu_table_group(pe); 26670bd97167SAlexey Kardashevskiy if (!table_group) { 26680bd97167SAlexey Kardashevskiy if (!pnv_pci_ioda_pe_dma_weight(pe)) 26690bd97167SAlexey Kardashevskiy continue; 26700bd97167SAlexey Kardashevskiy 26710bd97167SAlexey Kardashevskiy table_group = &pe->table_group; 26720bd97167SAlexey Kardashevskiy iommu_register_group(&pe->table_group, 26730bd97167SAlexey Kardashevskiy pe->phb->hose->global_number, 26740bd97167SAlexey Kardashevskiy pe->pe_number); 26750bd97167SAlexey Kardashevskiy } 26760bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe, table_group, 26770bd97167SAlexey Kardashevskiy pe->pbus); 26780bd97167SAlexey Kardashevskiy } 26795eada8a3SAlexey Kardashevskiy } 26805eada8a3SAlexey Kardashevskiy 26815eada8a3SAlexey Kardashevskiy /* 2682b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2683b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2684b5cb9ab1SAlexey Kardashevskiy */ 26850bd97167SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 26860bd97167SAlexey Kardashevskiy unsigned long pgsizes; 26870bd97167SAlexey Kardashevskiy 2688b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2689b5cb9ab1SAlexey Kardashevskiy 26907f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2691b5cb9ab1SAlexey Kardashevskiy continue; 2692b5cb9ab1SAlexey Kardashevskiy 26930bd97167SAlexey Kardashevskiy pgsizes = pnv_ioda_parse_tce_sizes(phb); 2694b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 26950bd97167SAlexey Kardashevskiy /* 26960bd97167SAlexey Kardashevskiy * IODA2 bridges get this set up from 26970bd97167SAlexey Kardashevskiy * pci_controller_ops::setup_bridge but NPU bridges 26980bd97167SAlexey Kardashevskiy * do not have this hook defined so we do it here. 26990bd97167SAlexey Kardashevskiy */ 27000bd97167SAlexey Kardashevskiy pe->table_group.pgsizes = pgsizes; 27010bd97167SAlexey Kardashevskiy pnv_npu_compound_attach(pe); 2702b5cb9ab1SAlexey Kardashevskiy } 2703b5cb9ab1SAlexey Kardashevskiy } 2704b5cb9ab1SAlexey Kardashevskiy } 2705b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2706b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2707f87a8864SAlexey Kardashevskiy #endif 2708f87a8864SAlexey Kardashevskiy 27097ef73cd3SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 27107ef73cd3SAlexey Kardashevskiy { 27117ef73cd3SAlexey Kardashevskiy struct pci_controller *hose = phb->hose; 27127ef73cd3SAlexey Kardashevskiy struct device_node *dn = hose->dn; 27137ef73cd3SAlexey Kardashevskiy unsigned long mask = 0; 27147ef73cd3SAlexey Kardashevskiy int i, rc, count; 27157ef73cd3SAlexey Kardashevskiy u32 val; 27167ef73cd3SAlexey Kardashevskiy 27177ef73cd3SAlexey Kardashevskiy count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 27187ef73cd3SAlexey Kardashevskiy if (count <= 0) { 27197ef73cd3SAlexey Kardashevskiy mask = SZ_4K | SZ_64K; 27207ef73cd3SAlexey Kardashevskiy /* Add 16M for POWER8 by default */ 27217ef73cd3SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_ARCH_207S) && 27227ef73cd3SAlexey Kardashevskiy !cpu_has_feature(CPU_FTR_ARCH_300)) 272300c376fdSAlexey Kardashevskiy mask |= SZ_16M | SZ_256M; 27247ef73cd3SAlexey Kardashevskiy return mask; 27257ef73cd3SAlexey Kardashevskiy } 27267ef73cd3SAlexey Kardashevskiy 27277ef73cd3SAlexey Kardashevskiy for (i = 0; i < count; i++) { 27287ef73cd3SAlexey Kardashevskiy rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 27297ef73cd3SAlexey Kardashevskiy i, &val); 27307ef73cd3SAlexey Kardashevskiy if (rc == 0) 27317ef73cd3SAlexey Kardashevskiy mask |= 1ULL << val; 27327ef73cd3SAlexey Kardashevskiy } 27337ef73cd3SAlexey Kardashevskiy 27347ef73cd3SAlexey Kardashevskiy return mask; 27357ef73cd3SAlexey Kardashevskiy } 27367ef73cd3SAlexey Kardashevskiy 2737373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2738373f5657SGavin Shan struct pnv_ioda_pe *pe) 2739373f5657SGavin Shan { 2740373f5657SGavin Shan int64_t rc; 2741373f5657SGavin Shan 2742ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2743ccd1c191SGavin Shan return; 2744ccd1c191SGavin Shan 2745f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2746f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2747f87a8864SAlexey Kardashevskiy 2748373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2749373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2750aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2751373f5657SGavin Shan 2752e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 27534793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 27544793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 27554793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 27564793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 27574793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 27587ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2759e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2760e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2761e5aad1e6SAlexey Kardashevskiy #endif 2762e5aad1e6SAlexey Kardashevskiy 276346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2764801846d1SGavin Shan if (rc) 276546d3e1e1SAlexey Kardashevskiy return; 276646d3e1e1SAlexey Kardashevskiy 276720f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 27685eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2769373f5657SGavin Shan } 2770373f5657SGavin Shan 27714ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2772137436c9SGavin Shan { 2773137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2774137436c9SGavin Shan ioda.irq_chip); 2775137436c9SGavin Shan 27764ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 27774ee11c1aSSuresh Warrier } 27784ee11c1aSSuresh Warrier 27794ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 27804ee11c1aSSuresh Warrier { 27814ee11c1aSSuresh Warrier int64_t rc; 27824ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 27834ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 27844ee11c1aSSuresh Warrier 27854ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2786137436c9SGavin Shan WARN_ON_ONCE(rc); 2787137436c9SGavin Shan 2788137436c9SGavin Shan icp_native_eoi(d); 2789137436c9SGavin Shan } 2790137436c9SGavin Shan 2791fd9a1c26SIan Munsie 2792f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2793fd9a1c26SIan Munsie { 2794fd9a1c26SIan Munsie struct irq_data *idata; 2795fd9a1c26SIan Munsie struct irq_chip *ichip; 2796fd9a1c26SIan Munsie 2797fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2798fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2799fd9a1c26SIan Munsie return; 2800fd9a1c26SIan Munsie 2801fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2802fd9a1c26SIan Munsie /* 2803fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2804fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2805fd9a1c26SIan Munsie */ 2806fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2807fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2808fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2809fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2810fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2811fd9a1c26SIan Munsie } 2812fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2813fd9a1c26SIan Munsie } 2814fd9a1c26SIan Munsie 28154ee11c1aSSuresh Warrier /* 28164ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 28174ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 28184ee11c1aSSuresh Warrier */ 28194ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 28204ee11c1aSSuresh Warrier { 28214ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 28224ee11c1aSSuresh Warrier } 28234ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 28244ee11c1aSSuresh Warrier 2825184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2826137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2827137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2828184cd4a3SBenjamin Herrenschmidt { 2829184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2830184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 28313a1a4661SBenjamin Herrenschmidt __be32 data; 2832184cd4a3SBenjamin Herrenschmidt int rc; 2833184cd4a3SBenjamin Herrenschmidt 2834184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2835184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2836184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2837184cd4a3SBenjamin Herrenschmidt 2838184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2839184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2840184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2841184cd4a3SBenjamin Herrenschmidt 2842b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 284336074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2844b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2845b72c1f65SBenjamin Herrenschmidt 2846184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2847184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2848184cd4a3SBenjamin Herrenschmidt if (rc) { 2849184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2850184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2851184cd4a3SBenjamin Herrenschmidt return -EIO; 2852184cd4a3SBenjamin Herrenschmidt } 2853184cd4a3SBenjamin Herrenschmidt 2854184cd4a3SBenjamin Herrenschmidt if (is_64) { 28553a1a4661SBenjamin Herrenschmidt __be64 addr64; 28563a1a4661SBenjamin Herrenschmidt 2857184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2858184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2859184cd4a3SBenjamin Herrenschmidt if (rc) { 2860184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2861184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2862184cd4a3SBenjamin Herrenschmidt return -EIO; 2863184cd4a3SBenjamin Herrenschmidt } 28643a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28653a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2866184cd4a3SBenjamin Herrenschmidt } else { 28673a1a4661SBenjamin Herrenschmidt __be32 addr32; 28683a1a4661SBenjamin Herrenschmidt 2869184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2870184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2871184cd4a3SBenjamin Herrenschmidt if (rc) { 2872184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2873184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2874184cd4a3SBenjamin Herrenschmidt return -EIO; 2875184cd4a3SBenjamin Herrenschmidt } 2876184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28773a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2878184cd4a3SBenjamin Herrenschmidt } 28793a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2880184cd4a3SBenjamin Herrenschmidt 2881f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2882137436c9SGavin Shan 2883184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 28841f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2885184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2886184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2887184cd4a3SBenjamin Herrenschmidt 2888184cd4a3SBenjamin Herrenschmidt return 0; 2889184cd4a3SBenjamin Herrenschmidt } 2890184cd4a3SBenjamin Herrenschmidt 2891184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2892184cd4a3SBenjamin Herrenschmidt { 2893fb1b55d6SGavin Shan unsigned int count; 2894184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2895184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2896184cd4a3SBenjamin Herrenschmidt if (!prop) { 2897184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2898184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2899184cd4a3SBenjamin Herrenschmidt } 2900184cd4a3SBenjamin Herrenschmidt if (!prop) 2901184cd4a3SBenjamin Herrenschmidt return; 2902184cd4a3SBenjamin Herrenschmidt 2903184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2904fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2905fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2906184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2907184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2908184cd4a3SBenjamin Herrenschmidt return; 2909184cd4a3SBenjamin Herrenschmidt } 2910fb1b55d6SGavin Shan 2911184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2912184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2913184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2914fb1b55d6SGavin Shan count, phb->msi_base); 2915184cd4a3SBenjamin Herrenschmidt } 2916184cd4a3SBenjamin Herrenschmidt 29176e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29186e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29196e628c7dSWei Yang { 2920f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2921f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2922f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29236e628c7dSWei Yang struct resource *res; 29246e628c7dSWei Yang int i; 2925dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29266e628c7dSWei Yang struct pci_dn *pdn; 29275b88ec22SWei Yang int mul, total_vfs; 29286e628c7dSWei Yang 292944bda4b7SHari Vyas if (!pdev->is_physfn || pci_dev_is_added(pdev)) 29306e628c7dSWei Yang return; 29316e628c7dSWei Yang 29326e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29336e628c7dSWei Yang pdn->vfs_expanded = 0; 2934ee8222feSWei Yang pdn->m64_single_mode = false; 29356e628c7dSWei Yang 29365b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 293792b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2938dfcc8d45SWei Yang total_vf_bar_sz = 0; 29395b88ec22SWei Yang 29405b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29415b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29425b88ec22SWei Yang if (!res->flags || res->parent) 29435b88ec22SWei Yang continue; 2944b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 2945b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2946b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29475b88ec22SWei Yang i, res); 2948b0331854SWei Yang goto truncate_iov; 29495b88ec22SWei Yang } 29505b88ec22SWei Yang 2951dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2952dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29535b88ec22SWei Yang 2954f2dd0afeSWei Yang /* 2955f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2956f2dd0afeSWei Yang * power of two. 2957f2dd0afeSWei Yang * 2958f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2959f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2960f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2961f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2962f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2963f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2964f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2965f2dd0afeSWei Yang */ 2966dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29675b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2968dfcc8d45SWei Yang dev_info(&pdev->dev, 2969dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2970dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2971ee8222feSWei Yang pdn->m64_single_mode = true; 29725b88ec22SWei Yang break; 29735b88ec22SWei Yang } 29745b88ec22SWei Yang } 29755b88ec22SWei Yang 29766e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29776e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29786e628c7dSWei Yang if (!res->flags || res->parent) 29796e628c7dSWei Yang continue; 29806e628c7dSWei Yang 29816e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2982ee8222feSWei Yang /* 2983ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2984ee8222feSWei Yang * mode is 32MB. 2985ee8222feSWei Yang */ 2986ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2987ee8222feSWei Yang goto truncate_iov; 2988ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29895b88ec22SWei Yang res->end = res->start + size * mul - 1; 29906e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 29916e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 29925b88ec22SWei Yang i, res, mul); 29936e628c7dSWei Yang } 29945b88ec22SWei Yang pdn->vfs_expanded = mul; 2995b0331854SWei Yang 2996b0331854SWei Yang return; 2997b0331854SWei Yang 2998b0331854SWei Yang truncate_iov: 2999b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3000b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3001b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3002b0331854SWei Yang res->flags = 0; 3003b0331854SWei Yang res->end = res->start - 1; 3004b0331854SWei Yang } 30056e628c7dSWei Yang } 30066e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 30076e628c7dSWei Yang 300823e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 300923e79425SGavin Shan struct resource *res) 301011685becSGavin Shan { 301123e79425SGavin Shan struct pnv_phb *phb = pe->phb; 301211685becSGavin Shan struct pci_bus_region region; 301323e79425SGavin Shan int index; 301423e79425SGavin Shan int64_t rc; 301511685becSGavin Shan 301623e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 301723e79425SGavin Shan return; 301811685becSGavin Shan 301911685becSGavin Shan if (res->flags & IORESOURCE_IO) { 302011685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 302111685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 302211685becSGavin Shan index = region.start / phb->ioda.io_segsize; 302311685becSGavin Shan 302492b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 302511685becSGavin Shan region.start <= region.end) { 302611685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 302711685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 302811685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 302911685becSGavin Shan if (rc != OPAL_SUCCESS) { 30301f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 303111685becSGavin Shan __func__, rc, index, pe->pe_number); 303211685becSGavin Shan break; 303311685becSGavin Shan } 303411685becSGavin Shan 303511685becSGavin Shan region.start += phb->ioda.io_segsize; 303611685becSGavin Shan index++; 303711685becSGavin Shan } 3038027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 30395958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 304011685becSGavin Shan region.start = res->start - 304123e79425SGavin Shan phb->hose->mem_offset[0] - 304211685becSGavin Shan phb->ioda.m32_pci_base; 304311685becSGavin Shan region.end = res->end - 304423e79425SGavin Shan phb->hose->mem_offset[0] - 304511685becSGavin Shan phb->ioda.m32_pci_base; 304611685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 304711685becSGavin Shan 304892b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 304911685becSGavin Shan region.start <= region.end) { 305011685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 305111685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 305211685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 305311685becSGavin Shan if (rc != OPAL_SUCCESS) { 30541f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 305511685becSGavin Shan __func__, rc, index, pe->pe_number); 305611685becSGavin Shan break; 305711685becSGavin Shan } 305811685becSGavin Shan 305911685becSGavin Shan region.start += phb->ioda.m32_segsize; 306011685becSGavin Shan index++; 306111685becSGavin Shan } 306211685becSGavin Shan } 306311685becSGavin Shan } 306423e79425SGavin Shan 306523e79425SGavin Shan /* 306623e79425SGavin Shan * This function is supposed to be called on basis of PE from top 306723e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 306803671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 306923e79425SGavin Shan */ 307023e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 307123e79425SGavin Shan { 307269d733e7SGavin Shan struct pci_dev *pdev; 307323e79425SGavin Shan int i; 307423e79425SGavin Shan 307523e79425SGavin Shan /* 307623e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 307723e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 307823e79425SGavin Shan * be figured out later. 307923e79425SGavin Shan */ 308023e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 308123e79425SGavin Shan 308269d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 308369d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 308469d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 308569d733e7SGavin Shan 308669d733e7SGavin Shan /* 308769d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 308869d733e7SGavin Shan * windows of the child bridges should be mapped to 308969d733e7SGavin Shan * the PE as well. 309069d733e7SGavin Shan */ 309169d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 309269d733e7SGavin Shan continue; 309369d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 309469d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 309569d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 309669d733e7SGavin Shan } 309711685becSGavin Shan } 309811685becSGavin Shan 309998b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 310098b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 310198b665daSRussell Currey { 310298b665daSRussell Currey struct pci_controller *hose; 310398b665daSRussell Currey struct pnv_phb *phb; 310498b665daSRussell Currey s64 ret; 310598b665daSRussell Currey 310698b665daSRussell Currey if (val != 1ULL) 310798b665daSRussell Currey return -EINVAL; 310898b665daSRussell Currey 310998b665daSRussell Currey hose = (struct pci_controller *)data; 311098b665daSRussell Currey if (!hose || !hose->private_data) 311198b665daSRussell Currey return -ENODEV; 311298b665daSRussell Currey 311398b665daSRussell Currey phb = hose->private_data; 311498b665daSRussell Currey 311598b665daSRussell Currey /* Retrieve the diag data from firmware */ 31165cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 31175cb1f8fdSRussell Currey phb->diag_data_size); 311898b665daSRussell Currey if (ret != OPAL_SUCCESS) 311998b665daSRussell Currey return -EIO; 312098b665daSRussell Currey 312198b665daSRussell Currey /* Print the diag data to the kernel log */ 31225cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 312398b665daSRussell Currey return 0; 312498b665daSRussell Currey } 312598b665daSRussell Currey 312698b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 312798b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 312898b665daSRussell Currey 312998b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 313098b665daSRussell Currey 313137c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 313237c367f2SGavin Shan { 313337c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 313437c367f2SGavin Shan struct pci_controller *hose, *tmp; 313537c367f2SGavin Shan struct pnv_phb *phb; 313637c367f2SGavin Shan char name[16]; 313737c367f2SGavin Shan 313837c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 313937c367f2SGavin Shan phb = hose->private_data; 314037c367f2SGavin Shan 3141ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3142ccd1c191SGavin Shan phb->initialized = 1; 3143ccd1c191SGavin Shan 314437c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 314537c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 314698b665daSRussell Currey if (!phb->dbgfs) { 3147f2c2cbccSJoe Perches pr_warn("%s: Error on creating debugfs on PHB#%x\n", 314837c367f2SGavin Shan __func__, hose->global_number); 314998b665daSRussell Currey continue; 315098b665daSRussell Currey } 315198b665daSRussell Currey 315298b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 315398b665daSRussell Currey &pnv_pci_diag_data_fops); 315437c367f2SGavin Shan } 315537c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 315637c367f2SGavin Shan } 315737c367f2SGavin Shan 3158db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 3159db217319SBenjamin Herrenschmidt { 3160db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 3161db217319SBenjamin Herrenschmidt struct pci_bus *child; 3162db217319SBenjamin Herrenschmidt 3163db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 3164db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 3165db217319SBenjamin Herrenschmidt return; 3166db217319SBenjamin Herrenschmidt 3167db217319SBenjamin Herrenschmidt /* 3168db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 3169db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 3170db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 3171db217319SBenjamin Herrenschmidt * fixed. 3172db217319SBenjamin Herrenschmidt */ 3173db217319SBenjamin Herrenschmidt if (dev) { 3174db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 3175db217319SBenjamin Herrenschmidt if (rc) 3176db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 3177db217319SBenjamin Herrenschmidt pci_set_master(dev); 3178db217319SBenjamin Herrenschmidt } 3179db217319SBenjamin Herrenschmidt 3180db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 3181db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 3182db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 3183db217319SBenjamin Herrenschmidt } 3184db217319SBenjamin Herrenschmidt 3185db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 3186db217319SBenjamin Herrenschmidt { 3187db217319SBenjamin Herrenschmidt struct pci_controller *hose; 3188db217319SBenjamin Herrenschmidt 3189db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 3190db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 3191db217319SBenjamin Herrenschmidt } 3192db217319SBenjamin Herrenschmidt 3193cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3194fb446ad0SGavin Shan { 3195fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3196ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 319737c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 319837c367f2SGavin Shan 3199db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 3200db217319SBenjamin Herrenschmidt 3201e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3202b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3203e9cc17d4SGavin Shan #endif 3204fb446ad0SGavin Shan } 3205fb446ad0SGavin Shan 3206271fd03aSGavin Shan /* 3207271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3208271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3209271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3210271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3211271fd03aSGavin Shan * 1MiB for memory) will be returned. 3212271fd03aSGavin Shan * 3213271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3214271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3215271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3216271fd03aSGavin Shan * resources. 3217271fd03aSGavin Shan */ 3218271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3219271fd03aSGavin Shan unsigned long type) 3220271fd03aSGavin Shan { 3221271fd03aSGavin Shan struct pci_dev *bridge; 3222271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3223271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3224271fd03aSGavin Shan int num_pci_bridges = 0; 3225271fd03aSGavin Shan 3226271fd03aSGavin Shan bridge = bus->self; 3227271fd03aSGavin Shan while (bridge) { 3228271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3229271fd03aSGavin Shan num_pci_bridges++; 3230271fd03aSGavin Shan if (num_pci_bridges >= 2) 3231271fd03aSGavin Shan return 1; 3232271fd03aSGavin Shan } 3233271fd03aSGavin Shan 3234271fd03aSGavin Shan bridge = bridge->bus->self; 3235271fd03aSGavin Shan } 3236271fd03aSGavin Shan 32375958d19aSBenjamin Herrenschmidt /* 32385958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 32395958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 32405958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 32415958d19aSBenjamin Herrenschmidt */ 3242b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3243262af557SGuo Chao return phb->ioda.m64_segsize; 3244271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3245271fd03aSGavin Shan return phb->ioda.m32_segsize; 3246271fd03aSGavin Shan 3247271fd03aSGavin Shan return phb->ioda.io_segsize; 3248271fd03aSGavin Shan } 3249271fd03aSGavin Shan 325040e2a47eSGavin Shan /* 325140e2a47eSGavin Shan * We are updating root port or the upstream port of the 325240e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 325340e2a47eSGavin Shan * to accommodate the changes on required resources during 325440e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 325540e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 325640e2a47eSGavin Shan * root port. 325740e2a47eSGavin Shan */ 325840e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 325940e2a47eSGavin Shan unsigned long type) 326040e2a47eSGavin Shan { 326140e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 326240e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 326340e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 326440e2a47eSGavin Shan struct resource *r, *w; 326540e2a47eSGavin Shan bool msi_region = false; 326640e2a47eSGavin Shan int i; 326740e2a47eSGavin Shan 326840e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 326940e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 327040e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 327140e2a47eSGavin Shan return; 327240e2a47eSGavin Shan 327340e2a47eSGavin Shan /* Fixup the resources */ 327440e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 327540e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 327640e2a47eSGavin Shan if (!r->flags || !r->parent) 327740e2a47eSGavin Shan continue; 327840e2a47eSGavin Shan 327940e2a47eSGavin Shan w = NULL; 328040e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 328140e2a47eSGavin Shan w = &hose->io_resource; 32825958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 328340e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 328440e2a47eSGavin Shan phb->ioda.m64_segsize) 328540e2a47eSGavin Shan w = &hose->mem_resources[1]; 328640e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 328740e2a47eSGavin Shan w = &hose->mem_resources[0]; 328840e2a47eSGavin Shan msi_region = true; 328940e2a47eSGavin Shan } 329040e2a47eSGavin Shan 329140e2a47eSGavin Shan r->start = w->start; 329240e2a47eSGavin Shan r->end = w->end; 329340e2a47eSGavin Shan 329440e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 329540e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 329640e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 329740e2a47eSGavin Shan * 329840e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 329940e2a47eSGavin Shan * 32-bits bridge window. 330040e2a47eSGavin Shan */ 330140e2a47eSGavin Shan if (msi_region) { 330240e2a47eSGavin Shan r->end += 0x10000; 330340e2a47eSGavin Shan r->end -= 0x100000; 330440e2a47eSGavin Shan } 330540e2a47eSGavin Shan } 330640e2a47eSGavin Shan } 330740e2a47eSGavin Shan 3308ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3309ccd1c191SGavin Shan { 3310ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3311ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3312ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3313ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3314ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3315ccd1c191SGavin Shan 331640e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 331740e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 331840e2a47eSGavin Shan 331963803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 332063803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 332163803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 332263803c39SGavin Shan if (pe) { 332363803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 332463803c39SGavin Shan phb->ioda.root_pe_populated = true; 332563803c39SGavin Shan } 332663803c39SGavin Shan } 332763803c39SGavin Shan 3328ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3329ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3330ccd1c191SGavin Shan return; 3331ccd1c191SGavin Shan 3332ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3333a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 3334ccd1c191SGavin Shan 3335ccd1c191SGavin Shan /* 3336ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3337ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3338ccd1c191SGavin Shan * not allocate resources again. 3339ccd1c191SGavin Shan */ 3340ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3341ccd1c191SGavin Shan if (!pe) 3342ccd1c191SGavin Shan return; 3343ccd1c191SGavin Shan 3344ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3345ccd1c191SGavin Shan switch (phb->type) { 3346ccd1c191SGavin Shan case PNV_PHB_IODA1: 3347ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3348ccd1c191SGavin Shan break; 3349ccd1c191SGavin Shan case PNV_PHB_IODA2: 3350ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3351ccd1c191SGavin Shan break; 3352ccd1c191SGavin Shan default: 33531f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3354ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3355ccd1c191SGavin Shan } 3356ccd1c191SGavin Shan } 3357ccd1c191SGavin Shan 335838274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 335938274637SYongji Xie { 336038274637SYongji Xie return PAGE_SIZE; 336138274637SYongji Xie } 336238274637SYongji Xie 33635350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 33645350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 33655350ab3fSWei Yang int resno) 33665350ab3fSWei Yang { 3367ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3368ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 33695350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 33707fbe7a93SWei Yang resource_size_t align; 33715350ab3fSWei Yang 33727fbe7a93SWei Yang /* 33737fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 33747fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 33757fbe7a93SWei Yang * BAR should be size aligned. 33767fbe7a93SWei Yang * 3377ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3378ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3379ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3380ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3381ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3382ee8222feSWei Yang * m64_segsize. 3383ee8222feSWei Yang * 33847fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 33857fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3386ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3387ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 33887fbe7a93SWei Yang */ 33895350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 33907fbe7a93SWei Yang if (!pdn->vfs_expanded) 33915350ab3fSWei Yang return align; 3392ee8222feSWei Yang if (pdn->m64_single_mode) 3393ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 33947fbe7a93SWei Yang 33957fbe7a93SWei Yang return pdn->vfs_expanded * align; 33965350ab3fSWei Yang } 33975350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 33985350ab3fSWei Yang 3399184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3400184cd4a3SBenjamin Herrenschmidt * assign a PE 3401184cd4a3SBenjamin Herrenschmidt */ 34028bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3403184cd4a3SBenjamin Herrenschmidt { 3404db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3405db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3406db1266c8SGavin Shan struct pci_dn *pdn; 3407184cd4a3SBenjamin Herrenschmidt 3408db1266c8SGavin Shan /* The function is probably called while the PEs have 3409db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3410db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3411db1266c8SGavin Shan * PEs isn't ready. 3412db1266c8SGavin Shan */ 3413db1266c8SGavin Shan if (!phb->initialized) 3414c88c2a18SDaniel Axtens return true; 3415db1266c8SGavin Shan 3416b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3417184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3418c88c2a18SDaniel Axtens return false; 3419db1266c8SGavin Shan 3420c88c2a18SDaniel Axtens return true; 3421184cd4a3SBenjamin Herrenschmidt } 3422184cd4a3SBenjamin Herrenschmidt 3423c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3424c5f7700bSGavin Shan int num) 3425c5f7700bSGavin Shan { 3426c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3427c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3428c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3429c5f7700bSGavin Shan unsigned int idx; 3430c5f7700bSGavin Shan long rc; 3431c5f7700bSGavin Shan 3432c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3433c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3434c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3435c5f7700bSGavin Shan continue; 3436c5f7700bSGavin Shan 3437c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3438c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3439c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3440c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3441c5f7700bSGavin Shan rc, idx); 3442c5f7700bSGavin Shan return rc; 3443c5f7700bSGavin Shan } 3444c5f7700bSGavin Shan 3445c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3446c5f7700bSGavin Shan } 3447c5f7700bSGavin Shan 3448c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3449c5f7700bSGavin Shan return OPAL_SUCCESS; 3450c5f7700bSGavin Shan } 3451c5f7700bSGavin Shan 3452c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3453c5f7700bSGavin Shan { 3454c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3455c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3456c5f7700bSGavin Shan int64_t rc; 3457c5f7700bSGavin Shan 3458c5f7700bSGavin Shan if (!weight) 3459c5f7700bSGavin Shan return; 3460c5f7700bSGavin Shan 3461c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3462c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3463c5f7700bSGavin Shan return; 3464c5f7700bSGavin Shan 3465a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3466c5f7700bSGavin Shan if (pe->table_group.group) { 3467c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3468c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3469c5f7700bSGavin Shan } 3470c5f7700bSGavin Shan 3471c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3472e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3473c5f7700bSGavin Shan } 3474c5f7700bSGavin Shan 3475c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3476c5f7700bSGavin Shan { 3477c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3478c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3479c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3480c5f7700bSGavin Shan int64_t rc; 3481c5f7700bSGavin Shan #endif 3482c5f7700bSGavin Shan 3483c5f7700bSGavin Shan if (!weight) 3484c5f7700bSGavin Shan return; 3485c5f7700bSGavin Shan 3486c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3487c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3488c5f7700bSGavin Shan if (rc) 3489c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3490c5f7700bSGavin Shan #endif 3491c5f7700bSGavin Shan 3492c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3493c5f7700bSGavin Shan if (pe->table_group.group) { 3494c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3495c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3496c5f7700bSGavin Shan } 3497c5f7700bSGavin Shan 3498e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3499c5f7700bSGavin Shan } 3500c5f7700bSGavin Shan 3501c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3502c5f7700bSGavin Shan unsigned short win, 3503c5f7700bSGavin Shan unsigned int *map) 3504c5f7700bSGavin Shan { 3505c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3506c5f7700bSGavin Shan int idx; 3507c5f7700bSGavin Shan int64_t rc; 3508c5f7700bSGavin Shan 3509c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3510c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3511c5f7700bSGavin Shan continue; 3512c5f7700bSGavin Shan 3513c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3514c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3515c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3516c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3517c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3518c5f7700bSGavin Shan else 3519c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3520c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3521c5f7700bSGavin Shan 3522c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3523c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3524c5f7700bSGavin Shan rc, win, idx); 3525c5f7700bSGavin Shan 3526c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3527c5f7700bSGavin Shan } 3528c5f7700bSGavin Shan } 3529c5f7700bSGavin Shan 3530c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3531c5f7700bSGavin Shan { 3532c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3533c5f7700bSGavin Shan 3534c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3535c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3536c5f7700bSGavin Shan phb->ioda.io_segmap); 3537c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3538c5f7700bSGavin Shan phb->ioda.m32_segmap); 3539c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3540c5f7700bSGavin Shan phb->ioda.m64_segmap); 3541c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3542c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3543c5f7700bSGavin Shan phb->ioda.m32_segmap); 3544c5f7700bSGavin Shan } 3545c5f7700bSGavin Shan } 3546c5f7700bSGavin Shan 3547c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3548c5f7700bSGavin Shan { 3549c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3550c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3551c5f7700bSGavin Shan 3552c5f7700bSGavin Shan list_del(&pe->list); 3553c5f7700bSGavin Shan switch (phb->type) { 3554c5f7700bSGavin Shan case PNV_PHB_IODA1: 3555c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3556c5f7700bSGavin Shan break; 3557c5f7700bSGavin Shan case PNV_PHB_IODA2: 3558c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3559c5f7700bSGavin Shan break; 3560c5f7700bSGavin Shan default: 3561c5f7700bSGavin Shan WARN_ON(1); 3562c5f7700bSGavin Shan } 3563c5f7700bSGavin Shan 3564c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3565c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3566b314427aSGavin Shan 3567b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3568b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3569b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3570b314427aSGavin Shan list_del(&slave->list); 3571b314427aSGavin Shan pnv_ioda_free_pe(slave); 3572b314427aSGavin Shan } 3573b314427aSGavin Shan } 3574b314427aSGavin Shan 35756eaed166SGavin Shan /* 35766eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 35776eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 35786eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 35796eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 35806eaed166SGavin Shan */ 35816eaed166SGavin Shan if (phb->ioda.root_pe_populated && 35826eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 35836eaed166SGavin Shan phb->ioda.root_pe_populated = false; 35846eaed166SGavin Shan else 3585c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3586c5f7700bSGavin Shan } 3587c5f7700bSGavin Shan 3588c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3589c5f7700bSGavin Shan { 3590c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3591c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3592c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3593c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3594c5f7700bSGavin Shan 3595c5f7700bSGavin Shan if (pdev->is_virtfn) 3596c5f7700bSGavin Shan return; 3597c5f7700bSGavin Shan 3598c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3599c5f7700bSGavin Shan return; 3600c5f7700bSGavin Shan 360129bf282dSGavin Shan /* 360229bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 360329bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 360429bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 360529bf282dSGavin Shan * device count is decreased on removing devices while failing to 360629bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 360729bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 360829bf282dSGavin Shan */ 3609c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 361029bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 361129bf282dSGavin Shan 3612c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3613c5f7700bSGavin Shan if (pe->device_count == 0) 3614c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3615c5f7700bSGavin Shan } 3616c5f7700bSGavin Shan 3617ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 3618ab7032e7SAlexey Kardashevskiy { 3619ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 3620ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 3621ab7032e7SAlexey Kardashevskiy 3622ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 3623ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 3624ab7032e7SAlexey Kardashevskiy } 3625ab7032e7SAlexey Kardashevskiy 36267a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 362773ed148aSBenjamin Herrenschmidt { 36287a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 36297a8e6bbfSMichael Neuling 3630d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 363173ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 363273ed148aSBenjamin Herrenschmidt } 363373ed148aSBenjamin Herrenschmidt 363492ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 363592ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 36361bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 363792ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 363892ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 363992ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3640c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 364192ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3642ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 364392ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3644763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 364553522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 36467a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 364792ae0353SDaniel Axtens }; 364892ae0353SDaniel Axtens 3649f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3650f9f83456SAlexey Kardashevskiy { 3651f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3652f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3653f9f83456SAlexey Kardashevskiy __func__); 3654f9f83456SAlexey Kardashevskiy return -EPERM; 3655f9f83456SAlexey Kardashevskiy } 3656f9f83456SAlexey Kardashevskiy 36575d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 36585d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 36595d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 36605d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 36615d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 36625d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 36635d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36645d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 36655d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 3666ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 36675d2aa710SAlistair Popple }; 36685d2aa710SAlistair Popple 36697f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 36707f2c39e9SFrederic Barrat .enable_device_hook = pnv_pci_enable_device_hook, 36717f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 36727f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36737f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 36747f2c39e9SFrederic Barrat }; 36757f2c39e9SFrederic Barrat 3676e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3677e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3678184cd4a3SBenjamin Herrenschmidt { 3679184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3680184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 36812b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 36822b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3683fd141d1aSBenjamin Herrenschmidt struct resource r; 3684c681b93cSAlistair Popple const __be64 *prop64; 36853a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3686f1b7cc3eSGavin Shan int len; 36873fa23ff8SGavin Shan unsigned int segno; 3688184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3689184cd4a3SBenjamin Herrenschmidt void *aux; 3690184cd4a3SBenjamin Herrenschmidt long rc; 3691184cd4a3SBenjamin Herrenschmidt 369208a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 369308a45b32SBenjamin Herrenschmidt return; 369408a45b32SBenjamin Herrenschmidt 3695b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3696184cd4a3SBenjamin Herrenschmidt 3697184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3698184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3699184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3700184cd4a3SBenjamin Herrenschmidt return; 3701184cd4a3SBenjamin Herrenschmidt } 3702184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3703184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3704184cd4a3SBenjamin Herrenschmidt 37057e1c4e27SMike Rapoport phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 370658d714ecSGavin Shan 370758d714ecSGavin Shan /* Allocate PCI controller */ 3708184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 370958d714ecSGavin Shan if (!phb->hose) { 3710b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3711b7c670d6SRob Herring np); 3712e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3713184cd4a3SBenjamin Herrenschmidt return; 3714184cd4a3SBenjamin Herrenschmidt } 3715184cd4a3SBenjamin Herrenschmidt 3716184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3717f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3718f1b7cc3eSGavin Shan if (prop32 && len == 8) { 37193a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 37203a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3721f1b7cc3eSGavin Shan } else { 3722b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3723184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3724184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3725f1b7cc3eSGavin Shan } 3726184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3727e9cc17d4SGavin Shan phb->hub_id = hub_id; 3728184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3729aa0c033fSGavin Shan phb->type = ioda_type; 3730781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3731184cd4a3SBenjamin Herrenschmidt 3732cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3733cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3734cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3735f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3736aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 37375d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 37385d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3739616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3740616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3741cee72d5bSBenjamin Herrenschmidt else 3742cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3743cee72d5bSBenjamin Herrenschmidt 37445cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 37455cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 37465cb1f8fdSRussell Currey if (prop32) 37475cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 37485cb1f8fdSRussell Currey else 37495cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 37505cb1f8fdSRussell Currey 37517e1c4e27SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 37525cb1f8fdSRussell Currey 3753aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 37542f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3755184cd4a3SBenjamin Herrenschmidt 3756aa0c033fSGavin Shan /* Get registers */ 3757fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3758fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3759fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3760184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3761184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3762fd141d1aSBenjamin Herrenschmidt } 3763577c8c88SGavin Shan 3764184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 376592b8f137SGavin Shan phb->ioda.total_pe_num = 1; 376636954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 376736954dc7SGavin Shan if (prop32) 376892b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 376936954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 377036954dc7SGavin Shan if (prop32) 377192b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3772262af557SGuo Chao 3773c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3774c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3775c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3776c127562aSGavin Shan 3777262af557SGuo Chao /* Parse 64-bit MMIO range */ 3778262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3779262af557SGuo Chao 3780184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3781aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3782184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3783184cd4a3SBenjamin Herrenschmidt 378492b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 37853fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3786184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 378792b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3788184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3789184cd4a3SBenjamin Herrenschmidt 37902b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 37912b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 37922b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 37932b923ed1SGavin Shan 3794c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 379592a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 379692a86756SAlexey Kardashevskiy sizeof(unsigned long)); 379793289d8cSGavin Shan m64map_off = size; 379893289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3799184cd4a3SBenjamin Herrenschmidt m32map_off = size; 380092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3801c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3802c35d2a8cSGavin Shan iomap_off = size; 380392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 38042b923ed1SGavin Shan dma32map_off = size; 38052b923ed1SGavin Shan size += phb->ioda.dma32_count * 38062b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3807c35d2a8cSGavin Shan } 3808184cd4a3SBenjamin Herrenschmidt pemap_off = size; 380992b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 38107e1c4e27SMike Rapoport aux = memblock_alloc(size, SMP_CACHE_BYTES); 3811184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 381293289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3813184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 381493289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 381593289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 38163fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 381793289d8cSGavin Shan } 38183fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3819184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 38203fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 38213fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 38222b923ed1SGavin Shan 38232b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 38242b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 38252b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 38263fa23ff8SGavin Shan } 3827184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 382863803c39SGavin Shan 382963803c39SGavin Shan /* 383063803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 383163803c39SGavin Shan * M64 resources consumed by its child devices. To pick 383263803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 383363803c39SGavin Shan */ 383463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 383563803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 383663803c39SGavin Shan phb->ioda.root_pe_idx = 1; 383763803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 383863803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 383963803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 384063803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 384163803c39SGavin Shan } else { 384263803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 384363803c39SGavin Shan } 3844184cd4a3SBenjamin Herrenschmidt 3845184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3846781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3847184cd4a3SBenjamin Herrenschmidt 3848184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 38492b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3850acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3851184cd4a3SBenjamin Herrenschmidt 3852aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3853184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3854184cd4a3SBenjamin Herrenschmidt window_type, 3855184cd4a3SBenjamin Herrenschmidt window_num, 3856184cd4a3SBenjamin Herrenschmidt starting_real_address, 3857184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3858184cd4a3SBenjamin Herrenschmidt segment_size); 3859184cd4a3SBenjamin Herrenschmidt #endif 3860184cd4a3SBenjamin Herrenschmidt 3861262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 386292b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3863262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3864262af557SGuo Chao if (phb->ioda.m64_size) 3865262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3866262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3867262af557SGuo Chao if (phb->ioda.io_size) 3868262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3869184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3870184cd4a3SBenjamin Herrenschmidt 3871262af557SGuo Chao 3872184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 387349dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 387449dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 387549dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3876184cd4a3SBenjamin Herrenschmidt 3877184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3878184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3879184cd4a3SBenjamin Herrenschmidt 3880c40a4210SGavin Shan /* 3881c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3882c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3883c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3884c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3885c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3886184cd4a3SBenjamin Herrenschmidt */ 3887fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 38885d2aa710SAlistair Popple 38897f2c39e9SFrederic Barrat switch (phb->type) { 38907f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 38915d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 38927f2c39e9SFrederic Barrat break; 38937f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 38947f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 38957f2c39e9SFrederic Barrat break; 38967f2c39e9SFrederic Barrat default: 3897f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 389892ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3899f9f83456SAlexey Kardashevskiy } 3900ad30cb99SMichael Ellerman 390138274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 390238274637SYongji Xie 39036e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 39046e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 39055350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3906988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3907988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3908ad30cb99SMichael Ellerman #endif 3909ad30cb99SMichael Ellerman 3910c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3911184cd4a3SBenjamin Herrenschmidt 3912184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3913d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3914184cd4a3SBenjamin Herrenschmidt if (rc) 3915f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3916361f2a2aSGavin Shan 39176060e9eaSAndrew Donnellan /* 39186060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3919361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3920361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 392145baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 392245baee14SGuilherme G. Piccoli * kernel parameter will force this reset too. 3923361f2a2aSGavin Shan */ 392445baee14SGuilherme G. Piccoli if (is_kdump_kernel() || pci_reset_phbs) { 3925361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3926cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3927cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3928361f2a2aSGavin Shan } 3929262af557SGuo Chao 39309e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 39319e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3932262af557SGuo Chao hose->mem_resources[1].flags = 0; 3933184cd4a3SBenjamin Herrenschmidt } 3934184cd4a3SBenjamin Herrenschmidt 393567975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3936aa0c033fSGavin Shan { 3937e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3938aa0c033fSGavin Shan } 3939aa0c033fSGavin Shan 39405d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 39415d2aa710SAlistair Popple { 39427f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 39435d2aa710SAlistair Popple } 39445d2aa710SAlistair Popple 39457f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 39467f2c39e9SFrederic Barrat { 39477f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3948184cd4a3SBenjamin Herrenschmidt } 3949184cd4a3SBenjamin Herrenschmidt 3950228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3951228c2f41SAndrew Donnellan { 3952228c2f41SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3953228c2f41SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 3954228c2f41SAndrew Donnellan 3955228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3956228c2f41SAndrew Donnellan return; 3957228c2f41SAndrew Donnellan 3958228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3959228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3960228c2f41SAndrew Donnellan } 3961228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3962228c2f41SAndrew Donnellan 3963184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3964184cd4a3SBenjamin Herrenschmidt { 3965184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3966184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 3967184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3968184cd4a3SBenjamin Herrenschmidt 3969b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3970184cd4a3SBenjamin Herrenschmidt 3971184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3972184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3973184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3974184cd4a3SBenjamin Herrenschmidt return; 3975184cd4a3SBenjamin Herrenschmidt } 3976184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3977184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3978184cd4a3SBenjamin Herrenschmidt 3979184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3980184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3981184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3982184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3983184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3984184cd4a3SBenjamin Herrenschmidt } 3985184cd4a3SBenjamin Herrenschmidt } 3986