1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 2057c8a661SMike Rapoport #include <linux/memblock.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 25e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 264793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 27184cd4a3SBenjamin Herrenschmidt 28184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 33fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 38137436c9SGavin Shan #include <asm/xics.h> 397644d581SMichael Ellerman #include <asm/debugfs.h> 40262af557SGuo Chao #include <asm/firmware.h> 4180c49c7eSIan Munsie #include <asm/pnv-pci.h> 42aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4380c49c7eSIan Munsie 44ec249dd8SMichael Neuling #include <misc/cxl-base.h> 45184cd4a3SBenjamin Herrenschmidt 46184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 47184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4844bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 49184cd4a3SBenjamin Herrenschmidt 5099451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5199451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53781a868fSWei Yang 547f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 557f2c39e9SFrederic Barrat "NPU_OCAPI" }; 56aca6913fSAlexey Kardashevskiy 577d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 586d31c2faSJoe Perches const char *fmt, ...) 596d31c2faSJoe Perches { 606d31c2faSJoe Perches struct va_format vaf; 616d31c2faSJoe Perches va_list args; 626d31c2faSJoe Perches char pfix[32]; 63184cd4a3SBenjamin Herrenschmidt 646d31c2faSJoe Perches va_start(args, fmt); 656d31c2faSJoe Perches 666d31c2faSJoe Perches vaf.fmt = fmt; 676d31c2faSJoe Perches vaf.va = &args; 686d31c2faSJoe Perches 69781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 706d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 71781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 726d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 736d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 74781a868fSWei Yang #ifdef CONFIG_PCI_IOV 75781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 76781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 77781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 78781a868fSWei Yang (pe->rid & 0xff00) >> 8, 79781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 80781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 816d31c2faSJoe Perches 821f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 836d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 846d31c2faSJoe Perches 856d31c2faSJoe Perches va_end(args); 866d31c2faSJoe Perches } 876d31c2faSJoe Perches 884e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8945baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 904e287840SThadeu Lima de Souza Cascardo 914e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 924e287840SThadeu Lima de Souza Cascardo { 934e287840SThadeu Lima de Souza Cascardo if (!str) 944e287840SThadeu Lima de Souza Cascardo return -EINVAL; 954e287840SThadeu Lima de Souza Cascardo 964e287840SThadeu Lima de Souza Cascardo while (*str) { 974e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 984e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 994e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1004e287840SThadeu Lima de Souza Cascardo break; 1014e287840SThadeu Lima de Souza Cascardo } 1024e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1034e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1044e287840SThadeu Lima de Souza Cascardo str++; 1054e287840SThadeu Lima de Souza Cascardo } 1064e287840SThadeu Lima de Souza Cascardo 1074e287840SThadeu Lima de Souza Cascardo return 0; 1084e287840SThadeu Lima de Souza Cascardo } 1094e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1104e287840SThadeu Lima de Souza Cascardo 11145baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11245baee14SGuilherme G. Piccoli { 11345baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11445baee14SGuilherme G. Piccoli return 0; 11545baee14SGuilherme G. Piccoli } 11645baee14SGuilherme G. Piccoli 11745baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11845baee14SGuilherme G. Piccoli 1195958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 120262af557SGuo Chao { 1215958d19aSBenjamin Herrenschmidt /* 1225958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1235958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1245958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1255958d19aSBenjamin Herrenschmidt * 1265958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1275958d19aSBenjamin Herrenschmidt */ 1285958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1295958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 130262af557SGuo Chao } 131262af557SGuo Chao 132b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 133b79331a5SRussell Currey { 134b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 135b79331a5SRussell Currey 136b79331a5SRussell Currey return (resource_flags & flags) == flags; 137b79331a5SRussell Currey } 138b79331a5SRussell Currey 1391e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1401e916772SGavin Shan { 141313483ddSGavin Shan s64 rc; 142313483ddSGavin Shan 1431e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1441e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1451e916772SGavin Shan 146313483ddSGavin Shan /* 147313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 148313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 149313483ddSGavin Shan * PE is already in unfrozen state. 150313483ddSGavin Shan */ 151313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 152313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 153d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1541f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 155313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 156313483ddSGavin Shan 1571e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1581e916772SGavin Shan } 1591e916772SGavin Shan 1604b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1614b82ab18SGavin Shan { 16292b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1631f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1644b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1654b82ab18SGavin Shan return; 1664b82ab18SGavin Shan } 1674b82ab18SGavin Shan 168e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1691f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1704b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1714b82ab18SGavin Shan 1721e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1734b82ab18SGavin Shan } 1744b82ab18SGavin Shan 1751e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 176184cd4a3SBenjamin Herrenschmidt { 17760964816SAndrzej Hajda long pe; 178184cd4a3SBenjamin Herrenschmidt 1799fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1809fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1811e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 182184cd4a3SBenjamin Herrenschmidt } 183184cd4a3SBenjamin Herrenschmidt 1849fcd6f4aSGavin Shan return NULL; 1859fcd6f4aSGavin Shan } 1869fcd6f4aSGavin Shan 1871e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 188184cd4a3SBenjamin Herrenschmidt { 1891e916772SGavin Shan struct pnv_phb *phb = pe->phb; 190caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 191184cd4a3SBenjamin Herrenschmidt 1921e916772SGavin Shan WARN_ON(pe->pdev); 1931e916772SGavin Shan 1941e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 195caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 196184cd4a3SBenjamin Herrenschmidt } 197184cd4a3SBenjamin Herrenschmidt 198262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 199262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 200262af557SGuo Chao { 201262af557SGuo Chao const char *desc; 202262af557SGuo Chao struct resource *r; 203262af557SGuo Chao s64 rc; 204262af557SGuo Chao 205262af557SGuo Chao /* Configure the default M64 BAR */ 206262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 207262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 208262af557SGuo Chao phb->ioda.m64_bar_idx, 209262af557SGuo Chao phb->ioda.m64_base, 210262af557SGuo Chao 0, /* unused */ 211262af557SGuo Chao phb->ioda.m64_size); 212262af557SGuo Chao if (rc != OPAL_SUCCESS) { 213262af557SGuo Chao desc = "configuring"; 214262af557SGuo Chao goto fail; 215262af557SGuo Chao } 216262af557SGuo Chao 217262af557SGuo Chao /* Enable the default M64 BAR */ 218262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 219262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 220262af557SGuo Chao phb->ioda.m64_bar_idx, 221262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 222262af557SGuo Chao if (rc != OPAL_SUCCESS) { 223262af557SGuo Chao desc = "enabling"; 224262af557SGuo Chao goto fail; 225262af557SGuo Chao } 226262af557SGuo Chao 227262af557SGuo Chao /* 22863803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22963803c39SGavin Shan * are first or last two PEs. 230262af557SGuo Chao */ 231262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23292b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23363803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23492b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23563803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 236262af557SGuo Chao else 2371f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23892b8f137SGavin Shan phb->ioda.reserved_pe_idx); 239262af557SGuo Chao 240262af557SGuo Chao return 0; 241262af557SGuo Chao 242262af557SGuo Chao fail: 243262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 244262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 245262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 246262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 247262af557SGuo Chao phb->ioda.m64_bar_idx, 248262af557SGuo Chao OPAL_DISABLE_M64); 249262af557SGuo Chao return -EIO; 250262af557SGuo Chao } 251262af557SGuo Chao 252c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25396a2f92bSGavin Shan unsigned long *pe_bitmap) 254262af557SGuo Chao { 25596a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25696a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 257262af557SGuo Chao struct resource *r; 25896a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25996a2f92bSGavin Shan int segno, i; 260262af557SGuo Chao 26196a2f92bSGavin Shan base = phb->ioda.m64_base; 26296a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26396a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26496a2f92bSGavin Shan r = &pdev->resource[i]; 2655958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 266262af557SGuo Chao continue; 267262af557SGuo Chao 26896a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 26996a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 27096a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27196a2f92bSGavin Shan if (pe_bitmap) 27296a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27396a2f92bSGavin Shan else 27496a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 275262af557SGuo Chao } 276262af557SGuo Chao } 277262af557SGuo Chao } 278262af557SGuo Chao 27999451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28099451551SGavin Shan { 28199451551SGavin Shan struct resource *r; 28299451551SGavin Shan int index; 28399451551SGavin Shan 28499451551SGavin Shan /* 28599451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28699451551SGavin Shan * there are as many M64 segments as the maximum number of 28799451551SGavin Shan * PEs, which is 128. 28899451551SGavin Shan */ 28999451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29099451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29199451551SGavin Shan int64_t rc; 29299451551SGavin Shan 29399451551SGavin Shan base = phb->ioda.m64_base + 29499451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29599451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29799451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29899451551SGavin Shan if (rc != OPAL_SUCCESS) { 2991f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30099451551SGavin Shan rc, phb->hose->global_number, index); 30199451551SGavin Shan goto fail; 30299451551SGavin Shan } 30399451551SGavin Shan 30499451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30699451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30799451551SGavin Shan if (rc != OPAL_SUCCESS) { 3081f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30999451551SGavin Shan rc, phb->hose->global_number, index); 31099451551SGavin Shan goto fail; 31199451551SGavin Shan } 31299451551SGavin Shan } 31399451551SGavin Shan 31499451551SGavin Shan /* 31563803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31663803c39SGavin Shan * are first or last two PEs. 31799451551SGavin Shan */ 31899451551SGavin Shan r = &phb->hose->mem_resources[1]; 31999451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 32063803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32199451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32263803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32399451551SGavin Shan else 3241f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32599451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32699451551SGavin Shan 32799451551SGavin Shan return 0; 32899451551SGavin Shan 32999451551SGavin Shan fail: 33099451551SGavin Shan for ( ; index >= 0; index--) 33199451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33299451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33399451551SGavin Shan 33499451551SGavin Shan return -EIO; 33599451551SGavin Shan } 33699451551SGavin Shan 337c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33896a2f92bSGavin Shan unsigned long *pe_bitmap, 33996a2f92bSGavin Shan bool all) 340262af557SGuo Chao { 341262af557SGuo Chao struct pci_dev *pdev; 34296a2f92bSGavin Shan 34396a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 344c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34596a2f92bSGavin Shan 34696a2f92bSGavin Shan if (all && pdev->subordinate) 347c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34896a2f92bSGavin Shan pe_bitmap, all); 34996a2f92bSGavin Shan } 35096a2f92bSGavin Shan } 35196a2f92bSGavin Shan 3521e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 353262af557SGuo Chao { 35426ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35526ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 356262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 357262af557SGuo Chao unsigned long size, *pe_alloc; 35826ba248dSGavin Shan int i; 359262af557SGuo Chao 360262af557SGuo Chao /* Root bus shouldn't use M64 */ 361262af557SGuo Chao if (pci_is_root_bus(bus)) 3621e916772SGavin Shan return NULL; 363262af557SGuo Chao 364262af557SGuo Chao /* Allocate bitmap */ 36592b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 366262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 367262af557SGuo Chao if (!pe_alloc) { 368262af557SGuo Chao pr_warn("%s: Out of memory !\n", 369262af557SGuo Chao __func__); 3701e916772SGavin Shan return NULL; 371262af557SGuo Chao } 372262af557SGuo Chao 37326ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 374c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 375262af557SGuo Chao 376262af557SGuo Chao /* 377262af557SGuo Chao * the current bus might not own M64 window and that's all 378262af557SGuo Chao * contributed by its child buses. For the case, we needn't 379262af557SGuo Chao * pick M64 dependent PE#. 380262af557SGuo Chao */ 38192b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 382262af557SGuo Chao kfree(pe_alloc); 3831e916772SGavin Shan return NULL; 384262af557SGuo Chao } 385262af557SGuo Chao 386262af557SGuo Chao /* 387262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 388262af557SGuo Chao * PE's list to form compound PE. 389262af557SGuo Chao */ 390262af557SGuo Chao master_pe = NULL; 391262af557SGuo Chao i = -1; 39292b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39392b8f137SGavin Shan phb->ioda.total_pe_num) { 394262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 395262af557SGuo Chao 39693289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 397262af557SGuo Chao if (!master_pe) { 398262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 399262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 400262af557SGuo Chao master_pe = pe; 401262af557SGuo Chao } else { 402262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 403262af557SGuo Chao pe->master = master_pe; 404262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 405262af557SGuo Chao } 40699451551SGavin Shan 40799451551SGavin Shan /* 40899451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40999451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 41099451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41199451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41299451551SGavin Shan * segment and PE# on P7IOC. 41399451551SGavin Shan */ 41499451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41599451551SGavin Shan int64_t rc; 41699451551SGavin Shan 41799451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41899451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41999451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 42099451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42199451551SGavin Shan if (rc != OPAL_SUCCESS) 4221f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42399451551SGavin Shan __func__, rc, phb->hose->global_number, 42499451551SGavin Shan pe->pe_number); 42599451551SGavin Shan } 426262af557SGuo Chao } 427262af557SGuo Chao 428262af557SGuo Chao kfree(pe_alloc); 4291e916772SGavin Shan return master_pe; 430262af557SGuo Chao } 431262af557SGuo Chao 432262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 433262af557SGuo Chao { 434262af557SGuo Chao struct pci_controller *hose = phb->hose; 435262af557SGuo Chao struct device_node *dn = hose->dn; 436262af557SGuo Chao struct resource *res; 437a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4380e7736c6SGavin Shan const __be32 *r; 439262af557SGuo Chao u64 pci_addr; 440262af557SGuo Chao 44199451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4421665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4431665c4a8SGavin Shan return; 4441665c4a8SGavin Shan } 4451665c4a8SGavin Shan 446e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 447262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 448262af557SGuo Chao return; 449262af557SGuo Chao } 450262af557SGuo Chao 451262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 452262af557SGuo Chao if (!r) { 453b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 454b7c670d6SRob Herring dn); 455262af557SGuo Chao return; 456262af557SGuo Chao } 457262af557SGuo Chao 458a1339fafSBenjamin Herrenschmidt /* 459a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 460a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 461a1339fafSBenjamin Herrenschmidt */ 462a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 463a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 464a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 465a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 466a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 467a1339fafSBenjamin Herrenschmidt } 468a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 469a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 470a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 471a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 472a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 473a1339fafSBenjamin Herrenschmidt } 474a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 475a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 476a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 477a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 478a1339fafSBenjamin Herrenschmidt return; 479a1339fafSBenjamin Herrenschmidt } 480a1339fafSBenjamin Herrenschmidt 481a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 482262af557SGuo Chao res = &hose->mem_resources[1]; 483e80c4e7cSGavin Shan res->name = dn->full_name; 484262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 485262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 486262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 487262af557SGuo Chao pci_addr = of_read_number(r, 2); 488262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 489262af557SGuo Chao 490262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49192b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 492262af557SGuo Chao phb->ioda.m64_base = pci_addr; 493262af557SGuo Chao 494a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 495a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 496a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 497a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 498a1339fafSBenjamin Herrenschmidt 499a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 500a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 501e9863e68SWei Yang 502262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 503a1339fafSBenjamin Herrenschmidt m64_range[1]--; 504a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 505a1339fafSBenjamin Herrenschmidt 506a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 507a1339fafSBenjamin Herrenschmidt 508a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 509a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 510a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 511a1339fafSBenjamin Herrenschmidt 512a1339fafSBenjamin Herrenschmidt /* 513a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 514a1339fafSBenjamin Herrenschmidt * the IODA2 code. 515a1339fafSBenjamin Herrenschmidt */ 51699451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51799451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51899451551SGavin Shan else 519262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 520262af557SGuo Chao } 521262af557SGuo Chao 52249dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52349dec922SGavin Shan { 52449dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52549dec922SGavin Shan struct pnv_ioda_pe *slave; 52649dec922SGavin Shan s64 rc; 52749dec922SGavin Shan 52849dec922SGavin Shan /* Fetch master PE */ 52949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53049dec922SGavin Shan pe = pe->master; 531ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 532ec8e4e9dSGavin Shan return; 533ec8e4e9dSGavin Shan 53449dec922SGavin Shan pe_no = pe->pe_number; 53549dec922SGavin Shan } 53649dec922SGavin Shan 53749dec922SGavin Shan /* Freeze master PE */ 53849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53949dec922SGavin Shan pe_no, 54049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54349dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54449dec922SGavin Shan return; 54549dec922SGavin Shan } 54649dec922SGavin Shan 54749dec922SGavin Shan /* Freeze slave PEs */ 54849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54949dec922SGavin Shan return; 55049dec922SGavin Shan 55149dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55249dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55349dec922SGavin Shan slave->pe_number, 55449dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55549dec922SGavin Shan if (rc != OPAL_SUCCESS) 55649dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55749dec922SGavin Shan __func__, rc, phb->hose->global_number, 55849dec922SGavin Shan slave->pe_number); 55949dec922SGavin Shan } 56049dec922SGavin Shan } 56149dec922SGavin Shan 562e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56349dec922SGavin Shan { 56449dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56549dec922SGavin Shan s64 rc; 56649dec922SGavin Shan 56749dec922SGavin Shan /* Find master PE */ 56849dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57049dec922SGavin Shan pe = pe->master; 57149dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57249dec922SGavin Shan pe_no = pe->pe_number; 57349dec922SGavin Shan } 57449dec922SGavin Shan 57549dec922SGavin Shan /* Clear frozen state for master PE */ 57649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58049dec922SGavin Shan return -EIO; 58149dec922SGavin Shan } 58249dec922SGavin Shan 58349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58449dec922SGavin Shan return 0; 58549dec922SGavin Shan 58649dec922SGavin Shan /* Clear frozen state for slave PEs */ 58749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58849dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58949dec922SGavin Shan slave->pe_number, 59049dec922SGavin Shan opt); 59149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59249dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59349dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59449dec922SGavin Shan slave->pe_number); 59549dec922SGavin Shan return -EIO; 59649dec922SGavin Shan } 59749dec922SGavin Shan } 59849dec922SGavin Shan 59949dec922SGavin Shan return 0; 60049dec922SGavin Shan } 60149dec922SGavin Shan 60249dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60349dec922SGavin Shan { 60449dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 605c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 606c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 60749dec922SGavin Shan s64 rc; 60849dec922SGavin Shan 60949dec922SGavin Shan /* Sanity check on PE number */ 61092b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61149dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61249dec922SGavin Shan 61349dec922SGavin Shan /* 61449dec922SGavin Shan * Fetch the master PE and the PE instance might be 61549dec922SGavin Shan * not initialized yet. 61649dec922SGavin Shan */ 61749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61949dec922SGavin Shan pe = pe->master; 62049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62149dec922SGavin Shan pe_no = pe->pe_number; 62249dec922SGavin Shan } 62349dec922SGavin Shan 62449dec922SGavin Shan /* Check the master PE */ 62549dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62649dec922SGavin Shan &state, &pcierr, NULL); 62749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62849dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62949dec922SGavin Shan "PHB#%x-PE#%x state\n", 63049dec922SGavin Shan __func__, rc, 63149dec922SGavin Shan phb->hose->global_number, pe_no); 63249dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63349dec922SGavin Shan } 63449dec922SGavin Shan 63549dec922SGavin Shan /* Check the slave PE */ 63649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63749dec922SGavin Shan return state; 63849dec922SGavin Shan 63949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64049dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64149dec922SGavin Shan slave->pe_number, 64249dec922SGavin Shan &fstate, 64349dec922SGavin Shan &pcierr, 64449dec922SGavin Shan NULL); 64549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64749dec922SGavin Shan "PHB#%x-PE#%x state\n", 64849dec922SGavin Shan __func__, rc, 64949dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65149dec922SGavin Shan } 65249dec922SGavin Shan 65349dec922SGavin Shan /* 65449dec922SGavin Shan * Override the result based on the ascending 65549dec922SGavin Shan * priority. 65649dec922SGavin Shan */ 65749dec922SGavin Shan if (fstate > state) 65849dec922SGavin Shan state = fstate; 65949dec922SGavin Shan } 66049dec922SGavin Shan 66149dec922SGavin Shan return state; 66249dec922SGavin Shan } 66349dec922SGavin Shan 664f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 665184cd4a3SBenjamin Herrenschmidt { 666184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 667184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 668b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 669184cd4a3SBenjamin Herrenschmidt 670184cd4a3SBenjamin Herrenschmidt if (!pdn) 671184cd4a3SBenjamin Herrenschmidt return NULL; 672184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 673184cd4a3SBenjamin Herrenschmidt return NULL; 674184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 675184cd4a3SBenjamin Herrenschmidt } 676184cd4a3SBenjamin Herrenschmidt 677b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 678b131a842SGavin Shan struct pnv_ioda_pe *parent, 679b131a842SGavin Shan struct pnv_ioda_pe *child, 680b131a842SGavin Shan bool is_add) 681b131a842SGavin Shan { 682b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 683b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 684b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 685b131a842SGavin Shan struct pnv_ioda_pe *slave; 686b131a842SGavin Shan long rc; 687b131a842SGavin Shan 688b131a842SGavin Shan /* Parent PE affects child PE */ 689b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 690b131a842SGavin Shan child->pe_number, op); 691b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 692b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 693b131a842SGavin Shan rc, desc); 694b131a842SGavin Shan return -ENXIO; 695b131a842SGavin Shan } 696b131a842SGavin Shan 697b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 698b131a842SGavin Shan return 0; 699b131a842SGavin Shan 700b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 701b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 702b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 703b131a842SGavin Shan slave->pe_number, op); 704b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 705b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 706b131a842SGavin Shan rc, desc); 707b131a842SGavin Shan return -ENXIO; 708b131a842SGavin Shan } 709b131a842SGavin Shan } 710b131a842SGavin Shan 711b131a842SGavin Shan return 0; 712b131a842SGavin Shan } 713b131a842SGavin Shan 714b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 715b131a842SGavin Shan struct pnv_ioda_pe *pe, 716b131a842SGavin Shan bool is_add) 717b131a842SGavin Shan { 718b131a842SGavin Shan struct pnv_ioda_pe *slave; 719781a868fSWei Yang struct pci_dev *pdev = NULL; 720b131a842SGavin Shan int ret; 721b131a842SGavin Shan 722b131a842SGavin Shan /* 723b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 724b131a842SGavin Shan * clear slave PE frozen state as well. 725b131a842SGavin Shan */ 726b131a842SGavin Shan if (is_add) { 727b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 728b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 729b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 730b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 731b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 732b131a842SGavin Shan slave->pe_number, 733b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 734b131a842SGavin Shan } 735b131a842SGavin Shan } 736b131a842SGavin Shan 737b131a842SGavin Shan /* 738b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 739b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 740b131a842SGavin Shan * originated from the PE might contribute to other 741b131a842SGavin Shan * PEs. 742b131a842SGavin Shan */ 743b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 744b131a842SGavin Shan if (ret) 745b131a842SGavin Shan return ret; 746b131a842SGavin Shan 747b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 748b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 749b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 750b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 751b131a842SGavin Shan if (ret) 752b131a842SGavin Shan return ret; 753b131a842SGavin Shan } 754b131a842SGavin Shan } 755b131a842SGavin Shan 756b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 757b131a842SGavin Shan pdev = pe->pbus->self; 758781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 759b131a842SGavin Shan pdev = pe->pdev->bus->self; 760781a868fSWei Yang #ifdef CONFIG_PCI_IOV 761781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 762283e2d8aSGavin Shan pdev = pe->parent_dev; 763781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 764b131a842SGavin Shan while (pdev) { 765b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 766b131a842SGavin Shan struct pnv_ioda_pe *parent; 767b131a842SGavin Shan 768b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 769b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 770b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 771b131a842SGavin Shan if (ret) 772b131a842SGavin Shan return ret; 773b131a842SGavin Shan } 774b131a842SGavin Shan 775b131a842SGavin Shan pdev = pdev->bus->self; 776b131a842SGavin Shan } 777b131a842SGavin Shan 778b131a842SGavin Shan return 0; 779b131a842SGavin Shan } 780b131a842SGavin Shan 781781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 782781a868fSWei Yang { 783781a868fSWei Yang struct pci_dev *parent; 784781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 785781a868fSWei Yang int64_t rc; 786781a868fSWei Yang long rid_end, rid; 787781a868fSWei Yang 788781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 789781a868fSWei Yang if (pe->pbus) { 790781a868fSWei Yang int count; 791781a868fSWei Yang 792781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 793781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 794781a868fSWei Yang parent = pe->pbus->self; 795781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 796781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 797781a868fSWei Yang else 798781a868fSWei Yang count = 1; 799781a868fSWei Yang 800781a868fSWei Yang switch(count) { 801781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 802781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 803781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 804781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 805781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 806781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 807781a868fSWei Yang default: 808781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 809781a868fSWei Yang count); 810781a868fSWei Yang /* Do an exact match only */ 811781a868fSWei Yang bcomp = OpalPciBusAll; 812781a868fSWei Yang } 813781a868fSWei Yang rid_end = pe->rid + (count << 8); 814781a868fSWei Yang } else { 81593e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 816781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 817781a868fSWei Yang parent = pe->parent_dev; 818781a868fSWei Yang else 81993e01a50SGavin Shan #endif 820781a868fSWei Yang parent = pe->pdev->bus->self; 821781a868fSWei Yang bcomp = OpalPciBusAll; 822781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 823781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 824781a868fSWei Yang rid_end = pe->rid + 1; 825781a868fSWei Yang } 826781a868fSWei Yang 827781a868fSWei Yang /* Clear the reverse map */ 828781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 829c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 830781a868fSWei Yang 831781a868fSWei Yang /* Release from all parents PELT-V */ 832781a868fSWei Yang while (parent) { 833781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 834781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 835781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 836781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 837781a868fSWei Yang /* XXX What to do in case of error ? */ 838781a868fSWei Yang } 839781a868fSWei Yang parent = parent->bus->self; 840781a868fSWei Yang } 841781a868fSWei Yang 842f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 843781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 844781a868fSWei Yang 845781a868fSWei Yang /* Disassociate PE in PELT */ 846781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 847781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 848781a868fSWei Yang if (rc) 849781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 850781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 851781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 852781a868fSWei Yang if (rc) 853781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 854781a868fSWei Yang 855781a868fSWei Yang pe->pbus = NULL; 856781a868fSWei Yang pe->pdev = NULL; 85793e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 858781a868fSWei Yang pe->parent_dev = NULL; 85993e01a50SGavin Shan #endif 860781a868fSWei Yang 861781a868fSWei Yang return 0; 862781a868fSWei Yang } 863781a868fSWei Yang 864cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 865184cd4a3SBenjamin Herrenschmidt { 866184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 867184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 868184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 869184cd4a3SBenjamin Herrenschmidt 870184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 871184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 872184cd4a3SBenjamin Herrenschmidt int count; 873184cd4a3SBenjamin Herrenschmidt 874184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 875184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 876184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 877fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 878b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 879fb446ad0SGavin Shan else 880fb446ad0SGavin Shan count = 1; 881fb446ad0SGavin Shan 882184cd4a3SBenjamin Herrenschmidt switch(count) { 883184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 884184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 885184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 886184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 887184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 888184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 889184cd4a3SBenjamin Herrenschmidt default: 890781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 891781a868fSWei Yang count); 892184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 893184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 894184cd4a3SBenjamin Herrenschmidt } 895184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 896184cd4a3SBenjamin Herrenschmidt } else { 897781a868fSWei Yang #ifdef CONFIG_PCI_IOV 898781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 899781a868fSWei Yang parent = pe->parent_dev; 900781a868fSWei Yang else 901781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 902184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 903184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 904184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 905184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 906184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 907184cd4a3SBenjamin Herrenschmidt } 908184cd4a3SBenjamin Herrenschmidt 909631ad691SGavin Shan /* 910631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 911631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 912631ad691SGavin Shan * originated from the PE might contribute to other 913631ad691SGavin Shan * PEs. 914631ad691SGavin Shan */ 915184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 916184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 917184cd4a3SBenjamin Herrenschmidt if (rc) { 918184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 919184cd4a3SBenjamin Herrenschmidt return -ENXIO; 920184cd4a3SBenjamin Herrenschmidt } 921631ad691SGavin Shan 9225d2aa710SAlistair Popple /* 9235d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9245d2aa710SAlistair Popple * configuration on them. 9255d2aa710SAlistair Popple */ 9267f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 927b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 928184cd4a3SBenjamin Herrenschmidt 929184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 930184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 931184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 932184cd4a3SBenjamin Herrenschmidt 933184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9344773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9354773f76bSGavin Shan pe->mve_number = 0; 9364773f76bSGavin Shan goto out; 9374773f76bSGavin Shan } 9384773f76bSGavin Shan 939184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9404773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9414773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9421f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 943184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 944184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 945184cd4a3SBenjamin Herrenschmidt } else { 946184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 947cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 948184cd4a3SBenjamin Herrenschmidt if (rc) { 9491f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 950184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 951184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 952184cd4a3SBenjamin Herrenschmidt } 953184cd4a3SBenjamin Herrenschmidt } 954184cd4a3SBenjamin Herrenschmidt 9554773f76bSGavin Shan out: 956184cd4a3SBenjamin Herrenschmidt return 0; 957184cd4a3SBenjamin Herrenschmidt } 958184cd4a3SBenjamin Herrenschmidt 959781a868fSWei Yang #ifdef CONFIG_PCI_IOV 960781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 961781a868fSWei Yang { 962781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 963781a868fSWei Yang int i; 964781a868fSWei Yang struct resource *res, res2; 965781a868fSWei Yang resource_size_t size; 966781a868fSWei Yang u16 num_vfs; 967781a868fSWei Yang 968781a868fSWei Yang if (!dev->is_physfn) 969781a868fSWei Yang return -EINVAL; 970781a868fSWei Yang 971781a868fSWei Yang /* 972781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 973781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 974781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 975781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 976781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 977781a868fSWei Yang * range of PEs the VFs are in. 978781a868fSWei Yang */ 979781a868fSWei Yang num_vfs = pdn->num_vfs; 980781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 981781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 982781a868fSWei Yang if (!res->flags || !res->parent) 983781a868fSWei Yang continue; 984781a868fSWei Yang 985781a868fSWei Yang /* 986781a868fSWei Yang * The actual IOV BAR range is determined by the start address 987781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 988781a868fSWei Yang * make sure that after shifting, the range will not overlap 989781a868fSWei Yang * with another device. 990781a868fSWei Yang */ 991781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 992781a868fSWei Yang res2.flags = res->flags; 993781a868fSWei Yang res2.start = res->start + (size * offset); 994781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 995781a868fSWei Yang 996781a868fSWei Yang if (res2.end > res->end) { 997781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 998781a868fSWei Yang i, &res2, res, num_vfs, offset); 999781a868fSWei Yang return -EBUSY; 1000781a868fSWei Yang } 1001781a868fSWei Yang } 1002781a868fSWei Yang 1003781a868fSWei Yang /* 1004d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1005d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1006d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1007d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1008d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1009d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1010781a868fSWei Yang */ 1011781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1012781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1013781a868fSWei Yang if (!res->flags || !res->parent) 1014781a868fSWei Yang continue; 1015781a868fSWei Yang 1016781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1017781a868fSWei Yang res2 = *res; 1018781a868fSWei Yang res->start += size * offset; 1019781a868fSWei Yang 102074703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 102174703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102274703cc4SWei Yang num_vfs, offset); 1023d6f934fdSAlexey Kardashevskiy 1024d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1025d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1026d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1027d6f934fdSAlexey Kardashevskiy } 1028d6f934fdSAlexey Kardashevskiy 1029781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1030d6f934fdSAlexey Kardashevskiy 1031d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1032d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1033d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1034d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1035d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1036d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1037d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1038d6f934fdSAlexey Kardashevskiy } 1039781a868fSWei Yang } 1040781a868fSWei Yang return 0; 1041781a868fSWei Yang } 1042781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1043781a868fSWei Yang 1044cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1045184cd4a3SBenjamin Herrenschmidt { 1046184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1047184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1048b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1049184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1050184cd4a3SBenjamin Herrenschmidt 1051184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1052184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1053184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1054184cd4a3SBenjamin Herrenschmidt return NULL; 1055184cd4a3SBenjamin Herrenschmidt } 1056184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1057184cd4a3SBenjamin Herrenschmidt return NULL; 1058184cd4a3SBenjamin Herrenschmidt 10591e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10601e916772SGavin Shan if (!pe) { 1061f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1062184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1063184cd4a3SBenjamin Herrenschmidt return NULL; 1064184cd4a3SBenjamin Herrenschmidt } 1065184cd4a3SBenjamin Herrenschmidt 1066184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1067184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1068184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1069184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1070184cd4a3SBenjamin Herrenschmidt * 1071184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1072184cd4a3SBenjamin Herrenschmidt */ 1073184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 10741e916772SGavin Shan pdn->pe_number = pe->pe_number; 10755d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1076184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1077184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1078184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1079184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1080184cd4a3SBenjamin Herrenschmidt 1081184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1082184cd4a3SBenjamin Herrenschmidt 1083184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1084184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10851e916772SGavin Shan pnv_ioda_free_pe(pe); 1086184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1087184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1088184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1089184cd4a3SBenjamin Herrenschmidt return NULL; 1090184cd4a3SBenjamin Herrenschmidt } 1091184cd4a3SBenjamin Herrenschmidt 10921d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10931d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10941d4e89cfSAlexey Kardashevskiy 1095184cd4a3SBenjamin Herrenschmidt return pe; 1096184cd4a3SBenjamin Herrenschmidt } 1097184cd4a3SBenjamin Herrenschmidt 1098184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1099184cd4a3SBenjamin Herrenschmidt { 1100184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1101184cd4a3SBenjamin Herrenschmidt 1102184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1103b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1104184cd4a3SBenjamin Herrenschmidt 1105184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1106184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1107184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1108184cd4a3SBenjamin Herrenschmidt continue; 1109184cd4a3SBenjamin Herrenschmidt } 1110ccd1c191SGavin Shan 1111ccd1c191SGavin Shan /* 1112ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1113ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1114ccd1c191SGavin Shan * again. 1115ccd1c191SGavin Shan */ 1116ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1117ccd1c191SGavin Shan continue; 1118ccd1c191SGavin Shan 1119c5f7700bSGavin Shan pe->device_count++; 1120184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1121fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1122184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1123184cd4a3SBenjamin Herrenschmidt } 1124184cd4a3SBenjamin Herrenschmidt } 1125184cd4a3SBenjamin Herrenschmidt 1126fb446ad0SGavin Shan /* 1127fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1128fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1129fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1130fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1131fb446ad0SGavin Shan */ 11321e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1133184cd4a3SBenjamin Herrenschmidt { 1134fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1135184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11361e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1137ccd1c191SGavin Shan unsigned int pe_num; 1138ccd1c191SGavin Shan 1139ccd1c191SGavin Shan /* 1140ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1141ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1142ccd1c191SGavin Shan */ 1143ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1144ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1145ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1146ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1147ccd1c191SGavin Shan return NULL; 1148ccd1c191SGavin Shan } 1149184cd4a3SBenjamin Herrenschmidt 115063803c39SGavin Shan /* PE number for root bus should have been reserved */ 115163803c39SGavin Shan if (pci_is_root_bus(bus) && 115263803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 115363803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 115463803c39SGavin Shan 1155262af557SGuo Chao /* Check if PE is determined by M64 */ 1156a25de7afSAlexey Kardashevskiy if (!pe) 1157a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1158262af557SGuo Chao 1159262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11601e916772SGavin Shan if (!pe) 11611e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1162262af557SGuo Chao 11631e916772SGavin Shan if (!pe) { 1164f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1165fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11661e916772SGavin Shan return NULL; 1167184cd4a3SBenjamin Herrenschmidt } 1168184cd4a3SBenjamin Herrenschmidt 1169262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1170184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1171184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1172184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1173b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1174184cd4a3SBenjamin Herrenschmidt 1175fb446ad0SGavin Shan if (all) 11761f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11771e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1178fb446ad0SGavin Shan else 11791f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11801e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1181184cd4a3SBenjamin Herrenschmidt 1182184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1183184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11841e916772SGavin Shan pnv_ioda_free_pe(pe); 1185184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11861e916772SGavin Shan return NULL; 1187184cd4a3SBenjamin Herrenschmidt } 1188184cd4a3SBenjamin Herrenschmidt 1189184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1190184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1191184cd4a3SBenjamin Herrenschmidt 11927ebdf956SGavin Shan /* Put PE to the list */ 11937ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11941e916772SGavin Shan 11951e916772SGavin Shan return pe; 1196184cd4a3SBenjamin Herrenschmidt } 1197184cd4a3SBenjamin Herrenschmidt 1198b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11995d2aa710SAlistair Popple { 1200b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1201b521549aSAlistair Popple long rid; 1202b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1203b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1204b521549aSAlistair Popple struct pci_dn *npu_pdn; 1205b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1206b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1207b521549aSAlistair Popple 1208b521549aSAlistair Popple /* 1209b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1210b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1211b521549aSAlistair Popple * which need to be assigned to four links, implying some 1212b521549aSAlistair Popple * links must share PEs. 1213b521549aSAlistair Popple * 1214b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1215b521549aSAlistair Popple * same GPU get assigned the same PE. 1216b521549aSAlistair Popple */ 1217b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 121892b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1219b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1220b521549aSAlistair Popple if (!pe->pdev) 1221b521549aSAlistair Popple continue; 1222b521549aSAlistair Popple 1223b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1224b521549aSAlistair Popple /* 1225b521549aSAlistair Popple * This device has the same peer GPU so should 1226b521549aSAlistair Popple * be assigned the same PE as the existing 1227b521549aSAlistair Popple * peer NPU. 1228b521549aSAlistair Popple */ 1229b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12301f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1231b521549aSAlistair Popple pci_dev_get(npu_pdev); 1232b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1233b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1234b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1235b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1236b521549aSAlistair Popple 1237b521549aSAlistair Popple /* Map the PE to this link */ 1238b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1239b521549aSAlistair Popple OpalPciBusAll, 1240b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1241b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1242b521549aSAlistair Popple OPAL_MAP_PE); 1243b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1244b521549aSAlistair Popple found_pe = true; 1245b521549aSAlistair Popple break; 1246b521549aSAlistair Popple } 1247b521549aSAlistair Popple } 1248b521549aSAlistair Popple 1249b521549aSAlistair Popple if (!found_pe) 1250b521549aSAlistair Popple /* 1251b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1252b521549aSAlistair Popple * one. 1253b521549aSAlistair Popple */ 1254b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1255b521549aSAlistair Popple else 1256b521549aSAlistair Popple return pe; 1257b521549aSAlistair Popple } 1258b521549aSAlistair Popple 1259b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1260b521549aSAlistair Popple { 12615d2aa710SAlistair Popple struct pci_dev *pdev; 12625d2aa710SAlistair Popple 12635d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1264b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12655d2aa710SAlistair Popple } 12665d2aa710SAlistair Popple 1267cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1268fb446ad0SGavin Shan { 12690e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1270262af557SGuo Chao struct pnv_phb *phb; 12717f2c39e9SFrederic Barrat struct pci_bus *bus; 12727f2c39e9SFrederic Barrat struct pci_dev *pdev; 12730e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1274fb446ad0SGavin Shan 12750e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1276262af557SGuo Chao phb = hose->private_data; 12777f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 127808f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 127908f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1280b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12811ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12820e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1283ccd1c191SGavin Shan } 12847f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_OCAPI) { 12857f2c39e9SFrederic Barrat bus = hose->bus; 12867f2c39e9SFrederic Barrat list_for_each_entry(pdev, &bus->devices, bus_list) 12877f2c39e9SFrederic Barrat pnv_ioda_setup_dev_PE(pdev); 12887f2c39e9SFrederic Barrat } 1289fb446ad0SGavin Shan } 12900e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 12910e759bd7SAlexey Kardashevskiy phb = hose->private_data; 12920e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 12930e759bd7SAlexey Kardashevskiy continue; 12940e759bd7SAlexey Kardashevskiy 12950e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 12960e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 12970e759bd7SAlexey Kardashevskiy } 1298fb446ad0SGavin Shan } 1299184cd4a3SBenjamin Herrenschmidt 1300a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1301ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1302781a868fSWei Yang { 1303781a868fSWei Yang struct pci_bus *bus; 1304781a868fSWei Yang struct pci_controller *hose; 1305781a868fSWei Yang struct pnv_phb *phb; 1306781a868fSWei Yang struct pci_dn *pdn; 130702639b0eSWei Yang int i, j; 1308ee8222feSWei Yang int m64_bars; 1309781a868fSWei Yang 1310781a868fSWei Yang bus = pdev->bus; 1311781a868fSWei Yang hose = pci_bus_to_host(bus); 1312781a868fSWei Yang phb = hose->private_data; 1313781a868fSWei Yang pdn = pci_get_pdn(pdev); 1314781a868fSWei Yang 1315ee8222feSWei Yang if (pdn->m64_single_mode) 1316ee8222feSWei Yang m64_bars = num_vfs; 1317ee8222feSWei Yang else 1318ee8222feSWei Yang m64_bars = 1; 1319ee8222feSWei Yang 132002639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1321ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1322ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1323781a868fSWei Yang continue; 1324781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1325ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1326ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1327ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1328781a868fSWei Yang } 1329781a868fSWei Yang 1330ee8222feSWei Yang kfree(pdn->m64_map); 1331781a868fSWei Yang return 0; 1332781a868fSWei Yang } 1333781a868fSWei Yang 133402639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1335781a868fSWei Yang { 1336781a868fSWei Yang struct pci_bus *bus; 1337781a868fSWei Yang struct pci_controller *hose; 1338781a868fSWei Yang struct pnv_phb *phb; 1339781a868fSWei Yang struct pci_dn *pdn; 1340781a868fSWei Yang unsigned int win; 1341781a868fSWei Yang struct resource *res; 134202639b0eSWei Yang int i, j; 1343781a868fSWei Yang int64_t rc; 134402639b0eSWei Yang int total_vfs; 134502639b0eSWei Yang resource_size_t size, start; 134602639b0eSWei Yang int pe_num; 1347ee8222feSWei Yang int m64_bars; 1348781a868fSWei Yang 1349781a868fSWei Yang bus = pdev->bus; 1350781a868fSWei Yang hose = pci_bus_to_host(bus); 1351781a868fSWei Yang phb = hose->private_data; 1352781a868fSWei Yang pdn = pci_get_pdn(pdev); 135302639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1354781a868fSWei Yang 1355ee8222feSWei Yang if (pdn->m64_single_mode) 1356ee8222feSWei Yang m64_bars = num_vfs; 1357ee8222feSWei Yang else 1358ee8222feSWei Yang m64_bars = 1; 135902639b0eSWei Yang 1360fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1361fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1362fb37e128SMarkus Elfring GFP_KERNEL); 1363ee8222feSWei Yang if (!pdn->m64_map) 1364ee8222feSWei Yang return -ENOMEM; 1365ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1366ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1367ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1368ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1369ee8222feSWei Yang 1370781a868fSWei Yang 1371781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1372781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1373781a868fSWei Yang if (!res->flags || !res->parent) 1374781a868fSWei Yang continue; 1375781a868fSWei Yang 1376ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1377781a868fSWei Yang do { 1378781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1379781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1380781a868fSWei Yang 1381781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1382781a868fSWei Yang goto m64_failed; 1383781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1384781a868fSWei Yang 1385ee8222feSWei Yang pdn->m64_map[j][i] = win; 138602639b0eSWei Yang 1387ee8222feSWei Yang if (pdn->m64_single_mode) { 138802639b0eSWei Yang size = pci_iov_resource_size(pdev, 138902639b0eSWei Yang PCI_IOV_RESOURCES + i); 139002639b0eSWei Yang start = res->start + size * j; 139102639b0eSWei Yang } else { 139202639b0eSWei Yang size = resource_size(res); 139302639b0eSWei Yang start = res->start; 139402639b0eSWei Yang } 1395781a868fSWei Yang 1396781a868fSWei Yang /* Map the M64 here */ 1397ee8222feSWei Yang if (pdn->m64_single_mode) { 1398be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 139902639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 140002639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1401ee8222feSWei Yang pdn->m64_map[j][i], 0); 140202639b0eSWei Yang } 140302639b0eSWei Yang 1404781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1405781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1406ee8222feSWei Yang pdn->m64_map[j][i], 140702639b0eSWei Yang start, 1408781a868fSWei Yang 0, /* unused */ 140902639b0eSWei Yang size); 141002639b0eSWei Yang 141102639b0eSWei Yang 1412781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1413781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1414781a868fSWei Yang win, rc); 1415781a868fSWei Yang goto m64_failed; 1416781a868fSWei Yang } 1417781a868fSWei Yang 1418ee8222feSWei Yang if (pdn->m64_single_mode) 1419781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1420ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 142102639b0eSWei Yang else 142202639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1423ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 142402639b0eSWei Yang 1425781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1426781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1427781a868fSWei Yang win, rc); 1428781a868fSWei Yang goto m64_failed; 1429781a868fSWei Yang } 1430781a868fSWei Yang } 143102639b0eSWei Yang } 1432781a868fSWei Yang return 0; 1433781a868fSWei Yang 1434781a868fSWei Yang m64_failed: 1435ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1436781a868fSWei Yang return -EBUSY; 1437781a868fSWei Yang } 1438781a868fSWei Yang 1439c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1440c035e37bSAlexey Kardashevskiy int num); 1441c035e37bSAlexey Kardashevskiy 1442781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1443781a868fSWei Yang { 1444781a868fSWei Yang struct iommu_table *tbl; 1445781a868fSWei Yang int64_t rc; 1446781a868fSWei Yang 1447b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1448c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1449781a868fSWei Yang if (rc) 1450781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1451781a868fSWei Yang 1452c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14530eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14540eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14550eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1456ac9a5889SAlexey Kardashevskiy } 1457e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1458781a868fSWei Yang } 1459781a868fSWei Yang 1460ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1461781a868fSWei Yang { 1462781a868fSWei Yang struct pci_bus *bus; 1463781a868fSWei Yang struct pci_controller *hose; 1464781a868fSWei Yang struct pnv_phb *phb; 1465781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1466781a868fSWei Yang struct pci_dn *pdn; 1467781a868fSWei Yang 1468781a868fSWei Yang bus = pdev->bus; 1469781a868fSWei Yang hose = pci_bus_to_host(bus); 1470781a868fSWei Yang phb = hose->private_data; 147102639b0eSWei Yang pdn = pci_get_pdn(pdev); 1472781a868fSWei Yang 1473781a868fSWei Yang if (!pdev->is_physfn) 1474781a868fSWei Yang return; 1475781a868fSWei Yang 1476781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1477781a868fSWei Yang if (pe->parent_dev != pdev) 1478781a868fSWei Yang continue; 1479781a868fSWei Yang 1480781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1481781a868fSWei Yang 1482781a868fSWei Yang /* Remove from list */ 1483781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1484781a868fSWei Yang list_del(&pe->list); 1485781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1486781a868fSWei Yang 1487781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1488781a868fSWei Yang 14891e916772SGavin Shan pnv_ioda_free_pe(pe); 1490781a868fSWei Yang } 1491781a868fSWei Yang } 1492781a868fSWei Yang 1493781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1494781a868fSWei Yang { 1495781a868fSWei Yang struct pci_bus *bus; 1496781a868fSWei Yang struct pci_controller *hose; 1497781a868fSWei Yang struct pnv_phb *phb; 14981e916772SGavin Shan struct pnv_ioda_pe *pe; 1499781a868fSWei Yang struct pci_dn *pdn; 1500be283eebSWei Yang u16 num_vfs, i; 1501781a868fSWei Yang 1502781a868fSWei Yang bus = pdev->bus; 1503781a868fSWei Yang hose = pci_bus_to_host(bus); 1504781a868fSWei Yang phb = hose->private_data; 1505781a868fSWei Yang pdn = pci_get_pdn(pdev); 1506781a868fSWei Yang num_vfs = pdn->num_vfs; 1507781a868fSWei Yang 1508781a868fSWei Yang /* Release VF PEs */ 1509ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1510781a868fSWei Yang 1511781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1512ee8222feSWei Yang if (!pdn->m64_single_mode) 1513be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1514781a868fSWei Yang 1515781a868fSWei Yang /* Release M64 windows */ 1516ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1517781a868fSWei Yang 1518781a868fSWei Yang /* Release PE numbers */ 1519be283eebSWei Yang if (pdn->m64_single_mode) { 1520be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15211e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15221e916772SGavin Shan continue; 15231e916772SGavin Shan 15241e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15251e916772SGavin Shan pnv_ioda_free_pe(pe); 1526be283eebSWei Yang } 1527be283eebSWei Yang } else 1528be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1529be283eebSWei Yang /* Releasing pe_num_map */ 1530be283eebSWei Yang kfree(pdn->pe_num_map); 1531781a868fSWei Yang } 1532781a868fSWei Yang } 1533781a868fSWei Yang 1534781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1535781a868fSWei Yang struct pnv_ioda_pe *pe); 15365eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15375eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe); 15385eada8a3SAlexey Kardashevskiy #endif 1539781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1540781a868fSWei Yang { 1541781a868fSWei Yang struct pci_bus *bus; 1542781a868fSWei Yang struct pci_controller *hose; 1543781a868fSWei Yang struct pnv_phb *phb; 1544781a868fSWei Yang struct pnv_ioda_pe *pe; 1545781a868fSWei Yang int pe_num; 1546781a868fSWei Yang u16 vf_index; 1547781a868fSWei Yang struct pci_dn *pdn; 1548781a868fSWei Yang 1549781a868fSWei Yang bus = pdev->bus; 1550781a868fSWei Yang hose = pci_bus_to_host(bus); 1551781a868fSWei Yang phb = hose->private_data; 1552781a868fSWei Yang pdn = pci_get_pdn(pdev); 1553781a868fSWei Yang 1554781a868fSWei Yang if (!pdev->is_physfn) 1555781a868fSWei Yang return; 1556781a868fSWei Yang 1557781a868fSWei Yang /* Reserve PE for each VF */ 1558781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1559be283eebSWei Yang if (pdn->m64_single_mode) 1560be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1561be283eebSWei Yang else 1562be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1563781a868fSWei Yang 1564781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1565781a868fSWei Yang pe->pe_number = pe_num; 1566781a868fSWei Yang pe->phb = phb; 1567781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1568781a868fSWei Yang pe->pbus = NULL; 1569781a868fSWei Yang pe->parent_dev = pdev; 1570781a868fSWei Yang pe->mve_number = -1; 1571781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1572781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1573781a868fSWei Yang 15741f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1575781a868fSWei Yang hose->global_number, pdev->bus->number, 1576781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1577781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1578781a868fSWei Yang 1579781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1580781a868fSWei Yang /* XXX What do we do here ? */ 15811e916772SGavin Shan pnv_ioda_free_pe(pe); 1582781a868fSWei Yang pe->pdev = NULL; 1583781a868fSWei Yang continue; 1584781a868fSWei Yang } 1585781a868fSWei Yang 1586781a868fSWei Yang /* Put PE to the list */ 1587781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1588781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1589781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1590781a868fSWei Yang 1591781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 15925eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15935eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe); 15945eada8a3SAlexey Kardashevskiy #endif 1595781a868fSWei Yang } 1596781a868fSWei Yang } 1597781a868fSWei Yang 1598781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1599781a868fSWei Yang { 1600781a868fSWei Yang struct pci_bus *bus; 1601781a868fSWei Yang struct pci_controller *hose; 1602781a868fSWei Yang struct pnv_phb *phb; 16031e916772SGavin Shan struct pnv_ioda_pe *pe; 1604781a868fSWei Yang struct pci_dn *pdn; 1605781a868fSWei Yang int ret; 1606be283eebSWei Yang u16 i; 1607781a868fSWei Yang 1608781a868fSWei Yang bus = pdev->bus; 1609781a868fSWei Yang hose = pci_bus_to_host(bus); 1610781a868fSWei Yang phb = hose->private_data; 1611781a868fSWei Yang pdn = pci_get_pdn(pdev); 1612781a868fSWei Yang 1613781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1614b0331854SWei Yang if (!pdn->vfs_expanded) { 1615b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1616b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1617b0331854SWei Yang return -ENOSPC; 1618b0331854SWei Yang } 1619b0331854SWei Yang 1620ee8222feSWei Yang /* 1621ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1622ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1623ee8222feSWei Yang */ 1624ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1625ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1626ee8222feSWei Yang return -EBUSY; 1627ee8222feSWei Yang } 1628ee8222feSWei Yang 1629be283eebSWei Yang /* Allocating pe_num_map */ 1630be283eebSWei Yang if (pdn->m64_single_mode) 1631fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1632fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1633be283eebSWei Yang GFP_KERNEL); 1634be283eebSWei Yang else 1635be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1636be283eebSWei Yang 1637be283eebSWei Yang if (!pdn->pe_num_map) 1638be283eebSWei Yang return -ENOMEM; 1639be283eebSWei Yang 1640be283eebSWei Yang if (pdn->m64_single_mode) 1641be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1642be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1643be283eebSWei Yang 1644781a868fSWei Yang /* Calculate available PE for required VFs */ 1645be283eebSWei Yang if (pdn->m64_single_mode) { 1646be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16471e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16481e916772SGavin Shan if (!pe) { 1649be283eebSWei Yang ret = -EBUSY; 1650be283eebSWei Yang goto m64_failed; 1651be283eebSWei Yang } 16521e916772SGavin Shan 16531e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1654be283eebSWei Yang } 1655be283eebSWei Yang } else { 1656781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1657be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 165892b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1659781a868fSWei Yang 0, num_vfs, 0); 166092b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1661781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1662781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1663be283eebSWei Yang kfree(pdn->pe_num_map); 1664781a868fSWei Yang return -EBUSY; 1665781a868fSWei Yang } 1666be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1667781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1668be283eebSWei Yang } 1669be283eebSWei Yang pdn->num_vfs = num_vfs; 1670781a868fSWei Yang 1671781a868fSWei Yang /* Assign M64 window accordingly */ 167202639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1673781a868fSWei Yang if (ret) { 1674781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1675781a868fSWei Yang goto m64_failed; 1676781a868fSWei Yang } 1677781a868fSWei Yang 1678781a868fSWei Yang /* 1679781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1680781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1681781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1682781a868fSWei Yang */ 1683ee8222feSWei Yang if (!pdn->m64_single_mode) { 1684be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1685781a868fSWei Yang if (ret) 1686781a868fSWei Yang goto m64_failed; 1687781a868fSWei Yang } 168802639b0eSWei Yang } 1689781a868fSWei Yang 1690781a868fSWei Yang /* Setup VF PEs */ 1691781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1692781a868fSWei Yang 1693781a868fSWei Yang return 0; 1694781a868fSWei Yang 1695781a868fSWei Yang m64_failed: 1696be283eebSWei Yang if (pdn->m64_single_mode) { 1697be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16981e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16991e916772SGavin Shan continue; 17001e916772SGavin Shan 17011e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 17021e916772SGavin Shan pnv_ioda_free_pe(pe); 1703be283eebSWei Yang } 1704be283eebSWei Yang } else 1705be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1706be283eebSWei Yang 1707be283eebSWei Yang /* Releasing pe_num_map */ 1708be283eebSWei Yang kfree(pdn->pe_num_map); 1709781a868fSWei Yang 1710781a868fSWei Yang return ret; 1711781a868fSWei Yang } 1712781a868fSWei Yang 1713988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1714a8b2f828SGavin Shan { 1715781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1716781a868fSWei Yang 1717a8b2f828SGavin Shan /* Release PCI data */ 1718a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1719a8b2f828SGavin Shan return 0; 1720a8b2f828SGavin Shan } 1721a8b2f828SGavin Shan 1722988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1723a8b2f828SGavin Shan { 1724a8b2f828SGavin Shan /* Allocate PCI data */ 1725a8b2f828SGavin Shan add_dev_pci_data(pdev); 1726781a868fSWei Yang 1727ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1728a8b2f828SGavin Shan } 1729a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1730a8b2f828SGavin Shan 1731959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1732184cd4a3SBenjamin Herrenschmidt { 1733b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1734959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1735184cd4a3SBenjamin Herrenschmidt 1736959c9bddSGavin Shan /* 1737959c9bddSGavin Shan * The function can be called while the PE# 1738959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1739959c9bddSGavin Shan * case. 1740959c9bddSGavin Shan */ 1741959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1742959c9bddSGavin Shan return; 1743184cd4a3SBenjamin Herrenschmidt 1744959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1745cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17460e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1747b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17484617082eSAlexey Kardashevskiy /* 17494617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17504617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17514617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17524617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17534617082eSAlexey Kardashevskiy */ 1754184cd4a3SBenjamin Herrenschmidt } 1755184cd4a3SBenjamin Herrenschmidt 1756a0f98629SRussell Currey static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1757a0f98629SRussell Currey { 1758a0f98629SRussell Currey unsigned short vendor = 0; 1759a0f98629SRussell Currey struct pci_dev *pdev; 1760a0f98629SRussell Currey 1761a0f98629SRussell Currey if (pe->device_count == 1) 1762a0f98629SRussell Currey return true; 1763a0f98629SRussell Currey 1764a0f98629SRussell Currey /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1765a0f98629SRussell Currey if (!pe->pbus) 1766a0f98629SRussell Currey return true; 1767a0f98629SRussell Currey 1768a0f98629SRussell Currey list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1769a0f98629SRussell Currey if (!vendor) { 1770a0f98629SRussell Currey vendor = pdev->vendor; 1771a0f98629SRussell Currey continue; 1772a0f98629SRussell Currey } 1773a0f98629SRussell Currey 1774a0f98629SRussell Currey if (pdev->vendor != vendor) 1775a0f98629SRussell Currey return false; 1776a0f98629SRussell Currey } 1777a0f98629SRussell Currey 1778a0f98629SRussell Currey return true; 1779a0f98629SRussell Currey } 1780a0f98629SRussell Currey 17818e3f1b1dSRussell Currey /* 17828e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17838e3f1b1dSRussell Currey * 17848e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17858e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17868e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17878e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17888e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17898e3f1b1dSRussell Currey * devices in TVE#0. 17908e3f1b1dSRussell Currey * 17918e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17928e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17938e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17948e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17958e3f1b1dSRussell Currey * 17968e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17978e3f1b1dSRussell Currey */ 17988e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17998e3f1b1dSRussell Currey { 18008e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 18018e3f1b1dSRussell Currey struct page *table_pages; 18028e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 18038e3f1b1dSRussell Currey __be64 *tces; 18048e3f1b1dSRussell Currey s64 rc; 18058e3f1b1dSRussell Currey 18068e3f1b1dSRussell Currey /* 18078e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 18088e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 18098e3f1b1dSRussell Currey */ 18108e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 18118e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 18128e3f1b1dSRussell Currey table_size = tce_count << 3; 18138e3f1b1dSRussell Currey 18148e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 18158e3f1b1dSRussell Currey table_size = PAGE_SIZE; 18168e3f1b1dSRussell Currey 18178e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 18188e3f1b1dSRussell Currey get_order(table_size)); 18198e3f1b1dSRussell Currey if (!table_pages) 18208e3f1b1dSRussell Currey goto err; 18218e3f1b1dSRussell Currey 18228e3f1b1dSRussell Currey tces = page_address(table_pages); 18238e3f1b1dSRussell Currey if (!tces) 18248e3f1b1dSRussell Currey goto err; 18258e3f1b1dSRussell Currey 18268e3f1b1dSRussell Currey memset(tces, 0, table_size); 18278e3f1b1dSRussell Currey 18288e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18298e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18308e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18318e3f1b1dSRussell Currey } 18328e3f1b1dSRussell Currey 18338e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18348e3f1b1dSRussell Currey pe->pe_number, 18358e3f1b1dSRussell Currey /* reconfigure window 0 */ 18368e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18378e3f1b1dSRussell Currey 1, 18388e3f1b1dSRussell Currey __pa(tces), 18398e3f1b1dSRussell Currey table_size, 18408e3f1b1dSRussell Currey 1 << tce_order); 18418e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18428e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18438e3f1b1dSRussell Currey return 0; 18448e3f1b1dSRussell Currey } 18458e3f1b1dSRussell Currey err: 18468e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18478e3f1b1dSRussell Currey return -EIO; 18488e3f1b1dSRussell Currey } 18498e3f1b1dSRussell Currey 1850763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1851cd15b048SBenjamin Herrenschmidt { 1852763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1853763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1854cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1855cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1856cd15b048SBenjamin Herrenschmidt uint64_t top; 1857cd15b048SBenjamin Herrenschmidt bool bypass = false; 18588e3f1b1dSRussell Currey s64 rc; 1859cd15b048SBenjamin Herrenschmidt 1860cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1861ed7158baSIngo Molnar return -ENODEV; 1862cd15b048SBenjamin Herrenschmidt 1863cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1864cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1865cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1866cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1867cd15b048SBenjamin Herrenschmidt } 1868cd15b048SBenjamin Herrenschmidt 1869cd15b048SBenjamin Herrenschmidt if (bypass) { 1870cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 18712d9d6f6cSChristoph Hellwig set_dma_ops(&pdev->dev, &dma_nommu_ops); 1872cd15b048SBenjamin Herrenschmidt } else { 18738e3f1b1dSRussell Currey /* 18748e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18758e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18768e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18778e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18788e3f1b1dSRussell Currey */ 18798e3f1b1dSRussell Currey if (dma_mask >> 32 && 18808e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 18818e3f1b1dSRussell Currey pnv_pci_ioda_pe_single_vendor(pe) && 18828e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18838e3f1b1dSRussell Currey /* Configure the bypass mode */ 18848e3f1b1dSRussell Currey rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18858e3f1b1dSRussell Currey if (rc) 18868e3f1b1dSRussell Currey return rc; 18878e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18888e3f1b1dSRussell Currey set_dma_offset(&pdev->dev, (1ULL << 32)); 18892d9d6f6cSChristoph Hellwig set_dma_ops(&pdev->dev, &dma_nommu_ops); 1890253fd51eSAlistair Popple } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1891253fd51eSAlistair Popple /* 1892253fd51eSAlistair Popple * Fail the request if a DMA mask between 32 and 64 bits 1893253fd51eSAlistair Popple * was requested but couldn't be fulfilled. Ideally we 1894253fd51eSAlistair Popple * would do this for 64-bits but historically we have 1895253fd51eSAlistair Popple * always fallen back to 32-bits. 1896253fd51eSAlistair Popple */ 1897253fd51eSAlistair Popple return -ENOMEM; 18988e3f1b1dSRussell Currey } else { 1899cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1900cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1901cd15b048SBenjamin Herrenschmidt } 19028e3f1b1dSRussell Currey } 1903a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 19045d2aa710SAlistair Popple 19055d2aa710SAlistair Popple /* Update peer npu devices */ 1906f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 19075d2aa710SAlistair Popple 1908cd15b048SBenjamin Herrenschmidt return 0; 1909cd15b048SBenjamin Herrenschmidt } 1910cd15b048SBenjamin Herrenschmidt 191153522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1912fe7e85c6SGavin Shan { 191353522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 191453522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1915fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1916fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1917fe7e85c6SGavin Shan u64 end, mask; 1918fe7e85c6SGavin Shan 1919fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1920fe7e85c6SGavin Shan return 0; 1921fe7e85c6SGavin Shan 1922fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1923fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1924fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1925fe7e85c6SGavin Shan 1926fe7e85c6SGavin Shan 1927fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1928fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1929fe7e85c6SGavin Shan mask += mask - 1; 1930fe7e85c6SGavin Shan 1931fe7e85c6SGavin Shan return mask; 1932fe7e85c6SGavin Shan } 1933fe7e85c6SGavin Shan 19345eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 193574251fe2SBenjamin Herrenschmidt { 193674251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 193774251fe2SBenjamin Herrenschmidt 193874251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1939b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1940e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 1941dff4a39eSGavin Shan 19425c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 19435eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 194474251fe2SBenjamin Herrenschmidt } 194574251fe2SBenjamin Herrenschmidt } 194674251fe2SBenjamin Herrenschmidt 1947fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1948fd141d1aSBenjamin Herrenschmidt bool real_mode) 1949fd141d1aSBenjamin Herrenschmidt { 1950fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1951fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1952fd141d1aSBenjamin Herrenschmidt } 1953fd141d1aSBenjamin Herrenschmidt 1954a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1955decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19564cce9550SGavin Shan { 19570eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19580eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19590eaf4defSAlexey Kardashevskiy next); 19600eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1961b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1962fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19634cce9550SGavin Shan unsigned long start, end, inc; 19644cce9550SGavin Shan 1965decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1966decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1967decbda25SAlexey Kardashevskiy npages - 1); 19684cce9550SGavin Shan 19694cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19704cce9550SGavin Shan start |= (1ull << 63); 19714cce9550SGavin Shan end |= (1ull << 63); 19724cce9550SGavin Shan inc = 16; 19734cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19744cce9550SGavin Shan 19754cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19764cce9550SGavin Shan while (start <= end) { 19778e0a1611SAlexey Kardashevskiy if (rm) 1978001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19798e0a1611SAlexey Kardashevskiy else 1980001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1981001ff2eeSMichael Ellerman 19824cce9550SGavin Shan start += inc; 19834cce9550SGavin Shan } 19844cce9550SGavin Shan 19854cce9550SGavin Shan /* 19864cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19874cce9550SGavin Shan * and we don't care on free() 19884cce9550SGavin Shan */ 19894cce9550SGavin Shan } 19904cce9550SGavin Shan 1991decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1992decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1993decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 199400085f1eSKrzysztof Kozlowski unsigned long attrs) 1995decbda25SAlexey Kardashevskiy { 1996decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1997decbda25SAlexey Kardashevskiy attrs); 1998decbda25SAlexey Kardashevskiy 199908acce1cSBenjamin Herrenschmidt if (!ret) 2000a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2001decbda25SAlexey Kardashevskiy 2002decbda25SAlexey Kardashevskiy return ret; 2003decbda25SAlexey Kardashevskiy } 2004decbda25SAlexey Kardashevskiy 200505c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 200605c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 200705c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 200805c6cfb9SAlexey Kardashevskiy { 2009a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 201005c6cfb9SAlexey Kardashevskiy 201108acce1cSBenjamin Herrenschmidt if (!ret) 2012a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 201305c6cfb9SAlexey Kardashevskiy 201405c6cfb9SAlexey Kardashevskiy return ret; 201505c6cfb9SAlexey Kardashevskiy } 2016a540aa56SAlexey Kardashevskiy 2017a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 2018a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2019a540aa56SAlexey Kardashevskiy { 2020a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 2021a540aa56SAlexey Kardashevskiy 2022a540aa56SAlexey Kardashevskiy if (!ret) 2023a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 2024a540aa56SAlexey Kardashevskiy 2025a540aa56SAlexey Kardashevskiy return ret; 2026a540aa56SAlexey Kardashevskiy } 202705c6cfb9SAlexey Kardashevskiy #endif 202805c6cfb9SAlexey Kardashevskiy 2029decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 2030decbda25SAlexey Kardashevskiy long npages) 2031decbda25SAlexey Kardashevskiy { 2032decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2033decbda25SAlexey Kardashevskiy 2034a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2035decbda25SAlexey Kardashevskiy } 2036decbda25SAlexey Kardashevskiy 2037da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2038decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 203905c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 204005c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 2041a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 2042090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 204305c6cfb9SAlexey Kardashevskiy #endif 2044decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 2045da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2046da004c36SAlexey Kardashevskiy }; 2047da004c36SAlexey Kardashevskiy 2048a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2049a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2050a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2051bef9253fSAlexey Kardashevskiy 20526b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20530bbcdb43SAlexey Kardashevskiy { 2054fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2055a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 20560bbcdb43SAlexey Kardashevskiy 20570bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 20580bbcdb43SAlexey Kardashevskiy if (rm) 2059001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 20600bbcdb43SAlexey Kardashevskiy else 2061001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20620bbcdb43SAlexey Kardashevskiy } 20630bbcdb43SAlexey Kardashevskiy 2064a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20655780fb04SAlexey Kardashevskiy { 20665780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2067fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2068a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20695780fb04SAlexey Kardashevskiy 20705780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2071001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20725780fb04SAlexey Kardashevskiy } 20735780fb04SAlexey Kardashevskiy 2074fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2075fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2076fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20774cce9550SGavin Shan { 20784d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20794cce9550SGavin Shan unsigned long start, end, inc; 20804cce9550SGavin Shan 20814cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2082a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2083fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20844cce9550SGavin Shan end = start; 20854cce9550SGavin Shan 20864cce9550SGavin Shan /* Figure out the start, end and step */ 2087decbda25SAlexey Kardashevskiy start |= (index << shift); 2088decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2089b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20904cce9550SGavin Shan mb(); 20914cce9550SGavin Shan 20924cce9550SGavin Shan while (start <= end) { 20938e0a1611SAlexey Kardashevskiy if (rm) 2094001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 20958e0a1611SAlexey Kardashevskiy else 2096001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 20974cce9550SGavin Shan start += inc; 20984cce9550SGavin Shan } 20994cce9550SGavin Shan } 21004cce9550SGavin Shan 2101f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2102f0228c41SBenjamin Herrenschmidt { 2103f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2104f0228c41SBenjamin Herrenschmidt 2105f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2106f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2107f0228c41SBenjamin Herrenschmidt else 2108f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2109f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2110f0228c41SBenjamin Herrenschmidt } 2111f0228c41SBenjamin Herrenschmidt 2112e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2113e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2114e57080f1SAlexey Kardashevskiy { 2115e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2116e57080f1SAlexey Kardashevskiy 2117a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2118e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2119e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2120f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2121f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2122f0228c41SBenjamin Herrenschmidt 2123616badd2SAlistair Popple /* 2124616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2125616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2126616badd2SAlistair Popple * should go via the OPAL call. 2127616badd2SAlistair Popple */ 2128616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 21290bbcdb43SAlexey Kardashevskiy /* 21300bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 21310bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 21320bbcdb43SAlexey Kardashevskiy * the entire cache for it. 21330bbcdb43SAlexey Kardashevskiy */ 2134f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21355d2aa710SAlistair Popple continue; 21365d2aa710SAlistair Popple } 2137f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2138f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 213985674868SAlexey Kardashevskiy index, npages); 2140f0228c41SBenjamin Herrenschmidt else 2141f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2142f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2143f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2144f0228c41SBenjamin Herrenschmidt index << shift, npages); 2145e57080f1SAlexey Kardashevskiy } 2146e57080f1SAlexey Kardashevskiy } 2147e57080f1SAlexey Kardashevskiy 21486b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 21496b3d12a9SAlistair Popple { 21506b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 21516b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21526b3d12a9SAlistair Popple else 21536b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 21546b3d12a9SAlistair Popple } 21556b3d12a9SAlistair Popple 2156decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2157decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2158decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 215900085f1eSKrzysztof Kozlowski unsigned long attrs) 21604cce9550SGavin Shan { 2161decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2162decbda25SAlexey Kardashevskiy attrs); 21634cce9550SGavin Shan 216408acce1cSBenjamin Herrenschmidt if (!ret) 2165decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2166decbda25SAlexey Kardashevskiy 2167decbda25SAlexey Kardashevskiy return ret; 2168decbda25SAlexey Kardashevskiy } 2169decbda25SAlexey Kardashevskiy 217005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 217105c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 217205c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 217305c6cfb9SAlexey Kardashevskiy { 2174a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 217505c6cfb9SAlexey Kardashevskiy 217608acce1cSBenjamin Herrenschmidt if (!ret) 217705c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 217805c6cfb9SAlexey Kardashevskiy 217905c6cfb9SAlexey Kardashevskiy return ret; 218005c6cfb9SAlexey Kardashevskiy } 2181a540aa56SAlexey Kardashevskiy 2182a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2183a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2184a540aa56SAlexey Kardashevskiy { 2185a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 2186a540aa56SAlexey Kardashevskiy 2187a540aa56SAlexey Kardashevskiy if (!ret) 2188a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2189a540aa56SAlexey Kardashevskiy 2190a540aa56SAlexey Kardashevskiy return ret; 2191a540aa56SAlexey Kardashevskiy } 219205c6cfb9SAlexey Kardashevskiy #endif 219305c6cfb9SAlexey Kardashevskiy 2194decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2195decbda25SAlexey Kardashevskiy long npages) 2196decbda25SAlexey Kardashevskiy { 2197decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2198decbda25SAlexey Kardashevskiy 2199decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 22004cce9550SGavin Shan } 22014cce9550SGavin Shan 2202da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2203decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 220405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 220505c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2206a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 2207090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 220805c6cfb9SAlexey Kardashevskiy #endif 2209decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2210da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2211da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 2212da004c36SAlexey Kardashevskiy }; 2213da004c36SAlexey Kardashevskiy 2214801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2215801846d1SGavin Shan { 2216801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2217801846d1SGavin Shan 2218801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2219801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2220801846d1SGavin Shan */ 2221801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2222801846d1SGavin Shan return 0; 2223801846d1SGavin Shan 2224801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2225801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2226801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2227801846d1SGavin Shan *weight += 3; 2228801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2229801846d1SGavin Shan *weight += 15; 2230801846d1SGavin Shan else 2231801846d1SGavin Shan *weight += 10; 2232801846d1SGavin Shan 2233801846d1SGavin Shan return 0; 2234801846d1SGavin Shan } 2235801846d1SGavin Shan 2236801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2237801846d1SGavin Shan { 2238801846d1SGavin Shan unsigned int weight = 0; 2239801846d1SGavin Shan 2240801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2241801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2242801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2243801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2244801846d1SGavin Shan return weight; 2245801846d1SGavin Shan } 2246801846d1SGavin Shan #endif 2247801846d1SGavin Shan 2248801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2249801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2250801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2251801846d1SGavin Shan struct pci_dev *pdev; 2252801846d1SGavin Shan 2253801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2254801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2255801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2256801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2257801846d1SGavin Shan } 2258801846d1SGavin Shan 2259801846d1SGavin Shan return weight; 2260801846d1SGavin Shan } 2261801846d1SGavin Shan 2262b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 22632b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2264184cd4a3SBenjamin Herrenschmidt { 2265184cd4a3SBenjamin Herrenschmidt 2266184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2267184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22682b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22692b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2270184cd4a3SBenjamin Herrenschmidt int64_t rc; 2271184cd4a3SBenjamin Herrenschmidt void *addr; 2272184cd4a3SBenjamin Herrenschmidt 2273184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2274184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2275184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22762b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22772b923ed1SGavin Shan if (!weight) 22782b923ed1SGavin Shan return; 2279184cd4a3SBenjamin Herrenschmidt 22802b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22812b923ed1SGavin Shan &total_weight); 22822b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22832b923ed1SGavin Shan if (!segs) 22842b923ed1SGavin Shan segs = 1; 22852b923ed1SGavin Shan 22862b923ed1SGavin Shan /* 22872b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22882b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22892b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22902b923ed1SGavin Shan * is allocated successfully. 22912b923ed1SGavin Shan */ 22922b923ed1SGavin Shan do { 22932b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22942b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22952b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22962b923ed1SGavin Shan IODA_INVALID_PE) 22972b923ed1SGavin Shan avail++; 22982b923ed1SGavin Shan } 22992b923ed1SGavin Shan 23002b923ed1SGavin Shan if (avail == segs) 23012b923ed1SGavin Shan goto found; 23022b923ed1SGavin Shan } 23032b923ed1SGavin Shan } while (--segs); 23042b923ed1SGavin Shan 23052b923ed1SGavin Shan if (!segs) { 23062b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 23072b923ed1SGavin Shan return; 23082b923ed1SGavin Shan } 23092b923ed1SGavin Shan 23102b923ed1SGavin Shan found: 23110eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 231282eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 231382eae1afSAlexey Kardashevskiy return; 231482eae1afSAlexey Kardashevskiy 2315b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2316b348aa65SAlexey Kardashevskiy pe->pe_number); 23170eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2318c5773822SAlexey Kardashevskiy 2319184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 23202b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 23212b923ed1SGavin Shan weight, total_weight, base, segs); 2322184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2323acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2324acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2325184cd4a3SBenjamin Herrenschmidt 2326184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2327184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2328184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2329184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2330acce971cSGavin Shan * 2331acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2332acce971cSGavin Shan * bytes 2333184cd4a3SBenjamin Herrenschmidt */ 2334acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2335184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2336acce971cSGavin Shan get_order(tce32_segsz * segs)); 2337184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2338184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2339184cd4a3SBenjamin Herrenschmidt goto fail; 2340184cd4a3SBenjamin Herrenschmidt } 2341184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2342acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2343184cd4a3SBenjamin Herrenschmidt 2344184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2345184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2346184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2347184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2348184cd4a3SBenjamin Herrenschmidt base + i, 1, 2349acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2350acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2351184cd4a3SBenjamin Herrenschmidt if (rc) { 2352184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2353184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2354184cd4a3SBenjamin Herrenschmidt goto fail; 2355184cd4a3SBenjamin Herrenschmidt } 2356184cd4a3SBenjamin Herrenschmidt } 2357184cd4a3SBenjamin Herrenschmidt 23582b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 23592b923ed1SGavin Shan for (i = base; i < base + segs; i++) 23602b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 23612b923ed1SGavin Shan 2362184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2363acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2364acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2365acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2366184cd4a3SBenjamin Herrenschmidt 2367da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23684793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23694793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2370184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2371184cd4a3SBenjamin Herrenschmidt 2372f21b0a45SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 23735eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 237474251fe2SBenjamin Herrenschmidt 2375184cd4a3SBenjamin Herrenschmidt return; 2376184cd4a3SBenjamin Herrenschmidt fail: 2377184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2378184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2379acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23800eaf4defSAlexey Kardashevskiy if (tbl) { 23810eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2382e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23830eaf4defSAlexey Kardashevskiy } 2384184cd4a3SBenjamin Herrenschmidt } 2385184cd4a3SBenjamin Herrenschmidt 238643cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 238743cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 238843cb60abSAlexey Kardashevskiy { 238943cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 239043cb60abSAlexey Kardashevskiy table_group); 239143cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 239243cb60abSAlexey Kardashevskiy int64_t rc; 2393bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2394bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 239543cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 239643cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 239743cb60abSAlexey Kardashevskiy 23984793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 239943cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 240043cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 240143cb60abSAlexey Kardashevskiy 240243cb60abSAlexey Kardashevskiy /* 240343cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 240443cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 240543cb60abSAlexey Kardashevskiy */ 240643cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 240743cb60abSAlexey Kardashevskiy pe->pe_number, 24084793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2409bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 241043cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2411bbb845c4SAlexey Kardashevskiy size << 3, 241243cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 241343cb60abSAlexey Kardashevskiy if (rc) { 241443cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 241543cb60abSAlexey Kardashevskiy return rc; 241643cb60abSAlexey Kardashevskiy } 241743cb60abSAlexey Kardashevskiy 241843cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 241943cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2420ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 242143cb60abSAlexey Kardashevskiy 242243cb60abSAlexey Kardashevskiy return 0; 242343cb60abSAlexey Kardashevskiy } 242443cb60abSAlexey Kardashevskiy 242525529100SFrederic Barrat void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2426cd15b048SBenjamin Herrenschmidt { 2427cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2428cd15b048SBenjamin Herrenschmidt int64_t rc; 2429cd15b048SBenjamin Herrenschmidt 2430cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2431cd15b048SBenjamin Herrenschmidt if (enable) { 2432cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2433cd15b048SBenjamin Herrenschmidt 2434cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2435cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2436cd15b048SBenjamin Herrenschmidt pe->pe_number, 2437cd15b048SBenjamin Herrenschmidt window_id, 2438cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2439cd15b048SBenjamin Herrenschmidt top); 2440cd15b048SBenjamin Herrenschmidt } else { 2441cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2442cd15b048SBenjamin Herrenschmidt pe->pe_number, 2443cd15b048SBenjamin Herrenschmidt window_id, 2444cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2445cd15b048SBenjamin Herrenschmidt 0); 2446cd15b048SBenjamin Herrenschmidt } 2447cd15b048SBenjamin Herrenschmidt if (rc) 2448cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2449cd15b048SBenjamin Herrenschmidt else 2450cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2451cd15b048SBenjamin Herrenschmidt } 2452cd15b048SBenjamin Herrenschmidt 24534793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 24544793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2455090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 24564793d65dSAlexey Kardashevskiy { 24574793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 24584793d65dSAlexey Kardashevskiy table_group); 24594793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 24604793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 24614793d65dSAlexey Kardashevskiy long ret; 24624793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 24634793d65dSAlexey Kardashevskiy 24644793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24654793d65dSAlexey Kardashevskiy if (!tbl) 24664793d65dSAlexey Kardashevskiy return -ENOMEM; 24674793d65dSAlexey Kardashevskiy 246811edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 246911edf116SAlexey Kardashevskiy 24704793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24714793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 2472090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 24734793d65dSAlexey Kardashevskiy if (ret) { 2474e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24754793d65dSAlexey Kardashevskiy return ret; 24764793d65dSAlexey Kardashevskiy } 24774793d65dSAlexey Kardashevskiy 24784793d65dSAlexey Kardashevskiy *ptbl = tbl; 24794793d65dSAlexey Kardashevskiy 24804793d65dSAlexey Kardashevskiy return 0; 24814793d65dSAlexey Kardashevskiy } 24824793d65dSAlexey Kardashevskiy 248346d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 248446d3e1e1SAlexey Kardashevskiy { 248546d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 248646d3e1e1SAlexey Kardashevskiy long rc; 248746d3e1e1SAlexey Kardashevskiy 2488bb005455SNishanth Aravamudan /* 2489fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2490fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2491fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2492fa144869SNishanth Aravamudan */ 2493fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2494fa144869SNishanth Aravamudan 2495fa144869SNishanth Aravamudan /* 2496bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2497bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2498bb005455SNishanth Aravamudan * cause errors later. 2499bb005455SNishanth Aravamudan */ 2500fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2501bb005455SNishanth Aravamudan 250246d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 250346d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2504bb005455SNishanth Aravamudan window_size, 2505090bad39SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl); 250646d3e1e1SAlexey Kardashevskiy if (rc) { 250746d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 250846d3e1e1SAlexey Kardashevskiy rc); 250946d3e1e1SAlexey Kardashevskiy return rc; 251046d3e1e1SAlexey Kardashevskiy } 251146d3e1e1SAlexey Kardashevskiy 251246d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 251346d3e1e1SAlexey Kardashevskiy 251446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 251546d3e1e1SAlexey Kardashevskiy if (rc) { 251646d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 251746d3e1e1SAlexey Kardashevskiy rc); 2518e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 251946d3e1e1SAlexey Kardashevskiy return rc; 252046d3e1e1SAlexey Kardashevskiy } 252146d3e1e1SAlexey Kardashevskiy 252246d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 252346d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 252446d3e1e1SAlexey Kardashevskiy 252546d3e1e1SAlexey Kardashevskiy return 0; 252646d3e1e1SAlexey Kardashevskiy } 252746d3e1e1SAlexey Kardashevskiy 2528b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2529b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2530b5926430SAlexey Kardashevskiy int num) 2531b5926430SAlexey Kardashevskiy { 2532b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2533b5926430SAlexey Kardashevskiy table_group); 2534b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2535b5926430SAlexey Kardashevskiy long ret; 2536b5926430SAlexey Kardashevskiy 2537b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2538b5926430SAlexey Kardashevskiy 2539b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2540b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2541b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2542b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2543b5926430SAlexey Kardashevskiy if (ret) 2544b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2545b5926430SAlexey Kardashevskiy else 2546ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2547b5926430SAlexey Kardashevskiy 2548b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2549b5926430SAlexey Kardashevskiy 2550b5926430SAlexey Kardashevskiy return ret; 2551b5926430SAlexey Kardashevskiy } 2552b5926430SAlexey Kardashevskiy #endif 2553b5926430SAlexey Kardashevskiy 2554f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 255500547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 255600547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 255700547193SAlexey Kardashevskiy { 255800547193SAlexey Kardashevskiy unsigned long bytes = 0; 255900547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 256000547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 256100547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 256200547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 256300547193SAlexey Kardashevskiy unsigned long direct_table_size; 256400547193SAlexey Kardashevskiy 256500547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 256600547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 256700547193SAlexey Kardashevskiy return 0; 256800547193SAlexey Kardashevskiy 256900547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 257000547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 257100547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 257200547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 257300547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 257400547193SAlexey Kardashevskiy 257500547193SAlexey Kardashevskiy for ( ; levels; --levels) { 257600547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 257700547193SAlexey Kardashevskiy 257800547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 257900547193SAlexey Kardashevskiy tce_table_size <<= 3; 2580e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2581e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 258200547193SAlexey Kardashevskiy } 258300547193SAlexey Kardashevskiy 2584090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2585090bad39SAlexey Kardashevskiy } 2586090bad39SAlexey Kardashevskiy 2587090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2588090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2589090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2590090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2591090bad39SAlexey Kardashevskiy { 2592090bad39SAlexey Kardashevskiy return pnv_pci_ioda2_create_table(table_group, 2593090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 259400547193SAlexey Kardashevskiy } 259500547193SAlexey Kardashevskiy 2596f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2597cd15b048SBenjamin Herrenschmidt { 2598f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2599f87a8864SAlexey Kardashevskiy table_group); 260046d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 260146d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2602cd15b048SBenjamin Herrenschmidt 2603f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 260446d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2605db08e1d5SAlexey Kardashevskiy if (pe->pbus) 26065eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2607e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2608cd15b048SBenjamin Herrenschmidt } 2609cd15b048SBenjamin Herrenschmidt 2610f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2611f87a8864SAlexey Kardashevskiy { 2612f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2613f87a8864SAlexey Kardashevskiy table_group); 2614f87a8864SAlexey Kardashevskiy 261546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2616db08e1d5SAlexey Kardashevskiy if (pe->pbus) 26175eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2618f87a8864SAlexey Kardashevskiy } 2619f87a8864SAlexey Kardashevskiy 2620f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 262100547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2622090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 26234793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 26244793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2625f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2626f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2627f87a8864SAlexey Kardashevskiy }; 2628b5cb9ab1SAlexey Kardashevskiy 2629b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2630b5cb9ab1SAlexey Kardashevskiy { 2631b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2632b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2633b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2634b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2635b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2636b5cb9ab1SAlexey Kardashevskiy 2637b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2638b5cb9ab1SAlexey Kardashevskiy return 0; 2639b5cb9ab1SAlexey Kardashevskiy 2640b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2641b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 26427f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2643b5cb9ab1SAlexey Kardashevskiy return 0; 2644b5cb9ab1SAlexey Kardashevskiy 2645b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2646b5cb9ab1SAlexey Kardashevskiy 2647b5cb9ab1SAlexey Kardashevskiy return 1; 2648b5cb9ab1SAlexey Kardashevskiy } 2649b5cb9ab1SAlexey Kardashevskiy 2650b5cb9ab1SAlexey Kardashevskiy /* 2651b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2652b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2653b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2654b5cb9ab1SAlexey Kardashevskiy */ 2655b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2656b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2657b5cb9ab1SAlexey Kardashevskiy { 2658b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2659b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2660b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2661b5cb9ab1SAlexey Kardashevskiy 2662b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2663b5cb9ab1SAlexey Kardashevskiy 2664b5cb9ab1SAlexey Kardashevskiy return npe; 2665b5cb9ab1SAlexey Kardashevskiy } 2666b5cb9ab1SAlexey Kardashevskiy 2667b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2668b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2669b5cb9ab1SAlexey Kardashevskiy { 2670d41ce7b1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2671d41ce7b1SAlexey Kardashevskiy int num2 = (num == 0) ? 1 : 0; 2672b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2673b5cb9ab1SAlexey Kardashevskiy 2674b5cb9ab1SAlexey Kardashevskiy if (ret) 2675b5cb9ab1SAlexey Kardashevskiy return ret; 2676b5cb9ab1SAlexey Kardashevskiy 2677d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2678d41ce7b1SAlexey Kardashevskiy pnv_npu_unset_window(npe, num2); 2679d41ce7b1SAlexey Kardashevskiy 2680d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_set_window(npe, num, tbl); 2681d41ce7b1SAlexey Kardashevskiy if (ret) { 2682b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2683d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2684d41ce7b1SAlexey Kardashevskiy pnv_npu_set_window(npe, num2, 2685d41ce7b1SAlexey Kardashevskiy table_group->tables[num2]); 2686d41ce7b1SAlexey Kardashevskiy } 2687b5cb9ab1SAlexey Kardashevskiy 2688b5cb9ab1SAlexey Kardashevskiy return ret; 2689b5cb9ab1SAlexey Kardashevskiy } 2690b5cb9ab1SAlexey Kardashevskiy 2691b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2692b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2693b5cb9ab1SAlexey Kardashevskiy int num) 2694b5cb9ab1SAlexey Kardashevskiy { 2695d41ce7b1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2696d41ce7b1SAlexey Kardashevskiy int num2 = (num == 0) ? 1 : 0; 2697b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2698b5cb9ab1SAlexey Kardashevskiy 2699b5cb9ab1SAlexey Kardashevskiy if (ret) 2700b5cb9ab1SAlexey Kardashevskiy return ret; 2701b5cb9ab1SAlexey Kardashevskiy 2702d41ce7b1SAlexey Kardashevskiy if (!npe->table_group.tables[num]) 2703d41ce7b1SAlexey Kardashevskiy return 0; 2704d41ce7b1SAlexey Kardashevskiy 2705d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_unset_window(npe, num); 2706d41ce7b1SAlexey Kardashevskiy if (ret) 2707d41ce7b1SAlexey Kardashevskiy return ret; 2708d41ce7b1SAlexey Kardashevskiy 2709d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2710d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]); 2711d41ce7b1SAlexey Kardashevskiy 2712d41ce7b1SAlexey Kardashevskiy return ret; 2713b5cb9ab1SAlexey Kardashevskiy } 2714b5cb9ab1SAlexey Kardashevskiy 2715b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2716b5cb9ab1SAlexey Kardashevskiy { 2717b5cb9ab1SAlexey Kardashevskiy /* 2718b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2719b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2720b5cb9ab1SAlexey Kardashevskiy */ 2721b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2722b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2723b5cb9ab1SAlexey Kardashevskiy } 2724b5cb9ab1SAlexey Kardashevskiy 2725b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2726b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2727090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 2728b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2729b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2730b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2731b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2732b5cb9ab1SAlexey Kardashevskiy }; 2733b5cb9ab1SAlexey Kardashevskiy 27345eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe, 27355eada8a3SAlexey Kardashevskiy struct pci_bus *bus) 27365eada8a3SAlexey Kardashevskiy { 27375eada8a3SAlexey Kardashevskiy struct pci_dev *dev; 27385eada8a3SAlexey Kardashevskiy 27395eada8a3SAlexey Kardashevskiy list_for_each_entry(dev, &bus->devices, bus_list) { 27405eada8a3SAlexey Kardashevskiy iommu_add_device(&pe->table_group, &dev->dev); 27415eada8a3SAlexey Kardashevskiy 27425eada8a3SAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 27435eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, 27445eada8a3SAlexey Kardashevskiy dev->subordinate); 27455eada8a3SAlexey Kardashevskiy } 27465eada8a3SAlexey Kardashevskiy } 27475eada8a3SAlexey Kardashevskiy 27485eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe) 27495eada8a3SAlexey Kardashevskiy { 27505eada8a3SAlexey Kardashevskiy if (!pnv_pci_ioda_pe_dma_weight(pe)) 27515eada8a3SAlexey Kardashevskiy return; 27525eada8a3SAlexey Kardashevskiy 27535eada8a3SAlexey Kardashevskiy iommu_register_group(&pe->table_group, pe->phb->hose->global_number, 27545eada8a3SAlexey Kardashevskiy pe->pe_number); 27555eada8a3SAlexey Kardashevskiy 27565eada8a3SAlexey Kardashevskiy /* 27575eada8a3SAlexey Kardashevskiy * set_iommu_table_base(&pe->pdev->dev, tbl) should have been called 27585eada8a3SAlexey Kardashevskiy * by now 27595eada8a3SAlexey Kardashevskiy */ 27605eada8a3SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 27615eada8a3SAlexey Kardashevskiy iommu_add_device(&pe->table_group, &pe->pdev->dev); 27625eada8a3SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 27635eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, pe->pbus); 27645eada8a3SAlexey Kardashevskiy } 27655eada8a3SAlexey Kardashevskiy 2766b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2767b5cb9ab1SAlexey Kardashevskiy { 2768b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2769b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2770b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2771b5cb9ab1SAlexey Kardashevskiy 2772b5cb9ab1SAlexey Kardashevskiy /* 27735eada8a3SAlexey Kardashevskiy * There are 4 types of PEs: 27745eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS: a downstream port with an adapter, 27755eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 27765eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it, 27775eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 27785eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_VF: a SRIOV virtual function, 27795eada8a3SAlexey Kardashevskiy * created from pnv_pcibios_sriov_enable(); 27805eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_DEV: an NPU or OCAPI device, 27815eada8a3SAlexey Kardashevskiy * created from pnv_pci_ioda_fixup(). 27825eada8a3SAlexey Kardashevskiy * 27835eada8a3SAlexey Kardashevskiy * Normally a PE is represented by an IOMMU group, however for 27845eada8a3SAlexey Kardashevskiy * devices with side channels the groups need to be more strict. 27855eada8a3SAlexey Kardashevskiy */ 27865eada8a3SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 27875eada8a3SAlexey Kardashevskiy phb = hose->private_data; 27885eada8a3SAlexey Kardashevskiy 27895eada8a3SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU_NVLINK) 27905eada8a3SAlexey Kardashevskiy continue; 27915eada8a3SAlexey Kardashevskiy 27925eada8a3SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 27935eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe); 27945eada8a3SAlexey Kardashevskiy } 27955eada8a3SAlexey Kardashevskiy 27965eada8a3SAlexey Kardashevskiy /* 2797b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2798b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2799b5cb9ab1SAlexey Kardashevskiy */ 2800b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2801b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2802b5cb9ab1SAlexey Kardashevskiy 28037f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2804b5cb9ab1SAlexey Kardashevskiy continue; 2805b5cb9ab1SAlexey Kardashevskiy 2806b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2807b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2808b5cb9ab1SAlexey Kardashevskiy if (gpe) 2809b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2810b5cb9ab1SAlexey Kardashevskiy } 2811b5cb9ab1SAlexey Kardashevskiy } 2812b5cb9ab1SAlexey Kardashevskiy } 2813b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2814b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2815f87a8864SAlexey Kardashevskiy #endif 2816f87a8864SAlexey Kardashevskiy 28177ef73cd3SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 28187ef73cd3SAlexey Kardashevskiy { 28197ef73cd3SAlexey Kardashevskiy struct pci_controller *hose = phb->hose; 28207ef73cd3SAlexey Kardashevskiy struct device_node *dn = hose->dn; 28217ef73cd3SAlexey Kardashevskiy unsigned long mask = 0; 28227ef73cd3SAlexey Kardashevskiy int i, rc, count; 28237ef73cd3SAlexey Kardashevskiy u32 val; 28247ef73cd3SAlexey Kardashevskiy 28257ef73cd3SAlexey Kardashevskiy count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 28267ef73cd3SAlexey Kardashevskiy if (count <= 0) { 28277ef73cd3SAlexey Kardashevskiy mask = SZ_4K | SZ_64K; 28287ef73cd3SAlexey Kardashevskiy /* Add 16M for POWER8 by default */ 28297ef73cd3SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_ARCH_207S) && 28307ef73cd3SAlexey Kardashevskiy !cpu_has_feature(CPU_FTR_ARCH_300)) 283100c376fdSAlexey Kardashevskiy mask |= SZ_16M | SZ_256M; 28327ef73cd3SAlexey Kardashevskiy return mask; 28337ef73cd3SAlexey Kardashevskiy } 28347ef73cd3SAlexey Kardashevskiy 28357ef73cd3SAlexey Kardashevskiy for (i = 0; i < count; i++) { 28367ef73cd3SAlexey Kardashevskiy rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 28377ef73cd3SAlexey Kardashevskiy i, &val); 28387ef73cd3SAlexey Kardashevskiy if (rc == 0) 28397ef73cd3SAlexey Kardashevskiy mask |= 1ULL << val; 28407ef73cd3SAlexey Kardashevskiy } 28417ef73cd3SAlexey Kardashevskiy 28427ef73cd3SAlexey Kardashevskiy return mask; 28437ef73cd3SAlexey Kardashevskiy } 28447ef73cd3SAlexey Kardashevskiy 2845373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2846373f5657SGavin Shan struct pnv_ioda_pe *pe) 2847373f5657SGavin Shan { 2848373f5657SGavin Shan int64_t rc; 2849373f5657SGavin Shan 2850ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2851ccd1c191SGavin Shan return; 2852ccd1c191SGavin Shan 2853f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2854f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2855f87a8864SAlexey Kardashevskiy 2856373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2857373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2858aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2859373f5657SGavin Shan 2860e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 28614793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 28624793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 28634793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 28644793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 28654793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 28667ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2867e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2868e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2869e5aad1e6SAlexey Kardashevskiy #endif 2870e5aad1e6SAlexey Kardashevskiy 287146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2872801846d1SGavin Shan if (rc) 287346d3e1e1SAlexey Kardashevskiy return; 287446d3e1e1SAlexey Kardashevskiy 287520f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 28765eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2877373f5657SGavin Shan } 2878373f5657SGavin Shan 28794ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2880137436c9SGavin Shan { 2881137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2882137436c9SGavin Shan ioda.irq_chip); 2883137436c9SGavin Shan 28844ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 28854ee11c1aSSuresh Warrier } 28864ee11c1aSSuresh Warrier 28874ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 28884ee11c1aSSuresh Warrier { 28894ee11c1aSSuresh Warrier int64_t rc; 28904ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 28914ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 28924ee11c1aSSuresh Warrier 28934ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2894137436c9SGavin Shan WARN_ON_ONCE(rc); 2895137436c9SGavin Shan 2896137436c9SGavin Shan icp_native_eoi(d); 2897137436c9SGavin Shan } 2898137436c9SGavin Shan 2899fd9a1c26SIan Munsie 2900f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2901fd9a1c26SIan Munsie { 2902fd9a1c26SIan Munsie struct irq_data *idata; 2903fd9a1c26SIan Munsie struct irq_chip *ichip; 2904fd9a1c26SIan Munsie 2905fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2906fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2907fd9a1c26SIan Munsie return; 2908fd9a1c26SIan Munsie 2909fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2910fd9a1c26SIan Munsie /* 2911fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2912fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2913fd9a1c26SIan Munsie */ 2914fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2915fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2916fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2917fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2918fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2919fd9a1c26SIan Munsie } 2920fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2921fd9a1c26SIan Munsie } 2922fd9a1c26SIan Munsie 29234ee11c1aSSuresh Warrier /* 29244ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 29254ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 29264ee11c1aSSuresh Warrier */ 29274ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 29284ee11c1aSSuresh Warrier { 29294ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 29304ee11c1aSSuresh Warrier } 29314ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 29324ee11c1aSSuresh Warrier 2933184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2934137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2935137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2936184cd4a3SBenjamin Herrenschmidt { 2937184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2938184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 29393a1a4661SBenjamin Herrenschmidt __be32 data; 2940184cd4a3SBenjamin Herrenschmidt int rc; 2941184cd4a3SBenjamin Herrenschmidt 2942184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2943184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2944184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2945184cd4a3SBenjamin Herrenschmidt 2946184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2947184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2948184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2949184cd4a3SBenjamin Herrenschmidt 2950b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 295136074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2952b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2953b72c1f65SBenjamin Herrenschmidt 2954184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2955184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2956184cd4a3SBenjamin Herrenschmidt if (rc) { 2957184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2958184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2959184cd4a3SBenjamin Herrenschmidt return -EIO; 2960184cd4a3SBenjamin Herrenschmidt } 2961184cd4a3SBenjamin Herrenschmidt 2962184cd4a3SBenjamin Herrenschmidt if (is_64) { 29633a1a4661SBenjamin Herrenschmidt __be64 addr64; 29643a1a4661SBenjamin Herrenschmidt 2965184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2966184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2967184cd4a3SBenjamin Herrenschmidt if (rc) { 2968184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2969184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2970184cd4a3SBenjamin Herrenschmidt return -EIO; 2971184cd4a3SBenjamin Herrenschmidt } 29723a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 29733a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2974184cd4a3SBenjamin Herrenschmidt } else { 29753a1a4661SBenjamin Herrenschmidt __be32 addr32; 29763a1a4661SBenjamin Herrenschmidt 2977184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2978184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2979184cd4a3SBenjamin Herrenschmidt if (rc) { 2980184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2981184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2982184cd4a3SBenjamin Herrenschmidt return -EIO; 2983184cd4a3SBenjamin Herrenschmidt } 2984184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 29853a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2986184cd4a3SBenjamin Herrenschmidt } 29873a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2988184cd4a3SBenjamin Herrenschmidt 2989f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2990137436c9SGavin Shan 2991184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 29921f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2993184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2994184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2995184cd4a3SBenjamin Herrenschmidt 2996184cd4a3SBenjamin Herrenschmidt return 0; 2997184cd4a3SBenjamin Herrenschmidt } 2998184cd4a3SBenjamin Herrenschmidt 2999184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 3000184cd4a3SBenjamin Herrenschmidt { 3001fb1b55d6SGavin Shan unsigned int count; 3002184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 3003184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 3004184cd4a3SBenjamin Herrenschmidt if (!prop) { 3005184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 3006184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 3007184cd4a3SBenjamin Herrenschmidt } 3008184cd4a3SBenjamin Herrenschmidt if (!prop) 3009184cd4a3SBenjamin Herrenschmidt return; 3010184cd4a3SBenjamin Herrenschmidt 3011184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 3012fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 3013fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3014184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3015184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 3016184cd4a3SBenjamin Herrenschmidt return; 3017184cd4a3SBenjamin Herrenschmidt } 3018fb1b55d6SGavin Shan 3019184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 3020184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 3021184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3022fb1b55d6SGavin Shan count, phb->msi_base); 3023184cd4a3SBenjamin Herrenschmidt } 3024184cd4a3SBenjamin Herrenschmidt 30256e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 30266e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 30276e628c7dSWei Yang { 3028f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3029f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 3030f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 30316e628c7dSWei Yang struct resource *res; 30326e628c7dSWei Yang int i; 3033dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 30346e628c7dSWei Yang struct pci_dn *pdn; 30355b88ec22SWei Yang int mul, total_vfs; 30366e628c7dSWei Yang 303744bda4b7SHari Vyas if (!pdev->is_physfn || pci_dev_is_added(pdev)) 30386e628c7dSWei Yang return; 30396e628c7dSWei Yang 30406e628c7dSWei Yang pdn = pci_get_pdn(pdev); 30416e628c7dSWei Yang pdn->vfs_expanded = 0; 3042ee8222feSWei Yang pdn->m64_single_mode = false; 30436e628c7dSWei Yang 30445b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 304592b8f137SGavin Shan mul = phb->ioda.total_pe_num; 3046dfcc8d45SWei Yang total_vf_bar_sz = 0; 30475b88ec22SWei Yang 30485b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 30495b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 30505b88ec22SWei Yang if (!res->flags || res->parent) 30515b88ec22SWei Yang continue; 3052b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 3053b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 3054b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 30555b88ec22SWei Yang i, res); 3056b0331854SWei Yang goto truncate_iov; 30575b88ec22SWei Yang } 30585b88ec22SWei Yang 3059dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 3060dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 30615b88ec22SWei Yang 3062f2dd0afeSWei Yang /* 3063f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 3064f2dd0afeSWei Yang * power of two. 3065f2dd0afeSWei Yang * 3066f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3067f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 3068f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3069f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 3070f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 3071f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 3072f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 3073f2dd0afeSWei Yang */ 3074dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 30755b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 3076dfcc8d45SWei Yang dev_info(&pdev->dev, 3077dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3078dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 3079ee8222feSWei Yang pdn->m64_single_mode = true; 30805b88ec22SWei Yang break; 30815b88ec22SWei Yang } 30825b88ec22SWei Yang } 30835b88ec22SWei Yang 30846e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 30856e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 30866e628c7dSWei Yang if (!res->flags || res->parent) 30876e628c7dSWei Yang continue; 30886e628c7dSWei Yang 30896e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3090ee8222feSWei Yang /* 3091ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 3092ee8222feSWei Yang * mode is 32MB. 3093ee8222feSWei Yang */ 3094ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3095ee8222feSWei Yang goto truncate_iov; 3096ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 30975b88ec22SWei Yang res->end = res->start + size * mul - 1; 30986e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 30996e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 31005b88ec22SWei Yang i, res, mul); 31016e628c7dSWei Yang } 31025b88ec22SWei Yang pdn->vfs_expanded = mul; 3103b0331854SWei Yang 3104b0331854SWei Yang return; 3105b0331854SWei Yang 3106b0331854SWei Yang truncate_iov: 3107b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3108b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3109b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3110b0331854SWei Yang res->flags = 0; 3111b0331854SWei Yang res->end = res->start - 1; 3112b0331854SWei Yang } 31136e628c7dSWei Yang } 31146e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 31156e628c7dSWei Yang 311623e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 311723e79425SGavin Shan struct resource *res) 311811685becSGavin Shan { 311923e79425SGavin Shan struct pnv_phb *phb = pe->phb; 312011685becSGavin Shan struct pci_bus_region region; 312123e79425SGavin Shan int index; 312223e79425SGavin Shan int64_t rc; 312311685becSGavin Shan 312423e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 312523e79425SGavin Shan return; 312611685becSGavin Shan 312711685becSGavin Shan if (res->flags & IORESOURCE_IO) { 312811685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 312911685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 313011685becSGavin Shan index = region.start / phb->ioda.io_segsize; 313111685becSGavin Shan 313292b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 313311685becSGavin Shan region.start <= region.end) { 313411685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 313511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 313611685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 313711685becSGavin Shan if (rc != OPAL_SUCCESS) { 31381f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 313911685becSGavin Shan __func__, rc, index, pe->pe_number); 314011685becSGavin Shan break; 314111685becSGavin Shan } 314211685becSGavin Shan 314311685becSGavin Shan region.start += phb->ioda.io_segsize; 314411685becSGavin Shan index++; 314511685becSGavin Shan } 3146027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 31475958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 314811685becSGavin Shan region.start = res->start - 314923e79425SGavin Shan phb->hose->mem_offset[0] - 315011685becSGavin Shan phb->ioda.m32_pci_base; 315111685becSGavin Shan region.end = res->end - 315223e79425SGavin Shan phb->hose->mem_offset[0] - 315311685becSGavin Shan phb->ioda.m32_pci_base; 315411685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 315511685becSGavin Shan 315692b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 315711685becSGavin Shan region.start <= region.end) { 315811685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 315911685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 316011685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 316111685becSGavin Shan if (rc != OPAL_SUCCESS) { 31621f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 316311685becSGavin Shan __func__, rc, index, pe->pe_number); 316411685becSGavin Shan break; 316511685becSGavin Shan } 316611685becSGavin Shan 316711685becSGavin Shan region.start += phb->ioda.m32_segsize; 316811685becSGavin Shan index++; 316911685becSGavin Shan } 317011685becSGavin Shan } 317111685becSGavin Shan } 317223e79425SGavin Shan 317323e79425SGavin Shan /* 317423e79425SGavin Shan * This function is supposed to be called on basis of PE from top 317523e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 317603671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 317723e79425SGavin Shan */ 317823e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 317923e79425SGavin Shan { 318069d733e7SGavin Shan struct pci_dev *pdev; 318123e79425SGavin Shan int i; 318223e79425SGavin Shan 318323e79425SGavin Shan /* 318423e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 318523e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 318623e79425SGavin Shan * be figured out later. 318723e79425SGavin Shan */ 318823e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 318923e79425SGavin Shan 319069d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 319169d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 319269d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 319369d733e7SGavin Shan 319469d733e7SGavin Shan /* 319569d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 319669d733e7SGavin Shan * windows of the child bridges should be mapped to 319769d733e7SGavin Shan * the PE as well. 319869d733e7SGavin Shan */ 319969d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 320069d733e7SGavin Shan continue; 320169d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 320269d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 320369d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 320469d733e7SGavin Shan } 320511685becSGavin Shan } 320611685becSGavin Shan 320798b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 320898b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 320998b665daSRussell Currey { 321098b665daSRussell Currey struct pci_controller *hose; 321198b665daSRussell Currey struct pnv_phb *phb; 321298b665daSRussell Currey s64 ret; 321398b665daSRussell Currey 321498b665daSRussell Currey if (val != 1ULL) 321598b665daSRussell Currey return -EINVAL; 321698b665daSRussell Currey 321798b665daSRussell Currey hose = (struct pci_controller *)data; 321898b665daSRussell Currey if (!hose || !hose->private_data) 321998b665daSRussell Currey return -ENODEV; 322098b665daSRussell Currey 322198b665daSRussell Currey phb = hose->private_data; 322298b665daSRussell Currey 322398b665daSRussell Currey /* Retrieve the diag data from firmware */ 32245cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 32255cb1f8fdSRussell Currey phb->diag_data_size); 322698b665daSRussell Currey if (ret != OPAL_SUCCESS) 322798b665daSRussell Currey return -EIO; 322898b665daSRussell Currey 322998b665daSRussell Currey /* Print the diag data to the kernel log */ 32305cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 323198b665daSRussell Currey return 0; 323298b665daSRussell Currey } 323398b665daSRussell Currey 323498b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 323598b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 323698b665daSRussell Currey 323798b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 323898b665daSRussell Currey 323937c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 324037c367f2SGavin Shan { 324137c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 324237c367f2SGavin Shan struct pci_controller *hose, *tmp; 324337c367f2SGavin Shan struct pnv_phb *phb; 324437c367f2SGavin Shan char name[16]; 324537c367f2SGavin Shan 324637c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 324737c367f2SGavin Shan phb = hose->private_data; 324837c367f2SGavin Shan 3249ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3250ccd1c191SGavin Shan phb->initialized = 1; 3251ccd1c191SGavin Shan 325237c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 325337c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 325498b665daSRussell Currey if (!phb->dbgfs) { 3255f2c2cbccSJoe Perches pr_warn("%s: Error on creating debugfs on PHB#%x\n", 325637c367f2SGavin Shan __func__, hose->global_number); 325798b665daSRussell Currey continue; 325898b665daSRussell Currey } 325998b665daSRussell Currey 326098b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 326198b665daSRussell Currey &pnv_pci_diag_data_fops); 326237c367f2SGavin Shan } 326337c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 326437c367f2SGavin Shan } 326537c367f2SGavin Shan 3266db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 3267db217319SBenjamin Herrenschmidt { 3268db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 3269db217319SBenjamin Herrenschmidt struct pci_bus *child; 3270db217319SBenjamin Herrenschmidt 3271db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 3272db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 3273db217319SBenjamin Herrenschmidt return; 3274db217319SBenjamin Herrenschmidt 3275db217319SBenjamin Herrenschmidt /* 3276db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 3277db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 3278db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 3279db217319SBenjamin Herrenschmidt * fixed. 3280db217319SBenjamin Herrenschmidt */ 3281db217319SBenjamin Herrenschmidt if (dev) { 3282db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 3283db217319SBenjamin Herrenschmidt if (rc) 3284db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 3285db217319SBenjamin Herrenschmidt pci_set_master(dev); 3286db217319SBenjamin Herrenschmidt } 3287db217319SBenjamin Herrenschmidt 3288db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 3289db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 3290db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 3291db217319SBenjamin Herrenschmidt } 3292db217319SBenjamin Herrenschmidt 3293db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 3294db217319SBenjamin Herrenschmidt { 3295db217319SBenjamin Herrenschmidt struct pci_controller *hose; 3296db217319SBenjamin Herrenschmidt 3297db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 3298db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 3299db217319SBenjamin Herrenschmidt } 3300db217319SBenjamin Herrenschmidt 3301cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3302fb446ad0SGavin Shan { 3303fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3304ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 330537c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 330637c367f2SGavin Shan 3307db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 3308db217319SBenjamin Herrenschmidt 3309e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3310b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3311e9cc17d4SGavin Shan #endif 3312fb446ad0SGavin Shan } 3313fb446ad0SGavin Shan 3314271fd03aSGavin Shan /* 3315271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3316271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3317271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3318271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3319271fd03aSGavin Shan * 1MiB for memory) will be returned. 3320271fd03aSGavin Shan * 3321271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3322271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3323271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3324271fd03aSGavin Shan * resources. 3325271fd03aSGavin Shan */ 3326271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3327271fd03aSGavin Shan unsigned long type) 3328271fd03aSGavin Shan { 3329271fd03aSGavin Shan struct pci_dev *bridge; 3330271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3331271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3332271fd03aSGavin Shan int num_pci_bridges = 0; 3333271fd03aSGavin Shan 3334271fd03aSGavin Shan bridge = bus->self; 3335271fd03aSGavin Shan while (bridge) { 3336271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3337271fd03aSGavin Shan num_pci_bridges++; 3338271fd03aSGavin Shan if (num_pci_bridges >= 2) 3339271fd03aSGavin Shan return 1; 3340271fd03aSGavin Shan } 3341271fd03aSGavin Shan 3342271fd03aSGavin Shan bridge = bridge->bus->self; 3343271fd03aSGavin Shan } 3344271fd03aSGavin Shan 33455958d19aSBenjamin Herrenschmidt /* 33465958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 33475958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 33485958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 33495958d19aSBenjamin Herrenschmidt */ 3350b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3351262af557SGuo Chao return phb->ioda.m64_segsize; 3352271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3353271fd03aSGavin Shan return phb->ioda.m32_segsize; 3354271fd03aSGavin Shan 3355271fd03aSGavin Shan return phb->ioda.io_segsize; 3356271fd03aSGavin Shan } 3357271fd03aSGavin Shan 335840e2a47eSGavin Shan /* 335940e2a47eSGavin Shan * We are updating root port or the upstream port of the 336040e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 336140e2a47eSGavin Shan * to accommodate the changes on required resources during 336240e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 336340e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 336440e2a47eSGavin Shan * root port. 336540e2a47eSGavin Shan */ 336640e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 336740e2a47eSGavin Shan unsigned long type) 336840e2a47eSGavin Shan { 336940e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 337040e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 337140e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 337240e2a47eSGavin Shan struct resource *r, *w; 337340e2a47eSGavin Shan bool msi_region = false; 337440e2a47eSGavin Shan int i; 337540e2a47eSGavin Shan 337640e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 337740e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 337840e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 337940e2a47eSGavin Shan return; 338040e2a47eSGavin Shan 338140e2a47eSGavin Shan /* Fixup the resources */ 338240e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 338340e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 338440e2a47eSGavin Shan if (!r->flags || !r->parent) 338540e2a47eSGavin Shan continue; 338640e2a47eSGavin Shan 338740e2a47eSGavin Shan w = NULL; 338840e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 338940e2a47eSGavin Shan w = &hose->io_resource; 33905958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 339140e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 339240e2a47eSGavin Shan phb->ioda.m64_segsize) 339340e2a47eSGavin Shan w = &hose->mem_resources[1]; 339440e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 339540e2a47eSGavin Shan w = &hose->mem_resources[0]; 339640e2a47eSGavin Shan msi_region = true; 339740e2a47eSGavin Shan } 339840e2a47eSGavin Shan 339940e2a47eSGavin Shan r->start = w->start; 340040e2a47eSGavin Shan r->end = w->end; 340140e2a47eSGavin Shan 340240e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 340340e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 340440e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 340540e2a47eSGavin Shan * 340640e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 340740e2a47eSGavin Shan * 32-bits bridge window. 340840e2a47eSGavin Shan */ 340940e2a47eSGavin Shan if (msi_region) { 341040e2a47eSGavin Shan r->end += 0x10000; 341140e2a47eSGavin Shan r->end -= 0x100000; 341240e2a47eSGavin Shan } 341340e2a47eSGavin Shan } 341440e2a47eSGavin Shan } 341540e2a47eSGavin Shan 3416ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3417ccd1c191SGavin Shan { 3418ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3419ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3420ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3421ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3422ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3423ccd1c191SGavin Shan 342440e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 342540e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 342640e2a47eSGavin Shan 342763803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 342863803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 342963803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 343063803c39SGavin Shan if (pe) { 343163803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 343263803c39SGavin Shan phb->ioda.root_pe_populated = true; 343363803c39SGavin Shan } 343463803c39SGavin Shan } 343563803c39SGavin Shan 3436ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3437ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3438ccd1c191SGavin Shan return; 3439ccd1c191SGavin Shan 3440ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3441a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 3442ccd1c191SGavin Shan 3443ccd1c191SGavin Shan /* 3444ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3445ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3446ccd1c191SGavin Shan * not allocate resources again. 3447ccd1c191SGavin Shan */ 3448ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3449ccd1c191SGavin Shan if (!pe) 3450ccd1c191SGavin Shan return; 3451ccd1c191SGavin Shan 3452ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3453ccd1c191SGavin Shan switch (phb->type) { 3454ccd1c191SGavin Shan case PNV_PHB_IODA1: 3455ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3456ccd1c191SGavin Shan break; 3457ccd1c191SGavin Shan case PNV_PHB_IODA2: 3458ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3459ccd1c191SGavin Shan break; 3460ccd1c191SGavin Shan default: 34611f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3462ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3463ccd1c191SGavin Shan } 3464ccd1c191SGavin Shan } 3465ccd1c191SGavin Shan 346638274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 346738274637SYongji Xie { 346838274637SYongji Xie return PAGE_SIZE; 346938274637SYongji Xie } 347038274637SYongji Xie 34715350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 34725350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 34735350ab3fSWei Yang int resno) 34745350ab3fSWei Yang { 3475ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3476ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 34775350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 34787fbe7a93SWei Yang resource_size_t align; 34795350ab3fSWei Yang 34807fbe7a93SWei Yang /* 34817fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 34827fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 34837fbe7a93SWei Yang * BAR should be size aligned. 34847fbe7a93SWei Yang * 3485ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3486ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3487ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3488ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3489ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3490ee8222feSWei Yang * m64_segsize. 3491ee8222feSWei Yang * 34927fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 34937fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3494ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3495ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 34967fbe7a93SWei Yang */ 34975350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 34987fbe7a93SWei Yang if (!pdn->vfs_expanded) 34995350ab3fSWei Yang return align; 3500ee8222feSWei Yang if (pdn->m64_single_mode) 3501ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 35027fbe7a93SWei Yang 35037fbe7a93SWei Yang return pdn->vfs_expanded * align; 35045350ab3fSWei Yang } 35055350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 35065350ab3fSWei Yang 3507184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3508184cd4a3SBenjamin Herrenschmidt * assign a PE 3509184cd4a3SBenjamin Herrenschmidt */ 35108bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3511184cd4a3SBenjamin Herrenschmidt { 3512db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3513db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3514db1266c8SGavin Shan struct pci_dn *pdn; 3515184cd4a3SBenjamin Herrenschmidt 3516db1266c8SGavin Shan /* The function is probably called while the PEs have 3517db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3518db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3519db1266c8SGavin Shan * PEs isn't ready. 3520db1266c8SGavin Shan */ 3521db1266c8SGavin Shan if (!phb->initialized) 3522c88c2a18SDaniel Axtens return true; 3523db1266c8SGavin Shan 3524b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3525184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3526c88c2a18SDaniel Axtens return false; 3527db1266c8SGavin Shan 3528c88c2a18SDaniel Axtens return true; 3529184cd4a3SBenjamin Herrenschmidt } 3530184cd4a3SBenjamin Herrenschmidt 3531c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3532c5f7700bSGavin Shan int num) 3533c5f7700bSGavin Shan { 3534c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3535c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3536c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3537c5f7700bSGavin Shan unsigned int idx; 3538c5f7700bSGavin Shan long rc; 3539c5f7700bSGavin Shan 3540c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3541c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3542c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3543c5f7700bSGavin Shan continue; 3544c5f7700bSGavin Shan 3545c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3546c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3547c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3548c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3549c5f7700bSGavin Shan rc, idx); 3550c5f7700bSGavin Shan return rc; 3551c5f7700bSGavin Shan } 3552c5f7700bSGavin Shan 3553c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3554c5f7700bSGavin Shan } 3555c5f7700bSGavin Shan 3556c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3557c5f7700bSGavin Shan return OPAL_SUCCESS; 3558c5f7700bSGavin Shan } 3559c5f7700bSGavin Shan 3560c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3561c5f7700bSGavin Shan { 3562c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3563c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3564c5f7700bSGavin Shan int64_t rc; 3565c5f7700bSGavin Shan 3566c5f7700bSGavin Shan if (!weight) 3567c5f7700bSGavin Shan return; 3568c5f7700bSGavin Shan 3569c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3570c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3571c5f7700bSGavin Shan return; 3572c5f7700bSGavin Shan 3573a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3574c5f7700bSGavin Shan if (pe->table_group.group) { 3575c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3576c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3577c5f7700bSGavin Shan } 3578c5f7700bSGavin Shan 3579c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3580e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3581c5f7700bSGavin Shan } 3582c5f7700bSGavin Shan 3583c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3584c5f7700bSGavin Shan { 3585c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3586c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3587c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3588c5f7700bSGavin Shan int64_t rc; 3589c5f7700bSGavin Shan #endif 3590c5f7700bSGavin Shan 3591c5f7700bSGavin Shan if (!weight) 3592c5f7700bSGavin Shan return; 3593c5f7700bSGavin Shan 3594c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3595c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3596c5f7700bSGavin Shan if (rc) 3597c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3598c5f7700bSGavin Shan #endif 3599c5f7700bSGavin Shan 3600c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3601c5f7700bSGavin Shan if (pe->table_group.group) { 3602c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3603c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3604c5f7700bSGavin Shan } 3605c5f7700bSGavin Shan 3606e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3607c5f7700bSGavin Shan } 3608c5f7700bSGavin Shan 3609c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3610c5f7700bSGavin Shan unsigned short win, 3611c5f7700bSGavin Shan unsigned int *map) 3612c5f7700bSGavin Shan { 3613c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3614c5f7700bSGavin Shan int idx; 3615c5f7700bSGavin Shan int64_t rc; 3616c5f7700bSGavin Shan 3617c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3618c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3619c5f7700bSGavin Shan continue; 3620c5f7700bSGavin Shan 3621c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3622c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3623c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3624c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3625c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3626c5f7700bSGavin Shan else 3627c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3628c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3629c5f7700bSGavin Shan 3630c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3631c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3632c5f7700bSGavin Shan rc, win, idx); 3633c5f7700bSGavin Shan 3634c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3635c5f7700bSGavin Shan } 3636c5f7700bSGavin Shan } 3637c5f7700bSGavin Shan 3638c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3639c5f7700bSGavin Shan { 3640c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3641c5f7700bSGavin Shan 3642c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3643c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3644c5f7700bSGavin Shan phb->ioda.io_segmap); 3645c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3646c5f7700bSGavin Shan phb->ioda.m32_segmap); 3647c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3648c5f7700bSGavin Shan phb->ioda.m64_segmap); 3649c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3650c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3651c5f7700bSGavin Shan phb->ioda.m32_segmap); 3652c5f7700bSGavin Shan } 3653c5f7700bSGavin Shan } 3654c5f7700bSGavin Shan 3655c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3656c5f7700bSGavin Shan { 3657c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3658c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3659c5f7700bSGavin Shan 3660c5f7700bSGavin Shan list_del(&pe->list); 3661c5f7700bSGavin Shan switch (phb->type) { 3662c5f7700bSGavin Shan case PNV_PHB_IODA1: 3663c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3664c5f7700bSGavin Shan break; 3665c5f7700bSGavin Shan case PNV_PHB_IODA2: 3666c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3667c5f7700bSGavin Shan break; 3668c5f7700bSGavin Shan default: 3669c5f7700bSGavin Shan WARN_ON(1); 3670c5f7700bSGavin Shan } 3671c5f7700bSGavin Shan 3672c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3673c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3674b314427aSGavin Shan 3675b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3676b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3677b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3678b314427aSGavin Shan list_del(&slave->list); 3679b314427aSGavin Shan pnv_ioda_free_pe(slave); 3680b314427aSGavin Shan } 3681b314427aSGavin Shan } 3682b314427aSGavin Shan 36836eaed166SGavin Shan /* 36846eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 36856eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 36866eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 36876eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 36886eaed166SGavin Shan */ 36896eaed166SGavin Shan if (phb->ioda.root_pe_populated && 36906eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 36916eaed166SGavin Shan phb->ioda.root_pe_populated = false; 36926eaed166SGavin Shan else 3693c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3694c5f7700bSGavin Shan } 3695c5f7700bSGavin Shan 3696c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3697c5f7700bSGavin Shan { 3698c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3699c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3700c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3701c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3702c5f7700bSGavin Shan 3703c5f7700bSGavin Shan if (pdev->is_virtfn) 3704c5f7700bSGavin Shan return; 3705c5f7700bSGavin Shan 3706c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3707c5f7700bSGavin Shan return; 3708c5f7700bSGavin Shan 370929bf282dSGavin Shan /* 371029bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 371129bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 371229bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 371329bf282dSGavin Shan * device count is decreased on removing devices while failing to 371429bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 371529bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 371629bf282dSGavin Shan */ 3717c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 371829bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 371929bf282dSGavin Shan 3720c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3721c5f7700bSGavin Shan if (pe->device_count == 0) 3722c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3723c5f7700bSGavin Shan } 3724c5f7700bSGavin Shan 3725ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 3726ab7032e7SAlexey Kardashevskiy { 3727ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 3728ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 3729ab7032e7SAlexey Kardashevskiy 3730ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 3731ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 3732ab7032e7SAlexey Kardashevskiy } 3733ab7032e7SAlexey Kardashevskiy 37347a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 373573ed148aSBenjamin Herrenschmidt { 37367a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 37377a8e6bbfSMichael Neuling 3738d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 373973ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 374073ed148aSBenjamin Herrenschmidt } 374173ed148aSBenjamin Herrenschmidt 374292ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 374392ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 37441bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 374592ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 374692ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 374792ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3748c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 374992ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3750ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 375192ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3752763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 375353522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 37547a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 375592ae0353SDaniel Axtens }; 375692ae0353SDaniel Axtens 3757f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3758f9f83456SAlexey Kardashevskiy { 3759f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3760f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3761f9f83456SAlexey Kardashevskiy __func__); 3762f9f83456SAlexey Kardashevskiy return -EPERM; 3763f9f83456SAlexey Kardashevskiy } 3764f9f83456SAlexey Kardashevskiy 37655d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 37665d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 37675d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 37685d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 37695d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 37705d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 37715d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37725d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 37735d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 3774ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 37755d2aa710SAlistair Popple }; 37765d2aa710SAlistair Popple 37777f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 37787f2c39e9SFrederic Barrat .enable_device_hook = pnv_pci_enable_device_hook, 37797f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 37807f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37817f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 37827f2c39e9SFrederic Barrat }; 37837f2c39e9SFrederic Barrat 3784e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3785e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3786184cd4a3SBenjamin Herrenschmidt { 3787184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3788184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 37892b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 37902b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3791fd141d1aSBenjamin Herrenschmidt struct resource r; 3792c681b93cSAlistair Popple const __be64 *prop64; 37933a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3794f1b7cc3eSGavin Shan int len; 37953fa23ff8SGavin Shan unsigned int segno; 3796184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3797184cd4a3SBenjamin Herrenschmidt void *aux; 3798184cd4a3SBenjamin Herrenschmidt long rc; 3799184cd4a3SBenjamin Herrenschmidt 380008a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 380108a45b32SBenjamin Herrenschmidt return; 380208a45b32SBenjamin Herrenschmidt 3803b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3804184cd4a3SBenjamin Herrenschmidt 3805184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3806184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3807184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3808184cd4a3SBenjamin Herrenschmidt return; 3809184cd4a3SBenjamin Herrenschmidt } 3810184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3811184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3812184cd4a3SBenjamin Herrenschmidt 38137e1c4e27SMike Rapoport phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 381458d714ecSGavin Shan 381558d714ecSGavin Shan /* Allocate PCI controller */ 3816184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 381758d714ecSGavin Shan if (!phb->hose) { 3818b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3819b7c670d6SRob Herring np); 3820e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3821184cd4a3SBenjamin Herrenschmidt return; 3822184cd4a3SBenjamin Herrenschmidt } 3823184cd4a3SBenjamin Herrenschmidt 3824184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3825f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3826f1b7cc3eSGavin Shan if (prop32 && len == 8) { 38273a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 38283a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3829f1b7cc3eSGavin Shan } else { 3830b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3831184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3832184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3833f1b7cc3eSGavin Shan } 3834184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3835e9cc17d4SGavin Shan phb->hub_id = hub_id; 3836184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3837aa0c033fSGavin Shan phb->type = ioda_type; 3838781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3839184cd4a3SBenjamin Herrenschmidt 3840cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3841cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3842cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3843f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3844aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 38455d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 38465d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3847616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3848616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3849cee72d5bSBenjamin Herrenschmidt else 3850cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3851cee72d5bSBenjamin Herrenschmidt 38525cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 38535cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 38545cb1f8fdSRussell Currey if (prop32) 38555cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 38565cb1f8fdSRussell Currey else 38575cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 38585cb1f8fdSRussell Currey 38597e1c4e27SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 38605cb1f8fdSRussell Currey 3861aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 38622f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3863184cd4a3SBenjamin Herrenschmidt 3864aa0c033fSGavin Shan /* Get registers */ 3865fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3866fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3867fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3868184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3869184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3870fd141d1aSBenjamin Herrenschmidt } 3871577c8c88SGavin Shan 3872184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 387392b8f137SGavin Shan phb->ioda.total_pe_num = 1; 387436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 387536954dc7SGavin Shan if (prop32) 387692b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 387736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 387836954dc7SGavin Shan if (prop32) 387992b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3880262af557SGuo Chao 3881c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3882c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3883c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3884c127562aSGavin Shan 3885262af557SGuo Chao /* Parse 64-bit MMIO range */ 3886262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3887262af557SGuo Chao 3888184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3889aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3890184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3891184cd4a3SBenjamin Herrenschmidt 389292b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 38933fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3894184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 389592b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3896184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3897184cd4a3SBenjamin Herrenschmidt 38982b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 38992b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 39002b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 39012b923ed1SGavin Shan 3902c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 390392a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 390492a86756SAlexey Kardashevskiy sizeof(unsigned long)); 390593289d8cSGavin Shan m64map_off = size; 390693289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3907184cd4a3SBenjamin Herrenschmidt m32map_off = size; 390892b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3909c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3910c35d2a8cSGavin Shan iomap_off = size; 391192b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 39122b923ed1SGavin Shan dma32map_off = size; 39132b923ed1SGavin Shan size += phb->ioda.dma32_count * 39142b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3915c35d2a8cSGavin Shan } 3916184cd4a3SBenjamin Herrenschmidt pemap_off = size; 391792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 39187e1c4e27SMike Rapoport aux = memblock_alloc(size, SMP_CACHE_BYTES); 3919184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 392093289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3921184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 392293289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 392393289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 39243fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 392593289d8cSGavin Shan } 39263fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3927184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 39283fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 39293fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 39302b923ed1SGavin Shan 39312b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 39322b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 39332b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 39343fa23ff8SGavin Shan } 3935184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 393663803c39SGavin Shan 393763803c39SGavin Shan /* 393863803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 393963803c39SGavin Shan * M64 resources consumed by its child devices. To pick 394063803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 394163803c39SGavin Shan */ 394263803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 394363803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 394463803c39SGavin Shan phb->ioda.root_pe_idx = 1; 394563803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 394663803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 394763803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 394863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 394963803c39SGavin Shan } else { 395063803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 395163803c39SGavin Shan } 3952184cd4a3SBenjamin Herrenschmidt 3953184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3954781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3955184cd4a3SBenjamin Herrenschmidt 3956184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 39572b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3958acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3959184cd4a3SBenjamin Herrenschmidt 3960aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3961184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3962184cd4a3SBenjamin Herrenschmidt window_type, 3963184cd4a3SBenjamin Herrenschmidt window_num, 3964184cd4a3SBenjamin Herrenschmidt starting_real_address, 3965184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3966184cd4a3SBenjamin Herrenschmidt segment_size); 3967184cd4a3SBenjamin Herrenschmidt #endif 3968184cd4a3SBenjamin Herrenschmidt 3969262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 397092b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3971262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3972262af557SGuo Chao if (phb->ioda.m64_size) 3973262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3974262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3975262af557SGuo Chao if (phb->ioda.io_size) 3976262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3977184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3978184cd4a3SBenjamin Herrenschmidt 3979262af557SGuo Chao 3980184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 398149dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 398249dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 398349dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3984184cd4a3SBenjamin Herrenschmidt 3985184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3986184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3987184cd4a3SBenjamin Herrenschmidt 3988c40a4210SGavin Shan /* 3989c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3990c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3991c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3992c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3993c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3994184cd4a3SBenjamin Herrenschmidt */ 3995fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 39965d2aa710SAlistair Popple 39977f2c39e9SFrederic Barrat switch (phb->type) { 39987f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 39995d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 40007f2c39e9SFrederic Barrat break; 40017f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 40027f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 40037f2c39e9SFrederic Barrat break; 40047f2c39e9SFrederic Barrat default: 4005f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 400692ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 4007f9f83456SAlexey Kardashevskiy } 4008ad30cb99SMichael Ellerman 400938274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 401038274637SYongji Xie 40116e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 40126e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 40135350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 4014988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 4015988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 4016ad30cb99SMichael Ellerman #endif 4017ad30cb99SMichael Ellerman 4018c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 4019184cd4a3SBenjamin Herrenschmidt 4020184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 4021d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 4022184cd4a3SBenjamin Herrenschmidt if (rc) 4023f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 4024361f2a2aSGavin Shan 40256060e9eaSAndrew Donnellan /* 40266060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 4027361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 4028361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 402945baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 403045baee14SGuilherme G. Piccoli * kernel parameter will force this reset too. 4031361f2a2aSGavin Shan */ 403245baee14SGuilherme G. Piccoli if (is_kdump_kernel() || pci_reset_phbs) { 4033361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 4034cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 4035cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 4036361f2a2aSGavin Shan } 4037262af557SGuo Chao 40389e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 40399e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 4040262af557SGuo Chao hose->mem_resources[1].flags = 0; 4041184cd4a3SBenjamin Herrenschmidt } 4042184cd4a3SBenjamin Herrenschmidt 404367975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4044aa0c033fSGavin Shan { 4045e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4046aa0c033fSGavin Shan } 4047aa0c033fSGavin Shan 40485d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 40495d2aa710SAlistair Popple { 40507f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 40515d2aa710SAlistair Popple } 40525d2aa710SAlistair Popple 40537f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 40547f2c39e9SFrederic Barrat { 40557f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 4056184cd4a3SBenjamin Herrenschmidt } 4057184cd4a3SBenjamin Herrenschmidt 4058228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 4059228c2f41SAndrew Donnellan { 4060228c2f41SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(dev->bus); 4061228c2f41SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 4062228c2f41SAndrew Donnellan 4063228c2f41SAndrew Donnellan if (!machine_is(powernv)) 4064228c2f41SAndrew Donnellan return; 4065228c2f41SAndrew Donnellan 4066228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 4067228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4068228c2f41SAndrew Donnellan } 4069228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 4070228c2f41SAndrew Donnellan 4071184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 4072184cd4a3SBenjamin Herrenschmidt { 4073184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 4074184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 4075184cd4a3SBenjamin Herrenschmidt u64 hub_id; 4076184cd4a3SBenjamin Herrenschmidt 4077b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 4078184cd4a3SBenjamin Herrenschmidt 4079184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4080184cd4a3SBenjamin Herrenschmidt if (!prop64) { 4081184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4082184cd4a3SBenjamin Herrenschmidt return; 4083184cd4a3SBenjamin Herrenschmidt } 4084184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 4085184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4086184cd4a3SBenjamin Herrenschmidt 4087184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 4088184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 4089184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 4090184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4091184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4092184cd4a3SBenjamin Herrenschmidt } 4093184cd4a3SBenjamin Herrenschmidt } 4094