12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23dbf77fedSAneesh Kumar K.V #include <linux/debugfs.h> 24e6f6390aSChristophe Leroy #include <linux/of_address.h> 25e6f6390aSChristophe Leroy #include <linux/of_irq.h> 26184cd4a3SBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 31fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 36137436c9SGavin Shan #include <asm/xics.h> 37262af557SGuo Chao #include <asm/firmware.h> 3880c49c7eSIan Munsie #include <asm/pnv-pci.h> 39aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 400fcfe224SCédric Le Goater #include <asm/xive.h> 4180c49c7eSIan Munsie 42ec249dd8SMichael Neuling #include <misc/cxl-base.h> 43184cd4a3SBenjamin Herrenschmidt 44184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 45184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4644bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 47184cd4a3SBenjamin Herrenschmidt 48562d1e20SChristoph Hellwig static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_OCAPI" }; 49aca6913fSAlexey Kardashevskiy 50c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 51dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus); 52c498a4f9SChristoph Hellwig 537d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 546d31c2faSJoe Perches const char *fmt, ...) 556d31c2faSJoe Perches { 566d31c2faSJoe Perches struct va_format vaf; 576d31c2faSJoe Perches va_list args; 586d31c2faSJoe Perches char pfix[32]; 59184cd4a3SBenjamin Herrenschmidt 606d31c2faSJoe Perches va_start(args, fmt); 616d31c2faSJoe Perches 626d31c2faSJoe Perches vaf.fmt = fmt; 636d31c2faSJoe Perches vaf.va = &args; 646d31c2faSJoe Perches 65781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 6614be3756SWolfram Sang strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 67781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 686d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 696d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 70781a868fSWei Yang #ifdef CONFIG_PCI_IOV 71781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 72781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 73781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 74781a868fSWei Yang (pe->rid & 0xff00) >> 8, 75781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 76781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 776d31c2faSJoe Perches 781f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 796d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 806d31c2faSJoe Perches 816d31c2faSJoe Perches va_end(args); 826d31c2faSJoe Perches } 836d31c2faSJoe Perches 844e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8545baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 864e287840SThadeu Lima de Souza Cascardo 874e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 884e287840SThadeu Lima de Souza Cascardo { 894e287840SThadeu Lima de Souza Cascardo if (!str) 904e287840SThadeu Lima de Souza Cascardo return -EINVAL; 914e287840SThadeu Lima de Souza Cascardo 924e287840SThadeu Lima de Souza Cascardo while (*str) { 934e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 944e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 954e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 964e287840SThadeu Lima de Souza Cascardo break; 974e287840SThadeu Lima de Souza Cascardo } 984e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 994e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1004e287840SThadeu Lima de Souza Cascardo str++; 1014e287840SThadeu Lima de Souza Cascardo } 1024e287840SThadeu Lima de Souza Cascardo 1034e287840SThadeu Lima de Souza Cascardo return 0; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1064e287840SThadeu Lima de Souza Cascardo 10745baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 10845baee14SGuilherme G. Piccoli { 10945baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11045baee14SGuilherme G. Piccoli return 0; 11145baee14SGuilherme G. Piccoli } 11245baee14SGuilherme G. Piccoli 11345baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11445baee14SGuilherme G. Piccoli 1151e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1161e916772SGavin Shan { 117313483ddSGavin Shan s64 rc; 118313483ddSGavin Shan 1191e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1201e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 12101e12629SOliver O'Halloran phb->ioda.pe_array[pe_no].dma_setup_done = false; 1221e916772SGavin Shan 123313483ddSGavin Shan /* 124313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 125313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 126313483ddSGavin Shan * PE is already in unfrozen state. 127313483ddSGavin Shan */ 128313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 129313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 130d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1311f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 132313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 133313483ddSGavin Shan 1341e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1351e916772SGavin Shan } 1361e916772SGavin Shan 1374b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1384b82ab18SGavin Shan { 13992b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1401f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1414b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1424b82ab18SGavin Shan return; 1434b82ab18SGavin Shan } 1444b82ab18SGavin Shan 145a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 146e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1471f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1484b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 149a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 1504b82ab18SGavin Shan 1511e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1524b82ab18SGavin Shan } 1534b82ab18SGavin Shan 154a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count) 155184cd4a3SBenjamin Herrenschmidt { 156a4bc676eSOliver O'Halloran struct pnv_ioda_pe *ret = NULL; 157a4bc676eSOliver O'Halloran int run = 0, pe, i; 158184cd4a3SBenjamin Herrenschmidt 159a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 160a4bc676eSOliver O'Halloran 161a4bc676eSOliver O'Halloran /* scan backwards for a run of @count cleared bits */ 1629fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 163a4bc676eSOliver O'Halloran if (test_bit(pe, phb->ioda.pe_alloc)) { 164a4bc676eSOliver O'Halloran run = 0; 165a4bc676eSOliver O'Halloran continue; 166184cd4a3SBenjamin Herrenschmidt } 167184cd4a3SBenjamin Herrenschmidt 168a4bc676eSOliver O'Halloran run++; 169a4bc676eSOliver O'Halloran if (run == count) 170a4bc676eSOliver O'Halloran break; 171a4bc676eSOliver O'Halloran } 172a4bc676eSOliver O'Halloran if (run != count) 173a4bc676eSOliver O'Halloran goto out; 174a4bc676eSOliver O'Halloran 175a4bc676eSOliver O'Halloran for (i = pe; i < pe + count; i++) { 176a4bc676eSOliver O'Halloran set_bit(i, phb->ioda.pe_alloc); 177a4bc676eSOliver O'Halloran pnv_ioda_init_pe(phb, i); 178a4bc676eSOliver O'Halloran } 179a4bc676eSOliver O'Halloran ret = &phb->ioda.pe_array[pe]; 180a4bc676eSOliver O'Halloran 181a4bc676eSOliver O'Halloran out: 182a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 183a4bc676eSOliver O'Halloran return ret; 1849fcd6f4aSGavin Shan } 1859fcd6f4aSGavin Shan 18637b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 187184cd4a3SBenjamin Herrenschmidt { 1881e916772SGavin Shan struct pnv_phb *phb = pe->phb; 189caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 190184cd4a3SBenjamin Herrenschmidt 1911e916772SGavin Shan WARN_ON(pe->pdev); 1921e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 193a4bc676eSOliver O'Halloran 194a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 195caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 196a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 197184cd4a3SBenjamin Herrenschmidt } 198184cd4a3SBenjamin Herrenschmidt 199262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 200262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 201262af557SGuo Chao { 202262af557SGuo Chao const char *desc; 203262af557SGuo Chao struct resource *r; 204262af557SGuo Chao s64 rc; 205262af557SGuo Chao 206262af557SGuo Chao /* Configure the default M64 BAR */ 207262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 208262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 209262af557SGuo Chao phb->ioda.m64_bar_idx, 210262af557SGuo Chao phb->ioda.m64_base, 211262af557SGuo Chao 0, /* unused */ 212262af557SGuo Chao phb->ioda.m64_size); 213262af557SGuo Chao if (rc != OPAL_SUCCESS) { 214262af557SGuo Chao desc = "configuring"; 215262af557SGuo Chao goto fail; 216262af557SGuo Chao } 217262af557SGuo Chao 218262af557SGuo Chao /* Enable the default M64 BAR */ 219262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 220262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 221262af557SGuo Chao phb->ioda.m64_bar_idx, 222262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 223262af557SGuo Chao if (rc != OPAL_SUCCESS) { 224262af557SGuo Chao desc = "enabling"; 225262af557SGuo Chao goto fail; 226262af557SGuo Chao } 227262af557SGuo Chao 228262af557SGuo Chao /* 22963803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23063803c39SGavin Shan * are first or last two PEs. 231262af557SGuo Chao */ 232262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23392b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23463803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23592b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23663803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 237262af557SGuo Chao else 2381f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23992b8f137SGavin Shan phb->ioda.reserved_pe_idx); 240262af557SGuo Chao 241262af557SGuo Chao return 0; 242262af557SGuo Chao 243262af557SGuo Chao fail: 244262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 245262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 246262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 247262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 248262af557SGuo Chao phb->ioda.m64_bar_idx, 249262af557SGuo Chao OPAL_DISABLE_M64); 250262af557SGuo Chao return -EIO; 251262af557SGuo Chao } 252262af557SGuo Chao 253c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25496a2f92bSGavin Shan unsigned long *pe_bitmap) 255262af557SGuo Chao { 2565609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 257262af557SGuo Chao struct resource *r; 25896a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25996a2f92bSGavin Shan int segno, i; 260262af557SGuo Chao 26196a2f92bSGavin Shan base = phb->ioda.m64_base; 26296a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26396a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26496a2f92bSGavin Shan r = &pdev->resource[i]; 2655958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 266262af557SGuo Chao continue; 267262af557SGuo Chao 268e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 269b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 27096a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27196a2f92bSGavin Shan if (pe_bitmap) 27296a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27396a2f92bSGavin Shan else 27496a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 275262af557SGuo Chao } 276262af557SGuo Chao } 277262af557SGuo Chao } 278262af557SGuo Chao 279c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 28096a2f92bSGavin Shan unsigned long *pe_bitmap, 28196a2f92bSGavin Shan bool all) 282262af557SGuo Chao { 283262af557SGuo Chao struct pci_dev *pdev; 28496a2f92bSGavin Shan 28596a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 286c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 28796a2f92bSGavin Shan 28896a2f92bSGavin Shan if (all && pdev->subordinate) 289c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 29096a2f92bSGavin Shan pe_bitmap, all); 29196a2f92bSGavin Shan } 29296a2f92bSGavin Shan } 29396a2f92bSGavin Shan 2941e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 295262af557SGuo Chao { 2965609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 297262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 298262af557SGuo Chao unsigned long size, *pe_alloc; 29926ba248dSGavin Shan int i; 300262af557SGuo Chao 301262af557SGuo Chao /* Root bus shouldn't use M64 */ 302262af557SGuo Chao if (pci_is_root_bus(bus)) 3031e916772SGavin Shan return NULL; 304262af557SGuo Chao 305262af557SGuo Chao /* Allocate bitmap */ 306b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 307262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 308262af557SGuo Chao if (!pe_alloc) { 309262af557SGuo Chao pr_warn("%s: Out of memory !\n", 310262af557SGuo Chao __func__); 3111e916772SGavin Shan return NULL; 312262af557SGuo Chao } 313262af557SGuo Chao 31426ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 315c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 316262af557SGuo Chao 317262af557SGuo Chao /* 318262af557SGuo Chao * the current bus might not own M64 window and that's all 319262af557SGuo Chao * contributed by its child buses. For the case, we needn't 320262af557SGuo Chao * pick M64 dependent PE#. 321262af557SGuo Chao */ 32292b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 323262af557SGuo Chao kfree(pe_alloc); 3241e916772SGavin Shan return NULL; 325262af557SGuo Chao } 326262af557SGuo Chao 327262af557SGuo Chao /* 328262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 329262af557SGuo Chao * PE's list to form compound PE. 330262af557SGuo Chao */ 331262af557SGuo Chao master_pe = NULL; 332262af557SGuo Chao i = -1; 33392b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 33492b8f137SGavin Shan phb->ioda.total_pe_num) { 335262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 336262af557SGuo Chao 33793289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 338262af557SGuo Chao if (!master_pe) { 339262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 340262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 341262af557SGuo Chao master_pe = pe; 342262af557SGuo Chao } else { 343262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 344262af557SGuo Chao pe->master = master_pe; 345262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 346262af557SGuo Chao } 347262af557SGuo Chao } 348262af557SGuo Chao 349262af557SGuo Chao kfree(pe_alloc); 3501e916772SGavin Shan return master_pe; 351262af557SGuo Chao } 352262af557SGuo Chao 353262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 354262af557SGuo Chao { 355262af557SGuo Chao struct pci_controller *hose = phb->hose; 356262af557SGuo Chao struct device_node *dn = hose->dn; 357262af557SGuo Chao struct resource *res; 358a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 3590e7736c6SGavin Shan const __be32 *r; 360262af557SGuo Chao u64 pci_addr; 361262af557SGuo Chao 36299451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 3631665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3641665c4a8SGavin Shan return; 3651665c4a8SGavin Shan } 3661665c4a8SGavin Shan 367e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 368262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 369262af557SGuo Chao return; 370262af557SGuo Chao } 371262af557SGuo Chao 372262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 373262af557SGuo Chao if (!r) { 374b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 375b7c670d6SRob Herring dn); 376262af557SGuo Chao return; 377262af557SGuo Chao } 378262af557SGuo Chao 379a1339fafSBenjamin Herrenschmidt /* 380a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 381a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 382a1339fafSBenjamin Herrenschmidt */ 383a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 384a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 385a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 386a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 387a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 388a1339fafSBenjamin Herrenschmidt } 389a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 390a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 391a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 392a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 393a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 394a1339fafSBenjamin Herrenschmidt } 395a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 396a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 397a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 398a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 399a1339fafSBenjamin Herrenschmidt return; 400a1339fafSBenjamin Herrenschmidt } 401a1339fafSBenjamin Herrenschmidt 402a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 403262af557SGuo Chao res = &hose->mem_resources[1]; 404e80c4e7cSGavin Shan res->name = dn->full_name; 405262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 406262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 407262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 408262af557SGuo Chao pci_addr = of_read_number(r, 2); 409262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 410262af557SGuo Chao 411262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 41292b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 413262af557SGuo Chao phb->ioda.m64_base = pci_addr; 414262af557SGuo Chao 415a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 416a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 417a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 418a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 419a1339fafSBenjamin Herrenschmidt 420a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 421a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 422e9863e68SWei Yang 423262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 424a1339fafSBenjamin Herrenschmidt m64_range[1]--; 425a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 426a1339fafSBenjamin Herrenschmidt 427a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 428a1339fafSBenjamin Herrenschmidt 429a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 430a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 431a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 432a1339fafSBenjamin Herrenschmidt 433a1339fafSBenjamin Herrenschmidt /* 434a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 435a1339fafSBenjamin Herrenschmidt * the IODA2 code. 436a1339fafSBenjamin Herrenschmidt */ 437262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 438262af557SGuo Chao } 439262af557SGuo Chao 44049dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 44149dec922SGavin Shan { 44249dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 44349dec922SGavin Shan struct pnv_ioda_pe *slave; 44449dec922SGavin Shan s64 rc; 44549dec922SGavin Shan 44649dec922SGavin Shan /* Fetch master PE */ 44749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 44849dec922SGavin Shan pe = pe->master; 449ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 450ec8e4e9dSGavin Shan return; 451ec8e4e9dSGavin Shan 45249dec922SGavin Shan pe_no = pe->pe_number; 45349dec922SGavin Shan } 45449dec922SGavin Shan 45549dec922SGavin Shan /* Freeze master PE */ 45649dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 45749dec922SGavin Shan pe_no, 45849dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 45949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 46049dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 46149dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 46249dec922SGavin Shan return; 46349dec922SGavin Shan } 46449dec922SGavin Shan 46549dec922SGavin Shan /* Freeze slave PEs */ 46649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 46749dec922SGavin Shan return; 46849dec922SGavin Shan 46949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 47049dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 47149dec922SGavin Shan slave->pe_number, 47249dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 47349dec922SGavin Shan if (rc != OPAL_SUCCESS) 47449dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 47549dec922SGavin Shan __func__, rc, phb->hose->global_number, 47649dec922SGavin Shan slave->pe_number); 47749dec922SGavin Shan } 47849dec922SGavin Shan } 47949dec922SGavin Shan 480e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 48149dec922SGavin Shan { 48249dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 48349dec922SGavin Shan s64 rc; 48449dec922SGavin Shan 48549dec922SGavin Shan /* Find master PE */ 48649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 48749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 48849dec922SGavin Shan pe = pe->master; 48949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 49049dec922SGavin Shan pe_no = pe->pe_number; 49149dec922SGavin Shan } 49249dec922SGavin Shan 49349dec922SGavin Shan /* Clear frozen state for master PE */ 49449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 49549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 49649dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 49749dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 49849dec922SGavin Shan return -EIO; 49949dec922SGavin Shan } 50049dec922SGavin Shan 50149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 50249dec922SGavin Shan return 0; 50349dec922SGavin Shan 50449dec922SGavin Shan /* Clear frozen state for slave PEs */ 50549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 50649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 50749dec922SGavin Shan slave->pe_number, 50849dec922SGavin Shan opt); 50949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 51049dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 51149dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 51249dec922SGavin Shan slave->pe_number); 51349dec922SGavin Shan return -EIO; 51449dec922SGavin Shan } 51549dec922SGavin Shan } 51649dec922SGavin Shan 51749dec922SGavin Shan return 0; 51849dec922SGavin Shan } 51949dec922SGavin Shan 52049dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 52149dec922SGavin Shan { 52249dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 523c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 524c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 52549dec922SGavin Shan s64 rc; 52649dec922SGavin Shan 52749dec922SGavin Shan /* Sanity check on PE number */ 52892b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 52949dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 53049dec922SGavin Shan 53149dec922SGavin Shan /* 53249dec922SGavin Shan * Fetch the master PE and the PE instance might be 53349dec922SGavin Shan * not initialized yet. 53449dec922SGavin Shan */ 53549dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 53649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53749dec922SGavin Shan pe = pe->master; 53849dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 53949dec922SGavin Shan pe_no = pe->pe_number; 54049dec922SGavin Shan } 54149dec922SGavin Shan 54249dec922SGavin Shan /* Check the master PE */ 54349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 54449dec922SGavin Shan &state, &pcierr, NULL); 54549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 54749dec922SGavin Shan "PHB#%x-PE#%x state\n", 54849dec922SGavin Shan __func__, rc, 54949dec922SGavin Shan phb->hose->global_number, pe_no); 55049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 55149dec922SGavin Shan } 55249dec922SGavin Shan 55349dec922SGavin Shan /* Check the slave PE */ 55449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55549dec922SGavin Shan return state; 55649dec922SGavin Shan 55749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 55949dec922SGavin Shan slave->pe_number, 56049dec922SGavin Shan &fstate, 56149dec922SGavin Shan &pcierr, 56249dec922SGavin Shan NULL); 56349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 56449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 56549dec922SGavin Shan "PHB#%x-PE#%x state\n", 56649dec922SGavin Shan __func__, rc, 56749dec922SGavin Shan phb->hose->global_number, slave->pe_number); 56849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 56949dec922SGavin Shan } 57049dec922SGavin Shan 57149dec922SGavin Shan /* 57249dec922SGavin Shan * Override the result based on the ascending 57349dec922SGavin Shan * priority. 57449dec922SGavin Shan */ 57549dec922SGavin Shan if (fstate > state) 57649dec922SGavin Shan state = fstate; 57749dec922SGavin Shan } 57849dec922SGavin Shan 57949dec922SGavin Shan return state; 58049dec922SGavin Shan } 58149dec922SGavin Shan 582a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 583a8d7d5fcSOliver O'Halloran { 584a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn]; 585a8d7d5fcSOliver O'Halloran 586a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE) 587a8d7d5fcSOliver O'Halloran return NULL; 588a8d7d5fcSOliver O'Halloran 589a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number]; 590a8d7d5fcSOliver O'Halloran } 591a8d7d5fcSOliver O'Halloran 592f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 593184cd4a3SBenjamin Herrenschmidt { 5945609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 595b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 596184cd4a3SBenjamin Herrenschmidt 597184cd4a3SBenjamin Herrenschmidt if (!pdn) 598184cd4a3SBenjamin Herrenschmidt return NULL; 599184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 600184cd4a3SBenjamin Herrenschmidt return NULL; 601184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 602184cd4a3SBenjamin Herrenschmidt } 603184cd4a3SBenjamin Herrenschmidt 604b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 605b131a842SGavin Shan struct pnv_ioda_pe *parent, 606b131a842SGavin Shan struct pnv_ioda_pe *child, 607b131a842SGavin Shan bool is_add) 608b131a842SGavin Shan { 609b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 610b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 611b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 612b131a842SGavin Shan struct pnv_ioda_pe *slave; 613b131a842SGavin Shan long rc; 614b131a842SGavin Shan 615b131a842SGavin Shan /* Parent PE affects child PE */ 616b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 617b131a842SGavin Shan child->pe_number, op); 618b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 619b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 620b131a842SGavin Shan rc, desc); 621b131a842SGavin Shan return -ENXIO; 622b131a842SGavin Shan } 623b131a842SGavin Shan 624b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 625b131a842SGavin Shan return 0; 626b131a842SGavin Shan 627b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 628b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 629b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 630b131a842SGavin Shan slave->pe_number, op); 631b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 632b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 633b131a842SGavin Shan rc, desc); 634b131a842SGavin Shan return -ENXIO; 635b131a842SGavin Shan } 636b131a842SGavin Shan } 637b131a842SGavin Shan 638b131a842SGavin Shan return 0; 639b131a842SGavin Shan } 640b131a842SGavin Shan 641b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 642b131a842SGavin Shan struct pnv_ioda_pe *pe, 643b131a842SGavin Shan bool is_add) 644b131a842SGavin Shan { 645b131a842SGavin Shan struct pnv_ioda_pe *slave; 646781a868fSWei Yang struct pci_dev *pdev = NULL; 647b131a842SGavin Shan int ret; 648b131a842SGavin Shan 649b131a842SGavin Shan /* 650b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 651b131a842SGavin Shan * clear slave PE frozen state as well. 652b131a842SGavin Shan */ 653b131a842SGavin Shan if (is_add) { 654b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 655b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 656b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 657b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 658b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 659b131a842SGavin Shan slave->pe_number, 660b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 661b131a842SGavin Shan } 662b131a842SGavin Shan } 663b131a842SGavin Shan 664b131a842SGavin Shan /* 665b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 666b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 667b131a842SGavin Shan * originated from the PE might contribute to other 668b131a842SGavin Shan * PEs. 669b131a842SGavin Shan */ 670b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 671b131a842SGavin Shan if (ret) 672b131a842SGavin Shan return ret; 673b131a842SGavin Shan 674b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 675b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 676b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 677b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 678b131a842SGavin Shan if (ret) 679b131a842SGavin Shan return ret; 680b131a842SGavin Shan } 681b131a842SGavin Shan } 682b131a842SGavin Shan 683b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 684b131a842SGavin Shan pdev = pe->pbus->self; 685781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 686b131a842SGavin Shan pdev = pe->pdev->bus->self; 687781a868fSWei Yang #ifdef CONFIG_PCI_IOV 688781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 689283e2d8aSGavin Shan pdev = pe->parent_dev; 690781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 691b131a842SGavin Shan while (pdev) { 692b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 693b131a842SGavin Shan struct pnv_ioda_pe *parent; 694b131a842SGavin Shan 695b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 696b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 697b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 698b131a842SGavin Shan if (ret) 699b131a842SGavin Shan return ret; 700b131a842SGavin Shan } 701b131a842SGavin Shan 702b131a842SGavin Shan pdev = pdev->bus->self; 703b131a842SGavin Shan } 704b131a842SGavin Shan 705b131a842SGavin Shan return 0; 706b131a842SGavin Shan } 707b131a842SGavin Shan 708f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 709f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 710f724385fSFrederic Barrat struct pci_dev *parent) 711f724385fSFrederic Barrat { 712f724385fSFrederic Barrat int64_t rc; 713f724385fSFrederic Barrat 714f724385fSFrederic Barrat while (parent) { 715f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 716f724385fSFrederic Barrat 717f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 718f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 719f724385fSFrederic Barrat pe->pe_number, 720f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 721f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 722f724385fSFrederic Barrat } 723f724385fSFrederic Barrat parent = parent->bus->self; 724f724385fSFrederic Barrat } 725f724385fSFrederic Barrat 726f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 727f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 728f724385fSFrederic Barrat 729f724385fSFrederic Barrat /* Disassociate PE in PELT */ 730f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 731f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 732f724385fSFrederic Barrat if (rc) 733f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 734f724385fSFrederic Barrat } 735f724385fSFrederic Barrat 73637b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 737781a868fSWei Yang { 738781a868fSWei Yang struct pci_dev *parent; 739781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 740781a868fSWei Yang int64_t rc; 741781a868fSWei Yang long rid_end, rid; 742781a868fSWei Yang 743781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 744781a868fSWei Yang if (pe->pbus) { 745781a868fSWei Yang int count; 746781a868fSWei Yang 747781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 748781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 749781a868fSWei Yang parent = pe->pbus->self; 750781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 751552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 752781a868fSWei Yang else 753781a868fSWei Yang count = 1; 754781a868fSWei Yang 755781a868fSWei Yang switch(count) { 756781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 757781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 758781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 759781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 760781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 761781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 762781a868fSWei Yang default: 763781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 764781a868fSWei Yang count); 765781a868fSWei Yang /* Do an exact match only */ 766781a868fSWei Yang bcomp = OpalPciBusAll; 767781a868fSWei Yang } 768781a868fSWei Yang rid_end = pe->rid + (count << 8); 769781a868fSWei Yang } else { 77093e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 771781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 772781a868fSWei Yang parent = pe->parent_dev; 773781a868fSWei Yang else 77493e01a50SGavin Shan #endif 775781a868fSWei Yang parent = pe->pdev->bus->self; 776781a868fSWei Yang bcomp = OpalPciBusAll; 777781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 778781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 779781a868fSWei Yang rid_end = pe->rid + 1; 780781a868fSWei Yang } 781781a868fSWei Yang 782781a868fSWei Yang /* Clear the reverse map */ 783781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 784c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 785781a868fSWei Yang 786f724385fSFrederic Barrat /* 787f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 788f724385fSFrederic Barrat * table 789f724385fSFrederic Barrat */ 790562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI) 791f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 792781a868fSWei Yang 793781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 794781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 795781a868fSWei Yang if (rc) 7961e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 797781a868fSWei Yang 798781a868fSWei Yang pe->pbus = NULL; 799781a868fSWei Yang pe->pdev = NULL; 80093e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 801781a868fSWei Yang pe->parent_dev = NULL; 80293e01a50SGavin Shan #endif 803781a868fSWei Yang 804781a868fSWei Yang return 0; 805781a868fSWei Yang } 806781a868fSWei Yang 80737b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 808184cd4a3SBenjamin Herrenschmidt { 809184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 810184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 811184cd4a3SBenjamin Herrenschmidt 812184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 813184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 814184cd4a3SBenjamin Herrenschmidt int count; 815184cd4a3SBenjamin Herrenschmidt 816184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 817184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 818fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 819552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 820fb446ad0SGavin Shan else 821fb446ad0SGavin Shan count = 1; 822fb446ad0SGavin Shan 823184cd4a3SBenjamin Herrenschmidt switch(count) { 824184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 825184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 826184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 827184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 828184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 829184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 830184cd4a3SBenjamin Herrenschmidt default: 831781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 832781a868fSWei Yang count); 833184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 834184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 835184cd4a3SBenjamin Herrenschmidt } 836184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 837184cd4a3SBenjamin Herrenschmidt } else { 838184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 839184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 840184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 841184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 842184cd4a3SBenjamin Herrenschmidt } 843184cd4a3SBenjamin Herrenschmidt 844631ad691SGavin Shan /* 845631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 846631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 847631ad691SGavin Shan * originated from the PE might contribute to other 848631ad691SGavin Shan * PEs. 849631ad691SGavin Shan */ 850184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 851184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 852184cd4a3SBenjamin Herrenschmidt if (rc) { 853184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 854184cd4a3SBenjamin Herrenschmidt return -ENXIO; 855184cd4a3SBenjamin Herrenschmidt } 856631ad691SGavin Shan 8575d2aa710SAlistair Popple /* 8585d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 8595d2aa710SAlistair Popple * configuration on them. 8605d2aa710SAlistair Popple */ 861562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI) 862b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 863184cd4a3SBenjamin Herrenschmidt 864184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 865184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 866184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 867184cd4a3SBenjamin Herrenschmidt 868184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8694773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8704773f76bSGavin Shan pe->mve_number = 0; 8714773f76bSGavin Shan goto out; 8724773f76bSGavin Shan } 8734773f76bSGavin Shan 874184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8754773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8764773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 8771f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 878184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 879184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 880184cd4a3SBenjamin Herrenschmidt } else { 881184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 882cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 883184cd4a3SBenjamin Herrenschmidt if (rc) { 8841f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 885184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 886184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 887184cd4a3SBenjamin Herrenschmidt } 888184cd4a3SBenjamin Herrenschmidt } 889184cd4a3SBenjamin Herrenschmidt 8904773f76bSGavin Shan out: 891184cd4a3SBenjamin Herrenschmidt return 0; 892184cd4a3SBenjamin Herrenschmidt } 893184cd4a3SBenjamin Herrenschmidt 894cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 895184cd4a3SBenjamin Herrenschmidt { 8965609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 897b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 898184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 899184cd4a3SBenjamin Herrenschmidt 900184cd4a3SBenjamin Herrenschmidt if (!pdn) { 901184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 902184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 903184cd4a3SBenjamin Herrenschmidt return NULL; 904184cd4a3SBenjamin Herrenschmidt } 905184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 906184cd4a3SBenjamin Herrenschmidt return NULL; 907184cd4a3SBenjamin Herrenschmidt 908a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 9091e916772SGavin Shan if (!pe) { 910f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 911184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 912184cd4a3SBenjamin Herrenschmidt return NULL; 913184cd4a3SBenjamin Herrenschmidt } 914184cd4a3SBenjamin Herrenschmidt 91505dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 91605dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 917562d1e20SChristoph Hellwig * destroyed at the same time. 918184cd4a3SBenjamin Herrenschmidt * 919184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 920184cd4a3SBenjamin Herrenschmidt */ 9211e916772SGavin Shan pdn->pe_number = pe->pe_number; 9225d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 923184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 924184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 925184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 926184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 927f724385fSFrederic Barrat pe->device_count++; 928184cd4a3SBenjamin Herrenschmidt 929184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 930184cd4a3SBenjamin Herrenschmidt 931184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 932184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 9331e916772SGavin Shan pnv_ioda_free_pe(pe); 934184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 935184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 936184cd4a3SBenjamin Herrenschmidt return NULL; 937184cd4a3SBenjamin Herrenschmidt } 938184cd4a3SBenjamin Herrenschmidt 9391d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 94080f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 9411d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 94280f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 943184cd4a3SBenjamin Herrenschmidt return pe; 944184cd4a3SBenjamin Herrenschmidt } 945184cd4a3SBenjamin Herrenschmidt 946fb446ad0SGavin Shan /* 947fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 948fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 949fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 950fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 951fb446ad0SGavin Shan */ 9521e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 953184cd4a3SBenjamin Herrenschmidt { 9545609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 9551e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 956ccd1c191SGavin Shan unsigned int pe_num; 957ccd1c191SGavin Shan 958ccd1c191SGavin Shan /* 959ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 960ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 961ccd1c191SGavin Shan */ 962ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 9636ae8aedfSOliver O'Halloran if (WARN_ON(pe_num != IODA_INVALID_PE)) { 964ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 965ccd1c191SGavin Shan return NULL; 966ccd1c191SGavin Shan } 967184cd4a3SBenjamin Herrenschmidt 96863803c39SGavin Shan /* PE number for root bus should have been reserved */ 969718d249aSOliver O'Halloran if (pci_is_root_bus(bus)) 97063803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 97163803c39SGavin Shan 972262af557SGuo Chao /* Check if PE is determined by M64 */ 973a25de7afSAlexey Kardashevskiy if (!pe) 974a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 975262af557SGuo Chao 976262af557SGuo Chao /* The PE number isn't pinned by M64 */ 9771e916772SGavin Shan if (!pe) 978a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 979262af557SGuo Chao 9801e916772SGavin Shan if (!pe) { 981f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 982fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 9831e916772SGavin Shan return NULL; 984184cd4a3SBenjamin Herrenschmidt } 985184cd4a3SBenjamin Herrenschmidt 986262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 987184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 988184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 989184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 990b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 991184cd4a3SBenjamin Herrenschmidt 992fb446ad0SGavin Shan if (all) 9931e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 9941e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 9951e496391SJoe Perches pe->pe_number); 996fb446ad0SGavin Shan else 9971e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 9981e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 999184cd4a3SBenjamin Herrenschmidt 1000184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1001184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10021e916772SGavin Shan pnv_ioda_free_pe(pe); 1003184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 10041e916772SGavin Shan return NULL; 1005184cd4a3SBenjamin Herrenschmidt } 1006184cd4a3SBenjamin Herrenschmidt 10077ebdf956SGavin Shan /* Put PE to the list */ 10087ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10091e916772SGavin Shan 10101e916772SGavin Shan return pe; 1011184cd4a3SBenjamin Herrenschmidt } 1012184cd4a3SBenjamin Herrenschmidt 10130a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1014184cd4a3SBenjamin Herrenschmidt { 10155609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1016b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1017959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1018184cd4a3SBenjamin Herrenschmidt 1019dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */ 1020dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1021dc3d8f85SOliver O'Halloran if (!pe) { 1022dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1023dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn)) 1024959c9bddSGavin Shan return; 1025184cd4a3SBenjamin Herrenschmidt 1026dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus); 1027dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1028dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1029dc3d8f85SOliver O'Halloran 1030dc3d8f85SOliver O'Halloran 1031dc3d8f85SOliver O'Halloran /* 1032dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly 1033dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device. 1034dc3d8f85SOliver O'Halloran */ 1035dc3d8f85SOliver O'Halloran if (WARN_ON(!pe)) 1036dc3d8f85SOliver O'Halloran return; 1037dc3d8f85SOliver O'Halloran } else { 1038dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1039dc3d8f85SOliver O'Halloran } 1040dc3d8f85SOliver O'Halloran 104101e12629SOliver O'Halloran /* 104201e12629SOliver O'Halloran * We assume that bridges *probably* don't need to do any DMA so we can 104301e12629SOliver O'Halloran * skip allocating a TCE table, etc unless we get a non-bridge device. 104401e12629SOliver O'Halloran */ 104501e12629SOliver O'Halloran if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { 104601e12629SOliver O'Halloran switch (phb->type) { 104701e12629SOliver O'Halloran case PNV_PHB_IODA2: 104801e12629SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe); 104901e12629SOliver O'Halloran break; 105001e12629SOliver O'Halloran default: 105101e12629SOliver O'Halloran pr_warn("%s: No DMA for PHB#%x (type %d)\n", 105201e12629SOliver O'Halloran __func__, phb->hose->global_number, phb->type); 105301e12629SOliver O'Halloran } 105401e12629SOliver O'Halloran } 105501e12629SOliver O'Halloran 1056dc3d8f85SOliver O'Halloran if (pdn) 1057dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number; 1058dc3d8f85SOliver O'Halloran pe->device_count++; 1059dc3d8f85SOliver O'Halloran 1060cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 10610617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1062b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 106384d8cc07SOliver O'Halloran 106484d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */ 106584d8cc07SOliver O'Halloran if (pe->table_group.group) 106684d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev); 1067184cd4a3SBenjamin Herrenschmidt } 1068184cd4a3SBenjamin Herrenschmidt 10698e3f1b1dSRussell Currey /* 10708e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 10718e3f1b1dSRussell Currey * 10728e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 10738e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 10748e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 10758e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 10768e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 10778e3f1b1dSRussell Currey * devices in TVE#0. 10788e3f1b1dSRussell Currey * 10798e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 10808e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 10818e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 10828e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 10838e3f1b1dSRussell Currey * 10848e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 10858e3f1b1dSRussell Currey */ 10868e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 10878e3f1b1dSRussell Currey { 10888e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 10898e3f1b1dSRussell Currey struct page *table_pages; 10908e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 10918e3f1b1dSRussell Currey __be64 *tces; 10928e3f1b1dSRussell Currey s64 rc; 10938e3f1b1dSRussell Currey 10948e3f1b1dSRussell Currey /* 10958e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 10968e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 10978e3f1b1dSRussell Currey */ 10988e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 10998e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 11008e3f1b1dSRussell Currey table_size = tce_count << 3; 11018e3f1b1dSRussell Currey 11028e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 11038e3f1b1dSRussell Currey table_size = PAGE_SIZE; 11048e3f1b1dSRussell Currey 11058e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 11068e3f1b1dSRussell Currey get_order(table_size)); 11078e3f1b1dSRussell Currey if (!table_pages) 11088e3f1b1dSRussell Currey goto err; 11098e3f1b1dSRussell Currey 11108e3f1b1dSRussell Currey tces = page_address(table_pages); 11118e3f1b1dSRussell Currey if (!tces) 11128e3f1b1dSRussell Currey goto err; 11138e3f1b1dSRussell Currey 11148e3f1b1dSRussell Currey memset(tces, 0, table_size); 11158e3f1b1dSRussell Currey 11168e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 11178e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 11188e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 11198e3f1b1dSRussell Currey } 11208e3f1b1dSRussell Currey 11218e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 11228e3f1b1dSRussell Currey pe->pe_number, 11238e3f1b1dSRussell Currey /* reconfigure window 0 */ 11248e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 11258e3f1b1dSRussell Currey 1, 11268e3f1b1dSRussell Currey __pa(tces), 11278e3f1b1dSRussell Currey table_size, 11288e3f1b1dSRussell Currey 1 << tce_order); 11298e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 11308e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 11318e3f1b1dSRussell Currey return 0; 11328e3f1b1dSRussell Currey } 11338e3f1b1dSRussell Currey err: 11348e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 11358e3f1b1dSRussell Currey return -EIO; 11368e3f1b1dSRussell Currey } 11378e3f1b1dSRussell Currey 11382d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 11392d6ad41bSChristoph Hellwig u64 dma_mask) 1140cd15b048SBenjamin Herrenschmidt { 11415609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1142cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1143cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1144cd15b048SBenjamin Herrenschmidt 1145cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1146b511cdd1SAlexey Kardashevskiy return false; 1147cd15b048SBenjamin Herrenschmidt 1148cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1149cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 11502d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 11512d6ad41bSChristoph Hellwig if (dma_mask >= top) 11522d6ad41bSChristoph Hellwig return true; 1153cd15b048SBenjamin Herrenschmidt } 1154cd15b048SBenjamin Herrenschmidt 11558e3f1b1dSRussell Currey /* 11568e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 11578e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 11588e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 11598e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 11608e3f1b1dSRussell Currey */ 11618e3f1b1dSRussell Currey if (dma_mask >> 32 && 11628e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1163661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1164661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 11658e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 11668e3f1b1dSRussell Currey /* Configure the bypass mode */ 11672d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 11688e3f1b1dSRussell Currey if (rc) 1169b511cdd1SAlexey Kardashevskiy return false; 11708e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 11710617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 11722d6ad41bSChristoph Hellwig return true; 1173cd15b048SBenjamin Herrenschmidt } 1174cd15b048SBenjamin Herrenschmidt 11752d6ad41bSChristoph Hellwig return false; 1176fe7e85c6SGavin Shan } 1177fe7e85c6SGavin Shan 1178cad32d9dSAlexey Kardashevskiy static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb) 1179fd141d1aSBenjamin Herrenschmidt { 1180cad32d9dSAlexey Kardashevskiy return phb->regs + 0x210; 1181fd141d1aSBenjamin Herrenschmidt } 1182fd141d1aSBenjamin Herrenschmidt 118305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 118435872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 118535872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 1186cad32d9dSAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 118705c6cfb9SAlexey Kardashevskiy { 1188cad32d9dSAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction); 1189a540aa56SAlexey Kardashevskiy } 119005c6cfb9SAlexey Kardashevskiy #endif 119105c6cfb9SAlexey Kardashevskiy 1192a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1193a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1194a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1195bef9253fSAlexey Kardashevskiy 1196a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 11975780fb04SAlexey Kardashevskiy { 11985780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1199cad32d9dSAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); 1200a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 12015780fb04SAlexey Kardashevskiy 12025780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1203001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 12045780fb04SAlexey Kardashevskiy } 12055780fb04SAlexey Kardashevskiy 1206cad32d9dSAlexey Kardashevskiy static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, 1207fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1208fd141d1aSBenjamin Herrenschmidt unsigned long npages) 12094cce9550SGavin Shan { 1210cad32d9dSAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); 12114cce9550SGavin Shan unsigned long start, end, inc; 12124cce9550SGavin Shan 12134cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1214a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1215fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 12164cce9550SGavin Shan end = start; 12174cce9550SGavin Shan 12184cce9550SGavin Shan /* Figure out the start, end and step */ 1219decbda25SAlexey Kardashevskiy start |= (index << shift); 1220decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1221b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 12224cce9550SGavin Shan mb(); 12234cce9550SGavin Shan 12244cce9550SGavin Shan while (start <= end) { 1225001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 12264cce9550SGavin Shan start += inc; 12274cce9550SGavin Shan } 12284cce9550SGavin Shan } 12294cce9550SGavin Shan 1230f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1231f0228c41SBenjamin Herrenschmidt { 1232f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1233f0228c41SBenjamin Herrenschmidt 1234f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1235f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1236f0228c41SBenjamin Herrenschmidt else 1237f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1238f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1239f0228c41SBenjamin Herrenschmidt } 1240f0228c41SBenjamin Herrenschmidt 1241e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1242cad32d9dSAlexey Kardashevskiy unsigned long index, unsigned long npages) 1243e57080f1SAlexey Kardashevskiy { 1244e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1245e57080f1SAlexey Kardashevskiy 1246a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1247e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1248e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1249f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1250f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1251f0228c41SBenjamin Herrenschmidt 1252f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1253cad32d9dSAlexey Kardashevskiy pnv_pci_phb3_tce_invalidate(pe, shift, 125485674868SAlexey Kardashevskiy index, npages); 1255f0228c41SBenjamin Herrenschmidt else 1256f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 1257f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1258f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1259f0228c41SBenjamin Herrenschmidt index << shift, npages); 1260e57080f1SAlexey Kardashevskiy } 1261e57080f1SAlexey Kardashevskiy } 1262e57080f1SAlexey Kardashevskiy 1263decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1264decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1265decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 126600085f1eSKrzysztof Kozlowski unsigned long attrs) 12674cce9550SGavin Shan { 1268decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1269decbda25SAlexey Kardashevskiy attrs); 12704cce9550SGavin Shan 127108acce1cSBenjamin Herrenschmidt if (!ret) 1272cad32d9dSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages); 1273decbda25SAlexey Kardashevskiy 1274decbda25SAlexey Kardashevskiy return ret; 1275decbda25SAlexey Kardashevskiy } 1276decbda25SAlexey Kardashevskiy 1277decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1278decbda25SAlexey Kardashevskiy long npages) 1279decbda25SAlexey Kardashevskiy { 1280decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1281decbda25SAlexey Kardashevskiy 1282cad32d9dSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages); 12834cce9550SGavin Shan } 12844cce9550SGavin Shan 1285da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1286decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 128705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 128835872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 128935872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 1290090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 129105c6cfb9SAlexey Kardashevskiy #endif 1292decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1293da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1294da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 1295da004c36SAlexey Kardashevskiy }; 1296da004c36SAlexey Kardashevskiy 129743cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 129843cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 129943cb60abSAlexey Kardashevskiy { 130043cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 130143cb60abSAlexey Kardashevskiy table_group); 130243cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 130343cb60abSAlexey Kardashevskiy int64_t rc; 1304bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1305bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 130643cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 130743cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 130843cb60abSAlexey Kardashevskiy 13091e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 13101e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 131143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 131243cb60abSAlexey Kardashevskiy 131343cb60abSAlexey Kardashevskiy /* 131443cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 131543cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 131643cb60abSAlexey Kardashevskiy */ 131743cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 131843cb60abSAlexey Kardashevskiy pe->pe_number, 13194793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 1320bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 132143cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 1322bbb845c4SAlexey Kardashevskiy size << 3, 132343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 132443cb60abSAlexey Kardashevskiy if (rc) { 13251e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 132643cb60abSAlexey Kardashevskiy return rc; 132743cb60abSAlexey Kardashevskiy } 132843cb60abSAlexey Kardashevskiy 132943cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 133043cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 1331ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 133243cb60abSAlexey Kardashevskiy 133343cb60abSAlexey Kardashevskiy return 0; 133443cb60abSAlexey Kardashevskiy } 133543cb60abSAlexey Kardashevskiy 1336c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1337cd15b048SBenjamin Herrenschmidt { 1338cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1339cd15b048SBenjamin Herrenschmidt int64_t rc; 1340cd15b048SBenjamin Herrenschmidt 1341cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1342cd15b048SBenjamin Herrenschmidt if (enable) { 1343cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1344cd15b048SBenjamin Herrenschmidt 1345cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1346cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1347cd15b048SBenjamin Herrenschmidt pe->pe_number, 1348cd15b048SBenjamin Herrenschmidt window_id, 1349cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1350cd15b048SBenjamin Herrenschmidt top); 1351cd15b048SBenjamin Herrenschmidt } else { 1352cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1353cd15b048SBenjamin Herrenschmidt pe->pe_number, 1354cd15b048SBenjamin Herrenschmidt window_id, 1355cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1356cd15b048SBenjamin Herrenschmidt 0); 1357cd15b048SBenjamin Herrenschmidt } 1358cd15b048SBenjamin Herrenschmidt if (rc) 1359cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1360cd15b048SBenjamin Herrenschmidt else 1361cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1362cd15b048SBenjamin Herrenschmidt } 1363cd15b048SBenjamin Herrenschmidt 13644793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 13654793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1366090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 13674793d65dSAlexey Kardashevskiy { 13684793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 13694793d65dSAlexey Kardashevskiy table_group); 13704793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 13714793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 13724793d65dSAlexey Kardashevskiy long ret; 13734793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 13744793d65dSAlexey Kardashevskiy 13754793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 13764793d65dSAlexey Kardashevskiy if (!tbl) 13774793d65dSAlexey Kardashevskiy return -ENOMEM; 13784793d65dSAlexey Kardashevskiy 137911edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 138011edf116SAlexey Kardashevskiy 13814793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 13824793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 1383090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 13844793d65dSAlexey Kardashevskiy if (ret) { 1385e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 13864793d65dSAlexey Kardashevskiy return ret; 13874793d65dSAlexey Kardashevskiy } 13884793d65dSAlexey Kardashevskiy 13894793d65dSAlexey Kardashevskiy *ptbl = tbl; 13904793d65dSAlexey Kardashevskiy 13914793d65dSAlexey Kardashevskiy return 0; 13924793d65dSAlexey Kardashevskiy } 13934793d65dSAlexey Kardashevskiy 139446d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 139546d3e1e1SAlexey Kardashevskiy { 139646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 139746d3e1e1SAlexey Kardashevskiy long rc; 1398201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 139946d3e1e1SAlexey Kardashevskiy 1400bb005455SNishanth Aravamudan /* 1401fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 1402fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 1403fa144869SNishanth Aravamudan * of 2, which will cause errors later. 1404fa144869SNishanth Aravamudan */ 1405fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 1406fa144869SNishanth Aravamudan 1407fa144869SNishanth Aravamudan /* 1408bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 1409bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 1410bb005455SNishanth Aravamudan * cause errors later. 1411bb005455SNishanth Aravamudan */ 141223baf831SKirill A. Shutemov const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER); 1413bb005455SNishanth Aravamudan 1414201ed7f3SAlexey Kardashevskiy /* 1415201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 1416201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 1417201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 1418201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 1419201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 1420201ed7f3SAlexey Kardashevskiy */ 1421201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 1422201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 1423201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 1424201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 1425201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 1426201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 1427201ed7f3SAlexey Kardashevskiy 1428201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 1429201ed7f3SAlexey Kardashevskiy levels += 1; 1430201ed7f3SAlexey Kardashevskiy /* 1431201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 1432201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 1433201ed7f3SAlexey Kardashevskiy */ 1434201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 1435201ed7f3SAlexey Kardashevskiy 1436201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 1437201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 143846d3e1e1SAlexey Kardashevskiy if (rc) { 143946d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 144046d3e1e1SAlexey Kardashevskiy rc); 144146d3e1e1SAlexey Kardashevskiy return rc; 144246d3e1e1SAlexey Kardashevskiy } 144346d3e1e1SAlexey Kardashevskiy 1444201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 1445201ed7f3SAlexey Kardashevskiy res_start = 0; 1446201ed7f3SAlexey Kardashevskiy res_end = 0; 1447201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 1448201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 1449201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 1450201ed7f3SAlexey Kardashevskiy } 145146d3e1e1SAlexey Kardashevskiy 1452d73b46c3SAlexey Kardashevskiy tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number; 14534be518d8SAlexey Kardashevskiy if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) 145446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 14554be518d8SAlexey Kardashevskiy else 14564be518d8SAlexey Kardashevskiy rc = -ENOMEM; 145746d3e1e1SAlexey Kardashevskiy if (rc) { 14584be518d8SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); 1459e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 14604be518d8SAlexey Kardashevskiy tbl = NULL; /* This clears iommu_table_base below */ 146146d3e1e1SAlexey Kardashevskiy } 146246d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 146346d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 146446d3e1e1SAlexey Kardashevskiy 14655636427dSAlexey Kardashevskiy /* 14665636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 14675636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 14685636427dSAlexey Kardashevskiy * from VFIO so do it here. 14695636427dSAlexey Kardashevskiy */ 14705636427dSAlexey Kardashevskiy if (pe->pdev) 14715636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 14725636427dSAlexey Kardashevskiy 147346d3e1e1SAlexey Kardashevskiy return 0; 147446d3e1e1SAlexey Kardashevskiy } 147546d3e1e1SAlexey Kardashevskiy 1476b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1477b5926430SAlexey Kardashevskiy int num) 1478b5926430SAlexey Kardashevskiy { 1479b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1480b5926430SAlexey Kardashevskiy table_group); 1481b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 1482b5926430SAlexey Kardashevskiy long ret; 1483b5926430SAlexey Kardashevskiy 1484b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 1485b5926430SAlexey Kardashevskiy 1486b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1487b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 1488b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 1489b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 1490b5926430SAlexey Kardashevskiy if (ret) 1491b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 1492b5926430SAlexey Kardashevskiy else 1493ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 1494b5926430SAlexey Kardashevskiy 1495b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 1496b5926430SAlexey Kardashevskiy 1497b5926430SAlexey Kardashevskiy return ret; 1498b5926430SAlexey Kardashevskiy } 1499b5926430SAlexey Kardashevskiy 1500f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15010bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 150200547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 150300547193SAlexey Kardashevskiy { 150400547193SAlexey Kardashevskiy unsigned long bytes = 0; 150500547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 150600547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 150700547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 150800547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 150900547193SAlexey Kardashevskiy unsigned long direct_table_size; 151000547193SAlexey Kardashevskiy 151100547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 151200547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 151300547193SAlexey Kardashevskiy return 0; 151400547193SAlexey Kardashevskiy 151500547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 151600547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 151700547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 151800547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 151900547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 152000547193SAlexey Kardashevskiy 152100547193SAlexey Kardashevskiy for ( ; levels; --levels) { 1522b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 152300547193SAlexey Kardashevskiy 152400547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 152500547193SAlexey Kardashevskiy tce_table_size <<= 3; 1526e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 1527e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 152800547193SAlexey Kardashevskiy } 152900547193SAlexey Kardashevskiy 1530090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 1531090bad39SAlexey Kardashevskiy } 1532090bad39SAlexey Kardashevskiy 1533090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 1534090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 1535090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1536090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 1537090bad39SAlexey Kardashevskiy { 153811f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 1539090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 154011f5acceSAlexey Kardashevskiy 154111f5acceSAlexey Kardashevskiy if (!ret) 154211f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 154311f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 154411f5acceSAlexey Kardashevskiy return ret; 154500547193SAlexey Kardashevskiy } 154600547193SAlexey Kardashevskiy 1547e3417faeSOliver O'Halloran static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 1548e3417faeSOliver O'Halloran { 1549e3417faeSOliver O'Halloran struct pci_dev *dev; 1550e3417faeSOliver O'Halloran 1551e3417faeSOliver O'Halloran list_for_each_entry(dev, &bus->devices, bus_list) { 1552e3417faeSOliver O'Halloran set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1553e3417faeSOliver O'Halloran dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1554e3417faeSOliver O'Halloran 1555e3417faeSOliver O'Halloran if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1556e3417faeSOliver O'Halloran pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1557e3417faeSOliver O'Halloran } 1558e3417faeSOliver O'Halloran } 1559e3417faeSOliver O'Halloran 15609d67c943SAlexey Kardashevskiy static long pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 1561cd15b048SBenjamin Herrenschmidt { 1562f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1563f87a8864SAlexey Kardashevskiy table_group); 156446d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 156546d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 1566cd15b048SBenjamin Herrenschmidt 1567a9409044SAlexey Kardashevskiy /* 1568a9409044SAlexey Kardashevskiy * iommu_ops transfers the ownership per a device and we mode 1569a9409044SAlexey Kardashevskiy * the group ownership with the first device in the group. 1570a9409044SAlexey Kardashevskiy */ 1571a9409044SAlexey Kardashevskiy if (!tbl) 1572a9409044SAlexey Kardashevskiy return 0; 1573a9409044SAlexey Kardashevskiy 1574f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 157546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1576db08e1d5SAlexey Kardashevskiy if (pe->pbus) 15775eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 15785636427dSAlexey Kardashevskiy else if (pe->pdev) 15795636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 1580e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 15819d67c943SAlexey Kardashevskiy 15829d67c943SAlexey Kardashevskiy return 0; 1583cd15b048SBenjamin Herrenschmidt } 1584cd15b048SBenjamin Herrenschmidt 1585f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 1586f87a8864SAlexey Kardashevskiy { 1587f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1588f87a8864SAlexey Kardashevskiy table_group); 1589f87a8864SAlexey Kardashevskiy 1590a9409044SAlexey Kardashevskiy /* See the comment about iommu_ops above */ 1591a9409044SAlexey Kardashevskiy if (pe->table_group.tables[0]) 1592a9409044SAlexey Kardashevskiy return; 159346d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 1594db08e1d5SAlexey Kardashevskiy if (pe->pbus) 15955eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 1596f87a8864SAlexey Kardashevskiy } 1597f87a8864SAlexey Kardashevskiy 1598f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 159900547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 1600090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 16014793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 16024793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 1603f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 1604f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 1605f87a8864SAlexey Kardashevskiy }; 1606f87a8864SAlexey Kardashevskiy #endif 1607f87a8864SAlexey Kardashevskiy 160837b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1609373f5657SGavin Shan struct pnv_ioda_pe *pe) 1610373f5657SGavin Shan { 1611373f5657SGavin Shan int64_t rc; 1612373f5657SGavin Shan 1613f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 1614f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 1615f87a8864SAlexey Kardashevskiy 1616373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1617373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1618aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 1619373f5657SGavin Shan 1620e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 16214793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 16224793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 16234793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 16244793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 16254793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 16267ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 1627e5aad1e6SAlexey Kardashevskiy 162846d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 1629801846d1SGavin Shan if (rc) 163046d3e1e1SAlexey Kardashevskiy return; 163146d3e1e1SAlexey Kardashevskiy 16329b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 16339b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 16349b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 16359b9408c5SOliver O'Halloran pe->pe_number); 16369b9408c5SOliver O'Halloran #endif 163701e12629SOliver O'Halloran pe->dma_setup_done = true; 1638373f5657SGavin Shan } 1639373f5657SGavin Shan 1640c325712bSCédric Le Goater /* 1641c325712bSCédric Le Goater * Called from KVM in real mode to EOI passthru interrupts. The ICP 1642c325712bSCédric Le Goater * EOI is handled directly in KVM in kvmppc_deliver_irq_passthru(). 1643c325712bSCédric Le Goater * 1644c325712bSCédric Le Goater * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call 1645c325712bSCédric Le Goater * needs an HW IRQ number mapped in the XICS IRQ domain. The HW IRQ 1646c325712bSCédric Le Goater * numbers of the in-the-middle MSI domain are vector numbers and it's 1647c325712bSCédric Le Goater * good enough for OPAL. Use that. 1648c325712bSCédric Le Goater */ 1649c325712bSCédric Le Goater int64_t pnv_opal_pci_msi_eoi(struct irq_data *d) 1650137436c9SGavin Shan { 1651c325712bSCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data); 1652c325712bSCédric Le Goater struct pnv_phb *phb = hose->private_data; 1653137436c9SGavin Shan 1654c325712bSCédric Le Goater return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq); 16554ee11c1aSSuresh Warrier } 16564ee11c1aSSuresh Warrier 16575cd69651SCédric Le Goater /* 16585cd69651SCédric Le Goater * The IRQ data is mapped in the XICS domain, with OPAL HW IRQ numbers 16595cd69651SCédric Le Goater */ 16604ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 16614ee11c1aSSuresh Warrier { 16624ee11c1aSSuresh Warrier int64_t rc; 16634ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 16645cd69651SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 16655cd69651SCédric Le Goater struct pnv_phb *phb = hose->private_data; 16664ee11c1aSSuresh Warrier 16675cd69651SCédric Le Goater rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1668137436c9SGavin Shan WARN_ON_ONCE(rc); 1669137436c9SGavin Shan 1670137436c9SGavin Shan icp_native_eoi(d); 1671137436c9SGavin Shan } 1672137436c9SGavin Shan 16735cd69651SCédric Le Goater /* P8/CXL only */ 1674f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 1675fd9a1c26SIan Munsie { 1676fd9a1c26SIan Munsie struct irq_data *idata; 1677fd9a1c26SIan Munsie struct irq_chip *ichip; 1678fd9a1c26SIan Munsie 1679fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 1680fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 1681fd9a1c26SIan Munsie return; 1682fd9a1c26SIan Munsie 1683fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 1684fd9a1c26SIan Munsie /* 1685fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 1686fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 1687fd9a1c26SIan Munsie */ 1688fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 1689fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 1690fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 1691fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 1692fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 1693fd9a1c26SIan Munsie } 1694fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 16955cd69651SCédric Le Goater irq_set_chip_data(virq, phb->hose); 1696fd9a1c26SIan Munsie } 1697fd9a1c26SIan Munsie 1698ba418a02SCédric Le Goater static struct irq_chip pnv_pci_msi_irq_chip; 1699ba418a02SCédric Le Goater 17004ee11c1aSSuresh Warrier /* 17014ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 17024ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 17034ee11c1aSSuresh Warrier */ 17044ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 17054ee11c1aSSuresh Warrier { 1706f1a377f8SCédric Le Goater return chip == &pnv_pci_msi_irq_chip; 17074ee11c1aSSuresh Warrier } 17084ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 17094ee11c1aSSuresh Warrier 17102c50d7e9SCédric Le Goater static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 17112c50d7e9SCédric Le Goater unsigned int xive_num, 1712137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 1713184cd4a3SBenjamin Herrenschmidt { 1714184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 17153a1a4661SBenjamin Herrenschmidt __be32 data; 1716184cd4a3SBenjamin Herrenschmidt int rc; 1717184cd4a3SBenjamin Herrenschmidt 17182c50d7e9SCédric Le Goater dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__, 17192c50d7e9SCédric Le Goater is_64 ? "64" : "32", xive_num); 17202c50d7e9SCédric Le Goater 1721184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 1722184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 1723184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1724184cd4a3SBenjamin Herrenschmidt 1725184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 1726184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 1727184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1728184cd4a3SBenjamin Herrenschmidt 1729b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 173036074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 1731b72c1f65SBenjamin Herrenschmidt is_64 = 0; 1732b72c1f65SBenjamin Herrenschmidt 1733184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 1734184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 1735184cd4a3SBenjamin Herrenschmidt if (rc) { 1736184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 1737184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 1738184cd4a3SBenjamin Herrenschmidt return -EIO; 1739184cd4a3SBenjamin Herrenschmidt } 1740184cd4a3SBenjamin Herrenschmidt 1741184cd4a3SBenjamin Herrenschmidt if (is_64) { 17423a1a4661SBenjamin Herrenschmidt __be64 addr64; 17433a1a4661SBenjamin Herrenschmidt 1744184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 1745184cd4a3SBenjamin Herrenschmidt &addr64, &data); 1746184cd4a3SBenjamin Herrenschmidt if (rc) { 1747184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 1748184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1749184cd4a3SBenjamin Herrenschmidt return -EIO; 1750184cd4a3SBenjamin Herrenschmidt } 17513a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 17523a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 1753184cd4a3SBenjamin Herrenschmidt } else { 17543a1a4661SBenjamin Herrenschmidt __be32 addr32; 17553a1a4661SBenjamin Herrenschmidt 1756184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 1757184cd4a3SBenjamin Herrenschmidt &addr32, &data); 1758184cd4a3SBenjamin Herrenschmidt if (rc) { 1759184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 1760184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1761184cd4a3SBenjamin Herrenschmidt return -EIO; 1762184cd4a3SBenjamin Herrenschmidt } 1763184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 17643a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 1765184cd4a3SBenjamin Herrenschmidt } 17663a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 1767184cd4a3SBenjamin Herrenschmidt 17682c50d7e9SCédric Le Goater return 0; 17692c50d7e9SCédric Le Goater } 17702c50d7e9SCédric Le Goater 17710fcfe224SCédric Le Goater /* 17720fcfe224SCédric Le Goater * The msi_free() op is called before irq_domain_free_irqs_top() when 17730fcfe224SCédric Le Goater * the handler data is still available. Use that to clear the XIVE 17740fcfe224SCédric Le Goater * controller. 17750fcfe224SCédric Le Goater */ 17760fcfe224SCédric Le Goater static void pnv_msi_ops_msi_free(struct irq_domain *domain, 17770fcfe224SCédric Le Goater struct msi_domain_info *info, 17780fcfe224SCédric Le Goater unsigned int irq) 17790fcfe224SCédric Le Goater { 17800fcfe224SCédric Le Goater if (xive_enabled()) 17810fcfe224SCédric Le Goater xive_irq_free_data(irq); 17820fcfe224SCédric Le Goater } 17830fcfe224SCédric Le Goater 17840fcfe224SCédric Le Goater static struct msi_domain_ops pnv_pci_msi_domain_ops = { 17850fcfe224SCédric Le Goater .msi_free = pnv_msi_ops_msi_free, 17860fcfe224SCédric Le Goater }; 17870fcfe224SCédric Le Goater 17880fcfe224SCédric Le Goater static void pnv_msi_shutdown(struct irq_data *d) 17890fcfe224SCédric Le Goater { 17900fcfe224SCédric Le Goater d = d->parent_data; 17910fcfe224SCédric Le Goater if (d->chip->irq_shutdown) 17920fcfe224SCédric Le Goater d->chip->irq_shutdown(d); 17930fcfe224SCédric Le Goater } 17940fcfe224SCédric Le Goater 17950fcfe224SCédric Le Goater static void pnv_msi_mask(struct irq_data *d) 17960fcfe224SCédric Le Goater { 17970fcfe224SCédric Le Goater pci_msi_mask_irq(d); 17980fcfe224SCédric Le Goater irq_chip_mask_parent(d); 17990fcfe224SCédric Le Goater } 18000fcfe224SCédric Le Goater 18010fcfe224SCédric Le Goater static void pnv_msi_unmask(struct irq_data *d) 18020fcfe224SCédric Le Goater { 18030fcfe224SCédric Le Goater pci_msi_unmask_irq(d); 18040fcfe224SCédric Le Goater irq_chip_unmask_parent(d); 18050fcfe224SCédric Le Goater } 18060fcfe224SCédric Le Goater 18070fcfe224SCédric Le Goater static struct irq_chip pnv_pci_msi_irq_chip = { 18080fcfe224SCédric Le Goater .name = "PNV-PCI-MSI", 18090fcfe224SCédric Le Goater .irq_shutdown = pnv_msi_shutdown, 18100fcfe224SCédric Le Goater .irq_mask = pnv_msi_mask, 18110fcfe224SCédric Le Goater .irq_unmask = pnv_msi_unmask, 18120fcfe224SCédric Le Goater .irq_eoi = irq_chip_eoi_parent, 18130fcfe224SCédric Le Goater }; 18140fcfe224SCédric Le Goater 18150fcfe224SCédric Le Goater static struct msi_domain_info pnv_msi_domain_info = { 18160fcfe224SCédric Le Goater .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 18170fcfe224SCédric Le Goater MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), 18180fcfe224SCédric Le Goater .ops = &pnv_pci_msi_domain_ops, 18190fcfe224SCédric Le Goater .chip = &pnv_pci_msi_irq_chip, 18200fcfe224SCédric Le Goater }; 18210fcfe224SCédric Le Goater 18220fcfe224SCédric Le Goater static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg) 18230fcfe224SCédric Le Goater { 18240fcfe224SCédric Le Goater struct msi_desc *entry = irq_data_get_msi_desc(d); 18250fcfe224SCédric Le Goater struct pci_dev *pdev = msi_desc_to_pci_dev(entry); 18260fcfe224SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 18270fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 18280fcfe224SCédric Le Goater int rc; 18290fcfe224SCédric Le Goater 18300fcfe224SCédric Le Goater rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq, 1831e58f2259SThomas Gleixner entry->pci.msi_attrib.is_64, msg); 18320fcfe224SCédric Le Goater if (rc) 18330fcfe224SCédric Le Goater dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n", 1834e58f2259SThomas Gleixner entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc); 18350fcfe224SCédric Le Goater } 18360fcfe224SCédric Le Goater 1837bbb25af8SCédric Le Goater /* 1838bbb25af8SCédric Le Goater * The IRQ data is mapped in the MSI domain in which HW IRQ numbers 1839bbb25af8SCédric Le Goater * correspond to vector numbers. 1840bbb25af8SCédric Le Goater */ 1841bbb25af8SCédric Le Goater static void pnv_msi_eoi(struct irq_data *d) 1842bbb25af8SCédric Le Goater { 1843bbb25af8SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 1844bbb25af8SCédric Le Goater struct pnv_phb *phb = hose->private_data; 1845bbb25af8SCédric Le Goater 1846bbb25af8SCédric Le Goater if (phb->model == PNV_PHB_MODEL_PHB3) { 1847bbb25af8SCédric Le Goater /* 1848bbb25af8SCédric Le Goater * The EOI OPAL call takes an OPAL HW IRQ number but 1849bbb25af8SCédric Le Goater * since it is translated into a vector number in 1850bbb25af8SCédric Le Goater * OPAL, use that directly. 1851bbb25af8SCédric Le Goater */ 1852bbb25af8SCédric Le Goater WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq)); 1853bbb25af8SCédric Le Goater } 1854bbb25af8SCédric Le Goater 1855bbb25af8SCédric Le Goater irq_chip_eoi_parent(d); 1856bbb25af8SCédric Le Goater } 1857bbb25af8SCédric Le Goater 18580fcfe224SCédric Le Goater static struct irq_chip pnv_msi_irq_chip = { 18590fcfe224SCédric Le Goater .name = "PNV-MSI", 18600fcfe224SCédric Le Goater .irq_shutdown = pnv_msi_shutdown, 18610fcfe224SCédric Le Goater .irq_mask = irq_chip_mask_parent, 18620fcfe224SCédric Le Goater .irq_unmask = irq_chip_unmask_parent, 1863bbb25af8SCédric Le Goater .irq_eoi = pnv_msi_eoi, 18640fcfe224SCédric Le Goater .irq_set_affinity = irq_chip_set_affinity_parent, 18650fcfe224SCédric Le Goater .irq_compose_msi_msg = pnv_msi_compose_msg, 18660fcfe224SCédric Le Goater }; 18670fcfe224SCédric Le Goater 18680fcfe224SCédric Le Goater static int pnv_irq_parent_domain_alloc(struct irq_domain *domain, 18690fcfe224SCédric Le Goater unsigned int virq, int hwirq) 18700fcfe224SCédric Le Goater { 18710fcfe224SCédric Le Goater struct irq_fwspec parent_fwspec; 18720fcfe224SCédric Le Goater int ret; 18730fcfe224SCédric Le Goater 18740fcfe224SCédric Le Goater parent_fwspec.fwnode = domain->parent->fwnode; 18750fcfe224SCédric Le Goater parent_fwspec.param_count = 2; 18760fcfe224SCédric Le Goater parent_fwspec.param[0] = hwirq; 18770fcfe224SCédric Le Goater parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING; 18780fcfe224SCédric Le Goater 18790fcfe224SCédric Le Goater ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); 18800fcfe224SCédric Le Goater if (ret) 18810fcfe224SCédric Le Goater return ret; 18820fcfe224SCédric Le Goater 18830fcfe224SCédric Le Goater return 0; 18840fcfe224SCédric Le Goater } 18850fcfe224SCédric Le Goater 18860fcfe224SCédric Le Goater static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 18870fcfe224SCédric Le Goater unsigned int nr_irqs, void *arg) 18880fcfe224SCédric Le Goater { 18890fcfe224SCédric Le Goater struct pci_controller *hose = domain->host_data; 18900fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 18910fcfe224SCédric Le Goater msi_alloc_info_t *info = arg; 18920fcfe224SCédric Le Goater struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc); 18930fcfe224SCédric Le Goater int hwirq; 18940fcfe224SCédric Le Goater int i, ret; 18950fcfe224SCédric Le Goater 18960fcfe224SCédric Le Goater hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs); 18970fcfe224SCédric Le Goater if (hwirq < 0) { 18980fcfe224SCédric Le Goater dev_warn(&pdev->dev, "failed to find a free MSI\n"); 18990fcfe224SCédric Le Goater return -ENOSPC; 19000fcfe224SCédric Le Goater } 19010fcfe224SCédric Le Goater 19020fcfe224SCédric Le Goater dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__, 19030fcfe224SCédric Le Goater hose->dn, virq, hwirq, nr_irqs); 19040fcfe224SCédric Le Goater 19050fcfe224SCédric Le Goater for (i = 0; i < nr_irqs; i++) { 19060fcfe224SCédric Le Goater ret = pnv_irq_parent_domain_alloc(domain, virq + i, 19070fcfe224SCédric Le Goater phb->msi_base + hwirq + i); 19080fcfe224SCédric Le Goater if (ret) 19090fcfe224SCédric Le Goater goto out; 19100fcfe224SCédric Le Goater 19110fcfe224SCédric Le Goater irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 19120fcfe224SCédric Le Goater &pnv_msi_irq_chip, hose); 19130fcfe224SCédric Le Goater } 19140fcfe224SCédric Le Goater 19150fcfe224SCédric Le Goater return 0; 19160fcfe224SCédric Le Goater 19170fcfe224SCédric Le Goater out: 19180fcfe224SCédric Le Goater irq_domain_free_irqs_parent(domain, virq, i - 1); 19190fcfe224SCédric Le Goater msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs); 19200fcfe224SCédric Le Goater return ret; 19210fcfe224SCédric Le Goater } 19220fcfe224SCédric Le Goater 19230fcfe224SCédric Le Goater static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq, 19240fcfe224SCédric Le Goater unsigned int nr_irqs) 19250fcfe224SCédric Le Goater { 19260fcfe224SCédric Le Goater struct irq_data *d = irq_domain_get_irq_data(domain, virq); 19270fcfe224SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 19280fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 19290fcfe224SCédric Le Goater 19300fcfe224SCédric Le Goater pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn, 19310fcfe224SCédric Le Goater virq, d->hwirq, nr_irqs); 19320fcfe224SCédric Le Goater 19330fcfe224SCédric Le Goater msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs); 19340fcfe224SCédric Le Goater /* XIVE domain is cleared through ->msi_free() */ 19350fcfe224SCédric Le Goater } 19360fcfe224SCédric Le Goater 19370fcfe224SCédric Le Goater static const struct irq_domain_ops pnv_irq_domain_ops = { 19380fcfe224SCédric Le Goater .alloc = pnv_irq_domain_alloc, 19390fcfe224SCédric Le Goater .free = pnv_irq_domain_free, 19400fcfe224SCédric Le Goater }; 19410fcfe224SCédric Le Goater 1942e5913db1SNick Child static int __init pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count) 19430fcfe224SCédric Le Goater { 19440fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 19450fcfe224SCédric Le Goater struct irq_domain *parent = irq_get_default_host(); 19460fcfe224SCédric Le Goater 19470fcfe224SCédric Le Goater hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id); 19480fcfe224SCédric Le Goater if (!hose->fwnode) 19490fcfe224SCédric Le Goater return -ENOMEM; 19500fcfe224SCédric Le Goater 19510fcfe224SCédric Le Goater hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count, 19520fcfe224SCédric Le Goater hose->fwnode, 19530fcfe224SCédric Le Goater &pnv_irq_domain_ops, hose); 19540fcfe224SCédric Le Goater if (!hose->dev_domain) { 19550fcfe224SCédric Le Goater pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n", 19560fcfe224SCédric Le Goater hose->dn, hose->global_number); 19570fcfe224SCédric Le Goater irq_domain_free_fwnode(hose->fwnode); 19580fcfe224SCédric Le Goater return -ENOMEM; 19590fcfe224SCédric Le Goater } 19600fcfe224SCédric Le Goater 19610fcfe224SCédric Le Goater hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn), 19620fcfe224SCédric Le Goater &pnv_msi_domain_info, 19630fcfe224SCédric Le Goater hose->dev_domain); 19640fcfe224SCédric Le Goater if (!hose->msi_domain) { 19650fcfe224SCédric Le Goater pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n", 19660fcfe224SCédric Le Goater hose->dn, hose->global_number); 19670fcfe224SCédric Le Goater irq_domain_free_fwnode(hose->fwnode); 19680fcfe224SCédric Le Goater irq_domain_remove(hose->dev_domain); 19690fcfe224SCédric Le Goater return -ENOMEM; 19700fcfe224SCédric Le Goater } 19710fcfe224SCédric Le Goater 19720fcfe224SCédric Le Goater return 0; 19730fcfe224SCédric Le Goater } 19740fcfe224SCédric Le Goater 1975e5913db1SNick Child static void __init pnv_pci_init_ioda_msis(struct pnv_phb *phb) 1976184cd4a3SBenjamin Herrenschmidt { 1977fb1b55d6SGavin Shan unsigned int count; 1978184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 1979184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 1980184cd4a3SBenjamin Herrenschmidt if (!prop) { 1981184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 1982184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 1983184cd4a3SBenjamin Herrenschmidt } 1984184cd4a3SBenjamin Herrenschmidt if (!prop) 1985184cd4a3SBenjamin Herrenschmidt return; 1986184cd4a3SBenjamin Herrenschmidt 1987184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 1988fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 1989fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 1990184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 1991184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 1992184cd4a3SBenjamin Herrenschmidt return; 1993184cd4a3SBenjamin Herrenschmidt } 1994fb1b55d6SGavin Shan 1995184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 1996fb1b55d6SGavin Shan count, phb->msi_base); 19970fcfe224SCédric Le Goater 19980fcfe224SCédric Le Goater pnv_msi_allocate_domains(phb->hose, count); 1999184cd4a3SBenjamin Herrenschmidt } 2000184cd4a3SBenjamin Herrenschmidt 200123e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 200223e79425SGavin Shan struct resource *res) 200311685becSGavin Shan { 200423e79425SGavin Shan struct pnv_phb *phb = pe->phb; 200511685becSGavin Shan struct pci_bus_region region; 200623e79425SGavin Shan int index; 200723e79425SGavin Shan int64_t rc; 200811685becSGavin Shan 2009e64e7105SFrederic Barrat if (!res || !res->flags || res->start > res->end || 2010e64e7105SFrederic Barrat res->flags & IORESOURCE_UNSET) 201123e79425SGavin Shan return; 201211685becSGavin Shan 201311685becSGavin Shan if (res->flags & IORESOURCE_IO) { 201411685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 201511685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 201611685becSGavin Shan index = region.start / phb->ioda.io_segsize; 201711685becSGavin Shan 201892b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 201911685becSGavin Shan region.start <= region.end) { 202011685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 202111685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 202211685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 202311685becSGavin Shan if (rc != OPAL_SUCCESS) { 20241f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 202511685becSGavin Shan __func__, rc, index, pe->pe_number); 202611685becSGavin Shan break; 202711685becSGavin Shan } 202811685becSGavin Shan 202911685becSGavin Shan region.start += phb->ioda.io_segsize; 203011685becSGavin Shan index++; 203111685becSGavin Shan } 2032027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 20335958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 203411685becSGavin Shan region.start = res->start - 203523e79425SGavin Shan phb->hose->mem_offset[0] - 203611685becSGavin Shan phb->ioda.m32_pci_base; 203711685becSGavin Shan region.end = res->end - 203823e79425SGavin Shan phb->hose->mem_offset[0] - 203911685becSGavin Shan phb->ioda.m32_pci_base; 204011685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 204111685becSGavin Shan 204292b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 204311685becSGavin Shan region.start <= region.end) { 204411685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 204511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 204611685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 204711685becSGavin Shan if (rc != OPAL_SUCCESS) { 20481f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 204911685becSGavin Shan __func__, rc, index, pe->pe_number); 205011685becSGavin Shan break; 205111685becSGavin Shan } 205211685becSGavin Shan 205311685becSGavin Shan region.start += phb->ioda.m32_segsize; 205411685becSGavin Shan index++; 205511685becSGavin Shan } 205611685becSGavin Shan } 205711685becSGavin Shan } 205823e79425SGavin Shan 205923e79425SGavin Shan /* 206023e79425SGavin Shan * This function is supposed to be called on basis of PE from top 206187c78b61SMichael Ellerman * to bottom style. So the I/O or MMIO segment assigned to 206203671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 206323e79425SGavin Shan */ 206423e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 206523e79425SGavin Shan { 206669d733e7SGavin Shan struct pci_dev *pdev; 206723e79425SGavin Shan int i; 206823e79425SGavin Shan 206923e79425SGavin Shan /* 207023e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 207123e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 207223e79425SGavin Shan * be figured out later. 207323e79425SGavin Shan */ 207423e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 207523e79425SGavin Shan 207669d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 207769d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 207869d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 207969d733e7SGavin Shan 208069d733e7SGavin Shan /* 208169d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 208269d733e7SGavin Shan * windows of the child bridges should be mapped to 208369d733e7SGavin Shan * the PE as well. 208469d733e7SGavin Shan */ 208569d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 208669d733e7SGavin Shan continue; 208769d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 208869d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 208969d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 209069d733e7SGavin Shan } 209111685becSGavin Shan } 209211685becSGavin Shan 209398b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 209498b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 209598b665daSRussell Currey { 209622ba7289SOliver O'Halloran struct pnv_phb *phb = data; 209798b665daSRussell Currey s64 ret; 209898b665daSRussell Currey 209998b665daSRussell Currey /* Retrieve the diag data from firmware */ 21005cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 21015cb1f8fdSRussell Currey phb->diag_data_size); 210298b665daSRussell Currey if (ret != OPAL_SUCCESS) 210398b665daSRussell Currey return -EIO; 210498b665daSRussell Currey 210598b665daSRussell Currey /* Print the diag data to the kernel log */ 21065cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 210798b665daSRussell Currey return 0; 210898b665daSRussell Currey } 210998b665daSRussell Currey 2110bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2111bfa2325eSYueHaibing "%llu\n"); 211298b665daSRussell Currey 211318697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 211418697d2bSOliver O'Halloran { 211518697d2bSOliver O'Halloran struct pnv_phb *phb = data; 211618697d2bSOliver O'Halloran int pe_num; 211718697d2bSOliver O'Halloran 211818697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 211918697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 212018697d2bSOliver O'Halloran 212118697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 212218697d2bSOliver O'Halloran continue; 212318697d2bSOliver O'Halloran 212418697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 212518697d2bSOliver O'Halloran pe->rid, pe->device_count, 212618697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 212718697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 212818697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 212918697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 213018697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 213118697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 213218697d2bSOliver O'Halloran } 213318697d2bSOliver O'Halloran 213418697d2bSOliver O'Halloran return 0; 213518697d2bSOliver O'Halloran } 213618697d2bSOliver O'Halloran 213718697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 213818697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 213918697d2bSOliver O'Halloran 214098b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 214198b665daSRussell Currey 214237c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 214337c367f2SGavin Shan { 214437c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 214537c367f2SGavin Shan struct pci_controller *hose, *tmp; 214637c367f2SGavin Shan struct pnv_phb *phb; 214737c367f2SGavin Shan char name[16]; 214837c367f2SGavin Shan 214937c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 215037c367f2SGavin Shan phb = hose->private_data; 215137c367f2SGavin Shan 215237c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 2153dbf77fedSAneesh Kumar K.V phb->dbgfs = debugfs_create_dir(name, arch_debugfs_dir); 215498b665daSRussell Currey 2155bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 215622ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 215718697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 215818697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 215937c367f2SGavin Shan } 216037c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 216137c367f2SGavin Shan } 216237c367f2SGavin Shan 2163db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 2164db217319SBenjamin Herrenschmidt { 2165db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 2166db217319SBenjamin Herrenschmidt struct pci_bus *child; 2167db217319SBenjamin Herrenschmidt 2168db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 2169db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 2170db217319SBenjamin Herrenschmidt return; 2171db217319SBenjamin Herrenschmidt 2172db217319SBenjamin Herrenschmidt /* 2173db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 2174db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 2175db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 2176db217319SBenjamin Herrenschmidt * fixed. 2177db217319SBenjamin Herrenschmidt */ 2178db217319SBenjamin Herrenschmidt if (dev) { 2179db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 2180db217319SBenjamin Herrenschmidt if (rc) 2181db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 2182db217319SBenjamin Herrenschmidt pci_set_master(dev); 2183db217319SBenjamin Herrenschmidt } 2184db217319SBenjamin Herrenschmidt 2185db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 2186db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 2187db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 2188db217319SBenjamin Herrenschmidt } 2189db217319SBenjamin Herrenschmidt 2190db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 2191db217319SBenjamin Herrenschmidt { 2192db217319SBenjamin Herrenschmidt struct pci_controller *hose; 2193db217319SBenjamin Herrenschmidt 2194db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 2195db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 2196db217319SBenjamin Herrenschmidt } 2197db217319SBenjamin Herrenschmidt 2198cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2199fb446ad0SGavin Shan { 220037c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 220137c367f2SGavin Shan 2202db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 2203db217319SBenjamin Herrenschmidt 2204e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2205b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 2206e9cc17d4SGavin Shan #endif 2207fb446ad0SGavin Shan } 2208fb446ad0SGavin Shan 2209271fd03aSGavin Shan /* 2210271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2211271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2212271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2213271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2214271fd03aSGavin Shan * 1MiB for memory) will be returned. 2215271fd03aSGavin Shan * 2216271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2217271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2218271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2219271fd03aSGavin Shan * resources. 2220271fd03aSGavin Shan */ 2221271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2222271fd03aSGavin Shan unsigned long type) 2223271fd03aSGavin Shan { 22245609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2225271fd03aSGavin Shan int num_pci_bridges = 0; 22265609ffddSOliver O'Halloran struct pci_dev *bridge; 2227271fd03aSGavin Shan 2228271fd03aSGavin Shan bridge = bus->self; 2229271fd03aSGavin Shan while (bridge) { 2230271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2231271fd03aSGavin Shan num_pci_bridges++; 2232271fd03aSGavin Shan if (num_pci_bridges >= 2) 2233271fd03aSGavin Shan return 1; 2234271fd03aSGavin Shan } 2235271fd03aSGavin Shan 2236271fd03aSGavin Shan bridge = bridge->bus->self; 2237271fd03aSGavin Shan } 2238271fd03aSGavin Shan 22395958d19aSBenjamin Herrenschmidt /* 22405958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 22415958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 22425958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 22435958d19aSBenjamin Herrenschmidt */ 2244b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 2245262af557SGuo Chao return phb->ioda.m64_segsize; 2246271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2247271fd03aSGavin Shan return phb->ioda.m32_segsize; 2248271fd03aSGavin Shan 2249271fd03aSGavin Shan return phb->ioda.io_segsize; 2250271fd03aSGavin Shan } 2251271fd03aSGavin Shan 225240e2a47eSGavin Shan /* 225340e2a47eSGavin Shan * We are updating root port or the upstream port of the 225440e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 225540e2a47eSGavin Shan * to accommodate the changes on required resources during 225640e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 225740e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 225840e2a47eSGavin Shan * root port. 225940e2a47eSGavin Shan */ 226040e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 226140e2a47eSGavin Shan unsigned long type) 226240e2a47eSGavin Shan { 226340e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 226440e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 226540e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 226640e2a47eSGavin Shan struct resource *r, *w; 226740e2a47eSGavin Shan bool msi_region = false; 226840e2a47eSGavin Shan int i; 226940e2a47eSGavin Shan 227040e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 227140e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 227240e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 227340e2a47eSGavin Shan return; 227440e2a47eSGavin Shan 227540e2a47eSGavin Shan /* Fixup the resources */ 227640e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 227740e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 227840e2a47eSGavin Shan if (!r->flags || !r->parent) 227940e2a47eSGavin Shan continue; 228040e2a47eSGavin Shan 228140e2a47eSGavin Shan w = NULL; 228240e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 228340e2a47eSGavin Shan w = &hose->io_resource; 22845958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 228540e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 228640e2a47eSGavin Shan phb->ioda.m64_segsize) 228740e2a47eSGavin Shan w = &hose->mem_resources[1]; 228840e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 228940e2a47eSGavin Shan w = &hose->mem_resources[0]; 229040e2a47eSGavin Shan msi_region = true; 229140e2a47eSGavin Shan } 229240e2a47eSGavin Shan 229340e2a47eSGavin Shan r->start = w->start; 229440e2a47eSGavin Shan r->end = w->end; 229540e2a47eSGavin Shan 229640e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 229740e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 229840e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 229940e2a47eSGavin Shan * 230040e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 230140e2a47eSGavin Shan * 32-bits bridge window. 230240e2a47eSGavin Shan */ 230340e2a47eSGavin Shan if (msi_region) { 230440e2a47eSGavin Shan r->end += 0x10000; 230540e2a47eSGavin Shan r->end -= 0x100000; 230640e2a47eSGavin Shan } 230740e2a47eSGavin Shan } 230840e2a47eSGavin Shan } 230940e2a47eSGavin Shan 2310dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus) 2311ccd1c191SGavin Shan { 2312ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 2313ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 2314dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 2315ccd1c191SGavin Shan 2316dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n"); 231740e2a47eSGavin Shan 2318ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 23196ae8aedfSOliver O'Halloran if (WARN_ON(list_empty(&bus->devices))) 2320ccd1c191SGavin Shan return; 2321ccd1c191SGavin Shan 2322ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 2323a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 2324ccd1c191SGavin Shan 2325ccd1c191SGavin Shan /* 2326ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 2327ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 2328ccd1c191SGavin Shan * not allocate resources again. 2329ccd1c191SGavin Shan */ 2330ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 2331ccd1c191SGavin Shan if (!pe) 2332ccd1c191SGavin Shan return; 2333ccd1c191SGavin Shan 2334ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 2335ccd1c191SGavin Shan } 2336ccd1c191SGavin Shan 233738274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 233838274637SYongji Xie { 233938274637SYongji Xie return PAGE_SIZE; 234038274637SYongji Xie } 234138274637SYongji Xie 2342184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 2343184cd4a3SBenjamin Herrenschmidt * assign a PE 2344184cd4a3SBenjamin Herrenschmidt */ 23458bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2346184cd4a3SBenjamin Herrenschmidt { 2347db1266c8SGavin Shan struct pci_dn *pdn; 2348184cd4a3SBenjamin Herrenschmidt 2349b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 23506c58b1b4SOliver O'Halloran if (!pdn || pdn->pe_number == IODA_INVALID_PE) { 23516c58b1b4SOliver O'Halloran pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); 2352c88c2a18SDaniel Axtens return false; 23536c58b1b4SOliver O'Halloran } 2354db1266c8SGavin Shan 2355c88c2a18SDaniel Axtens return true; 2356184cd4a3SBenjamin Herrenschmidt } 2357184cd4a3SBenjamin Herrenschmidt 2358c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 2359c1a2feadSFrederic Barrat { 2360c1a2feadSFrederic Barrat struct pci_dn *pdn; 2361c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 2362c1a2feadSFrederic Barrat 2363c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 2364c1a2feadSFrederic Barrat if (!pdn) 2365c1a2feadSFrederic Barrat return false; 2366c1a2feadSFrederic Barrat 2367c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 2368c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 2369c1a2feadSFrederic Barrat if (!pe) 2370c1a2feadSFrederic Barrat return false; 2371c1a2feadSFrederic Barrat } 2372c1a2feadSFrederic Barrat return true; 2373c1a2feadSFrederic Barrat } 2374c1a2feadSFrederic Barrat 237537b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 2376c5f7700bSGavin Shan { 2377c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2378c5f7700bSGavin Shan int64_t rc; 2379c5f7700bSGavin Shan 2380e17a7c0eSFrederic Barrat if (!pe->dma_setup_done) 2381c5f7700bSGavin Shan return; 2382c5f7700bSGavin Shan 2383c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2384c5f7700bSGavin Shan if (rc) 23851e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 2386c5f7700bSGavin Shan 2387c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 2388c5f7700bSGavin Shan if (pe->table_group.group) { 2389c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2390c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2391c5f7700bSGavin Shan } 2392c5f7700bSGavin Shan 2393e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2394c5f7700bSGavin Shan } 2395c5f7700bSGavin Shan 2396c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 2397c5f7700bSGavin Shan unsigned short win, 2398c5f7700bSGavin Shan unsigned int *map) 2399c5f7700bSGavin Shan { 2400c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2401c5f7700bSGavin Shan int idx; 2402c5f7700bSGavin Shan int64_t rc; 2403c5f7700bSGavin Shan 2404c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 2405c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 2406c5f7700bSGavin Shan continue; 2407c5f7700bSGavin Shan 2408c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2409c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 2410c5f7700bSGavin Shan 2411c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 24121e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 2413c5f7700bSGavin Shan rc, win, idx); 2414c5f7700bSGavin Shan 2415c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 2416c5f7700bSGavin Shan } 2417c5f7700bSGavin Shan } 2418c5f7700bSGavin Shan 2419c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 2420c5f7700bSGavin Shan { 2421c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2422c5f7700bSGavin Shan 2423*5ac129cdSJoel Stanley if (phb->type == PNV_PHB_IODA2) { 2424c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2425c5f7700bSGavin Shan phb->ioda.m32_segmap); 2426c5f7700bSGavin Shan } 2427c5f7700bSGavin Shan } 2428c5f7700bSGavin Shan 2429c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 2430c5f7700bSGavin Shan { 2431c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2432c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 2433c5f7700bSGavin Shan 2434e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n"); 2435e5500ab6SOliver O'Halloran 243680f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 2437c5f7700bSGavin Shan list_del(&pe->list); 243880f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 243980f1ff83SFrederic Barrat 2440c5f7700bSGavin Shan switch (phb->type) { 2441c5f7700bSGavin Shan case PNV_PHB_IODA2: 2442c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 2443c5f7700bSGavin Shan break; 2444f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 2445f724385fSFrederic Barrat break; 2446c5f7700bSGavin Shan default: 2447c5f7700bSGavin Shan WARN_ON(1); 2448c5f7700bSGavin Shan } 2449c5f7700bSGavin Shan 2450c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 2451c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 2452b314427aSGavin Shan 2453b314427aSGavin Shan /* Release slave PEs in the compound PE */ 2454b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 2455b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 2456b314427aSGavin Shan list_del(&slave->list); 2457b314427aSGavin Shan pnv_ioda_free_pe(slave); 2458b314427aSGavin Shan } 2459b314427aSGavin Shan } 2460b314427aSGavin Shan 24616eaed166SGavin Shan /* 24626eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 24636eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 24646eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 24656eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 24666eaed166SGavin Shan */ 2467718d249aSOliver O'Halloran if (phb->ioda.root_pe_idx == pe->pe_number) 2468718d249aSOliver O'Halloran return; 2469718d249aSOliver O'Halloran 2470c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 2471c5f7700bSGavin Shan } 2472c5f7700bSGavin Shan 2473c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 2474c5f7700bSGavin Shan { 24755609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2476c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 2477c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 2478c5f7700bSGavin Shan 247937b59ef0SOliver O'Halloran /* The VF PE state is torn down when sriov_disable() is called */ 2480c5f7700bSGavin Shan if (pdev->is_virtfn) 2481c5f7700bSGavin Shan return; 2482c5f7700bSGavin Shan 2483c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2484c5f7700bSGavin Shan return; 2485c5f7700bSGavin Shan 248637b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV 248737b59ef0SOliver O'Halloran /* 248837b59ef0SOliver O'Halloran * FIXME: Try move this to sriov_disable(). It's here since we allocate 248937b59ef0SOliver O'Halloran * the iov state at probe time since we need to fiddle with the IOV 249037b59ef0SOliver O'Halloran * resources. 249137b59ef0SOliver O'Halloran */ 249237b59ef0SOliver O'Halloran if (pdev->is_physfn) 249337b59ef0SOliver O'Halloran kfree(pdev->dev.archdata.iov_data); 249437b59ef0SOliver O'Halloran #endif 249537b59ef0SOliver O'Halloran 249629bf282dSGavin Shan /* 249729bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 249829bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 249929bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 250029bf282dSGavin Shan * device count is decreased on removing devices while failing to 250129bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 250229bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 250329bf282dSGavin Shan */ 2504c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 250529bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 250629bf282dSGavin Shan 2507c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 2508c5f7700bSGavin Shan if (pe->device_count == 0) 2509c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 2510c5f7700bSGavin Shan } 2511c5f7700bSGavin Shan 25127a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 251373ed148aSBenjamin Herrenschmidt { 25147a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 25157a8e6bbfSMichael Neuling 2516d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 251773ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 251873ed148aSBenjamin Herrenschmidt } 251973ed148aSBenjamin Herrenschmidt 2520946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 2521946743d0SOliver O'Halloran { 25225609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2523946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 2524946743d0SOliver O'Halloran 2525946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2526946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 2527946743d0SOliver O'Halloran continue; 2528946743d0SOliver O'Halloran 2529946743d0SOliver O'Halloran if (!pe->pbus) 2530946743d0SOliver O'Halloran continue; 2531946743d0SOliver O'Halloran 2532946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 2533946743d0SOliver O'Halloran pe->pbus = bus; 2534946743d0SOliver O'Halloran break; 2535946743d0SOliver O'Halloran } 2536946743d0SOliver O'Halloran } 2537946743d0SOliver O'Halloran } 2538946743d0SOliver O'Halloran 2539a9409044SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2540a9409044SAlexey Kardashevskiy static struct iommu_group *pnv_pci_device_group(struct pci_controller *hose, 2541a9409044SAlexey Kardashevskiy struct pci_dev *pdev) 2542a9409044SAlexey Kardashevskiy { 2543a9409044SAlexey Kardashevskiy struct pnv_phb *phb = hose->private_data; 2544a9409044SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 2545a9409044SAlexey Kardashevskiy 2546a9409044SAlexey Kardashevskiy if (WARN_ON(!phb)) 2547a9409044SAlexey Kardashevskiy return ERR_PTR(-ENODEV); 2548a9409044SAlexey Kardashevskiy 2549a9409044SAlexey Kardashevskiy pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 2550a9409044SAlexey Kardashevskiy if (!pe) 2551a9409044SAlexey Kardashevskiy return ERR_PTR(-ENODEV); 2552a9409044SAlexey Kardashevskiy 2553a9409044SAlexey Kardashevskiy if (!pe->table_group.group) 2554a9409044SAlexey Kardashevskiy return ERR_PTR(-ENODEV); 2555a9409044SAlexey Kardashevskiy 2556a9409044SAlexey Kardashevskiy return iommu_group_ref_get(pe->table_group.group); 2557a9409044SAlexey Kardashevskiy } 2558a9409044SAlexey Kardashevskiy #endif 2559a9409044SAlexey Kardashevskiy 256092ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 25610a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 2562946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 25632d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 256492ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 2565c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 256692ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 2567dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources, 256892ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 25697a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 2570a9409044SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2571a9409044SAlexey Kardashevskiy .device_group = pnv_pci_device_group, 2572a9409044SAlexey Kardashevskiy #endif 257392ae0353SDaniel Axtens }; 257492ae0353SDaniel Axtens 25757f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 2576c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 2577f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 25787f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 25797f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 25807f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 25817f2c39e9SFrederic Barrat }; 25827f2c39e9SFrederic Barrat 2583e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2584e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 2585184cd4a3SBenjamin Herrenschmidt { 2586184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 2587184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 25882b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 2589718d249aSOliver O'Halloran struct pnv_ioda_pe *root_pe; 2590fd141d1aSBenjamin Herrenschmidt struct resource r; 2591c681b93cSAlistair Popple const __be64 *prop64; 25923a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 2593f1b7cc3eSGavin Shan int len; 25943fa23ff8SGavin Shan unsigned int segno; 2595184cd4a3SBenjamin Herrenschmidt u64 phb_id; 2596184cd4a3SBenjamin Herrenschmidt void *aux; 2597184cd4a3SBenjamin Herrenschmidt long rc; 2598184cd4a3SBenjamin Herrenschmidt 259908a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 260008a45b32SBenjamin Herrenschmidt return; 260108a45b32SBenjamin Herrenschmidt 2602b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 2603184cd4a3SBenjamin Herrenschmidt 2604184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2605184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2606184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2607184cd4a3SBenjamin Herrenschmidt return; 2608184cd4a3SBenjamin Herrenschmidt } 2609184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 2610184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2611184cd4a3SBenjamin Herrenschmidt 2612dea6f4c6SMichael Ellerman phb = kzalloc(sizeof(*phb), GFP_KERNEL); 26138a7f97b9SMike Rapoport if (!phb) 26148a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 26158a7f97b9SMike Rapoport sizeof(*phb)); 261658d714ecSGavin Shan 261758d714ecSGavin Shan /* Allocate PCI controller */ 2618184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 261958d714ecSGavin Shan if (!phb->hose) { 2620b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 2621b7c670d6SRob Herring np); 26224421cca0SMike Rapoport memblock_free(phb, sizeof(struct pnv_phb)); 2623184cd4a3SBenjamin Herrenschmidt return; 2624184cd4a3SBenjamin Herrenschmidt } 2625184cd4a3SBenjamin Herrenschmidt 2626184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 2627f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 2628f1b7cc3eSGavin Shan if (prop32 && len == 8) { 26293a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 26303a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 2631f1b7cc3eSGavin Shan } else { 2632b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 2633184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 2634184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 2635f1b7cc3eSGavin Shan } 2636184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 2637e9cc17d4SGavin Shan phb->hub_id = hub_id; 2638184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 2639aa0c033fSGavin Shan phb->type = ioda_type; 2640781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 2641184cd4a3SBenjamin Herrenschmidt 2642cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 2643cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 2644cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 2645f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 2646aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 2647cee72d5bSBenjamin Herrenschmidt else 2648cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 2649cee72d5bSBenjamin Herrenschmidt 26505cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 26515cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 26525cb1f8fdSRussell Currey if (prop32) 26535cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 26545cb1f8fdSRussell Currey else 26555cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 26565cb1f8fdSRussell Currey 2657dea6f4c6SMichael Ellerman phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL); 26588a7f97b9SMike Rapoport if (!phb->diag_data) 26598a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 26608a7f97b9SMike Rapoport phb->diag_data_size); 26615cb1f8fdSRussell Currey 2662aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 26632f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 2664184cd4a3SBenjamin Herrenschmidt 2665aa0c033fSGavin Shan /* Get registers */ 2666fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 2667fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 2668fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 2669184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 2670184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 2671fd141d1aSBenjamin Herrenschmidt } 2672577c8c88SGavin Shan 2673184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 267492b8f137SGavin Shan phb->ioda.total_pe_num = 1; 267536954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 267636954dc7SGavin Shan if (prop32) 267792b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 267836954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 267936954dc7SGavin Shan if (prop32) 268092b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 2681262af557SGuo Chao 2682c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 2683c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 2684c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 2685c127562aSGavin Shan 2686262af557SGuo Chao /* Parse 64-bit MMIO range */ 2687262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 2688262af557SGuo Chao 2689184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 2690aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 2691184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 2692184cd4a3SBenjamin Herrenschmidt 269392b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 26943fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 2695184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 269692b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 2697184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 2698184cd4a3SBenjamin Herrenschmidt 2699c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 2700b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 270192a86756SAlexey Kardashevskiy sizeof(unsigned long)); 270293289d8cSGavin Shan m64map_off = size; 270393289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 2704184cd4a3SBenjamin Herrenschmidt m32map_off = size; 270592b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 2706184cd4a3SBenjamin Herrenschmidt pemap_off = size; 270792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 2708dea6f4c6SMichael Ellerman aux = kzalloc(size, GFP_KERNEL); 27098a7f97b9SMike Rapoport if (!aux) 27108a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 2711fbbefb32SOliver O'Halloran 2712184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 271393289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 2714184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 271593289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 271693289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 27173fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 271893289d8cSGavin Shan } 2719184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 272063803c39SGavin Shan 272163803c39SGavin Shan /* 272263803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 272363803c39SGavin Shan * M64 resources consumed by its child devices. To pick 272463803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 272563803c39SGavin Shan */ 272663803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 272763803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 272863803c39SGavin Shan phb->ioda.root_pe_idx = 1; 272963803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 273063803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 273163803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 273263803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 273363803c39SGavin Shan } else { 2734718d249aSOliver O'Halloran /* otherwise just allocate one */ 2735a4bc676eSOliver O'Halloran root_pe = pnv_ioda_alloc_pe(phb, 1); 2736718d249aSOliver O'Halloran phb->ioda.root_pe_idx = root_pe->pe_number; 273763803c39SGavin Shan } 2738184cd4a3SBenjamin Herrenschmidt 2739184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 2740781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 2741184cd4a3SBenjamin Herrenschmidt 2742aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 2743184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 2744184cd4a3SBenjamin Herrenschmidt window_type, 2745184cd4a3SBenjamin Herrenschmidt window_num, 2746184cd4a3SBenjamin Herrenschmidt starting_real_address, 2747184cd4a3SBenjamin Herrenschmidt starting_pci_address, 2748184cd4a3SBenjamin Herrenschmidt segment_size); 2749184cd4a3SBenjamin Herrenschmidt #endif 2750184cd4a3SBenjamin Herrenschmidt 2751262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 275292b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 2753262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 2754262af557SGuo Chao if (phb->ioda.m64_size) 2755262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 2756262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 2757262af557SGuo Chao if (phb->ioda.io_size) 2758262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 2759184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 2760184cd4a3SBenjamin Herrenschmidt 2761262af557SGuo Chao 2762184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 276349dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 276449dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 276549dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 2766184cd4a3SBenjamin Herrenschmidt 2767184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 2768184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 2769184cd4a3SBenjamin Herrenschmidt 2770c40a4210SGavin Shan /* 2771c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 2772c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 2773c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 2774c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 2775c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 2776184cd4a3SBenjamin Herrenschmidt */ 2777fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 27785d2aa710SAlistair Popple 27797f2c39e9SFrederic Barrat switch (phb->type) { 27807f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 27817f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 27827f2c39e9SFrederic Barrat break; 27837f2c39e9SFrederic Barrat default: 278492ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 2785f9f83456SAlexey Kardashevskiy } 2786ad30cb99SMichael Ellerman 278738274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 278838274637SYongji Xie 27896e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 2790965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 27915350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 2792988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 2793988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 2794ad30cb99SMichael Ellerman #endif 2795ad30cb99SMichael Ellerman 2796c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 2797184cd4a3SBenjamin Herrenschmidt 2798184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 2799d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 2800184cd4a3SBenjamin Herrenschmidt if (rc) 2801f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 2802361f2a2aSGavin Shan 28036060e9eaSAndrew Donnellan /* 28046060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 2805361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 2806361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 280745baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 2808b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 2809b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 2810b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 2811b174b4fbSOliver O'Halloran * boot. 2812361f2a2aSGavin Shan */ 2813b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 2814361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 2815cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 2816cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 2817361f2a2aSGavin Shan } 2818262af557SGuo Chao 28199e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 28209e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 2821262af557SGuo Chao hose->mem_resources[1].flags = 0; 2822fbbefb32SOliver O'Halloran 2823fbbefb32SOliver O'Halloran /* create pci_dn's for DT nodes under this PHB */ 2824fbbefb32SOliver O'Halloran pci_devs_phb_init_dynamic(hose); 2825184cd4a3SBenjamin Herrenschmidt } 2826184cd4a3SBenjamin Herrenschmidt 282767975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 2828aa0c033fSGavin Shan { 2829e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 2830aa0c033fSGavin Shan } 2831aa0c033fSGavin Shan 28327f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 28337f2c39e9SFrederic Barrat { 28347f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 28355d2aa710SAlistair Popple } 28365d2aa710SAlistair Popple 2837228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 2838228c2f41SAndrew Donnellan { 28395609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 2840228c2f41SAndrew Donnellan 2841228c2f41SAndrew Donnellan if (!machine_is(powernv)) 2842228c2f41SAndrew Donnellan return; 2843228c2f41SAndrew Donnellan 2844228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 2845228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 2846228c2f41SAndrew Donnellan } 2847228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 2848