1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 2057c8a661SMike Rapoport #include <linux/memblock.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 25e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 264793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 27184cd4a3SBenjamin Herrenschmidt 28184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 33fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 38137436c9SGavin Shan #include <asm/xics.h> 397644d581SMichael Ellerman #include <asm/debugfs.h> 40262af557SGuo Chao #include <asm/firmware.h> 4180c49c7eSIan Munsie #include <asm/pnv-pci.h> 42aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4380c49c7eSIan Munsie 44ec249dd8SMichael Neuling #include <misc/cxl-base.h> 45184cd4a3SBenjamin Herrenschmidt 46184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 47184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4844bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 49184cd4a3SBenjamin Herrenschmidt 5099451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5199451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53781a868fSWei Yang 547f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 557f2c39e9SFrederic Barrat "NPU_OCAPI" }; 56aca6913fSAlexey Kardashevskiy 577d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 586d31c2faSJoe Perches const char *fmt, ...) 596d31c2faSJoe Perches { 606d31c2faSJoe Perches struct va_format vaf; 616d31c2faSJoe Perches va_list args; 626d31c2faSJoe Perches char pfix[32]; 63184cd4a3SBenjamin Herrenschmidt 646d31c2faSJoe Perches va_start(args, fmt); 656d31c2faSJoe Perches 666d31c2faSJoe Perches vaf.fmt = fmt; 676d31c2faSJoe Perches vaf.va = &args; 686d31c2faSJoe Perches 69781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 706d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 71781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 726d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 736d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 74781a868fSWei Yang #ifdef CONFIG_PCI_IOV 75781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 76781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 77781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 78781a868fSWei Yang (pe->rid & 0xff00) >> 8, 79781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 80781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 816d31c2faSJoe Perches 821f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 836d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 846d31c2faSJoe Perches 856d31c2faSJoe Perches va_end(args); 866d31c2faSJoe Perches } 876d31c2faSJoe Perches 884e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8945baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 904e287840SThadeu Lima de Souza Cascardo 914e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 924e287840SThadeu Lima de Souza Cascardo { 934e287840SThadeu Lima de Souza Cascardo if (!str) 944e287840SThadeu Lima de Souza Cascardo return -EINVAL; 954e287840SThadeu Lima de Souza Cascardo 964e287840SThadeu Lima de Souza Cascardo while (*str) { 974e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 984e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 994e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1004e287840SThadeu Lima de Souza Cascardo break; 1014e287840SThadeu Lima de Souza Cascardo } 1024e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1034e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1044e287840SThadeu Lima de Souza Cascardo str++; 1054e287840SThadeu Lima de Souza Cascardo } 1064e287840SThadeu Lima de Souza Cascardo 1074e287840SThadeu Lima de Souza Cascardo return 0; 1084e287840SThadeu Lima de Souza Cascardo } 1094e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1104e287840SThadeu Lima de Souza Cascardo 11145baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11245baee14SGuilherme G. Piccoli { 11345baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11445baee14SGuilherme G. Piccoli return 0; 11545baee14SGuilherme G. Piccoli } 11645baee14SGuilherme G. Piccoli 11745baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11845baee14SGuilherme G. Piccoli 1195958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 120262af557SGuo Chao { 1215958d19aSBenjamin Herrenschmidt /* 1225958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1235958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1245958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1255958d19aSBenjamin Herrenschmidt * 1265958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1275958d19aSBenjamin Herrenschmidt */ 1285958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1295958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 130262af557SGuo Chao } 131262af557SGuo Chao 132b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 133b79331a5SRussell Currey { 134b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 135b79331a5SRussell Currey 136b79331a5SRussell Currey return (resource_flags & flags) == flags; 137b79331a5SRussell Currey } 138b79331a5SRussell Currey 1391e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1401e916772SGavin Shan { 141313483ddSGavin Shan s64 rc; 142313483ddSGavin Shan 1431e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1441e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1451e916772SGavin Shan 146313483ddSGavin Shan /* 147313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 148313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 149313483ddSGavin Shan * PE is already in unfrozen state. 150313483ddSGavin Shan */ 151313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 152313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 153d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1541f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 155313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 156313483ddSGavin Shan 1571e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1581e916772SGavin Shan } 1591e916772SGavin Shan 1604b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1614b82ab18SGavin Shan { 16292b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1631f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1644b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1654b82ab18SGavin Shan return; 1664b82ab18SGavin Shan } 1674b82ab18SGavin Shan 168e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1691f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1704b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1714b82ab18SGavin Shan 1721e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1734b82ab18SGavin Shan } 1744b82ab18SGavin Shan 1751e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 176184cd4a3SBenjamin Herrenschmidt { 17760964816SAndrzej Hajda long pe; 178184cd4a3SBenjamin Herrenschmidt 1799fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1809fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1811e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 182184cd4a3SBenjamin Herrenschmidt } 183184cd4a3SBenjamin Herrenschmidt 1849fcd6f4aSGavin Shan return NULL; 1859fcd6f4aSGavin Shan } 1869fcd6f4aSGavin Shan 1871e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 188184cd4a3SBenjamin Herrenschmidt { 1891e916772SGavin Shan struct pnv_phb *phb = pe->phb; 190caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 191184cd4a3SBenjamin Herrenschmidt 1921e916772SGavin Shan WARN_ON(pe->pdev); 1931e916772SGavin Shan 1941e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 195caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 196184cd4a3SBenjamin Herrenschmidt } 197184cd4a3SBenjamin Herrenschmidt 198262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 199262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 200262af557SGuo Chao { 201262af557SGuo Chao const char *desc; 202262af557SGuo Chao struct resource *r; 203262af557SGuo Chao s64 rc; 204262af557SGuo Chao 205262af557SGuo Chao /* Configure the default M64 BAR */ 206262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 207262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 208262af557SGuo Chao phb->ioda.m64_bar_idx, 209262af557SGuo Chao phb->ioda.m64_base, 210262af557SGuo Chao 0, /* unused */ 211262af557SGuo Chao phb->ioda.m64_size); 212262af557SGuo Chao if (rc != OPAL_SUCCESS) { 213262af557SGuo Chao desc = "configuring"; 214262af557SGuo Chao goto fail; 215262af557SGuo Chao } 216262af557SGuo Chao 217262af557SGuo Chao /* Enable the default M64 BAR */ 218262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 219262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 220262af557SGuo Chao phb->ioda.m64_bar_idx, 221262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 222262af557SGuo Chao if (rc != OPAL_SUCCESS) { 223262af557SGuo Chao desc = "enabling"; 224262af557SGuo Chao goto fail; 225262af557SGuo Chao } 226262af557SGuo Chao 227262af557SGuo Chao /* 22863803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22963803c39SGavin Shan * are first or last two PEs. 230262af557SGuo Chao */ 231262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23292b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23363803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23492b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23563803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 236262af557SGuo Chao else 2371f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23892b8f137SGavin Shan phb->ioda.reserved_pe_idx); 239262af557SGuo Chao 240262af557SGuo Chao return 0; 241262af557SGuo Chao 242262af557SGuo Chao fail: 243262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 244262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 245262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 246262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 247262af557SGuo Chao phb->ioda.m64_bar_idx, 248262af557SGuo Chao OPAL_DISABLE_M64); 249262af557SGuo Chao return -EIO; 250262af557SGuo Chao } 251262af557SGuo Chao 252c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25396a2f92bSGavin Shan unsigned long *pe_bitmap) 254262af557SGuo Chao { 25596a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25696a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 257262af557SGuo Chao struct resource *r; 25896a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25996a2f92bSGavin Shan int segno, i; 260262af557SGuo Chao 26196a2f92bSGavin Shan base = phb->ioda.m64_base; 26296a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26396a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26496a2f92bSGavin Shan r = &pdev->resource[i]; 2655958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 266262af557SGuo Chao continue; 267262af557SGuo Chao 26896a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 26996a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 27096a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27196a2f92bSGavin Shan if (pe_bitmap) 27296a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27396a2f92bSGavin Shan else 27496a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 275262af557SGuo Chao } 276262af557SGuo Chao } 277262af557SGuo Chao } 278262af557SGuo Chao 27999451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28099451551SGavin Shan { 28199451551SGavin Shan struct resource *r; 28299451551SGavin Shan int index; 28399451551SGavin Shan 28499451551SGavin Shan /* 28599451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28699451551SGavin Shan * there are as many M64 segments as the maximum number of 28799451551SGavin Shan * PEs, which is 128. 28899451551SGavin Shan */ 28999451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29099451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29199451551SGavin Shan int64_t rc; 29299451551SGavin Shan 29399451551SGavin Shan base = phb->ioda.m64_base + 29499451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29599451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29799451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29899451551SGavin Shan if (rc != OPAL_SUCCESS) { 2991f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30099451551SGavin Shan rc, phb->hose->global_number, index); 30199451551SGavin Shan goto fail; 30299451551SGavin Shan } 30399451551SGavin Shan 30499451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30699451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30799451551SGavin Shan if (rc != OPAL_SUCCESS) { 3081f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30999451551SGavin Shan rc, phb->hose->global_number, index); 31099451551SGavin Shan goto fail; 31199451551SGavin Shan } 31299451551SGavin Shan } 31399451551SGavin Shan 31499451551SGavin Shan /* 31563803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31663803c39SGavin Shan * are first or last two PEs. 31799451551SGavin Shan */ 31899451551SGavin Shan r = &phb->hose->mem_resources[1]; 31999451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 32063803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32199451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32263803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32399451551SGavin Shan else 3241f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32599451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32699451551SGavin Shan 32799451551SGavin Shan return 0; 32899451551SGavin Shan 32999451551SGavin Shan fail: 33099451551SGavin Shan for ( ; index >= 0; index--) 33199451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33299451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33399451551SGavin Shan 33499451551SGavin Shan return -EIO; 33599451551SGavin Shan } 33699451551SGavin Shan 337c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33896a2f92bSGavin Shan unsigned long *pe_bitmap, 33996a2f92bSGavin Shan bool all) 340262af557SGuo Chao { 341262af557SGuo Chao struct pci_dev *pdev; 34296a2f92bSGavin Shan 34396a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 344c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34596a2f92bSGavin Shan 34696a2f92bSGavin Shan if (all && pdev->subordinate) 347c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34896a2f92bSGavin Shan pe_bitmap, all); 34996a2f92bSGavin Shan } 35096a2f92bSGavin Shan } 35196a2f92bSGavin Shan 3521e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 353262af557SGuo Chao { 35426ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35526ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 356262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 357262af557SGuo Chao unsigned long size, *pe_alloc; 35826ba248dSGavin Shan int i; 359262af557SGuo Chao 360262af557SGuo Chao /* Root bus shouldn't use M64 */ 361262af557SGuo Chao if (pci_is_root_bus(bus)) 3621e916772SGavin Shan return NULL; 363262af557SGuo Chao 364262af557SGuo Chao /* Allocate bitmap */ 36592b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 366262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 367262af557SGuo Chao if (!pe_alloc) { 368262af557SGuo Chao pr_warn("%s: Out of memory !\n", 369262af557SGuo Chao __func__); 3701e916772SGavin Shan return NULL; 371262af557SGuo Chao } 372262af557SGuo Chao 37326ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 374c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 375262af557SGuo Chao 376262af557SGuo Chao /* 377262af557SGuo Chao * the current bus might not own M64 window and that's all 378262af557SGuo Chao * contributed by its child buses. For the case, we needn't 379262af557SGuo Chao * pick M64 dependent PE#. 380262af557SGuo Chao */ 38192b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 382262af557SGuo Chao kfree(pe_alloc); 3831e916772SGavin Shan return NULL; 384262af557SGuo Chao } 385262af557SGuo Chao 386262af557SGuo Chao /* 387262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 388262af557SGuo Chao * PE's list to form compound PE. 389262af557SGuo Chao */ 390262af557SGuo Chao master_pe = NULL; 391262af557SGuo Chao i = -1; 39292b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39392b8f137SGavin Shan phb->ioda.total_pe_num) { 394262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 395262af557SGuo Chao 39693289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 397262af557SGuo Chao if (!master_pe) { 398262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 399262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 400262af557SGuo Chao master_pe = pe; 401262af557SGuo Chao } else { 402262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 403262af557SGuo Chao pe->master = master_pe; 404262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 405262af557SGuo Chao } 40699451551SGavin Shan 40799451551SGavin Shan /* 40899451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40999451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 41099451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41199451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41299451551SGavin Shan * segment and PE# on P7IOC. 41399451551SGavin Shan */ 41499451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41599451551SGavin Shan int64_t rc; 41699451551SGavin Shan 41799451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41899451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41999451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 42099451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42199451551SGavin Shan if (rc != OPAL_SUCCESS) 4221f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42399451551SGavin Shan __func__, rc, phb->hose->global_number, 42499451551SGavin Shan pe->pe_number); 42599451551SGavin Shan } 426262af557SGuo Chao } 427262af557SGuo Chao 428262af557SGuo Chao kfree(pe_alloc); 4291e916772SGavin Shan return master_pe; 430262af557SGuo Chao } 431262af557SGuo Chao 432262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 433262af557SGuo Chao { 434262af557SGuo Chao struct pci_controller *hose = phb->hose; 435262af557SGuo Chao struct device_node *dn = hose->dn; 436262af557SGuo Chao struct resource *res; 437a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4380e7736c6SGavin Shan const __be32 *r; 439262af557SGuo Chao u64 pci_addr; 440262af557SGuo Chao 44199451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4421665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4431665c4a8SGavin Shan return; 4441665c4a8SGavin Shan } 4451665c4a8SGavin Shan 446e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 447262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 448262af557SGuo Chao return; 449262af557SGuo Chao } 450262af557SGuo Chao 451262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 452262af557SGuo Chao if (!r) { 453b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 454b7c670d6SRob Herring dn); 455262af557SGuo Chao return; 456262af557SGuo Chao } 457262af557SGuo Chao 458a1339fafSBenjamin Herrenschmidt /* 459a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 460a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 461a1339fafSBenjamin Herrenschmidt */ 462a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 463a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 464a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 465a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 466a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 467a1339fafSBenjamin Herrenschmidt } 468a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 469a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 470a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 471a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 472a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 473a1339fafSBenjamin Herrenschmidt } 474a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 475a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 476a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 477a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 478a1339fafSBenjamin Herrenschmidt return; 479a1339fafSBenjamin Herrenschmidt } 480a1339fafSBenjamin Herrenschmidt 481a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 482262af557SGuo Chao res = &hose->mem_resources[1]; 483e80c4e7cSGavin Shan res->name = dn->full_name; 484262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 485262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 486262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 487262af557SGuo Chao pci_addr = of_read_number(r, 2); 488262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 489262af557SGuo Chao 490262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49192b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 492262af557SGuo Chao phb->ioda.m64_base = pci_addr; 493262af557SGuo Chao 494a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 495a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 496a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 497a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 498a1339fafSBenjamin Herrenschmidt 499a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 500a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 501e9863e68SWei Yang 502262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 503a1339fafSBenjamin Herrenschmidt m64_range[1]--; 504a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 505a1339fafSBenjamin Herrenschmidt 506a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 507a1339fafSBenjamin Herrenschmidt 508a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 509a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 510a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 511a1339fafSBenjamin Herrenschmidt 512a1339fafSBenjamin Herrenschmidt /* 513a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 514a1339fafSBenjamin Herrenschmidt * the IODA2 code. 515a1339fafSBenjamin Herrenschmidt */ 51699451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51799451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51899451551SGavin Shan else 519262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 520c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 521c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 522262af557SGuo Chao } 523262af557SGuo Chao 52449dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52549dec922SGavin Shan { 52649dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52749dec922SGavin Shan struct pnv_ioda_pe *slave; 52849dec922SGavin Shan s64 rc; 52949dec922SGavin Shan 53049dec922SGavin Shan /* Fetch master PE */ 53149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53249dec922SGavin Shan pe = pe->master; 533ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 534ec8e4e9dSGavin Shan return; 535ec8e4e9dSGavin Shan 53649dec922SGavin Shan pe_no = pe->pe_number; 53749dec922SGavin Shan } 53849dec922SGavin Shan 53949dec922SGavin Shan /* Freeze master PE */ 54049dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54149dec922SGavin Shan pe_no, 54249dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54449dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54549dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54649dec922SGavin Shan return; 54749dec922SGavin Shan } 54849dec922SGavin Shan 54949dec922SGavin Shan /* Freeze slave PEs */ 55049dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55149dec922SGavin Shan return; 55249dec922SGavin Shan 55349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55549dec922SGavin Shan slave->pe_number, 55649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55749dec922SGavin Shan if (rc != OPAL_SUCCESS) 55849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55949dec922SGavin Shan __func__, rc, phb->hose->global_number, 56049dec922SGavin Shan slave->pe_number); 56149dec922SGavin Shan } 56249dec922SGavin Shan } 56349dec922SGavin Shan 564e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56549dec922SGavin Shan { 56649dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56749dec922SGavin Shan s64 rc; 56849dec922SGavin Shan 56949dec922SGavin Shan /* Find master PE */ 57049dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57249dec922SGavin Shan pe = pe->master; 57349dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57449dec922SGavin Shan pe_no = pe->pe_number; 57549dec922SGavin Shan } 57649dec922SGavin Shan 57749dec922SGavin Shan /* Clear frozen state for master PE */ 57849dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58049dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58149dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58249dec922SGavin Shan return -EIO; 58349dec922SGavin Shan } 58449dec922SGavin Shan 58549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58649dec922SGavin Shan return 0; 58749dec922SGavin Shan 58849dec922SGavin Shan /* Clear frozen state for slave PEs */ 58949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59049dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59149dec922SGavin Shan slave->pe_number, 59249dec922SGavin Shan opt); 59349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59649dec922SGavin Shan slave->pe_number); 59749dec922SGavin Shan return -EIO; 59849dec922SGavin Shan } 59949dec922SGavin Shan } 60049dec922SGavin Shan 60149dec922SGavin Shan return 0; 60249dec922SGavin Shan } 60349dec922SGavin Shan 60449dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60549dec922SGavin Shan { 60649dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 60749dec922SGavin Shan u8 fstate, state; 60849dec922SGavin Shan __be16 pcierr; 60949dec922SGavin Shan s64 rc; 61049dec922SGavin Shan 61149dec922SGavin Shan /* Sanity check on PE number */ 61292b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61349dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61449dec922SGavin Shan 61549dec922SGavin Shan /* 61649dec922SGavin Shan * Fetch the master PE and the PE instance might be 61749dec922SGavin Shan * not initialized yet. 61849dec922SGavin Shan */ 61949dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62049dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62149dec922SGavin Shan pe = pe->master; 62249dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62349dec922SGavin Shan pe_no = pe->pe_number; 62449dec922SGavin Shan } 62549dec922SGavin Shan 62649dec922SGavin Shan /* Check the master PE */ 62749dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62849dec922SGavin Shan &state, &pcierr, NULL); 62949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63049dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63149dec922SGavin Shan "PHB#%x-PE#%x state\n", 63249dec922SGavin Shan __func__, rc, 63349dec922SGavin Shan phb->hose->global_number, pe_no); 63449dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63549dec922SGavin Shan } 63649dec922SGavin Shan 63749dec922SGavin Shan /* Check the slave PE */ 63849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63949dec922SGavin Shan return state; 64049dec922SGavin Shan 64149dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64249dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64349dec922SGavin Shan slave->pe_number, 64449dec922SGavin Shan &fstate, 64549dec922SGavin Shan &pcierr, 64649dec922SGavin Shan NULL); 64749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64849dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64949dec922SGavin Shan "PHB#%x-PE#%x state\n", 65049dec922SGavin Shan __func__, rc, 65149dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65249dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65349dec922SGavin Shan } 65449dec922SGavin Shan 65549dec922SGavin Shan /* 65649dec922SGavin Shan * Override the result based on the ascending 65749dec922SGavin Shan * priority. 65849dec922SGavin Shan */ 65949dec922SGavin Shan if (fstate > state) 66049dec922SGavin Shan state = fstate; 66149dec922SGavin Shan } 66249dec922SGavin Shan 66349dec922SGavin Shan return state; 66449dec922SGavin Shan } 66549dec922SGavin Shan 666184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 667184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 668184cd4a3SBenjamin Herrenschmidt */ 669184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 670f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 671184cd4a3SBenjamin Herrenschmidt { 672184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 673184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 674b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 675184cd4a3SBenjamin Herrenschmidt 676184cd4a3SBenjamin Herrenschmidt if (!pdn) 677184cd4a3SBenjamin Herrenschmidt return NULL; 678184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 679184cd4a3SBenjamin Herrenschmidt return NULL; 680184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 681184cd4a3SBenjamin Herrenschmidt } 682184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 683184cd4a3SBenjamin Herrenschmidt 684b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 685b131a842SGavin Shan struct pnv_ioda_pe *parent, 686b131a842SGavin Shan struct pnv_ioda_pe *child, 687b131a842SGavin Shan bool is_add) 688b131a842SGavin Shan { 689b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 690b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 691b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 692b131a842SGavin Shan struct pnv_ioda_pe *slave; 693b131a842SGavin Shan long rc; 694b131a842SGavin Shan 695b131a842SGavin Shan /* Parent PE affects child PE */ 696b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 697b131a842SGavin Shan child->pe_number, op); 698b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 699b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 700b131a842SGavin Shan rc, desc); 701b131a842SGavin Shan return -ENXIO; 702b131a842SGavin Shan } 703b131a842SGavin Shan 704b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 705b131a842SGavin Shan return 0; 706b131a842SGavin Shan 707b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 708b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 709b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 710b131a842SGavin Shan slave->pe_number, op); 711b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 712b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 713b131a842SGavin Shan rc, desc); 714b131a842SGavin Shan return -ENXIO; 715b131a842SGavin Shan } 716b131a842SGavin Shan } 717b131a842SGavin Shan 718b131a842SGavin Shan return 0; 719b131a842SGavin Shan } 720b131a842SGavin Shan 721b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 722b131a842SGavin Shan struct pnv_ioda_pe *pe, 723b131a842SGavin Shan bool is_add) 724b131a842SGavin Shan { 725b131a842SGavin Shan struct pnv_ioda_pe *slave; 726781a868fSWei Yang struct pci_dev *pdev = NULL; 727b131a842SGavin Shan int ret; 728b131a842SGavin Shan 729b131a842SGavin Shan /* 730b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 731b131a842SGavin Shan * clear slave PE frozen state as well. 732b131a842SGavin Shan */ 733b131a842SGavin Shan if (is_add) { 734b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 735b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 736b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 737b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 738b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 739b131a842SGavin Shan slave->pe_number, 740b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 741b131a842SGavin Shan } 742b131a842SGavin Shan } 743b131a842SGavin Shan 744b131a842SGavin Shan /* 745b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 746b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 747b131a842SGavin Shan * originated from the PE might contribute to other 748b131a842SGavin Shan * PEs. 749b131a842SGavin Shan */ 750b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 751b131a842SGavin Shan if (ret) 752b131a842SGavin Shan return ret; 753b131a842SGavin Shan 754b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 755b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 756b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 757b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 758b131a842SGavin Shan if (ret) 759b131a842SGavin Shan return ret; 760b131a842SGavin Shan } 761b131a842SGavin Shan } 762b131a842SGavin Shan 763b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 764b131a842SGavin Shan pdev = pe->pbus->self; 765781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 766b131a842SGavin Shan pdev = pe->pdev->bus->self; 767781a868fSWei Yang #ifdef CONFIG_PCI_IOV 768781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 769283e2d8aSGavin Shan pdev = pe->parent_dev; 770781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 771b131a842SGavin Shan while (pdev) { 772b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 773b131a842SGavin Shan struct pnv_ioda_pe *parent; 774b131a842SGavin Shan 775b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 776b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 777b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 778b131a842SGavin Shan if (ret) 779b131a842SGavin Shan return ret; 780b131a842SGavin Shan } 781b131a842SGavin Shan 782b131a842SGavin Shan pdev = pdev->bus->self; 783b131a842SGavin Shan } 784b131a842SGavin Shan 785b131a842SGavin Shan return 0; 786b131a842SGavin Shan } 787b131a842SGavin Shan 788781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 789781a868fSWei Yang { 790781a868fSWei Yang struct pci_dev *parent; 791781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 792781a868fSWei Yang int64_t rc; 793781a868fSWei Yang long rid_end, rid; 794781a868fSWei Yang 795781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 796781a868fSWei Yang if (pe->pbus) { 797781a868fSWei Yang int count; 798781a868fSWei Yang 799781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 800781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 801781a868fSWei Yang parent = pe->pbus->self; 802781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 803781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 804781a868fSWei Yang else 805781a868fSWei Yang count = 1; 806781a868fSWei Yang 807781a868fSWei Yang switch(count) { 808781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 809781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 810781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 811781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 812781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 813781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 814781a868fSWei Yang default: 815781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 816781a868fSWei Yang count); 817781a868fSWei Yang /* Do an exact match only */ 818781a868fSWei Yang bcomp = OpalPciBusAll; 819781a868fSWei Yang } 820781a868fSWei Yang rid_end = pe->rid + (count << 8); 821781a868fSWei Yang } else { 82293e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 823781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 824781a868fSWei Yang parent = pe->parent_dev; 825781a868fSWei Yang else 82693e01a50SGavin Shan #endif 827781a868fSWei Yang parent = pe->pdev->bus->self; 828781a868fSWei Yang bcomp = OpalPciBusAll; 829781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 830781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 831781a868fSWei Yang rid_end = pe->rid + 1; 832781a868fSWei Yang } 833781a868fSWei Yang 834781a868fSWei Yang /* Clear the reverse map */ 835781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 836c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 837781a868fSWei Yang 838781a868fSWei Yang /* Release from all parents PELT-V */ 839781a868fSWei Yang while (parent) { 840781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 841781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 842781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 843781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 844781a868fSWei Yang /* XXX What to do in case of error ? */ 845781a868fSWei Yang } 846781a868fSWei Yang parent = parent->bus->self; 847781a868fSWei Yang } 848781a868fSWei Yang 849f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 850781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 851781a868fSWei Yang 852781a868fSWei Yang /* Disassociate PE in PELT */ 853781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 854781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 855781a868fSWei Yang if (rc) 856781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 857781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 858781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 859781a868fSWei Yang if (rc) 860781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 861781a868fSWei Yang 862781a868fSWei Yang pe->pbus = NULL; 863781a868fSWei Yang pe->pdev = NULL; 86493e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 865781a868fSWei Yang pe->parent_dev = NULL; 86693e01a50SGavin Shan #endif 867781a868fSWei Yang 868781a868fSWei Yang return 0; 869781a868fSWei Yang } 870781a868fSWei Yang 871cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 872184cd4a3SBenjamin Herrenschmidt { 873184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 874184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 875184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 876184cd4a3SBenjamin Herrenschmidt 877184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 878184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 879184cd4a3SBenjamin Herrenschmidt int count; 880184cd4a3SBenjamin Herrenschmidt 881184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 882184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 883184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 884fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 885b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 886fb446ad0SGavin Shan else 887fb446ad0SGavin Shan count = 1; 888fb446ad0SGavin Shan 889184cd4a3SBenjamin Herrenschmidt switch(count) { 890184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 891184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 892184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 893184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 894184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 895184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 896184cd4a3SBenjamin Herrenschmidt default: 897781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 898781a868fSWei Yang count); 899184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 900184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 901184cd4a3SBenjamin Herrenschmidt } 902184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 903184cd4a3SBenjamin Herrenschmidt } else { 904781a868fSWei Yang #ifdef CONFIG_PCI_IOV 905781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 906781a868fSWei Yang parent = pe->parent_dev; 907781a868fSWei Yang else 908781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 909184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 910184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 911184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 912184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 913184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 914184cd4a3SBenjamin Herrenschmidt } 915184cd4a3SBenjamin Herrenschmidt 916631ad691SGavin Shan /* 917631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 918631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 919631ad691SGavin Shan * originated from the PE might contribute to other 920631ad691SGavin Shan * PEs. 921631ad691SGavin Shan */ 922184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 923184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 924184cd4a3SBenjamin Herrenschmidt if (rc) { 925184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 926184cd4a3SBenjamin Herrenschmidt return -ENXIO; 927184cd4a3SBenjamin Herrenschmidt } 928631ad691SGavin Shan 9295d2aa710SAlistair Popple /* 9305d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9315d2aa710SAlistair Popple * configuration on them. 9325d2aa710SAlistair Popple */ 9337f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 934b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 935184cd4a3SBenjamin Herrenschmidt 936184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 937184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 938184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 939184cd4a3SBenjamin Herrenschmidt 940184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9414773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9424773f76bSGavin Shan pe->mve_number = 0; 9434773f76bSGavin Shan goto out; 9444773f76bSGavin Shan } 9454773f76bSGavin Shan 946184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9474773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9484773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9491f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 950184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 951184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 952184cd4a3SBenjamin Herrenschmidt } else { 953184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 954cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 955184cd4a3SBenjamin Herrenschmidt if (rc) { 9561f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 957184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 958184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 959184cd4a3SBenjamin Herrenschmidt } 960184cd4a3SBenjamin Herrenschmidt } 961184cd4a3SBenjamin Herrenschmidt 9624773f76bSGavin Shan out: 963184cd4a3SBenjamin Herrenschmidt return 0; 964184cd4a3SBenjamin Herrenschmidt } 965184cd4a3SBenjamin Herrenschmidt 966781a868fSWei Yang #ifdef CONFIG_PCI_IOV 967781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 968781a868fSWei Yang { 969781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 970781a868fSWei Yang int i; 971781a868fSWei Yang struct resource *res, res2; 972781a868fSWei Yang resource_size_t size; 973781a868fSWei Yang u16 num_vfs; 974781a868fSWei Yang 975781a868fSWei Yang if (!dev->is_physfn) 976781a868fSWei Yang return -EINVAL; 977781a868fSWei Yang 978781a868fSWei Yang /* 979781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 980781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 981781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 982781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 983781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 984781a868fSWei Yang * range of PEs the VFs are in. 985781a868fSWei Yang */ 986781a868fSWei Yang num_vfs = pdn->num_vfs; 987781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 988781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 989781a868fSWei Yang if (!res->flags || !res->parent) 990781a868fSWei Yang continue; 991781a868fSWei Yang 992781a868fSWei Yang /* 993781a868fSWei Yang * The actual IOV BAR range is determined by the start address 994781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 995781a868fSWei Yang * make sure that after shifting, the range will not overlap 996781a868fSWei Yang * with another device. 997781a868fSWei Yang */ 998781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 999781a868fSWei Yang res2.flags = res->flags; 1000781a868fSWei Yang res2.start = res->start + (size * offset); 1001781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 1002781a868fSWei Yang 1003781a868fSWei Yang if (res2.end > res->end) { 1004781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1005781a868fSWei Yang i, &res2, res, num_vfs, offset); 1006781a868fSWei Yang return -EBUSY; 1007781a868fSWei Yang } 1008781a868fSWei Yang } 1009781a868fSWei Yang 1010781a868fSWei Yang /* 1011d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1012d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1013d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1014d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1015d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1016d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1017781a868fSWei Yang */ 1018781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1019781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1020781a868fSWei Yang if (!res->flags || !res->parent) 1021781a868fSWei Yang continue; 1022781a868fSWei Yang 1023781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1024781a868fSWei Yang res2 = *res; 1025781a868fSWei Yang res->start += size * offset; 1026781a868fSWei Yang 102774703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 102874703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102974703cc4SWei Yang num_vfs, offset); 1030d6f934fdSAlexey Kardashevskiy 1031d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1032d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1033d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1034d6f934fdSAlexey Kardashevskiy } 1035d6f934fdSAlexey Kardashevskiy 1036781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1037d6f934fdSAlexey Kardashevskiy 1038d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1039d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1040d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1041d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1042d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1043d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1044d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1045d6f934fdSAlexey Kardashevskiy } 1046781a868fSWei Yang } 1047781a868fSWei Yang return 0; 1048781a868fSWei Yang } 1049781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1050781a868fSWei Yang 1051cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1052184cd4a3SBenjamin Herrenschmidt { 1053184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1054184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1055b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1056184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1057184cd4a3SBenjamin Herrenschmidt 1058184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1059184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1060184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1061184cd4a3SBenjamin Herrenschmidt return NULL; 1062184cd4a3SBenjamin Herrenschmidt } 1063184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1064184cd4a3SBenjamin Herrenschmidt return NULL; 1065184cd4a3SBenjamin Herrenschmidt 10661e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10671e916772SGavin Shan if (!pe) { 1068f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1069184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1070184cd4a3SBenjamin Herrenschmidt return NULL; 1071184cd4a3SBenjamin Herrenschmidt } 1072184cd4a3SBenjamin Herrenschmidt 1073184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1074184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1075184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1076184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1077184cd4a3SBenjamin Herrenschmidt * 1078184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1079184cd4a3SBenjamin Herrenschmidt */ 1080184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 10811e916772SGavin Shan pdn->pe_number = pe->pe_number; 10825d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1083184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1084184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1085184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1086184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1087184cd4a3SBenjamin Herrenschmidt 1088184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1089184cd4a3SBenjamin Herrenschmidt 1090184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1091184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10921e916772SGavin Shan pnv_ioda_free_pe(pe); 1093184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1094184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1095184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1096184cd4a3SBenjamin Herrenschmidt return NULL; 1097184cd4a3SBenjamin Herrenschmidt } 1098184cd4a3SBenjamin Herrenschmidt 10991d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 11001d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 11011d4e89cfSAlexey Kardashevskiy 1102184cd4a3SBenjamin Herrenschmidt return pe; 1103184cd4a3SBenjamin Herrenschmidt } 1104184cd4a3SBenjamin Herrenschmidt 1105184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1106184cd4a3SBenjamin Herrenschmidt { 1107184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1108184cd4a3SBenjamin Herrenschmidt 1109184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1110b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1111184cd4a3SBenjamin Herrenschmidt 1112184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1113184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1114184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1115184cd4a3SBenjamin Herrenschmidt continue; 1116184cd4a3SBenjamin Herrenschmidt } 1117ccd1c191SGavin Shan 1118ccd1c191SGavin Shan /* 1119ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1120ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1121ccd1c191SGavin Shan * again. 1122ccd1c191SGavin Shan */ 1123ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1124ccd1c191SGavin Shan continue; 1125ccd1c191SGavin Shan 1126c5f7700bSGavin Shan pe->device_count++; 1127184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1128fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1129184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1130184cd4a3SBenjamin Herrenschmidt } 1131184cd4a3SBenjamin Herrenschmidt } 1132184cd4a3SBenjamin Herrenschmidt 1133fb446ad0SGavin Shan /* 1134fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1135fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1136fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1137fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1138fb446ad0SGavin Shan */ 11391e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1140184cd4a3SBenjamin Herrenschmidt { 1141fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1142184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11431e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1144ccd1c191SGavin Shan unsigned int pe_num; 1145ccd1c191SGavin Shan 1146ccd1c191SGavin Shan /* 1147ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1148ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1149ccd1c191SGavin Shan */ 1150ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1151ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1152ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1153ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1154ccd1c191SGavin Shan return NULL; 1155ccd1c191SGavin Shan } 1156184cd4a3SBenjamin Herrenschmidt 115763803c39SGavin Shan /* PE number for root bus should have been reserved */ 115863803c39SGavin Shan if (pci_is_root_bus(bus) && 115963803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 116063803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 116163803c39SGavin Shan 1162262af557SGuo Chao /* Check if PE is determined by M64 */ 116363803c39SGavin Shan if (!pe && phb->pick_m64_pe) 11641e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1165262af557SGuo Chao 1166262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11671e916772SGavin Shan if (!pe) 11681e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1169262af557SGuo Chao 11701e916772SGavin Shan if (!pe) { 1171f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1172fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11731e916772SGavin Shan return NULL; 1174184cd4a3SBenjamin Herrenschmidt } 1175184cd4a3SBenjamin Herrenschmidt 1176262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1177184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1178184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1179184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1180b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1181184cd4a3SBenjamin Herrenschmidt 1182fb446ad0SGavin Shan if (all) 11831f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11841e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1185fb446ad0SGavin Shan else 11861f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11871e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1188184cd4a3SBenjamin Herrenschmidt 1189184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1190184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11911e916772SGavin Shan pnv_ioda_free_pe(pe); 1192184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11931e916772SGavin Shan return NULL; 1194184cd4a3SBenjamin Herrenschmidt } 1195184cd4a3SBenjamin Herrenschmidt 1196184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1197184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1198184cd4a3SBenjamin Herrenschmidt 11997ebdf956SGavin Shan /* Put PE to the list */ 12007ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 12011e916772SGavin Shan 12021e916772SGavin Shan return pe; 1203184cd4a3SBenjamin Herrenschmidt } 1204184cd4a3SBenjamin Herrenschmidt 1205b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 12065d2aa710SAlistair Popple { 1207b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1208b521549aSAlistair Popple long rid; 1209b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1210b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1211b521549aSAlistair Popple struct pci_dn *npu_pdn; 1212b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1213b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1214b521549aSAlistair Popple 1215b521549aSAlistair Popple /* 1216b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1217b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1218b521549aSAlistair Popple * which need to be assigned to four links, implying some 1219b521549aSAlistair Popple * links must share PEs. 1220b521549aSAlistair Popple * 1221b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1222b521549aSAlistair Popple * same GPU get assigned the same PE. 1223b521549aSAlistair Popple */ 1224b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 122592b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1226b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1227b521549aSAlistair Popple if (!pe->pdev) 1228b521549aSAlistair Popple continue; 1229b521549aSAlistair Popple 1230b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1231b521549aSAlistair Popple /* 1232b521549aSAlistair Popple * This device has the same peer GPU so should 1233b521549aSAlistair Popple * be assigned the same PE as the existing 1234b521549aSAlistair Popple * peer NPU. 1235b521549aSAlistair Popple */ 1236b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12371f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1238b521549aSAlistair Popple pci_dev_get(npu_pdev); 1239b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1240b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1241b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1242b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1243b521549aSAlistair Popple 1244b521549aSAlistair Popple /* Map the PE to this link */ 1245b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1246b521549aSAlistair Popple OpalPciBusAll, 1247b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1248b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1249b521549aSAlistair Popple OPAL_MAP_PE); 1250b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1251b521549aSAlistair Popple found_pe = true; 1252b521549aSAlistair Popple break; 1253b521549aSAlistair Popple } 1254b521549aSAlistair Popple } 1255b521549aSAlistair Popple 1256b521549aSAlistair Popple if (!found_pe) 1257b521549aSAlistair Popple /* 1258b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1259b521549aSAlistair Popple * one. 1260b521549aSAlistair Popple */ 1261b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1262b521549aSAlistair Popple else 1263b521549aSAlistair Popple return pe; 1264b521549aSAlistair Popple } 1265b521549aSAlistair Popple 1266b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1267b521549aSAlistair Popple { 12685d2aa710SAlistair Popple struct pci_dev *pdev; 12695d2aa710SAlistair Popple 12705d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1271b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12725d2aa710SAlistair Popple } 12735d2aa710SAlistair Popple 1274cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1275fb446ad0SGavin Shan { 1276fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1277262af557SGuo Chao struct pnv_phb *phb; 12787f2c39e9SFrederic Barrat struct pci_bus *bus; 12797f2c39e9SFrederic Barrat struct pci_dev *pdev; 1280fb446ad0SGavin Shan 1281fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1282262af557SGuo Chao phb = hose->private_data; 12837f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 128408f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 128508f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1286b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12871ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12881ab66d1fSAlistair Popple pnv_npu2_init(phb); 1289ccd1c191SGavin Shan } 12907f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_OCAPI) { 12917f2c39e9SFrederic Barrat bus = hose->bus; 12927f2c39e9SFrederic Barrat list_for_each_entry(pdev, &bus->devices, bus_list) 12937f2c39e9SFrederic Barrat pnv_ioda_setup_dev_PE(pdev); 12947f2c39e9SFrederic Barrat } 1295fb446ad0SGavin Shan } 1296fb446ad0SGavin Shan } 1297184cd4a3SBenjamin Herrenschmidt 1298a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1299ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1300781a868fSWei Yang { 1301781a868fSWei Yang struct pci_bus *bus; 1302781a868fSWei Yang struct pci_controller *hose; 1303781a868fSWei Yang struct pnv_phb *phb; 1304781a868fSWei Yang struct pci_dn *pdn; 130502639b0eSWei Yang int i, j; 1306ee8222feSWei Yang int m64_bars; 1307781a868fSWei Yang 1308781a868fSWei Yang bus = pdev->bus; 1309781a868fSWei Yang hose = pci_bus_to_host(bus); 1310781a868fSWei Yang phb = hose->private_data; 1311781a868fSWei Yang pdn = pci_get_pdn(pdev); 1312781a868fSWei Yang 1313ee8222feSWei Yang if (pdn->m64_single_mode) 1314ee8222feSWei Yang m64_bars = num_vfs; 1315ee8222feSWei Yang else 1316ee8222feSWei Yang m64_bars = 1; 1317ee8222feSWei Yang 131802639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1319ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1320ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1321781a868fSWei Yang continue; 1322781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1323ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1324ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1325ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1326781a868fSWei Yang } 1327781a868fSWei Yang 1328ee8222feSWei Yang kfree(pdn->m64_map); 1329781a868fSWei Yang return 0; 1330781a868fSWei Yang } 1331781a868fSWei Yang 133202639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1333781a868fSWei Yang { 1334781a868fSWei Yang struct pci_bus *bus; 1335781a868fSWei Yang struct pci_controller *hose; 1336781a868fSWei Yang struct pnv_phb *phb; 1337781a868fSWei Yang struct pci_dn *pdn; 1338781a868fSWei Yang unsigned int win; 1339781a868fSWei Yang struct resource *res; 134002639b0eSWei Yang int i, j; 1341781a868fSWei Yang int64_t rc; 134202639b0eSWei Yang int total_vfs; 134302639b0eSWei Yang resource_size_t size, start; 134402639b0eSWei Yang int pe_num; 1345ee8222feSWei Yang int m64_bars; 1346781a868fSWei Yang 1347781a868fSWei Yang bus = pdev->bus; 1348781a868fSWei Yang hose = pci_bus_to_host(bus); 1349781a868fSWei Yang phb = hose->private_data; 1350781a868fSWei Yang pdn = pci_get_pdn(pdev); 135102639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1352781a868fSWei Yang 1353ee8222feSWei Yang if (pdn->m64_single_mode) 1354ee8222feSWei Yang m64_bars = num_vfs; 1355ee8222feSWei Yang else 1356ee8222feSWei Yang m64_bars = 1; 135702639b0eSWei Yang 1358fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1359fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1360fb37e128SMarkus Elfring GFP_KERNEL); 1361ee8222feSWei Yang if (!pdn->m64_map) 1362ee8222feSWei Yang return -ENOMEM; 1363ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1364ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1365ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1366ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1367ee8222feSWei Yang 1368781a868fSWei Yang 1369781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1370781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1371781a868fSWei Yang if (!res->flags || !res->parent) 1372781a868fSWei Yang continue; 1373781a868fSWei Yang 1374ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1375781a868fSWei Yang do { 1376781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1377781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1378781a868fSWei Yang 1379781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1380781a868fSWei Yang goto m64_failed; 1381781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1382781a868fSWei Yang 1383ee8222feSWei Yang pdn->m64_map[j][i] = win; 138402639b0eSWei Yang 1385ee8222feSWei Yang if (pdn->m64_single_mode) { 138602639b0eSWei Yang size = pci_iov_resource_size(pdev, 138702639b0eSWei Yang PCI_IOV_RESOURCES + i); 138802639b0eSWei Yang start = res->start + size * j; 138902639b0eSWei Yang } else { 139002639b0eSWei Yang size = resource_size(res); 139102639b0eSWei Yang start = res->start; 139202639b0eSWei Yang } 1393781a868fSWei Yang 1394781a868fSWei Yang /* Map the M64 here */ 1395ee8222feSWei Yang if (pdn->m64_single_mode) { 1396be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 139702639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 139802639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1399ee8222feSWei Yang pdn->m64_map[j][i], 0); 140002639b0eSWei Yang } 140102639b0eSWei Yang 1402781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1403781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1404ee8222feSWei Yang pdn->m64_map[j][i], 140502639b0eSWei Yang start, 1406781a868fSWei Yang 0, /* unused */ 140702639b0eSWei Yang size); 140802639b0eSWei Yang 140902639b0eSWei Yang 1410781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1411781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1412781a868fSWei Yang win, rc); 1413781a868fSWei Yang goto m64_failed; 1414781a868fSWei Yang } 1415781a868fSWei Yang 1416ee8222feSWei Yang if (pdn->m64_single_mode) 1417781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1418ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 141902639b0eSWei Yang else 142002639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1421ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 142202639b0eSWei Yang 1423781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1424781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1425781a868fSWei Yang win, rc); 1426781a868fSWei Yang goto m64_failed; 1427781a868fSWei Yang } 1428781a868fSWei Yang } 142902639b0eSWei Yang } 1430781a868fSWei Yang return 0; 1431781a868fSWei Yang 1432781a868fSWei Yang m64_failed: 1433ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1434781a868fSWei Yang return -EBUSY; 1435781a868fSWei Yang } 1436781a868fSWei Yang 1437c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1438c035e37bSAlexey Kardashevskiy int num); 1439c035e37bSAlexey Kardashevskiy 1440781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1441781a868fSWei Yang { 1442781a868fSWei Yang struct iommu_table *tbl; 1443781a868fSWei Yang int64_t rc; 1444781a868fSWei Yang 1445b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1446c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1447781a868fSWei Yang if (rc) 1448781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1449781a868fSWei Yang 1450c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14510eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14520eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14530eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1454ac9a5889SAlexey Kardashevskiy } 1455e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1456781a868fSWei Yang } 1457781a868fSWei Yang 1458ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1459781a868fSWei Yang { 1460781a868fSWei Yang struct pci_bus *bus; 1461781a868fSWei Yang struct pci_controller *hose; 1462781a868fSWei Yang struct pnv_phb *phb; 1463781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1464781a868fSWei Yang struct pci_dn *pdn; 1465781a868fSWei Yang 1466781a868fSWei Yang bus = pdev->bus; 1467781a868fSWei Yang hose = pci_bus_to_host(bus); 1468781a868fSWei Yang phb = hose->private_data; 146902639b0eSWei Yang pdn = pci_get_pdn(pdev); 1470781a868fSWei Yang 1471781a868fSWei Yang if (!pdev->is_physfn) 1472781a868fSWei Yang return; 1473781a868fSWei Yang 1474781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1475781a868fSWei Yang if (pe->parent_dev != pdev) 1476781a868fSWei Yang continue; 1477781a868fSWei Yang 1478781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1479781a868fSWei Yang 1480781a868fSWei Yang /* Remove from list */ 1481781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1482781a868fSWei Yang list_del(&pe->list); 1483781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1484781a868fSWei Yang 1485781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1486781a868fSWei Yang 14871e916772SGavin Shan pnv_ioda_free_pe(pe); 1488781a868fSWei Yang } 1489781a868fSWei Yang } 1490781a868fSWei Yang 1491781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1492781a868fSWei Yang { 1493781a868fSWei Yang struct pci_bus *bus; 1494781a868fSWei Yang struct pci_controller *hose; 1495781a868fSWei Yang struct pnv_phb *phb; 14961e916772SGavin Shan struct pnv_ioda_pe *pe; 1497781a868fSWei Yang struct pci_dn *pdn; 1498be283eebSWei Yang u16 num_vfs, i; 1499781a868fSWei Yang 1500781a868fSWei Yang bus = pdev->bus; 1501781a868fSWei Yang hose = pci_bus_to_host(bus); 1502781a868fSWei Yang phb = hose->private_data; 1503781a868fSWei Yang pdn = pci_get_pdn(pdev); 1504781a868fSWei Yang num_vfs = pdn->num_vfs; 1505781a868fSWei Yang 1506781a868fSWei Yang /* Release VF PEs */ 1507ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1508781a868fSWei Yang 1509781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1510ee8222feSWei Yang if (!pdn->m64_single_mode) 1511be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1512781a868fSWei Yang 1513781a868fSWei Yang /* Release M64 windows */ 1514ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1515781a868fSWei Yang 1516781a868fSWei Yang /* Release PE numbers */ 1517be283eebSWei Yang if (pdn->m64_single_mode) { 1518be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15191e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15201e916772SGavin Shan continue; 15211e916772SGavin Shan 15221e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15231e916772SGavin Shan pnv_ioda_free_pe(pe); 1524be283eebSWei Yang } 1525be283eebSWei Yang } else 1526be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1527be283eebSWei Yang /* Releasing pe_num_map */ 1528be283eebSWei Yang kfree(pdn->pe_num_map); 1529781a868fSWei Yang } 1530781a868fSWei Yang } 1531781a868fSWei Yang 1532781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1533781a868fSWei Yang struct pnv_ioda_pe *pe); 1534781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1535781a868fSWei Yang { 1536781a868fSWei Yang struct pci_bus *bus; 1537781a868fSWei Yang struct pci_controller *hose; 1538781a868fSWei Yang struct pnv_phb *phb; 1539781a868fSWei Yang struct pnv_ioda_pe *pe; 1540781a868fSWei Yang int pe_num; 1541781a868fSWei Yang u16 vf_index; 1542781a868fSWei Yang struct pci_dn *pdn; 1543781a868fSWei Yang 1544781a868fSWei Yang bus = pdev->bus; 1545781a868fSWei Yang hose = pci_bus_to_host(bus); 1546781a868fSWei Yang phb = hose->private_data; 1547781a868fSWei Yang pdn = pci_get_pdn(pdev); 1548781a868fSWei Yang 1549781a868fSWei Yang if (!pdev->is_physfn) 1550781a868fSWei Yang return; 1551781a868fSWei Yang 1552781a868fSWei Yang /* Reserve PE for each VF */ 1553781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1554be283eebSWei Yang if (pdn->m64_single_mode) 1555be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1556be283eebSWei Yang else 1557be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1558781a868fSWei Yang 1559781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1560781a868fSWei Yang pe->pe_number = pe_num; 1561781a868fSWei Yang pe->phb = phb; 1562781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1563781a868fSWei Yang pe->pbus = NULL; 1564781a868fSWei Yang pe->parent_dev = pdev; 1565781a868fSWei Yang pe->mve_number = -1; 1566781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1567781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1568781a868fSWei Yang 15691f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1570781a868fSWei Yang hose->global_number, pdev->bus->number, 1571781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1572781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1573781a868fSWei Yang 1574781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1575781a868fSWei Yang /* XXX What do we do here ? */ 15761e916772SGavin Shan pnv_ioda_free_pe(pe); 1577781a868fSWei Yang pe->pdev = NULL; 1578781a868fSWei Yang continue; 1579781a868fSWei Yang } 1580781a868fSWei Yang 1581781a868fSWei Yang /* Put PE to the list */ 1582781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1583781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1584781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1585781a868fSWei Yang 1586781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1587781a868fSWei Yang } 1588781a868fSWei Yang } 1589781a868fSWei Yang 1590781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1591781a868fSWei Yang { 1592781a868fSWei Yang struct pci_bus *bus; 1593781a868fSWei Yang struct pci_controller *hose; 1594781a868fSWei Yang struct pnv_phb *phb; 15951e916772SGavin Shan struct pnv_ioda_pe *pe; 1596781a868fSWei Yang struct pci_dn *pdn; 1597781a868fSWei Yang int ret; 1598be283eebSWei Yang u16 i; 1599781a868fSWei Yang 1600781a868fSWei Yang bus = pdev->bus; 1601781a868fSWei Yang hose = pci_bus_to_host(bus); 1602781a868fSWei Yang phb = hose->private_data; 1603781a868fSWei Yang pdn = pci_get_pdn(pdev); 1604781a868fSWei Yang 1605781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1606b0331854SWei Yang if (!pdn->vfs_expanded) { 1607b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1608b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1609b0331854SWei Yang return -ENOSPC; 1610b0331854SWei Yang } 1611b0331854SWei Yang 1612ee8222feSWei Yang /* 1613ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1614ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1615ee8222feSWei Yang */ 1616ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1617ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1618ee8222feSWei Yang return -EBUSY; 1619ee8222feSWei Yang } 1620ee8222feSWei Yang 1621be283eebSWei Yang /* Allocating pe_num_map */ 1622be283eebSWei Yang if (pdn->m64_single_mode) 1623fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1624fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1625be283eebSWei Yang GFP_KERNEL); 1626be283eebSWei Yang else 1627be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1628be283eebSWei Yang 1629be283eebSWei Yang if (!pdn->pe_num_map) 1630be283eebSWei Yang return -ENOMEM; 1631be283eebSWei Yang 1632be283eebSWei Yang if (pdn->m64_single_mode) 1633be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1634be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1635be283eebSWei Yang 1636781a868fSWei Yang /* Calculate available PE for required VFs */ 1637be283eebSWei Yang if (pdn->m64_single_mode) { 1638be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16391e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16401e916772SGavin Shan if (!pe) { 1641be283eebSWei Yang ret = -EBUSY; 1642be283eebSWei Yang goto m64_failed; 1643be283eebSWei Yang } 16441e916772SGavin Shan 16451e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1646be283eebSWei Yang } 1647be283eebSWei Yang } else { 1648781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1649be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 165092b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1651781a868fSWei Yang 0, num_vfs, 0); 165292b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1653781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1654781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1655be283eebSWei Yang kfree(pdn->pe_num_map); 1656781a868fSWei Yang return -EBUSY; 1657781a868fSWei Yang } 1658be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1659781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1660be283eebSWei Yang } 1661be283eebSWei Yang pdn->num_vfs = num_vfs; 1662781a868fSWei Yang 1663781a868fSWei Yang /* Assign M64 window accordingly */ 166402639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1665781a868fSWei Yang if (ret) { 1666781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1667781a868fSWei Yang goto m64_failed; 1668781a868fSWei Yang } 1669781a868fSWei Yang 1670781a868fSWei Yang /* 1671781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1672781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1673781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1674781a868fSWei Yang */ 1675ee8222feSWei Yang if (!pdn->m64_single_mode) { 1676be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1677781a868fSWei Yang if (ret) 1678781a868fSWei Yang goto m64_failed; 1679781a868fSWei Yang } 168002639b0eSWei Yang } 1681781a868fSWei Yang 1682781a868fSWei Yang /* Setup VF PEs */ 1683781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1684781a868fSWei Yang 1685781a868fSWei Yang return 0; 1686781a868fSWei Yang 1687781a868fSWei Yang m64_failed: 1688be283eebSWei Yang if (pdn->m64_single_mode) { 1689be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16901e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16911e916772SGavin Shan continue; 16921e916772SGavin Shan 16931e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16941e916772SGavin Shan pnv_ioda_free_pe(pe); 1695be283eebSWei Yang } 1696be283eebSWei Yang } else 1697be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1698be283eebSWei Yang 1699be283eebSWei Yang /* Releasing pe_num_map */ 1700be283eebSWei Yang kfree(pdn->pe_num_map); 1701781a868fSWei Yang 1702781a868fSWei Yang return ret; 1703781a868fSWei Yang } 1704781a868fSWei Yang 1705988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1706a8b2f828SGavin Shan { 1707781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1708781a868fSWei Yang 1709a8b2f828SGavin Shan /* Release PCI data */ 1710a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1711a8b2f828SGavin Shan return 0; 1712a8b2f828SGavin Shan } 1713a8b2f828SGavin Shan 1714988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1715a8b2f828SGavin Shan { 1716a8b2f828SGavin Shan /* Allocate PCI data */ 1717a8b2f828SGavin Shan add_dev_pci_data(pdev); 1718781a868fSWei Yang 1719ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1720a8b2f828SGavin Shan } 1721a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1722a8b2f828SGavin Shan 1723959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1724184cd4a3SBenjamin Herrenschmidt { 1725b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1726959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1727184cd4a3SBenjamin Herrenschmidt 1728959c9bddSGavin Shan /* 1729959c9bddSGavin Shan * The function can be called while the PE# 1730959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1731959c9bddSGavin Shan * case. 1732959c9bddSGavin Shan */ 1733959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1734959c9bddSGavin Shan return; 1735184cd4a3SBenjamin Herrenschmidt 1736959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1737cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17380e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1739b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17404617082eSAlexey Kardashevskiy /* 17414617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17424617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17434617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17444617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17454617082eSAlexey Kardashevskiy */ 1746184cd4a3SBenjamin Herrenschmidt } 1747184cd4a3SBenjamin Herrenschmidt 1748a0f98629SRussell Currey static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1749a0f98629SRussell Currey { 1750a0f98629SRussell Currey unsigned short vendor = 0; 1751a0f98629SRussell Currey struct pci_dev *pdev; 1752a0f98629SRussell Currey 1753a0f98629SRussell Currey if (pe->device_count == 1) 1754a0f98629SRussell Currey return true; 1755a0f98629SRussell Currey 1756a0f98629SRussell Currey /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1757a0f98629SRussell Currey if (!pe->pbus) 1758a0f98629SRussell Currey return true; 1759a0f98629SRussell Currey 1760a0f98629SRussell Currey list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1761a0f98629SRussell Currey if (!vendor) { 1762a0f98629SRussell Currey vendor = pdev->vendor; 1763a0f98629SRussell Currey continue; 1764a0f98629SRussell Currey } 1765a0f98629SRussell Currey 1766a0f98629SRussell Currey if (pdev->vendor != vendor) 1767a0f98629SRussell Currey return false; 1768a0f98629SRussell Currey } 1769a0f98629SRussell Currey 1770a0f98629SRussell Currey return true; 1771a0f98629SRussell Currey } 1772a0f98629SRussell Currey 17738e3f1b1dSRussell Currey /* 17748e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17758e3f1b1dSRussell Currey * 17768e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17778e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17788e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17798e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17808e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17818e3f1b1dSRussell Currey * devices in TVE#0. 17828e3f1b1dSRussell Currey * 17838e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17848e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17858e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17868e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17878e3f1b1dSRussell Currey * 17888e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17898e3f1b1dSRussell Currey */ 17908e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17918e3f1b1dSRussell Currey { 17928e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17938e3f1b1dSRussell Currey struct page *table_pages; 17948e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 17958e3f1b1dSRussell Currey __be64 *tces; 17968e3f1b1dSRussell Currey s64 rc; 17978e3f1b1dSRussell Currey 17988e3f1b1dSRussell Currey /* 17998e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 18008e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 18018e3f1b1dSRussell Currey */ 18028e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 18038e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 18048e3f1b1dSRussell Currey table_size = tce_count << 3; 18058e3f1b1dSRussell Currey 18068e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 18078e3f1b1dSRussell Currey table_size = PAGE_SIZE; 18088e3f1b1dSRussell Currey 18098e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 18108e3f1b1dSRussell Currey get_order(table_size)); 18118e3f1b1dSRussell Currey if (!table_pages) 18128e3f1b1dSRussell Currey goto err; 18138e3f1b1dSRussell Currey 18148e3f1b1dSRussell Currey tces = page_address(table_pages); 18158e3f1b1dSRussell Currey if (!tces) 18168e3f1b1dSRussell Currey goto err; 18178e3f1b1dSRussell Currey 18188e3f1b1dSRussell Currey memset(tces, 0, table_size); 18198e3f1b1dSRussell Currey 18208e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18218e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18228e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18238e3f1b1dSRussell Currey } 18248e3f1b1dSRussell Currey 18258e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18268e3f1b1dSRussell Currey pe->pe_number, 18278e3f1b1dSRussell Currey /* reconfigure window 0 */ 18288e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18298e3f1b1dSRussell Currey 1, 18308e3f1b1dSRussell Currey __pa(tces), 18318e3f1b1dSRussell Currey table_size, 18328e3f1b1dSRussell Currey 1 << tce_order); 18338e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18348e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18358e3f1b1dSRussell Currey return 0; 18368e3f1b1dSRussell Currey } 18378e3f1b1dSRussell Currey err: 18388e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18398e3f1b1dSRussell Currey return -EIO; 18408e3f1b1dSRussell Currey } 18418e3f1b1dSRussell Currey 1842763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1843cd15b048SBenjamin Herrenschmidt { 1844763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1845763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1846cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1847cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1848cd15b048SBenjamin Herrenschmidt uint64_t top; 1849cd15b048SBenjamin Herrenschmidt bool bypass = false; 18508e3f1b1dSRussell Currey s64 rc; 1851cd15b048SBenjamin Herrenschmidt 1852cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1853ed7158baSIngo Molnar return -ENODEV; 1854cd15b048SBenjamin Herrenschmidt 1855cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1856cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1857cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1858cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1859cd15b048SBenjamin Herrenschmidt } 1860cd15b048SBenjamin Herrenschmidt 1861cd15b048SBenjamin Herrenschmidt if (bypass) { 1862cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 18632d9d6f6cSChristoph Hellwig set_dma_ops(&pdev->dev, &dma_nommu_ops); 1864cd15b048SBenjamin Herrenschmidt } else { 18658e3f1b1dSRussell Currey /* 18668e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18678e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18688e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18698e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18708e3f1b1dSRussell Currey */ 18718e3f1b1dSRussell Currey if (dma_mask >> 32 && 18728e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 18738e3f1b1dSRussell Currey pnv_pci_ioda_pe_single_vendor(pe) && 18748e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18758e3f1b1dSRussell Currey /* Configure the bypass mode */ 18768e3f1b1dSRussell Currey rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18778e3f1b1dSRussell Currey if (rc) 18788e3f1b1dSRussell Currey return rc; 18798e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18808e3f1b1dSRussell Currey set_dma_offset(&pdev->dev, (1ULL << 32)); 18812d9d6f6cSChristoph Hellwig set_dma_ops(&pdev->dev, &dma_nommu_ops); 1882253fd51eSAlistair Popple } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1883253fd51eSAlistair Popple /* 1884253fd51eSAlistair Popple * Fail the request if a DMA mask between 32 and 64 bits 1885253fd51eSAlistair Popple * was requested but couldn't be fulfilled. Ideally we 1886253fd51eSAlistair Popple * would do this for 64-bits but historically we have 1887253fd51eSAlistair Popple * always fallen back to 32-bits. 1888253fd51eSAlistair Popple */ 1889253fd51eSAlistair Popple return -ENOMEM; 18908e3f1b1dSRussell Currey } else { 1891cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1892cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1893cd15b048SBenjamin Herrenschmidt } 18948e3f1b1dSRussell Currey } 1895a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 18965d2aa710SAlistair Popple 18975d2aa710SAlistair Popple /* Update peer npu devices */ 1898f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 18995d2aa710SAlistair Popple 1900cd15b048SBenjamin Herrenschmidt return 0; 1901cd15b048SBenjamin Herrenschmidt } 1902cd15b048SBenjamin Herrenschmidt 190353522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1904fe7e85c6SGavin Shan { 190553522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 190653522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1907fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1908fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1909fe7e85c6SGavin Shan u64 end, mask; 1910fe7e85c6SGavin Shan 1911fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1912fe7e85c6SGavin Shan return 0; 1913fe7e85c6SGavin Shan 1914fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1915fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1916fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1917fe7e85c6SGavin Shan 1918fe7e85c6SGavin Shan 1919fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1920fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1921fe7e85c6SGavin Shan mask += mask - 1; 1922fe7e85c6SGavin Shan 1923fe7e85c6SGavin Shan return mask; 1924fe7e85c6SGavin Shan } 1925fe7e85c6SGavin Shan 1926dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1927db08e1d5SAlexey Kardashevskiy struct pci_bus *bus, 1928db08e1d5SAlexey Kardashevskiy bool add_to_group) 192974251fe2SBenjamin Herrenschmidt { 193074251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 193174251fe2SBenjamin Herrenschmidt 193274251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1933b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1934e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 1935db08e1d5SAlexey Kardashevskiy if (add_to_group) 19364617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1937dff4a39eSGavin Shan 19385c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1939db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1940db08e1d5SAlexey Kardashevskiy add_to_group); 194174251fe2SBenjamin Herrenschmidt } 194274251fe2SBenjamin Herrenschmidt } 194374251fe2SBenjamin Herrenschmidt 1944fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1945fd141d1aSBenjamin Herrenschmidt bool real_mode) 1946fd141d1aSBenjamin Herrenschmidt { 1947fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1948fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1949fd141d1aSBenjamin Herrenschmidt } 1950fd141d1aSBenjamin Herrenschmidt 1951a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1952decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19534cce9550SGavin Shan { 19540eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19550eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19560eaf4defSAlexey Kardashevskiy next); 19570eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1958b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1959fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19604cce9550SGavin Shan unsigned long start, end, inc; 19614cce9550SGavin Shan 1962decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1963decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1964decbda25SAlexey Kardashevskiy npages - 1); 19654cce9550SGavin Shan 19664cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19674cce9550SGavin Shan start |= (1ull << 63); 19684cce9550SGavin Shan end |= (1ull << 63); 19694cce9550SGavin Shan inc = 16; 19704cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19714cce9550SGavin Shan 19724cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19734cce9550SGavin Shan while (start <= end) { 19748e0a1611SAlexey Kardashevskiy if (rm) 1975001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19768e0a1611SAlexey Kardashevskiy else 1977001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1978001ff2eeSMichael Ellerman 19794cce9550SGavin Shan start += inc; 19804cce9550SGavin Shan } 19814cce9550SGavin Shan 19824cce9550SGavin Shan /* 19834cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19844cce9550SGavin Shan * and we don't care on free() 19854cce9550SGavin Shan */ 19864cce9550SGavin Shan } 19874cce9550SGavin Shan 1988decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1989decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1990decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 199100085f1eSKrzysztof Kozlowski unsigned long attrs) 1992decbda25SAlexey Kardashevskiy { 1993decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1994decbda25SAlexey Kardashevskiy attrs); 1995decbda25SAlexey Kardashevskiy 199608acce1cSBenjamin Herrenschmidt if (!ret) 1997a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1998decbda25SAlexey Kardashevskiy 1999decbda25SAlexey Kardashevskiy return ret; 2000decbda25SAlexey Kardashevskiy } 2001decbda25SAlexey Kardashevskiy 200205c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 200305c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 200405c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 200505c6cfb9SAlexey Kardashevskiy { 2006a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 200705c6cfb9SAlexey Kardashevskiy 200808acce1cSBenjamin Herrenschmidt if (!ret) 2009a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 201005c6cfb9SAlexey Kardashevskiy 201105c6cfb9SAlexey Kardashevskiy return ret; 201205c6cfb9SAlexey Kardashevskiy } 2013a540aa56SAlexey Kardashevskiy 2014a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 2015a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2016a540aa56SAlexey Kardashevskiy { 2017a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 2018a540aa56SAlexey Kardashevskiy 2019a540aa56SAlexey Kardashevskiy if (!ret) 2020a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 2021a540aa56SAlexey Kardashevskiy 2022a540aa56SAlexey Kardashevskiy return ret; 2023a540aa56SAlexey Kardashevskiy } 202405c6cfb9SAlexey Kardashevskiy #endif 202505c6cfb9SAlexey Kardashevskiy 2026decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 2027decbda25SAlexey Kardashevskiy long npages) 2028decbda25SAlexey Kardashevskiy { 2029decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2030decbda25SAlexey Kardashevskiy 2031a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2032decbda25SAlexey Kardashevskiy } 2033decbda25SAlexey Kardashevskiy 2034da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2035decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 203605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 203705c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 2038a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 2039090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 204005c6cfb9SAlexey Kardashevskiy #endif 2041decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 2042da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2043da004c36SAlexey Kardashevskiy }; 2044da004c36SAlexey Kardashevskiy 2045a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2046a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2047a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2048bef9253fSAlexey Kardashevskiy 20496b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20500bbcdb43SAlexey Kardashevskiy { 2051fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2052a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 20530bbcdb43SAlexey Kardashevskiy 20540bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 20550bbcdb43SAlexey Kardashevskiy if (rm) 2056001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 20570bbcdb43SAlexey Kardashevskiy else 2058001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20590bbcdb43SAlexey Kardashevskiy } 20600bbcdb43SAlexey Kardashevskiy 2061a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20625780fb04SAlexey Kardashevskiy { 20635780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2064fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2065a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20665780fb04SAlexey Kardashevskiy 20675780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2068001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20695780fb04SAlexey Kardashevskiy } 20705780fb04SAlexey Kardashevskiy 2071fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2072fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2073fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20744cce9550SGavin Shan { 20754d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20764cce9550SGavin Shan unsigned long start, end, inc; 20774cce9550SGavin Shan 20784cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2079a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2080fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20814cce9550SGavin Shan end = start; 20824cce9550SGavin Shan 20834cce9550SGavin Shan /* Figure out the start, end and step */ 2084decbda25SAlexey Kardashevskiy start |= (index << shift); 2085decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2086b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20874cce9550SGavin Shan mb(); 20884cce9550SGavin Shan 20894cce9550SGavin Shan while (start <= end) { 20908e0a1611SAlexey Kardashevskiy if (rm) 2091001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 20928e0a1611SAlexey Kardashevskiy else 2093001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 20944cce9550SGavin Shan start += inc; 20954cce9550SGavin Shan } 20964cce9550SGavin Shan } 20974cce9550SGavin Shan 2098f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2099f0228c41SBenjamin Herrenschmidt { 2100f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2101f0228c41SBenjamin Herrenschmidt 2102f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2103f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2104f0228c41SBenjamin Herrenschmidt else 2105f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2106f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2107f0228c41SBenjamin Herrenschmidt } 2108f0228c41SBenjamin Herrenschmidt 2109e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2110e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2111e57080f1SAlexey Kardashevskiy { 2112e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2113e57080f1SAlexey Kardashevskiy 2114a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2115e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2116e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2117f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2118f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2119f0228c41SBenjamin Herrenschmidt 2120616badd2SAlistair Popple /* 2121616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2122616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2123616badd2SAlistair Popple * should go via the OPAL call. 2124616badd2SAlistair Popple */ 2125616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 21260bbcdb43SAlexey Kardashevskiy /* 21270bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 21280bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 21290bbcdb43SAlexey Kardashevskiy * the entire cache for it. 21300bbcdb43SAlexey Kardashevskiy */ 2131f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21325d2aa710SAlistair Popple continue; 21335d2aa710SAlistair Popple } 2134f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2135f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 213685674868SAlexey Kardashevskiy index, npages); 2137f0228c41SBenjamin Herrenschmidt else 2138f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2139f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2140f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2141f0228c41SBenjamin Herrenschmidt index << shift, npages); 2142e57080f1SAlexey Kardashevskiy } 2143e57080f1SAlexey Kardashevskiy } 2144e57080f1SAlexey Kardashevskiy 21456b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 21466b3d12a9SAlistair Popple { 21476b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 21486b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21496b3d12a9SAlistair Popple else 21506b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 21516b3d12a9SAlistair Popple } 21526b3d12a9SAlistair Popple 2153decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2154decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2155decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 215600085f1eSKrzysztof Kozlowski unsigned long attrs) 21574cce9550SGavin Shan { 2158decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2159decbda25SAlexey Kardashevskiy attrs); 21604cce9550SGavin Shan 216108acce1cSBenjamin Herrenschmidt if (!ret) 2162decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2163decbda25SAlexey Kardashevskiy 2164decbda25SAlexey Kardashevskiy return ret; 2165decbda25SAlexey Kardashevskiy } 2166decbda25SAlexey Kardashevskiy 216705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 216805c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 216905c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 217005c6cfb9SAlexey Kardashevskiy { 2171a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 217205c6cfb9SAlexey Kardashevskiy 217308acce1cSBenjamin Herrenschmidt if (!ret) 217405c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 217505c6cfb9SAlexey Kardashevskiy 217605c6cfb9SAlexey Kardashevskiy return ret; 217705c6cfb9SAlexey Kardashevskiy } 2178a540aa56SAlexey Kardashevskiy 2179a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2180a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2181a540aa56SAlexey Kardashevskiy { 2182a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 2183a540aa56SAlexey Kardashevskiy 2184a540aa56SAlexey Kardashevskiy if (!ret) 2185a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2186a540aa56SAlexey Kardashevskiy 2187a540aa56SAlexey Kardashevskiy return ret; 2188a540aa56SAlexey Kardashevskiy } 218905c6cfb9SAlexey Kardashevskiy #endif 219005c6cfb9SAlexey Kardashevskiy 2191decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2192decbda25SAlexey Kardashevskiy long npages) 2193decbda25SAlexey Kardashevskiy { 2194decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2195decbda25SAlexey Kardashevskiy 2196decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 21974cce9550SGavin Shan } 21984cce9550SGavin Shan 2199da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2200decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 220105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 220205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2203a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 2204090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 220505c6cfb9SAlexey Kardashevskiy #endif 2206decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2207da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2208da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 2209da004c36SAlexey Kardashevskiy }; 2210da004c36SAlexey Kardashevskiy 2211801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2212801846d1SGavin Shan { 2213801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2214801846d1SGavin Shan 2215801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2216801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2217801846d1SGavin Shan */ 2218801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2219801846d1SGavin Shan return 0; 2220801846d1SGavin Shan 2221801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2222801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2223801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2224801846d1SGavin Shan *weight += 3; 2225801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2226801846d1SGavin Shan *weight += 15; 2227801846d1SGavin Shan else 2228801846d1SGavin Shan *weight += 10; 2229801846d1SGavin Shan 2230801846d1SGavin Shan return 0; 2231801846d1SGavin Shan } 2232801846d1SGavin Shan 2233801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2234801846d1SGavin Shan { 2235801846d1SGavin Shan unsigned int weight = 0; 2236801846d1SGavin Shan 2237801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2238801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2239801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2240801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2241801846d1SGavin Shan return weight; 2242801846d1SGavin Shan } 2243801846d1SGavin Shan #endif 2244801846d1SGavin Shan 2245801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2246801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2247801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2248801846d1SGavin Shan struct pci_dev *pdev; 2249801846d1SGavin Shan 2250801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2251801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2252801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2253801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2254801846d1SGavin Shan } 2255801846d1SGavin Shan 2256801846d1SGavin Shan return weight; 2257801846d1SGavin Shan } 2258801846d1SGavin Shan 2259b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 22602b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2261184cd4a3SBenjamin Herrenschmidt { 2262184cd4a3SBenjamin Herrenschmidt 2263184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2264184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22652b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22662b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2267184cd4a3SBenjamin Herrenschmidt int64_t rc; 2268184cd4a3SBenjamin Herrenschmidt void *addr; 2269184cd4a3SBenjamin Herrenschmidt 2270184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2271184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2272184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22732b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22742b923ed1SGavin Shan if (!weight) 22752b923ed1SGavin Shan return; 2276184cd4a3SBenjamin Herrenschmidt 22772b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22782b923ed1SGavin Shan &total_weight); 22792b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22802b923ed1SGavin Shan if (!segs) 22812b923ed1SGavin Shan segs = 1; 22822b923ed1SGavin Shan 22832b923ed1SGavin Shan /* 22842b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22852b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22862b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22872b923ed1SGavin Shan * is allocated successfully. 22882b923ed1SGavin Shan */ 22892b923ed1SGavin Shan do { 22902b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22912b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22922b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22932b923ed1SGavin Shan IODA_INVALID_PE) 22942b923ed1SGavin Shan avail++; 22952b923ed1SGavin Shan } 22962b923ed1SGavin Shan 22972b923ed1SGavin Shan if (avail == segs) 22982b923ed1SGavin Shan goto found; 22992b923ed1SGavin Shan } 23002b923ed1SGavin Shan } while (--segs); 23012b923ed1SGavin Shan 23022b923ed1SGavin Shan if (!segs) { 23032b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 23042b923ed1SGavin Shan return; 23052b923ed1SGavin Shan } 23062b923ed1SGavin Shan 23072b923ed1SGavin Shan found: 23080eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 230982eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 231082eae1afSAlexey Kardashevskiy return; 231182eae1afSAlexey Kardashevskiy 2312b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2313b348aa65SAlexey Kardashevskiy pe->pe_number); 23140eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2315c5773822SAlexey Kardashevskiy 2316184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 23172b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 23182b923ed1SGavin Shan weight, total_weight, base, segs); 2319184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2320acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2321acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2322184cd4a3SBenjamin Herrenschmidt 2323184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2324184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2325184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2326184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2327acce971cSGavin Shan * 2328acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2329acce971cSGavin Shan * bytes 2330184cd4a3SBenjamin Herrenschmidt */ 2331acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2332184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2333acce971cSGavin Shan get_order(tce32_segsz * segs)); 2334184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2335184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2336184cd4a3SBenjamin Herrenschmidt goto fail; 2337184cd4a3SBenjamin Herrenschmidt } 2338184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2339acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2340184cd4a3SBenjamin Herrenschmidt 2341184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2342184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2343184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2344184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2345184cd4a3SBenjamin Herrenschmidt base + i, 1, 2346acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2347acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2348184cd4a3SBenjamin Herrenschmidt if (rc) { 2349184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2350184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2351184cd4a3SBenjamin Herrenschmidt goto fail; 2352184cd4a3SBenjamin Herrenschmidt } 2353184cd4a3SBenjamin Herrenschmidt } 2354184cd4a3SBenjamin Herrenschmidt 23552b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 23562b923ed1SGavin Shan for (i = base; i < base + segs; i++) 23572b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 23582b923ed1SGavin Shan 2359184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2360acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2361acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2362acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2363184cd4a3SBenjamin Herrenschmidt 2364da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23654793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23664793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2367184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2368184cd4a3SBenjamin Herrenschmidt 2369781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 23704617082eSAlexey Kardashevskiy /* 23714617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 23724617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 23734617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 23744617082eSAlexey Kardashevskiy */ 23754617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 23764617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2377c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2378db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 237974251fe2SBenjamin Herrenschmidt 2380184cd4a3SBenjamin Herrenschmidt return; 2381184cd4a3SBenjamin Herrenschmidt fail: 2382184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2383184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2384acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23850eaf4defSAlexey Kardashevskiy if (tbl) { 23860eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2387e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23880eaf4defSAlexey Kardashevskiy } 2389184cd4a3SBenjamin Herrenschmidt } 2390184cd4a3SBenjamin Herrenschmidt 239143cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 239243cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 239343cb60abSAlexey Kardashevskiy { 239443cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 239543cb60abSAlexey Kardashevskiy table_group); 239643cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 239743cb60abSAlexey Kardashevskiy int64_t rc; 2398bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2399bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 240043cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 240143cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 240243cb60abSAlexey Kardashevskiy 24034793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 240443cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 240543cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 240643cb60abSAlexey Kardashevskiy 240743cb60abSAlexey Kardashevskiy /* 240843cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 240943cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 241043cb60abSAlexey Kardashevskiy */ 241143cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 241243cb60abSAlexey Kardashevskiy pe->pe_number, 24134793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2414bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 241543cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2416bbb845c4SAlexey Kardashevskiy size << 3, 241743cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 241843cb60abSAlexey Kardashevskiy if (rc) { 241943cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 242043cb60abSAlexey Kardashevskiy return rc; 242143cb60abSAlexey Kardashevskiy } 242243cb60abSAlexey Kardashevskiy 242343cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 242443cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2425ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 242643cb60abSAlexey Kardashevskiy 242743cb60abSAlexey Kardashevskiy return 0; 242843cb60abSAlexey Kardashevskiy } 242943cb60abSAlexey Kardashevskiy 243025529100SFrederic Barrat void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2431cd15b048SBenjamin Herrenschmidt { 2432cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2433cd15b048SBenjamin Herrenschmidt int64_t rc; 2434cd15b048SBenjamin Herrenschmidt 2435cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2436cd15b048SBenjamin Herrenschmidt if (enable) { 2437cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2438cd15b048SBenjamin Herrenschmidt 2439cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2440cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2441cd15b048SBenjamin Herrenschmidt pe->pe_number, 2442cd15b048SBenjamin Herrenschmidt window_id, 2443cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2444cd15b048SBenjamin Herrenschmidt top); 2445cd15b048SBenjamin Herrenschmidt } else { 2446cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2447cd15b048SBenjamin Herrenschmidt pe->pe_number, 2448cd15b048SBenjamin Herrenschmidt window_id, 2449cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2450cd15b048SBenjamin Herrenschmidt 0); 2451cd15b048SBenjamin Herrenschmidt } 2452cd15b048SBenjamin Herrenschmidt if (rc) 2453cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2454cd15b048SBenjamin Herrenschmidt else 2455cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2456cd15b048SBenjamin Herrenschmidt } 2457cd15b048SBenjamin Herrenschmidt 24584793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 24594793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2460090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 24614793d65dSAlexey Kardashevskiy { 24624793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 24634793d65dSAlexey Kardashevskiy table_group); 24644793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 24654793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 24664793d65dSAlexey Kardashevskiy long ret; 24674793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 24684793d65dSAlexey Kardashevskiy 24694793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24704793d65dSAlexey Kardashevskiy if (!tbl) 24714793d65dSAlexey Kardashevskiy return -ENOMEM; 24724793d65dSAlexey Kardashevskiy 247311edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 247411edf116SAlexey Kardashevskiy 24754793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24764793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 2477090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 24784793d65dSAlexey Kardashevskiy if (ret) { 2479e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24804793d65dSAlexey Kardashevskiy return ret; 24814793d65dSAlexey Kardashevskiy } 24824793d65dSAlexey Kardashevskiy 24834793d65dSAlexey Kardashevskiy *ptbl = tbl; 24844793d65dSAlexey Kardashevskiy 24854793d65dSAlexey Kardashevskiy return 0; 24864793d65dSAlexey Kardashevskiy } 24874793d65dSAlexey Kardashevskiy 248846d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 248946d3e1e1SAlexey Kardashevskiy { 249046d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 249146d3e1e1SAlexey Kardashevskiy long rc; 249246d3e1e1SAlexey Kardashevskiy 2493bb005455SNishanth Aravamudan /* 2494fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2495fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2496fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2497fa144869SNishanth Aravamudan */ 2498fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2499fa144869SNishanth Aravamudan 2500fa144869SNishanth Aravamudan /* 2501bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2502bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2503bb005455SNishanth Aravamudan * cause errors later. 2504bb005455SNishanth Aravamudan */ 2505fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2506bb005455SNishanth Aravamudan 250746d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 250846d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2509bb005455SNishanth Aravamudan window_size, 2510090bad39SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl); 251146d3e1e1SAlexey Kardashevskiy if (rc) { 251246d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 251346d3e1e1SAlexey Kardashevskiy rc); 251446d3e1e1SAlexey Kardashevskiy return rc; 251546d3e1e1SAlexey Kardashevskiy } 251646d3e1e1SAlexey Kardashevskiy 251746d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 251846d3e1e1SAlexey Kardashevskiy 251946d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 252046d3e1e1SAlexey Kardashevskiy if (rc) { 252146d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 252246d3e1e1SAlexey Kardashevskiy rc); 2523e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 252446d3e1e1SAlexey Kardashevskiy return rc; 252546d3e1e1SAlexey Kardashevskiy } 252646d3e1e1SAlexey Kardashevskiy 252746d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 252846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 252946d3e1e1SAlexey Kardashevskiy 253046d3e1e1SAlexey Kardashevskiy /* 253146d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 253246d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 253346d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 253446d3e1e1SAlexey Kardashevskiy */ 253546d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 253646d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 253746d3e1e1SAlexey Kardashevskiy 253846d3e1e1SAlexey Kardashevskiy return 0; 253946d3e1e1SAlexey Kardashevskiy } 254046d3e1e1SAlexey Kardashevskiy 2541b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2542b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2543b5926430SAlexey Kardashevskiy int num) 2544b5926430SAlexey Kardashevskiy { 2545b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2546b5926430SAlexey Kardashevskiy table_group); 2547b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2548b5926430SAlexey Kardashevskiy long ret; 2549b5926430SAlexey Kardashevskiy 2550b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2551b5926430SAlexey Kardashevskiy 2552b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2553b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2554b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2555b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2556b5926430SAlexey Kardashevskiy if (ret) 2557b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2558b5926430SAlexey Kardashevskiy else 2559ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2560b5926430SAlexey Kardashevskiy 2561b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2562b5926430SAlexey Kardashevskiy 2563b5926430SAlexey Kardashevskiy return ret; 2564b5926430SAlexey Kardashevskiy } 2565b5926430SAlexey Kardashevskiy #endif 2566b5926430SAlexey Kardashevskiy 2567f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 256800547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 256900547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 257000547193SAlexey Kardashevskiy { 257100547193SAlexey Kardashevskiy unsigned long bytes = 0; 257200547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 257300547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 257400547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 257500547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 257600547193SAlexey Kardashevskiy unsigned long direct_table_size; 257700547193SAlexey Kardashevskiy 257800547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 257900547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 258000547193SAlexey Kardashevskiy return 0; 258100547193SAlexey Kardashevskiy 258200547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 258300547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 258400547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 258500547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 258600547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 258700547193SAlexey Kardashevskiy 258800547193SAlexey Kardashevskiy for ( ; levels; --levels) { 258900547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 259000547193SAlexey Kardashevskiy 259100547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 259200547193SAlexey Kardashevskiy tce_table_size <<= 3; 2593e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2594e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 259500547193SAlexey Kardashevskiy } 259600547193SAlexey Kardashevskiy 2597090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2598090bad39SAlexey Kardashevskiy } 2599090bad39SAlexey Kardashevskiy 2600090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2601090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2602090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2603090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2604090bad39SAlexey Kardashevskiy { 2605090bad39SAlexey Kardashevskiy return pnv_pci_ioda2_create_table(table_group, 2606090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 260700547193SAlexey Kardashevskiy } 260800547193SAlexey Kardashevskiy 2609f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2610cd15b048SBenjamin Herrenschmidt { 2611f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2612f87a8864SAlexey Kardashevskiy table_group); 261346d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 261446d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2615cd15b048SBenjamin Herrenschmidt 2616f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 261746d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2618db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2619db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2620e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2621cd15b048SBenjamin Herrenschmidt } 2622cd15b048SBenjamin Herrenschmidt 2623f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2624f87a8864SAlexey Kardashevskiy { 2625f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2626f87a8864SAlexey Kardashevskiy table_group); 2627f87a8864SAlexey Kardashevskiy 262846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2629db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2630db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2631f87a8864SAlexey Kardashevskiy } 2632f87a8864SAlexey Kardashevskiy 2633f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 263400547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2635090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 26364793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 26374793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2638f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2639f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2640f87a8864SAlexey Kardashevskiy }; 2641b5cb9ab1SAlexey Kardashevskiy 2642b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2643b5cb9ab1SAlexey Kardashevskiy { 2644b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2645b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2646b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2647b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2648b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2649b5cb9ab1SAlexey Kardashevskiy 2650b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2651b5cb9ab1SAlexey Kardashevskiy return 0; 2652b5cb9ab1SAlexey Kardashevskiy 2653b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2654b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 26557f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2656b5cb9ab1SAlexey Kardashevskiy return 0; 2657b5cb9ab1SAlexey Kardashevskiy 2658b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2659b5cb9ab1SAlexey Kardashevskiy 2660b5cb9ab1SAlexey Kardashevskiy return 1; 2661b5cb9ab1SAlexey Kardashevskiy } 2662b5cb9ab1SAlexey Kardashevskiy 2663b5cb9ab1SAlexey Kardashevskiy /* 2664b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2665b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2666b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2667b5cb9ab1SAlexey Kardashevskiy */ 2668b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2669b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2670b5cb9ab1SAlexey Kardashevskiy { 2671b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2672b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2673b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2674b5cb9ab1SAlexey Kardashevskiy 2675b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2676b5cb9ab1SAlexey Kardashevskiy 2677b5cb9ab1SAlexey Kardashevskiy return npe; 2678b5cb9ab1SAlexey Kardashevskiy } 2679b5cb9ab1SAlexey Kardashevskiy 2680b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2681b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2682b5cb9ab1SAlexey Kardashevskiy { 2683d41ce7b1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2684d41ce7b1SAlexey Kardashevskiy int num2 = (num == 0) ? 1 : 0; 2685b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2686b5cb9ab1SAlexey Kardashevskiy 2687b5cb9ab1SAlexey Kardashevskiy if (ret) 2688b5cb9ab1SAlexey Kardashevskiy return ret; 2689b5cb9ab1SAlexey Kardashevskiy 2690d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2691d41ce7b1SAlexey Kardashevskiy pnv_npu_unset_window(npe, num2); 2692d41ce7b1SAlexey Kardashevskiy 2693d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_set_window(npe, num, tbl); 2694d41ce7b1SAlexey Kardashevskiy if (ret) { 2695b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2696d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2697d41ce7b1SAlexey Kardashevskiy pnv_npu_set_window(npe, num2, 2698d41ce7b1SAlexey Kardashevskiy table_group->tables[num2]); 2699d41ce7b1SAlexey Kardashevskiy } 2700b5cb9ab1SAlexey Kardashevskiy 2701b5cb9ab1SAlexey Kardashevskiy return ret; 2702b5cb9ab1SAlexey Kardashevskiy } 2703b5cb9ab1SAlexey Kardashevskiy 2704b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2705b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2706b5cb9ab1SAlexey Kardashevskiy int num) 2707b5cb9ab1SAlexey Kardashevskiy { 2708d41ce7b1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2709d41ce7b1SAlexey Kardashevskiy int num2 = (num == 0) ? 1 : 0; 2710b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2711b5cb9ab1SAlexey Kardashevskiy 2712b5cb9ab1SAlexey Kardashevskiy if (ret) 2713b5cb9ab1SAlexey Kardashevskiy return ret; 2714b5cb9ab1SAlexey Kardashevskiy 2715d41ce7b1SAlexey Kardashevskiy if (!npe->table_group.tables[num]) 2716d41ce7b1SAlexey Kardashevskiy return 0; 2717d41ce7b1SAlexey Kardashevskiy 2718d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_unset_window(npe, num); 2719d41ce7b1SAlexey Kardashevskiy if (ret) 2720d41ce7b1SAlexey Kardashevskiy return ret; 2721d41ce7b1SAlexey Kardashevskiy 2722d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2723d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]); 2724d41ce7b1SAlexey Kardashevskiy 2725d41ce7b1SAlexey Kardashevskiy return ret; 2726b5cb9ab1SAlexey Kardashevskiy } 2727b5cb9ab1SAlexey Kardashevskiy 2728b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2729b5cb9ab1SAlexey Kardashevskiy { 2730b5cb9ab1SAlexey Kardashevskiy /* 2731b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2732b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2733b5cb9ab1SAlexey Kardashevskiy */ 2734b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2735b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2736b5cb9ab1SAlexey Kardashevskiy } 2737b5cb9ab1SAlexey Kardashevskiy 2738b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2739b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2740090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 2741b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2742b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2743b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2744b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2745b5cb9ab1SAlexey Kardashevskiy }; 2746b5cb9ab1SAlexey Kardashevskiy 2747b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2748b5cb9ab1SAlexey Kardashevskiy { 2749b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2750b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2751b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2752b5cb9ab1SAlexey Kardashevskiy 2753b5cb9ab1SAlexey Kardashevskiy /* 2754b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2755b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2756b5cb9ab1SAlexey Kardashevskiy */ 2757b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2758b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2759b5cb9ab1SAlexey Kardashevskiy 27607f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2761b5cb9ab1SAlexey Kardashevskiy continue; 2762b5cb9ab1SAlexey Kardashevskiy 2763b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2764b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2765b5cb9ab1SAlexey Kardashevskiy if (gpe) 2766b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2767b5cb9ab1SAlexey Kardashevskiy } 2768b5cb9ab1SAlexey Kardashevskiy } 2769b5cb9ab1SAlexey Kardashevskiy } 2770b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2771b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2772f87a8864SAlexey Kardashevskiy #endif 2773f87a8864SAlexey Kardashevskiy 27747ef73cd3SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 27757ef73cd3SAlexey Kardashevskiy { 27767ef73cd3SAlexey Kardashevskiy struct pci_controller *hose = phb->hose; 27777ef73cd3SAlexey Kardashevskiy struct device_node *dn = hose->dn; 27787ef73cd3SAlexey Kardashevskiy unsigned long mask = 0; 27797ef73cd3SAlexey Kardashevskiy int i, rc, count; 27807ef73cd3SAlexey Kardashevskiy u32 val; 27817ef73cd3SAlexey Kardashevskiy 27827ef73cd3SAlexey Kardashevskiy count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 27837ef73cd3SAlexey Kardashevskiy if (count <= 0) { 27847ef73cd3SAlexey Kardashevskiy mask = SZ_4K | SZ_64K; 27857ef73cd3SAlexey Kardashevskiy /* Add 16M for POWER8 by default */ 27867ef73cd3SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_ARCH_207S) && 27877ef73cd3SAlexey Kardashevskiy !cpu_has_feature(CPU_FTR_ARCH_300)) 278800c376fdSAlexey Kardashevskiy mask |= SZ_16M | SZ_256M; 27897ef73cd3SAlexey Kardashevskiy return mask; 27907ef73cd3SAlexey Kardashevskiy } 27917ef73cd3SAlexey Kardashevskiy 27927ef73cd3SAlexey Kardashevskiy for (i = 0; i < count; i++) { 27937ef73cd3SAlexey Kardashevskiy rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 27947ef73cd3SAlexey Kardashevskiy i, &val); 27957ef73cd3SAlexey Kardashevskiy if (rc == 0) 27967ef73cd3SAlexey Kardashevskiy mask |= 1ULL << val; 27977ef73cd3SAlexey Kardashevskiy } 27987ef73cd3SAlexey Kardashevskiy 27997ef73cd3SAlexey Kardashevskiy return mask; 28007ef73cd3SAlexey Kardashevskiy } 28017ef73cd3SAlexey Kardashevskiy 2802373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2803373f5657SGavin Shan struct pnv_ioda_pe *pe) 2804373f5657SGavin Shan { 2805373f5657SGavin Shan int64_t rc; 2806373f5657SGavin Shan 2807ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2808ccd1c191SGavin Shan return; 2809ccd1c191SGavin Shan 2810f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2811f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2812f87a8864SAlexey Kardashevskiy 2813b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2814b348aa65SAlexey Kardashevskiy pe->pe_number); 2815c5773822SAlexey Kardashevskiy 2816373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2817373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2818aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2819373f5657SGavin Shan 2820e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 28214793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 28224793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 28234793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 28244793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 28254793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 28267ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2827e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2828e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2829e5aad1e6SAlexey Kardashevskiy #endif 2830e5aad1e6SAlexey Kardashevskiy 283146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2832801846d1SGavin Shan if (rc) 283346d3e1e1SAlexey Kardashevskiy return; 283446d3e1e1SAlexey Kardashevskiy 283520f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2836db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2837373f5657SGavin Shan } 2838373f5657SGavin Shan 2839184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 28404ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2841137436c9SGavin Shan { 2842137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2843137436c9SGavin Shan ioda.irq_chip); 2844137436c9SGavin Shan 28454ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 28464ee11c1aSSuresh Warrier } 28474ee11c1aSSuresh Warrier 28484ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 28494ee11c1aSSuresh Warrier { 28504ee11c1aSSuresh Warrier int64_t rc; 28514ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 28524ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 28534ee11c1aSSuresh Warrier 28544ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2855137436c9SGavin Shan WARN_ON_ONCE(rc); 2856137436c9SGavin Shan 2857137436c9SGavin Shan icp_native_eoi(d); 2858137436c9SGavin Shan } 2859137436c9SGavin Shan 2860fd9a1c26SIan Munsie 2861f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2862fd9a1c26SIan Munsie { 2863fd9a1c26SIan Munsie struct irq_data *idata; 2864fd9a1c26SIan Munsie struct irq_chip *ichip; 2865fd9a1c26SIan Munsie 2866fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2867fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2868fd9a1c26SIan Munsie return; 2869fd9a1c26SIan Munsie 2870fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2871fd9a1c26SIan Munsie /* 2872fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2873fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2874fd9a1c26SIan Munsie */ 2875fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2876fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2877fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2878fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2879fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2880fd9a1c26SIan Munsie } 2881fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2882fd9a1c26SIan Munsie } 2883fd9a1c26SIan Munsie 28844ee11c1aSSuresh Warrier /* 28854ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 28864ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 28874ee11c1aSSuresh Warrier */ 28884ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 28894ee11c1aSSuresh Warrier { 28904ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 28914ee11c1aSSuresh Warrier } 28924ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 28934ee11c1aSSuresh Warrier 2894184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2895137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2896137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2897184cd4a3SBenjamin Herrenschmidt { 2898184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2899184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 29003a1a4661SBenjamin Herrenschmidt __be32 data; 2901184cd4a3SBenjamin Herrenschmidt int rc; 2902184cd4a3SBenjamin Herrenschmidt 2903184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2904184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2905184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2906184cd4a3SBenjamin Herrenschmidt 2907184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2908184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2909184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2910184cd4a3SBenjamin Herrenschmidt 2911b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 291236074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2913b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2914b72c1f65SBenjamin Herrenschmidt 2915184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2916184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2917184cd4a3SBenjamin Herrenschmidt if (rc) { 2918184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2919184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2920184cd4a3SBenjamin Herrenschmidt return -EIO; 2921184cd4a3SBenjamin Herrenschmidt } 2922184cd4a3SBenjamin Herrenschmidt 2923184cd4a3SBenjamin Herrenschmidt if (is_64) { 29243a1a4661SBenjamin Herrenschmidt __be64 addr64; 29253a1a4661SBenjamin Herrenschmidt 2926184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2927184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2928184cd4a3SBenjamin Herrenschmidt if (rc) { 2929184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2930184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2931184cd4a3SBenjamin Herrenschmidt return -EIO; 2932184cd4a3SBenjamin Herrenschmidt } 29333a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 29343a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2935184cd4a3SBenjamin Herrenschmidt } else { 29363a1a4661SBenjamin Herrenschmidt __be32 addr32; 29373a1a4661SBenjamin Herrenschmidt 2938184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2939184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2940184cd4a3SBenjamin Herrenschmidt if (rc) { 2941184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2942184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2943184cd4a3SBenjamin Herrenschmidt return -EIO; 2944184cd4a3SBenjamin Herrenschmidt } 2945184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 29463a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2947184cd4a3SBenjamin Herrenschmidt } 29483a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2949184cd4a3SBenjamin Herrenschmidt 2950f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2951137436c9SGavin Shan 2952184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 29531f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2954184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2955184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2956184cd4a3SBenjamin Herrenschmidt 2957184cd4a3SBenjamin Herrenschmidt return 0; 2958184cd4a3SBenjamin Herrenschmidt } 2959184cd4a3SBenjamin Herrenschmidt 2960184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2961184cd4a3SBenjamin Herrenschmidt { 2962fb1b55d6SGavin Shan unsigned int count; 2963184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2964184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2965184cd4a3SBenjamin Herrenschmidt if (!prop) { 2966184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2967184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2968184cd4a3SBenjamin Herrenschmidt } 2969184cd4a3SBenjamin Herrenschmidt if (!prop) 2970184cd4a3SBenjamin Herrenschmidt return; 2971184cd4a3SBenjamin Herrenschmidt 2972184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2973fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2974fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2975184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2976184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2977184cd4a3SBenjamin Herrenschmidt return; 2978184cd4a3SBenjamin Herrenschmidt } 2979fb1b55d6SGavin Shan 2980184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2981184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2982184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2983fb1b55d6SGavin Shan count, phb->msi_base); 2984184cd4a3SBenjamin Herrenschmidt } 2985184cd4a3SBenjamin Herrenschmidt #else 2986184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2987184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2988184cd4a3SBenjamin Herrenschmidt 29896e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29906e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29916e628c7dSWei Yang { 2992f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2993f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2994f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29956e628c7dSWei Yang struct resource *res; 29966e628c7dSWei Yang int i; 2997dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29986e628c7dSWei Yang struct pci_dn *pdn; 29995b88ec22SWei Yang int mul, total_vfs; 30006e628c7dSWei Yang 300144bda4b7SHari Vyas if (!pdev->is_physfn || pci_dev_is_added(pdev)) 30026e628c7dSWei Yang return; 30036e628c7dSWei Yang 30046e628c7dSWei Yang pdn = pci_get_pdn(pdev); 30056e628c7dSWei Yang pdn->vfs_expanded = 0; 3006ee8222feSWei Yang pdn->m64_single_mode = false; 30076e628c7dSWei Yang 30085b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 300992b8f137SGavin Shan mul = phb->ioda.total_pe_num; 3010dfcc8d45SWei Yang total_vf_bar_sz = 0; 30115b88ec22SWei Yang 30125b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 30135b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 30145b88ec22SWei Yang if (!res->flags || res->parent) 30155b88ec22SWei Yang continue; 3016b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 3017b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 3018b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 30195b88ec22SWei Yang i, res); 3020b0331854SWei Yang goto truncate_iov; 30215b88ec22SWei Yang } 30225b88ec22SWei Yang 3023dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 3024dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 30255b88ec22SWei Yang 3026f2dd0afeSWei Yang /* 3027f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 3028f2dd0afeSWei Yang * power of two. 3029f2dd0afeSWei Yang * 3030f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3031f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 3032f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3033f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 3034f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 3035f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 3036f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 3037f2dd0afeSWei Yang */ 3038dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 30395b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 3040dfcc8d45SWei Yang dev_info(&pdev->dev, 3041dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3042dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 3043ee8222feSWei Yang pdn->m64_single_mode = true; 30445b88ec22SWei Yang break; 30455b88ec22SWei Yang } 30465b88ec22SWei Yang } 30475b88ec22SWei Yang 30486e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 30496e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 30506e628c7dSWei Yang if (!res->flags || res->parent) 30516e628c7dSWei Yang continue; 30526e628c7dSWei Yang 30536e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3054ee8222feSWei Yang /* 3055ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 3056ee8222feSWei Yang * mode is 32MB. 3057ee8222feSWei Yang */ 3058ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3059ee8222feSWei Yang goto truncate_iov; 3060ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 30615b88ec22SWei Yang res->end = res->start + size * mul - 1; 30626e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 30636e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 30645b88ec22SWei Yang i, res, mul); 30656e628c7dSWei Yang } 30665b88ec22SWei Yang pdn->vfs_expanded = mul; 3067b0331854SWei Yang 3068b0331854SWei Yang return; 3069b0331854SWei Yang 3070b0331854SWei Yang truncate_iov: 3071b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3072b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3073b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3074b0331854SWei Yang res->flags = 0; 3075b0331854SWei Yang res->end = res->start - 1; 3076b0331854SWei Yang } 30776e628c7dSWei Yang } 30786e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 30796e628c7dSWei Yang 308023e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 308123e79425SGavin Shan struct resource *res) 308211685becSGavin Shan { 308323e79425SGavin Shan struct pnv_phb *phb = pe->phb; 308411685becSGavin Shan struct pci_bus_region region; 308523e79425SGavin Shan int index; 308623e79425SGavin Shan int64_t rc; 308711685becSGavin Shan 308823e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 308923e79425SGavin Shan return; 309011685becSGavin Shan 309111685becSGavin Shan if (res->flags & IORESOURCE_IO) { 309211685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 309311685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 309411685becSGavin Shan index = region.start / phb->ioda.io_segsize; 309511685becSGavin Shan 309692b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 309711685becSGavin Shan region.start <= region.end) { 309811685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 309911685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 310011685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 310111685becSGavin Shan if (rc != OPAL_SUCCESS) { 31021f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 310311685becSGavin Shan __func__, rc, index, pe->pe_number); 310411685becSGavin Shan break; 310511685becSGavin Shan } 310611685becSGavin Shan 310711685becSGavin Shan region.start += phb->ioda.io_segsize; 310811685becSGavin Shan index++; 310911685becSGavin Shan } 3110027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 31115958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 311211685becSGavin Shan region.start = res->start - 311323e79425SGavin Shan phb->hose->mem_offset[0] - 311411685becSGavin Shan phb->ioda.m32_pci_base; 311511685becSGavin Shan region.end = res->end - 311623e79425SGavin Shan phb->hose->mem_offset[0] - 311711685becSGavin Shan phb->ioda.m32_pci_base; 311811685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 311911685becSGavin Shan 312092b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 312111685becSGavin Shan region.start <= region.end) { 312211685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 312311685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 312411685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 312511685becSGavin Shan if (rc != OPAL_SUCCESS) { 31261f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 312711685becSGavin Shan __func__, rc, index, pe->pe_number); 312811685becSGavin Shan break; 312911685becSGavin Shan } 313011685becSGavin Shan 313111685becSGavin Shan region.start += phb->ioda.m32_segsize; 313211685becSGavin Shan index++; 313311685becSGavin Shan } 313411685becSGavin Shan } 313511685becSGavin Shan } 313623e79425SGavin Shan 313723e79425SGavin Shan /* 313823e79425SGavin Shan * This function is supposed to be called on basis of PE from top 313923e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 314003671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 314123e79425SGavin Shan */ 314223e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 314323e79425SGavin Shan { 314469d733e7SGavin Shan struct pci_dev *pdev; 314523e79425SGavin Shan int i; 314623e79425SGavin Shan 314723e79425SGavin Shan /* 314823e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 314923e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 315023e79425SGavin Shan * be figured out later. 315123e79425SGavin Shan */ 315223e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 315323e79425SGavin Shan 315469d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 315569d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 315669d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 315769d733e7SGavin Shan 315869d733e7SGavin Shan /* 315969d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 316069d733e7SGavin Shan * windows of the child bridges should be mapped to 316169d733e7SGavin Shan * the PE as well. 316269d733e7SGavin Shan */ 316369d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 316469d733e7SGavin Shan continue; 316569d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 316669d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 316769d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 316869d733e7SGavin Shan } 316911685becSGavin Shan } 317011685becSGavin Shan 317198b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 317298b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 317398b665daSRussell Currey { 317498b665daSRussell Currey struct pci_controller *hose; 317598b665daSRussell Currey struct pnv_phb *phb; 317698b665daSRussell Currey s64 ret; 317798b665daSRussell Currey 317898b665daSRussell Currey if (val != 1ULL) 317998b665daSRussell Currey return -EINVAL; 318098b665daSRussell Currey 318198b665daSRussell Currey hose = (struct pci_controller *)data; 318298b665daSRussell Currey if (!hose || !hose->private_data) 318398b665daSRussell Currey return -ENODEV; 318498b665daSRussell Currey 318598b665daSRussell Currey phb = hose->private_data; 318698b665daSRussell Currey 318798b665daSRussell Currey /* Retrieve the diag data from firmware */ 31885cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 31895cb1f8fdSRussell Currey phb->diag_data_size); 319098b665daSRussell Currey if (ret != OPAL_SUCCESS) 319198b665daSRussell Currey return -EIO; 319298b665daSRussell Currey 319398b665daSRussell Currey /* Print the diag data to the kernel log */ 31945cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 319598b665daSRussell Currey return 0; 319698b665daSRussell Currey } 319798b665daSRussell Currey 319898b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 319998b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 320098b665daSRussell Currey 320198b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 320298b665daSRussell Currey 320337c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 320437c367f2SGavin Shan { 320537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 320637c367f2SGavin Shan struct pci_controller *hose, *tmp; 320737c367f2SGavin Shan struct pnv_phb *phb; 320837c367f2SGavin Shan char name[16]; 320937c367f2SGavin Shan 321037c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 321137c367f2SGavin Shan phb = hose->private_data; 321237c367f2SGavin Shan 3213ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3214ccd1c191SGavin Shan phb->initialized = 1; 3215ccd1c191SGavin Shan 321637c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 321737c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 321898b665daSRussell Currey if (!phb->dbgfs) { 3219f2c2cbccSJoe Perches pr_warn("%s: Error on creating debugfs on PHB#%x\n", 322037c367f2SGavin Shan __func__, hose->global_number); 322198b665daSRussell Currey continue; 322298b665daSRussell Currey } 322398b665daSRussell Currey 322498b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 322598b665daSRussell Currey &pnv_pci_diag_data_fops); 322637c367f2SGavin Shan } 322737c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 322837c367f2SGavin Shan } 322937c367f2SGavin Shan 3230db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 3231db217319SBenjamin Herrenschmidt { 3232db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 3233db217319SBenjamin Herrenschmidt struct pci_bus *child; 3234db217319SBenjamin Herrenschmidt 3235db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 3236db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 3237db217319SBenjamin Herrenschmidt return; 3238db217319SBenjamin Herrenschmidt 3239db217319SBenjamin Herrenschmidt /* 3240db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 3241db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 3242db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 3243db217319SBenjamin Herrenschmidt * fixed. 3244db217319SBenjamin Herrenschmidt */ 3245db217319SBenjamin Herrenschmidt if (dev) { 3246db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 3247db217319SBenjamin Herrenschmidt if (rc) 3248db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 3249db217319SBenjamin Herrenschmidt pci_set_master(dev); 3250db217319SBenjamin Herrenschmidt } 3251db217319SBenjamin Herrenschmidt 3252db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 3253db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 3254db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 3255db217319SBenjamin Herrenschmidt } 3256db217319SBenjamin Herrenschmidt 3257db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 3258db217319SBenjamin Herrenschmidt { 3259db217319SBenjamin Herrenschmidt struct pci_controller *hose; 3260db217319SBenjamin Herrenschmidt 3261db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 3262db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 3263db217319SBenjamin Herrenschmidt } 3264db217319SBenjamin Herrenschmidt 3265cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3266fb446ad0SGavin Shan { 3267fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3268ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 326937c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 327037c367f2SGavin Shan 3271db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 3272db217319SBenjamin Herrenschmidt 3273e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3274b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3275e9cc17d4SGavin Shan #endif 3276fb446ad0SGavin Shan } 3277fb446ad0SGavin Shan 3278271fd03aSGavin Shan /* 3279271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3280271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3281271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3282271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3283271fd03aSGavin Shan * 1MiB for memory) will be returned. 3284271fd03aSGavin Shan * 3285271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3286271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3287271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3288271fd03aSGavin Shan * resources. 3289271fd03aSGavin Shan */ 3290271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3291271fd03aSGavin Shan unsigned long type) 3292271fd03aSGavin Shan { 3293271fd03aSGavin Shan struct pci_dev *bridge; 3294271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3295271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3296271fd03aSGavin Shan int num_pci_bridges = 0; 3297271fd03aSGavin Shan 3298271fd03aSGavin Shan bridge = bus->self; 3299271fd03aSGavin Shan while (bridge) { 3300271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3301271fd03aSGavin Shan num_pci_bridges++; 3302271fd03aSGavin Shan if (num_pci_bridges >= 2) 3303271fd03aSGavin Shan return 1; 3304271fd03aSGavin Shan } 3305271fd03aSGavin Shan 3306271fd03aSGavin Shan bridge = bridge->bus->self; 3307271fd03aSGavin Shan } 3308271fd03aSGavin Shan 33095958d19aSBenjamin Herrenschmidt /* 33105958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 33115958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 33125958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 33135958d19aSBenjamin Herrenschmidt */ 3314b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3315262af557SGuo Chao return phb->ioda.m64_segsize; 3316271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3317271fd03aSGavin Shan return phb->ioda.m32_segsize; 3318271fd03aSGavin Shan 3319271fd03aSGavin Shan return phb->ioda.io_segsize; 3320271fd03aSGavin Shan } 3321271fd03aSGavin Shan 332240e2a47eSGavin Shan /* 332340e2a47eSGavin Shan * We are updating root port or the upstream port of the 332440e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 332540e2a47eSGavin Shan * to accommodate the changes on required resources during 332640e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 332740e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 332840e2a47eSGavin Shan * root port. 332940e2a47eSGavin Shan */ 333040e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 333140e2a47eSGavin Shan unsigned long type) 333240e2a47eSGavin Shan { 333340e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 333440e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 333540e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 333640e2a47eSGavin Shan struct resource *r, *w; 333740e2a47eSGavin Shan bool msi_region = false; 333840e2a47eSGavin Shan int i; 333940e2a47eSGavin Shan 334040e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 334140e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 334240e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 334340e2a47eSGavin Shan return; 334440e2a47eSGavin Shan 334540e2a47eSGavin Shan /* Fixup the resources */ 334640e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 334740e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 334840e2a47eSGavin Shan if (!r->flags || !r->parent) 334940e2a47eSGavin Shan continue; 335040e2a47eSGavin Shan 335140e2a47eSGavin Shan w = NULL; 335240e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 335340e2a47eSGavin Shan w = &hose->io_resource; 33545958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 335540e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 335640e2a47eSGavin Shan phb->ioda.m64_segsize) 335740e2a47eSGavin Shan w = &hose->mem_resources[1]; 335840e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 335940e2a47eSGavin Shan w = &hose->mem_resources[0]; 336040e2a47eSGavin Shan msi_region = true; 336140e2a47eSGavin Shan } 336240e2a47eSGavin Shan 336340e2a47eSGavin Shan r->start = w->start; 336440e2a47eSGavin Shan r->end = w->end; 336540e2a47eSGavin Shan 336640e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 336740e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 336840e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 336940e2a47eSGavin Shan * 337040e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 337140e2a47eSGavin Shan * 32-bits bridge window. 337240e2a47eSGavin Shan */ 337340e2a47eSGavin Shan if (msi_region) { 337440e2a47eSGavin Shan r->end += 0x10000; 337540e2a47eSGavin Shan r->end -= 0x100000; 337640e2a47eSGavin Shan } 337740e2a47eSGavin Shan } 337840e2a47eSGavin Shan } 337940e2a47eSGavin Shan 3380ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3381ccd1c191SGavin Shan { 3382ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3383ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3384ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3385ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3386ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3387ccd1c191SGavin Shan 338840e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 338940e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 339040e2a47eSGavin Shan 339163803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 339263803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 339363803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 339463803c39SGavin Shan if (pe) { 339563803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 339663803c39SGavin Shan phb->ioda.root_pe_populated = true; 339763803c39SGavin Shan } 339863803c39SGavin Shan } 339963803c39SGavin Shan 3400ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3401ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3402ccd1c191SGavin Shan return; 3403ccd1c191SGavin Shan 3404ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3405ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3406ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3407ccd1c191SGavin Shan 3408ccd1c191SGavin Shan /* 3409ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3410ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3411ccd1c191SGavin Shan * not allocate resources again. 3412ccd1c191SGavin Shan */ 3413ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3414ccd1c191SGavin Shan if (!pe) 3415ccd1c191SGavin Shan return; 3416ccd1c191SGavin Shan 3417ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3418ccd1c191SGavin Shan switch (phb->type) { 3419ccd1c191SGavin Shan case PNV_PHB_IODA1: 3420ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3421ccd1c191SGavin Shan break; 3422ccd1c191SGavin Shan case PNV_PHB_IODA2: 3423ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3424ccd1c191SGavin Shan break; 3425ccd1c191SGavin Shan default: 34261f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3427ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3428ccd1c191SGavin Shan } 3429ccd1c191SGavin Shan } 3430ccd1c191SGavin Shan 343138274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 343238274637SYongji Xie { 343338274637SYongji Xie return PAGE_SIZE; 343438274637SYongji Xie } 343538274637SYongji Xie 34365350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 34375350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 34385350ab3fSWei Yang int resno) 34395350ab3fSWei Yang { 3440ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3441ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 34425350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 34437fbe7a93SWei Yang resource_size_t align; 34445350ab3fSWei Yang 34457fbe7a93SWei Yang /* 34467fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 34477fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 34487fbe7a93SWei Yang * BAR should be size aligned. 34497fbe7a93SWei Yang * 3450ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3451ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3452ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3453ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3454ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3455ee8222feSWei Yang * m64_segsize. 3456ee8222feSWei Yang * 34577fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 34587fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3459ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3460ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 34617fbe7a93SWei Yang */ 34625350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 34637fbe7a93SWei Yang if (!pdn->vfs_expanded) 34645350ab3fSWei Yang return align; 3465ee8222feSWei Yang if (pdn->m64_single_mode) 3466ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 34677fbe7a93SWei Yang 34687fbe7a93SWei Yang return pdn->vfs_expanded * align; 34695350ab3fSWei Yang } 34705350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 34715350ab3fSWei Yang 3472184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3473184cd4a3SBenjamin Herrenschmidt * assign a PE 3474184cd4a3SBenjamin Herrenschmidt */ 34758bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3476184cd4a3SBenjamin Herrenschmidt { 3477db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3478db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3479db1266c8SGavin Shan struct pci_dn *pdn; 3480184cd4a3SBenjamin Herrenschmidt 3481db1266c8SGavin Shan /* The function is probably called while the PEs have 3482db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3483db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3484db1266c8SGavin Shan * PEs isn't ready. 3485db1266c8SGavin Shan */ 3486db1266c8SGavin Shan if (!phb->initialized) 3487c88c2a18SDaniel Axtens return true; 3488db1266c8SGavin Shan 3489b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3490184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3491c88c2a18SDaniel Axtens return false; 3492db1266c8SGavin Shan 3493c88c2a18SDaniel Axtens return true; 3494184cd4a3SBenjamin Herrenschmidt } 3495184cd4a3SBenjamin Herrenschmidt 3496c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3497c5f7700bSGavin Shan int num) 3498c5f7700bSGavin Shan { 3499c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3500c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3501c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3502c5f7700bSGavin Shan unsigned int idx; 3503c5f7700bSGavin Shan long rc; 3504c5f7700bSGavin Shan 3505c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3506c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3507c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3508c5f7700bSGavin Shan continue; 3509c5f7700bSGavin Shan 3510c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3511c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3512c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3513c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3514c5f7700bSGavin Shan rc, idx); 3515c5f7700bSGavin Shan return rc; 3516c5f7700bSGavin Shan } 3517c5f7700bSGavin Shan 3518c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3519c5f7700bSGavin Shan } 3520c5f7700bSGavin Shan 3521c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3522c5f7700bSGavin Shan return OPAL_SUCCESS; 3523c5f7700bSGavin Shan } 3524c5f7700bSGavin Shan 3525c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3526c5f7700bSGavin Shan { 3527c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3528c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3529c5f7700bSGavin Shan int64_t rc; 3530c5f7700bSGavin Shan 3531c5f7700bSGavin Shan if (!weight) 3532c5f7700bSGavin Shan return; 3533c5f7700bSGavin Shan 3534c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3535c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3536c5f7700bSGavin Shan return; 3537c5f7700bSGavin Shan 3538a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3539c5f7700bSGavin Shan if (pe->table_group.group) { 3540c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3541c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3542c5f7700bSGavin Shan } 3543c5f7700bSGavin Shan 3544c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3545e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3546c5f7700bSGavin Shan } 3547c5f7700bSGavin Shan 3548c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3549c5f7700bSGavin Shan { 3550c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3551c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3552c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3553c5f7700bSGavin Shan int64_t rc; 3554c5f7700bSGavin Shan #endif 3555c5f7700bSGavin Shan 3556c5f7700bSGavin Shan if (!weight) 3557c5f7700bSGavin Shan return; 3558c5f7700bSGavin Shan 3559c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3560c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3561c5f7700bSGavin Shan if (rc) 3562c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3563c5f7700bSGavin Shan #endif 3564c5f7700bSGavin Shan 3565c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3566c5f7700bSGavin Shan if (pe->table_group.group) { 3567c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3568c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3569c5f7700bSGavin Shan } 3570c5f7700bSGavin Shan 3571e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3572c5f7700bSGavin Shan } 3573c5f7700bSGavin Shan 3574c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3575c5f7700bSGavin Shan unsigned short win, 3576c5f7700bSGavin Shan unsigned int *map) 3577c5f7700bSGavin Shan { 3578c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3579c5f7700bSGavin Shan int idx; 3580c5f7700bSGavin Shan int64_t rc; 3581c5f7700bSGavin Shan 3582c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3583c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3584c5f7700bSGavin Shan continue; 3585c5f7700bSGavin Shan 3586c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3587c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3588c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3589c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3590c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3591c5f7700bSGavin Shan else 3592c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3593c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3594c5f7700bSGavin Shan 3595c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3596c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3597c5f7700bSGavin Shan rc, win, idx); 3598c5f7700bSGavin Shan 3599c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3600c5f7700bSGavin Shan } 3601c5f7700bSGavin Shan } 3602c5f7700bSGavin Shan 3603c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3604c5f7700bSGavin Shan { 3605c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3606c5f7700bSGavin Shan 3607c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3608c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3609c5f7700bSGavin Shan phb->ioda.io_segmap); 3610c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3611c5f7700bSGavin Shan phb->ioda.m32_segmap); 3612c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3613c5f7700bSGavin Shan phb->ioda.m64_segmap); 3614c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3615c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3616c5f7700bSGavin Shan phb->ioda.m32_segmap); 3617c5f7700bSGavin Shan } 3618c5f7700bSGavin Shan } 3619c5f7700bSGavin Shan 3620c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3621c5f7700bSGavin Shan { 3622c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3623c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3624c5f7700bSGavin Shan 3625c5f7700bSGavin Shan list_del(&pe->list); 3626c5f7700bSGavin Shan switch (phb->type) { 3627c5f7700bSGavin Shan case PNV_PHB_IODA1: 3628c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3629c5f7700bSGavin Shan break; 3630c5f7700bSGavin Shan case PNV_PHB_IODA2: 3631c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3632c5f7700bSGavin Shan break; 3633c5f7700bSGavin Shan default: 3634c5f7700bSGavin Shan WARN_ON(1); 3635c5f7700bSGavin Shan } 3636c5f7700bSGavin Shan 3637c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3638c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3639b314427aSGavin Shan 3640b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3641b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3642b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3643b314427aSGavin Shan list_del(&slave->list); 3644b314427aSGavin Shan pnv_ioda_free_pe(slave); 3645b314427aSGavin Shan } 3646b314427aSGavin Shan } 3647b314427aSGavin Shan 36486eaed166SGavin Shan /* 36496eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 36506eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 36516eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 36526eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 36536eaed166SGavin Shan */ 36546eaed166SGavin Shan if (phb->ioda.root_pe_populated && 36556eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 36566eaed166SGavin Shan phb->ioda.root_pe_populated = false; 36576eaed166SGavin Shan else 3658c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3659c5f7700bSGavin Shan } 3660c5f7700bSGavin Shan 3661c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3662c5f7700bSGavin Shan { 3663c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3664c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3665c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3666c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3667c5f7700bSGavin Shan 3668c5f7700bSGavin Shan if (pdev->is_virtfn) 3669c5f7700bSGavin Shan return; 3670c5f7700bSGavin Shan 3671c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3672c5f7700bSGavin Shan return; 3673c5f7700bSGavin Shan 367429bf282dSGavin Shan /* 367529bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 367629bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 367729bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 367829bf282dSGavin Shan * device count is decreased on removing devices while failing to 367929bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 368029bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 368129bf282dSGavin Shan */ 3682c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 368329bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 368429bf282dSGavin Shan 3685c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3686c5f7700bSGavin Shan if (pe->device_count == 0) 3687c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3688c5f7700bSGavin Shan } 3689c5f7700bSGavin Shan 36907a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 369173ed148aSBenjamin Herrenschmidt { 36927a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 36937a8e6bbfSMichael Neuling 3694d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 369573ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 369673ed148aSBenjamin Herrenschmidt } 369773ed148aSBenjamin Herrenschmidt 369892ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 369992ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 37001bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 370192ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 370292ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 370392ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 370492ae0353SDaniel Axtens #endif 370592ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3706c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 370792ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3708ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 370992ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3710763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 371153522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 37127a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 371392ae0353SDaniel Axtens }; 371492ae0353SDaniel Axtens 3715f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3716f9f83456SAlexey Kardashevskiy { 3717f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3718f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3719f9f83456SAlexey Kardashevskiy __func__); 3720f9f83456SAlexey Kardashevskiy return -EPERM; 3721f9f83456SAlexey Kardashevskiy } 3722f9f83456SAlexey Kardashevskiy 37235d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 37245d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 37255d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 37265d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 37275d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 37285d2aa710SAlistair Popple #endif 37295d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 37305d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 37315d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37325d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 37335d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 37345d2aa710SAlistair Popple }; 37355d2aa710SAlistair Popple 37367f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 37377f2c39e9SFrederic Barrat .enable_device_hook = pnv_pci_enable_device_hook, 37387f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 37397f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37407f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 37417f2c39e9SFrederic Barrat }; 37427f2c39e9SFrederic Barrat 3743e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3744e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3745184cd4a3SBenjamin Herrenschmidt { 3746184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3747184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 37482b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 37492b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3750fd141d1aSBenjamin Herrenschmidt struct resource r; 3751c681b93cSAlistair Popple const __be64 *prop64; 37523a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3753f1b7cc3eSGavin Shan int len; 37543fa23ff8SGavin Shan unsigned int segno; 3755184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3756184cd4a3SBenjamin Herrenschmidt void *aux; 3757184cd4a3SBenjamin Herrenschmidt long rc; 3758184cd4a3SBenjamin Herrenschmidt 375908a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 376008a45b32SBenjamin Herrenschmidt return; 376108a45b32SBenjamin Herrenschmidt 3762b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3763184cd4a3SBenjamin Herrenschmidt 3764184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3765184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3766184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3767184cd4a3SBenjamin Herrenschmidt return; 3768184cd4a3SBenjamin Herrenschmidt } 3769184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3770184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3771184cd4a3SBenjamin Herrenschmidt 3772eb31d559SMike Rapoport phb = memblock_alloc(sizeof(*phb), 0); 377358d714ecSGavin Shan 377458d714ecSGavin Shan /* Allocate PCI controller */ 3775184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 377658d714ecSGavin Shan if (!phb->hose) { 3777b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3778b7c670d6SRob Herring np); 3779e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3780184cd4a3SBenjamin Herrenschmidt return; 3781184cd4a3SBenjamin Herrenschmidt } 3782184cd4a3SBenjamin Herrenschmidt 3783184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3784f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3785f1b7cc3eSGavin Shan if (prop32 && len == 8) { 37863a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 37873a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3788f1b7cc3eSGavin Shan } else { 3789b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3790184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3791184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3792f1b7cc3eSGavin Shan } 3793184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3794e9cc17d4SGavin Shan phb->hub_id = hub_id; 3795184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3796aa0c033fSGavin Shan phb->type = ioda_type; 3797781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3798184cd4a3SBenjamin Herrenschmidt 3799cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3800cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3801cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3802f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3803aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 38045d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 38055d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3806616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3807616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3808cee72d5bSBenjamin Herrenschmidt else 3809cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3810cee72d5bSBenjamin Herrenschmidt 38115cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 38125cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 38135cb1f8fdSRussell Currey if (prop32) 38145cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 38155cb1f8fdSRussell Currey else 38165cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 38175cb1f8fdSRussell Currey 3818eb31d559SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, 0); 38195cb1f8fdSRussell Currey 3820aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 38212f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3822184cd4a3SBenjamin Herrenschmidt 3823aa0c033fSGavin Shan /* Get registers */ 3824fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3825fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3826fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3827184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3828184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3829fd141d1aSBenjamin Herrenschmidt } 3830577c8c88SGavin Shan 3831184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 383292b8f137SGavin Shan phb->ioda.total_pe_num = 1; 383336954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 383436954dc7SGavin Shan if (prop32) 383592b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 383636954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 383736954dc7SGavin Shan if (prop32) 383892b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3839262af557SGuo Chao 3840c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3841c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3842c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3843c127562aSGavin Shan 3844262af557SGuo Chao /* Parse 64-bit MMIO range */ 3845262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3846262af557SGuo Chao 3847184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3848aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3849184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3850184cd4a3SBenjamin Herrenschmidt 385192b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 38523fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3853184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 385492b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3855184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3856184cd4a3SBenjamin Herrenschmidt 38572b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 38582b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 38592b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 38602b923ed1SGavin Shan 3861c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 386292a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 386392a86756SAlexey Kardashevskiy sizeof(unsigned long)); 386493289d8cSGavin Shan m64map_off = size; 386593289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3866184cd4a3SBenjamin Herrenschmidt m32map_off = size; 386792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3868c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3869c35d2a8cSGavin Shan iomap_off = size; 387092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 38712b923ed1SGavin Shan dma32map_off = size; 38722b923ed1SGavin Shan size += phb->ioda.dma32_count * 38732b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3874c35d2a8cSGavin Shan } 3875184cd4a3SBenjamin Herrenschmidt pemap_off = size; 387692b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3877eb31d559SMike Rapoport aux = memblock_alloc(size, 0); 3878184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 387993289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3880184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 388193289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 388293289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 38833fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 388493289d8cSGavin Shan } 38853fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3886184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 38873fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 38883fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 38892b923ed1SGavin Shan 38902b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 38912b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 38922b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 38933fa23ff8SGavin Shan } 3894184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 389563803c39SGavin Shan 389663803c39SGavin Shan /* 389763803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 389863803c39SGavin Shan * M64 resources consumed by its child devices. To pick 389963803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 390063803c39SGavin Shan */ 390163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 390263803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 390363803c39SGavin Shan phb->ioda.root_pe_idx = 1; 390463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 390563803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 390663803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 390763803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 390863803c39SGavin Shan } else { 390963803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 391063803c39SGavin Shan } 3911184cd4a3SBenjamin Herrenschmidt 3912184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3913781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3914184cd4a3SBenjamin Herrenschmidt 3915184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 39162b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3917acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3918184cd4a3SBenjamin Herrenschmidt 3919aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3920184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3921184cd4a3SBenjamin Herrenschmidt window_type, 3922184cd4a3SBenjamin Herrenschmidt window_num, 3923184cd4a3SBenjamin Herrenschmidt starting_real_address, 3924184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3925184cd4a3SBenjamin Herrenschmidt segment_size); 3926184cd4a3SBenjamin Herrenschmidt #endif 3927184cd4a3SBenjamin Herrenschmidt 3928262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 392992b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3930262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3931262af557SGuo Chao if (phb->ioda.m64_size) 3932262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3933262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3934262af557SGuo Chao if (phb->ioda.io_size) 3935262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3936184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3937184cd4a3SBenjamin Herrenschmidt 3938262af557SGuo Chao 3939184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 394049dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 394149dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 394249dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3943184cd4a3SBenjamin Herrenschmidt 3944184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3945184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3946184cd4a3SBenjamin Herrenschmidt 3947c40a4210SGavin Shan /* 3948c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3949c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3950c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3951c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3952c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3953184cd4a3SBenjamin Herrenschmidt */ 3954fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 39555d2aa710SAlistair Popple 39567f2c39e9SFrederic Barrat switch (phb->type) { 39577f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 39585d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 39597f2c39e9SFrederic Barrat break; 39607f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 39617f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 39627f2c39e9SFrederic Barrat break; 39637f2c39e9SFrederic Barrat default: 3964f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 396592ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3966f9f83456SAlexey Kardashevskiy } 3967ad30cb99SMichael Ellerman 396838274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 396938274637SYongji Xie 39706e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 39716e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 39725350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3973988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3974988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3975ad30cb99SMichael Ellerman #endif 3976ad30cb99SMichael Ellerman 3977c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3978184cd4a3SBenjamin Herrenschmidt 3979184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3980d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3981184cd4a3SBenjamin Herrenschmidt if (rc) 3982f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3983361f2a2aSGavin Shan 39846060e9eaSAndrew Donnellan /* 39856060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3986361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3987361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 398845baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 398945baee14SGuilherme G. Piccoli * kernel parameter will force this reset too. 3990361f2a2aSGavin Shan */ 399145baee14SGuilherme G. Piccoli if (is_kdump_kernel() || pci_reset_phbs) { 3992361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3993cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3994cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3995361f2a2aSGavin Shan } 3996262af557SGuo Chao 39979e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 39989e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3999262af557SGuo Chao hose->mem_resources[1].flags = 0; 4000184cd4a3SBenjamin Herrenschmidt } 4001184cd4a3SBenjamin Herrenschmidt 400267975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4003aa0c033fSGavin Shan { 4004e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4005aa0c033fSGavin Shan } 4006aa0c033fSGavin Shan 40075d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 40085d2aa710SAlistair Popple { 40097f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 40105d2aa710SAlistair Popple } 40115d2aa710SAlistair Popple 40127f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 40137f2c39e9SFrederic Barrat { 40147f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 4015184cd4a3SBenjamin Herrenschmidt } 4016184cd4a3SBenjamin Herrenschmidt 4017228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 4018228c2f41SAndrew Donnellan { 4019228c2f41SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(dev->bus); 4020228c2f41SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 4021228c2f41SAndrew Donnellan 4022228c2f41SAndrew Donnellan if (!machine_is(powernv)) 4023228c2f41SAndrew Donnellan return; 4024228c2f41SAndrew Donnellan 4025228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 4026228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4027228c2f41SAndrew Donnellan } 4028228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 4029228c2f41SAndrew Donnellan 4030184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 4031184cd4a3SBenjamin Herrenschmidt { 4032184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 4033184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 4034184cd4a3SBenjamin Herrenschmidt u64 hub_id; 4035184cd4a3SBenjamin Herrenschmidt 4036b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 4037184cd4a3SBenjamin Herrenschmidt 4038184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4039184cd4a3SBenjamin Herrenschmidt if (!prop64) { 4040184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4041184cd4a3SBenjamin Herrenschmidt return; 4042184cd4a3SBenjamin Herrenschmidt } 4043184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 4044184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4045184cd4a3SBenjamin Herrenschmidt 4046184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 4047184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 4048184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 4049184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4050184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4051184cd4a3SBenjamin Herrenschmidt } 4052184cd4a3SBenjamin Herrenschmidt } 4053