1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 5199451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5299451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54781a868fSWei Yang 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 57bbb845c4SAlexey Kardashevskiy 589497a1c1SGavin Shan static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; 59aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 60aca6913fSAlexey Kardashevskiy 617d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 626d31c2faSJoe Perches const char *fmt, ...) 636d31c2faSJoe Perches { 646d31c2faSJoe Perches struct va_format vaf; 656d31c2faSJoe Perches va_list args; 666d31c2faSJoe Perches char pfix[32]; 67184cd4a3SBenjamin Herrenschmidt 686d31c2faSJoe Perches va_start(args, fmt); 696d31c2faSJoe Perches 706d31c2faSJoe Perches vaf.fmt = fmt; 716d31c2faSJoe Perches vaf.va = &args; 726d31c2faSJoe Perches 73781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 746d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 75781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 766d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 776d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 78781a868fSWei Yang #ifdef CONFIG_PCI_IOV 79781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 80781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 81781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 82781a868fSWei Yang (pe->rid & 0xff00) >> 8, 83781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 84781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 856d31c2faSJoe Perches 866d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 876d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 886d31c2faSJoe Perches 896d31c2faSJoe Perches va_end(args); 906d31c2faSJoe Perches } 916d31c2faSJoe Perches 924e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 934e287840SThadeu Lima de Souza Cascardo 944e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 954e287840SThadeu Lima de Souza Cascardo { 964e287840SThadeu Lima de Souza Cascardo if (!str) 974e287840SThadeu Lima de Souza Cascardo return -EINVAL; 984e287840SThadeu Lima de Souza Cascardo 994e287840SThadeu Lima de Souza Cascardo while (*str) { 1004e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1014e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1024e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1034e287840SThadeu Lima de Souza Cascardo break; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1064e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1074e287840SThadeu Lima de Souza Cascardo str++; 1084e287840SThadeu Lima de Souza Cascardo } 1094e287840SThadeu Lima de Souza Cascardo 1104e287840SThadeu Lima de Souza Cascardo return 0; 1114e287840SThadeu Lima de Souza Cascardo } 1124e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1134e287840SThadeu Lima de Souza Cascardo 1145958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 115262af557SGuo Chao { 1165958d19aSBenjamin Herrenschmidt /* 1175958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1185958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1195958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1205958d19aSBenjamin Herrenschmidt * 1215958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1225958d19aSBenjamin Herrenschmidt */ 1235958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1245958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 125262af557SGuo Chao } 126262af557SGuo Chao 1271e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1281e916772SGavin Shan { 1291e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1301e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1311e916772SGavin Shan 1321e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1331e916772SGavin Shan } 1341e916772SGavin Shan 1354b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1364b82ab18SGavin Shan { 13792b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1384b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1394b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1404b82ab18SGavin Shan return; 1414b82ab18SGavin Shan } 1424b82ab18SGavin Shan 143e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 144e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1454b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1464b82ab18SGavin Shan 1471e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1484b82ab18SGavin Shan } 1494b82ab18SGavin Shan 1501e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 151184cd4a3SBenjamin Herrenschmidt { 1529fcd6f4aSGavin Shan unsigned long pe = phb->ioda.total_pe_num - 1; 153184cd4a3SBenjamin Herrenschmidt 1549fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1559fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1561e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 157184cd4a3SBenjamin Herrenschmidt } 158184cd4a3SBenjamin Herrenschmidt 1599fcd6f4aSGavin Shan return NULL; 1609fcd6f4aSGavin Shan } 1619fcd6f4aSGavin Shan 1621e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 163184cd4a3SBenjamin Herrenschmidt { 1641e916772SGavin Shan struct pnv_phb *phb = pe->phb; 165184cd4a3SBenjamin Herrenschmidt 1661e916772SGavin Shan WARN_ON(pe->pdev); 1671e916772SGavin Shan 1681e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 1691e916772SGavin Shan clear_bit(pe->pe_number, phb->ioda.pe_alloc); 170184cd4a3SBenjamin Herrenschmidt } 171184cd4a3SBenjamin Herrenschmidt 172262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 173262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 174262af557SGuo Chao { 175262af557SGuo Chao const char *desc; 176262af557SGuo Chao struct resource *r; 177262af557SGuo Chao s64 rc; 178262af557SGuo Chao 179262af557SGuo Chao /* Configure the default M64 BAR */ 180262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 181262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 182262af557SGuo Chao phb->ioda.m64_bar_idx, 183262af557SGuo Chao phb->ioda.m64_base, 184262af557SGuo Chao 0, /* unused */ 185262af557SGuo Chao phb->ioda.m64_size); 186262af557SGuo Chao if (rc != OPAL_SUCCESS) { 187262af557SGuo Chao desc = "configuring"; 188262af557SGuo Chao goto fail; 189262af557SGuo Chao } 190262af557SGuo Chao 191262af557SGuo Chao /* Enable the default M64 BAR */ 192262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 193262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 194262af557SGuo Chao phb->ioda.m64_bar_idx, 195262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 196262af557SGuo Chao if (rc != OPAL_SUCCESS) { 197262af557SGuo Chao desc = "enabling"; 198262af557SGuo Chao goto fail; 199262af557SGuo Chao } 200262af557SGuo Chao 201262af557SGuo Chao /* 20263803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 20363803c39SGavin Shan * are first or last two PEs. 204262af557SGuo Chao */ 205262af557SGuo Chao r = &phb->hose->mem_resources[1]; 20692b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 20763803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 20892b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 20963803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 210262af557SGuo Chao else 211262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 21292b8f137SGavin Shan phb->ioda.reserved_pe_idx); 213262af557SGuo Chao 214262af557SGuo Chao return 0; 215262af557SGuo Chao 216262af557SGuo Chao fail: 217262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 218262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 219262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 220262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 221262af557SGuo Chao phb->ioda.m64_bar_idx, 222262af557SGuo Chao OPAL_DISABLE_M64); 223262af557SGuo Chao return -EIO; 224262af557SGuo Chao } 225262af557SGuo Chao 226c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 22796a2f92bSGavin Shan unsigned long *pe_bitmap) 228262af557SGuo Chao { 22996a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 23096a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 231262af557SGuo Chao struct resource *r; 23296a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 23396a2f92bSGavin Shan int segno, i; 234262af557SGuo Chao 23596a2f92bSGavin Shan base = phb->ioda.m64_base; 23696a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 23796a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 23896a2f92bSGavin Shan r = &pdev->resource[i]; 2395958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 240262af557SGuo Chao continue; 241262af557SGuo Chao 24296a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 24396a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 24496a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 24596a2f92bSGavin Shan if (pe_bitmap) 24696a2f92bSGavin Shan set_bit(segno, pe_bitmap); 24796a2f92bSGavin Shan else 24896a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 249262af557SGuo Chao } 250262af557SGuo Chao } 251262af557SGuo Chao } 252262af557SGuo Chao 25399451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 25499451551SGavin Shan { 25599451551SGavin Shan struct resource *r; 25699451551SGavin Shan int index; 25799451551SGavin Shan 25899451551SGavin Shan /* 25999451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 26099451551SGavin Shan * there are as many M64 segments as the maximum number of 26199451551SGavin Shan * PEs, which is 128. 26299451551SGavin Shan */ 26399451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 26499451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 26599451551SGavin Shan int64_t rc; 26699451551SGavin Shan 26799451551SGavin Shan base = phb->ioda.m64_base + 26899451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 26999451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 27099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 27199451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 27299451551SGavin Shan if (rc != OPAL_SUCCESS) { 27399451551SGavin Shan pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 27499451551SGavin Shan rc, phb->hose->global_number, index); 27599451551SGavin Shan goto fail; 27699451551SGavin Shan } 27799451551SGavin Shan 27899451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 27999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 28099451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 28199451551SGavin Shan if (rc != OPAL_SUCCESS) { 28299451551SGavin Shan pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 28399451551SGavin Shan rc, phb->hose->global_number, index); 28499451551SGavin Shan goto fail; 28599451551SGavin Shan } 28699451551SGavin Shan } 28799451551SGavin Shan 28899451551SGavin Shan /* 28963803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 29063803c39SGavin Shan * are first or last two PEs. 29199451551SGavin Shan */ 29299451551SGavin Shan r = &phb->hose->mem_resources[1]; 29399451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 29463803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 29599451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 29663803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 29799451551SGavin Shan else 29899451551SGavin Shan WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 29999451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 30099451551SGavin Shan 30199451551SGavin Shan return 0; 30299451551SGavin Shan 30399451551SGavin Shan fail: 30499451551SGavin Shan for ( ; index >= 0; index--) 30599451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 30699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 30799451551SGavin Shan 30899451551SGavin Shan return -EIO; 30999451551SGavin Shan } 31099451551SGavin Shan 311c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 31296a2f92bSGavin Shan unsigned long *pe_bitmap, 31396a2f92bSGavin Shan bool all) 314262af557SGuo Chao { 315262af557SGuo Chao struct pci_dev *pdev; 31696a2f92bSGavin Shan 31796a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 318c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 31996a2f92bSGavin Shan 32096a2f92bSGavin Shan if (all && pdev->subordinate) 321c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 32296a2f92bSGavin Shan pe_bitmap, all); 32396a2f92bSGavin Shan } 32496a2f92bSGavin Shan } 32596a2f92bSGavin Shan 3261e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 327262af557SGuo Chao { 32826ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 32926ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 330262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 331262af557SGuo Chao unsigned long size, *pe_alloc; 33226ba248dSGavin Shan int i; 333262af557SGuo Chao 334262af557SGuo Chao /* Root bus shouldn't use M64 */ 335262af557SGuo Chao if (pci_is_root_bus(bus)) 3361e916772SGavin Shan return NULL; 337262af557SGuo Chao 338262af557SGuo Chao /* Allocate bitmap */ 33992b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 340262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 341262af557SGuo Chao if (!pe_alloc) { 342262af557SGuo Chao pr_warn("%s: Out of memory !\n", 343262af557SGuo Chao __func__); 3441e916772SGavin Shan return NULL; 345262af557SGuo Chao } 346262af557SGuo Chao 34726ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 348c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 349262af557SGuo Chao 350262af557SGuo Chao /* 351262af557SGuo Chao * the current bus might not own M64 window and that's all 352262af557SGuo Chao * contributed by its child buses. For the case, we needn't 353262af557SGuo Chao * pick M64 dependent PE#. 354262af557SGuo Chao */ 35592b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 356262af557SGuo Chao kfree(pe_alloc); 3571e916772SGavin Shan return NULL; 358262af557SGuo Chao } 359262af557SGuo Chao 360262af557SGuo Chao /* 361262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 362262af557SGuo Chao * PE's list to form compound PE. 363262af557SGuo Chao */ 364262af557SGuo Chao master_pe = NULL; 365262af557SGuo Chao i = -1; 36692b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 36792b8f137SGavin Shan phb->ioda.total_pe_num) { 368262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 369262af557SGuo Chao 37093289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 371262af557SGuo Chao if (!master_pe) { 372262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 373262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 374262af557SGuo Chao master_pe = pe; 375262af557SGuo Chao } else { 376262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 377262af557SGuo Chao pe->master = master_pe; 378262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 379262af557SGuo Chao } 38099451551SGavin Shan 38199451551SGavin Shan /* 38299451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 38399451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 38499451551SGavin Shan * between M64 segment and PE#. In order to have same logic 38599451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 38699451551SGavin Shan * segment and PE# on P7IOC. 38799451551SGavin Shan */ 38899451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 38999451551SGavin Shan int64_t rc; 39099451551SGavin Shan 39199451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 39299451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 39399451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 39499451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 39599451551SGavin Shan if (rc != OPAL_SUCCESS) 39699451551SGavin Shan pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 39799451551SGavin Shan __func__, rc, phb->hose->global_number, 39899451551SGavin Shan pe->pe_number); 39999451551SGavin Shan } 400262af557SGuo Chao } 401262af557SGuo Chao 402262af557SGuo Chao kfree(pe_alloc); 4031e916772SGavin Shan return master_pe; 404262af557SGuo Chao } 405262af557SGuo Chao 406262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 407262af557SGuo Chao { 408262af557SGuo Chao struct pci_controller *hose = phb->hose; 409262af557SGuo Chao struct device_node *dn = hose->dn; 410262af557SGuo Chao struct resource *res; 411a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 412262af557SGuo Chao const u32 *r; 413262af557SGuo Chao u64 pci_addr; 414262af557SGuo Chao 41599451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4161665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4171665c4a8SGavin Shan return; 4181665c4a8SGavin Shan } 4191665c4a8SGavin Shan 420e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 421262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 422262af557SGuo Chao return; 423262af557SGuo Chao } 424262af557SGuo Chao 425262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 426262af557SGuo Chao if (!r) { 427262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 428262af557SGuo Chao dn->full_name); 429262af557SGuo Chao return; 430262af557SGuo Chao } 431262af557SGuo Chao 432a1339fafSBenjamin Herrenschmidt /* 433a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 434a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 435a1339fafSBenjamin Herrenschmidt */ 436a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 437a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 438a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 439a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 440a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 441a1339fafSBenjamin Herrenschmidt } 442a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 443a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 444a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 445a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 446a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 447a1339fafSBenjamin Herrenschmidt } 448a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 449a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 450a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 451a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 452a1339fafSBenjamin Herrenschmidt return; 453a1339fafSBenjamin Herrenschmidt } 454a1339fafSBenjamin Herrenschmidt 455a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 456262af557SGuo Chao res = &hose->mem_resources[1]; 457e80c4e7cSGavin Shan res->name = dn->full_name; 458262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 459262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 460262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 461262af557SGuo Chao pci_addr = of_read_number(r, 2); 462262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 463262af557SGuo Chao 464262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 46592b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 466262af557SGuo Chao phb->ioda.m64_base = pci_addr; 467262af557SGuo Chao 468a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 469a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 470a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 471a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 472a1339fafSBenjamin Herrenschmidt 473a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 474a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 475e9863e68SWei Yang 476262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 477a1339fafSBenjamin Herrenschmidt m64_range[1]--; 478a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 479a1339fafSBenjamin Herrenschmidt 480a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 481a1339fafSBenjamin Herrenschmidt 482a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 483a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 484a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 485a1339fafSBenjamin Herrenschmidt 486a1339fafSBenjamin Herrenschmidt /* 487a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 488a1339fafSBenjamin Herrenschmidt * the IODA2 code. 489a1339fafSBenjamin Herrenschmidt */ 49099451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 49199451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 49299451551SGavin Shan else 493262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 494c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 495c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 496262af557SGuo Chao } 497262af557SGuo Chao 49849dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 49949dec922SGavin Shan { 50049dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 50149dec922SGavin Shan struct pnv_ioda_pe *slave; 50249dec922SGavin Shan s64 rc; 50349dec922SGavin Shan 50449dec922SGavin Shan /* Fetch master PE */ 50549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 50649dec922SGavin Shan pe = pe->master; 507ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 508ec8e4e9dSGavin Shan return; 509ec8e4e9dSGavin Shan 51049dec922SGavin Shan pe_no = pe->pe_number; 51149dec922SGavin Shan } 51249dec922SGavin Shan 51349dec922SGavin Shan /* Freeze master PE */ 51449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 51549dec922SGavin Shan pe_no, 51649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 51749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 51849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 51949dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 52049dec922SGavin Shan return; 52149dec922SGavin Shan } 52249dec922SGavin Shan 52349dec922SGavin Shan /* Freeze slave PEs */ 52449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 52549dec922SGavin Shan return; 52649dec922SGavin Shan 52749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 52849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 52949dec922SGavin Shan slave->pe_number, 53049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 53149dec922SGavin Shan if (rc != OPAL_SUCCESS) 53249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 53349dec922SGavin Shan __func__, rc, phb->hose->global_number, 53449dec922SGavin Shan slave->pe_number); 53549dec922SGavin Shan } 53649dec922SGavin Shan } 53749dec922SGavin Shan 538e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 53949dec922SGavin Shan { 54049dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 54149dec922SGavin Shan s64 rc; 54249dec922SGavin Shan 54349dec922SGavin Shan /* Find master PE */ 54449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 54549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 54649dec922SGavin Shan pe = pe->master; 54749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 54849dec922SGavin Shan pe_no = pe->pe_number; 54949dec922SGavin Shan } 55049dec922SGavin Shan 55149dec922SGavin Shan /* Clear frozen state for master PE */ 55249dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 55349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 55449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 55549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 55649dec922SGavin Shan return -EIO; 55749dec922SGavin Shan } 55849dec922SGavin Shan 55949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 56049dec922SGavin Shan return 0; 56149dec922SGavin Shan 56249dec922SGavin Shan /* Clear frozen state for slave PEs */ 56349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 56449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 56549dec922SGavin Shan slave->pe_number, 56649dec922SGavin Shan opt); 56749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 56849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 56949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 57049dec922SGavin Shan slave->pe_number); 57149dec922SGavin Shan return -EIO; 57249dec922SGavin Shan } 57349dec922SGavin Shan } 57449dec922SGavin Shan 57549dec922SGavin Shan return 0; 57649dec922SGavin Shan } 57749dec922SGavin Shan 57849dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 57949dec922SGavin Shan { 58049dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 58149dec922SGavin Shan u8 fstate, state; 58249dec922SGavin Shan __be16 pcierr; 58349dec922SGavin Shan s64 rc; 58449dec922SGavin Shan 58549dec922SGavin Shan /* Sanity check on PE number */ 58692b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 58749dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 58849dec922SGavin Shan 58949dec922SGavin Shan /* 59049dec922SGavin Shan * Fetch the master PE and the PE instance might be 59149dec922SGavin Shan * not initialized yet. 59249dec922SGavin Shan */ 59349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 59449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 59549dec922SGavin Shan pe = pe->master; 59649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 59749dec922SGavin Shan pe_no = pe->pe_number; 59849dec922SGavin Shan } 59949dec922SGavin Shan 60049dec922SGavin Shan /* Check the master PE */ 60149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 60249dec922SGavin Shan &state, &pcierr, NULL); 60349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 60449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 60549dec922SGavin Shan "PHB#%x-PE#%x state\n", 60649dec922SGavin Shan __func__, rc, 60749dec922SGavin Shan phb->hose->global_number, pe_no); 60849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 60949dec922SGavin Shan } 61049dec922SGavin Shan 61149dec922SGavin Shan /* Check the slave PE */ 61249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 61349dec922SGavin Shan return state; 61449dec922SGavin Shan 61549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 61649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 61749dec922SGavin Shan slave->pe_number, 61849dec922SGavin Shan &fstate, 61949dec922SGavin Shan &pcierr, 62049dec922SGavin Shan NULL); 62149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62249dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62349dec922SGavin Shan "PHB#%x-PE#%x state\n", 62449dec922SGavin Shan __func__, rc, 62549dec922SGavin Shan phb->hose->global_number, slave->pe_number); 62649dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 62749dec922SGavin Shan } 62849dec922SGavin Shan 62949dec922SGavin Shan /* 63049dec922SGavin Shan * Override the result based on the ascending 63149dec922SGavin Shan * priority. 63249dec922SGavin Shan */ 63349dec922SGavin Shan if (fstate > state) 63449dec922SGavin Shan state = fstate; 63549dec922SGavin Shan } 63649dec922SGavin Shan 63749dec922SGavin Shan return state; 63849dec922SGavin Shan } 63949dec922SGavin Shan 640184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 641184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 642184cd4a3SBenjamin Herrenschmidt */ 643184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 644f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 645184cd4a3SBenjamin Herrenschmidt { 646184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 647184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 648b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 649184cd4a3SBenjamin Herrenschmidt 650184cd4a3SBenjamin Herrenschmidt if (!pdn) 651184cd4a3SBenjamin Herrenschmidt return NULL; 652184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 653184cd4a3SBenjamin Herrenschmidt return NULL; 654184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 655184cd4a3SBenjamin Herrenschmidt } 656184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 657184cd4a3SBenjamin Herrenschmidt 658b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 659b131a842SGavin Shan struct pnv_ioda_pe *parent, 660b131a842SGavin Shan struct pnv_ioda_pe *child, 661b131a842SGavin Shan bool is_add) 662b131a842SGavin Shan { 663b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 664b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 665b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 666b131a842SGavin Shan struct pnv_ioda_pe *slave; 667b131a842SGavin Shan long rc; 668b131a842SGavin Shan 669b131a842SGavin Shan /* Parent PE affects child PE */ 670b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 671b131a842SGavin Shan child->pe_number, op); 672b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 673b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 674b131a842SGavin Shan rc, desc); 675b131a842SGavin Shan return -ENXIO; 676b131a842SGavin Shan } 677b131a842SGavin Shan 678b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 679b131a842SGavin Shan return 0; 680b131a842SGavin Shan 681b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 682b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 683b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 684b131a842SGavin Shan slave->pe_number, op); 685b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 686b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 687b131a842SGavin Shan rc, desc); 688b131a842SGavin Shan return -ENXIO; 689b131a842SGavin Shan } 690b131a842SGavin Shan } 691b131a842SGavin Shan 692b131a842SGavin Shan return 0; 693b131a842SGavin Shan } 694b131a842SGavin Shan 695b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 696b131a842SGavin Shan struct pnv_ioda_pe *pe, 697b131a842SGavin Shan bool is_add) 698b131a842SGavin Shan { 699b131a842SGavin Shan struct pnv_ioda_pe *slave; 700781a868fSWei Yang struct pci_dev *pdev = NULL; 701b131a842SGavin Shan int ret; 702b131a842SGavin Shan 703b131a842SGavin Shan /* 704b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 705b131a842SGavin Shan * clear slave PE frozen state as well. 706b131a842SGavin Shan */ 707b131a842SGavin Shan if (is_add) { 708b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 709b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 710b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 711b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 712b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 713b131a842SGavin Shan slave->pe_number, 714b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 715b131a842SGavin Shan } 716b131a842SGavin Shan } 717b131a842SGavin Shan 718b131a842SGavin Shan /* 719b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 720b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 721b131a842SGavin Shan * originated from the PE might contribute to other 722b131a842SGavin Shan * PEs. 723b131a842SGavin Shan */ 724b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 725b131a842SGavin Shan if (ret) 726b131a842SGavin Shan return ret; 727b131a842SGavin Shan 728b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 729b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 730b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 731b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 732b131a842SGavin Shan if (ret) 733b131a842SGavin Shan return ret; 734b131a842SGavin Shan } 735b131a842SGavin Shan } 736b131a842SGavin Shan 737b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 738b131a842SGavin Shan pdev = pe->pbus->self; 739781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 740b131a842SGavin Shan pdev = pe->pdev->bus->self; 741781a868fSWei Yang #ifdef CONFIG_PCI_IOV 742781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 743283e2d8aSGavin Shan pdev = pe->parent_dev; 744781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 745b131a842SGavin Shan while (pdev) { 746b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 747b131a842SGavin Shan struct pnv_ioda_pe *parent; 748b131a842SGavin Shan 749b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 750b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 751b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 752b131a842SGavin Shan if (ret) 753b131a842SGavin Shan return ret; 754b131a842SGavin Shan } 755b131a842SGavin Shan 756b131a842SGavin Shan pdev = pdev->bus->self; 757b131a842SGavin Shan } 758b131a842SGavin Shan 759b131a842SGavin Shan return 0; 760b131a842SGavin Shan } 761b131a842SGavin Shan 762781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 763781a868fSWei Yang { 764781a868fSWei Yang struct pci_dev *parent; 765781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 766781a868fSWei Yang int64_t rc; 767781a868fSWei Yang long rid_end, rid; 768781a868fSWei Yang 769781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 770781a868fSWei Yang if (pe->pbus) { 771781a868fSWei Yang int count; 772781a868fSWei Yang 773781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 774781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 775781a868fSWei Yang parent = pe->pbus->self; 776781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 777781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 778781a868fSWei Yang else 779781a868fSWei Yang count = 1; 780781a868fSWei Yang 781781a868fSWei Yang switch(count) { 782781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 783781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 784781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 785781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 786781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 787781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 788781a868fSWei Yang default: 789781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 790781a868fSWei Yang count); 791781a868fSWei Yang /* Do an exact match only */ 792781a868fSWei Yang bcomp = OpalPciBusAll; 793781a868fSWei Yang } 794781a868fSWei Yang rid_end = pe->rid + (count << 8); 795781a868fSWei Yang } else { 79693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 797781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 798781a868fSWei Yang parent = pe->parent_dev; 799781a868fSWei Yang else 80093e01a50SGavin Shan #endif 801781a868fSWei Yang parent = pe->pdev->bus->self; 802781a868fSWei Yang bcomp = OpalPciBusAll; 803781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 804781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 805781a868fSWei Yang rid_end = pe->rid + 1; 806781a868fSWei Yang } 807781a868fSWei Yang 808781a868fSWei Yang /* Clear the reverse map */ 809781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 810c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 811781a868fSWei Yang 812781a868fSWei Yang /* Release from all parents PELT-V */ 813781a868fSWei Yang while (parent) { 814781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 815781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 816781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 817781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 818781a868fSWei Yang /* XXX What to do in case of error ? */ 819781a868fSWei Yang } 820781a868fSWei Yang parent = parent->bus->self; 821781a868fSWei Yang } 822781a868fSWei Yang 823f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 824781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 825781a868fSWei Yang 826781a868fSWei Yang /* Disassociate PE in PELT */ 827781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 828781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 829781a868fSWei Yang if (rc) 830781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 831781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 832781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 833781a868fSWei Yang if (rc) 834781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 835781a868fSWei Yang 836781a868fSWei Yang pe->pbus = NULL; 837781a868fSWei Yang pe->pdev = NULL; 83893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 839781a868fSWei Yang pe->parent_dev = NULL; 84093e01a50SGavin Shan #endif 841781a868fSWei Yang 842781a868fSWei Yang return 0; 843781a868fSWei Yang } 844781a868fSWei Yang 845cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 846184cd4a3SBenjamin Herrenschmidt { 847184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 848184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 849184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 850184cd4a3SBenjamin Herrenschmidt 851184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 852184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 853184cd4a3SBenjamin Herrenschmidt int count; 854184cd4a3SBenjamin Herrenschmidt 855184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 856184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 857184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 858fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 859b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 860fb446ad0SGavin Shan else 861fb446ad0SGavin Shan count = 1; 862fb446ad0SGavin Shan 863184cd4a3SBenjamin Herrenschmidt switch(count) { 864184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 865184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 866184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 867184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 868184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 869184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 870184cd4a3SBenjamin Herrenschmidt default: 871781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 872781a868fSWei Yang count); 873184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 874184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 875184cd4a3SBenjamin Herrenschmidt } 876184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 877184cd4a3SBenjamin Herrenschmidt } else { 878781a868fSWei Yang #ifdef CONFIG_PCI_IOV 879781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 880781a868fSWei Yang parent = pe->parent_dev; 881781a868fSWei Yang else 882781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 883184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 884184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 885184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 886184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 887184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 888184cd4a3SBenjamin Herrenschmidt } 889184cd4a3SBenjamin Herrenschmidt 890631ad691SGavin Shan /* 891631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 892631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 893631ad691SGavin Shan * originated from the PE might contribute to other 894631ad691SGavin Shan * PEs. 895631ad691SGavin Shan */ 896184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 897184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 898184cd4a3SBenjamin Herrenschmidt if (rc) { 899184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 900184cd4a3SBenjamin Herrenschmidt return -ENXIO; 901184cd4a3SBenjamin Herrenschmidt } 902631ad691SGavin Shan 9035d2aa710SAlistair Popple /* 9045d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9055d2aa710SAlistair Popple * configuration on them. 9065d2aa710SAlistair Popple */ 9075d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 908b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 909184cd4a3SBenjamin Herrenschmidt 910184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 911184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 912184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 913184cd4a3SBenjamin Herrenschmidt 914184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9154773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9164773f76bSGavin Shan pe->mve_number = 0; 9174773f76bSGavin Shan goto out; 9184773f76bSGavin Shan } 9194773f76bSGavin Shan 920184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9214773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9224773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 923184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 924184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 925184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 926184cd4a3SBenjamin Herrenschmidt } else { 927184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 928cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 929184cd4a3SBenjamin Herrenschmidt if (rc) { 930184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 931184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 932184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 933184cd4a3SBenjamin Herrenschmidt } 934184cd4a3SBenjamin Herrenschmidt } 935184cd4a3SBenjamin Herrenschmidt 9364773f76bSGavin Shan out: 937184cd4a3SBenjamin Herrenschmidt return 0; 938184cd4a3SBenjamin Herrenschmidt } 939184cd4a3SBenjamin Herrenschmidt 940781a868fSWei Yang #ifdef CONFIG_PCI_IOV 941781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 942781a868fSWei Yang { 943781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 944781a868fSWei Yang int i; 945781a868fSWei Yang struct resource *res, res2; 946781a868fSWei Yang resource_size_t size; 947781a868fSWei Yang u16 num_vfs; 948781a868fSWei Yang 949781a868fSWei Yang if (!dev->is_physfn) 950781a868fSWei Yang return -EINVAL; 951781a868fSWei Yang 952781a868fSWei Yang /* 953781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 954781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 955781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 956781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 957781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 958781a868fSWei Yang * range of PEs the VFs are in. 959781a868fSWei Yang */ 960781a868fSWei Yang num_vfs = pdn->num_vfs; 961781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 962781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 963781a868fSWei Yang if (!res->flags || !res->parent) 964781a868fSWei Yang continue; 965781a868fSWei Yang 966781a868fSWei Yang /* 967781a868fSWei Yang * The actual IOV BAR range is determined by the start address 968781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 969781a868fSWei Yang * make sure that after shifting, the range will not overlap 970781a868fSWei Yang * with another device. 971781a868fSWei Yang */ 972781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 973781a868fSWei Yang res2.flags = res->flags; 974781a868fSWei Yang res2.start = res->start + (size * offset); 975781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 976781a868fSWei Yang 977781a868fSWei Yang if (res2.end > res->end) { 978781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 979781a868fSWei Yang i, &res2, res, num_vfs, offset); 980781a868fSWei Yang return -EBUSY; 981781a868fSWei Yang } 982781a868fSWei Yang } 983781a868fSWei Yang 984781a868fSWei Yang /* 985781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 986781a868fSWei Yang * offset is a positive value. It looks like the device return some 987781a868fSWei Yang * mmio back to the system, which actually no one could use it. 988781a868fSWei Yang */ 989781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 990781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 991781a868fSWei Yang if (!res->flags || !res->parent) 992781a868fSWei Yang continue; 993781a868fSWei Yang 994781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 995781a868fSWei Yang res2 = *res; 996781a868fSWei Yang res->start += size * offset; 997781a868fSWei Yang 99874703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 99974703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 100074703cc4SWei Yang num_vfs, offset); 1001781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1002781a868fSWei Yang } 1003781a868fSWei Yang return 0; 1004781a868fSWei Yang } 1005781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1006781a868fSWei Yang 1007cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1008184cd4a3SBenjamin Herrenschmidt { 1009184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1010184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1011b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1012184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1013184cd4a3SBenjamin Herrenschmidt 1014184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1015184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1016184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1017184cd4a3SBenjamin Herrenschmidt return NULL; 1018184cd4a3SBenjamin Herrenschmidt } 1019184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1020184cd4a3SBenjamin Herrenschmidt return NULL; 1021184cd4a3SBenjamin Herrenschmidt 10221e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10231e916772SGavin Shan if (!pe) { 1024184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 1025184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1026184cd4a3SBenjamin Herrenschmidt return NULL; 1027184cd4a3SBenjamin Herrenschmidt } 1028184cd4a3SBenjamin Herrenschmidt 1029184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1030184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1031184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1032184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1033184cd4a3SBenjamin Herrenschmidt * 1034184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1035184cd4a3SBenjamin Herrenschmidt */ 1036184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 1037184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 10381e916772SGavin Shan pdn->pe_number = pe->pe_number; 10395d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1040184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1041184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1042184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1043184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1044184cd4a3SBenjamin Herrenschmidt 1045184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1046184cd4a3SBenjamin Herrenschmidt 1047184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1048184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10491e916772SGavin Shan pnv_ioda_free_pe(pe); 1050184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1051184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1052184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1053184cd4a3SBenjamin Herrenschmidt return NULL; 1054184cd4a3SBenjamin Herrenschmidt } 1055184cd4a3SBenjamin Herrenschmidt 10561d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10571d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10581d4e89cfSAlexey Kardashevskiy 1059184cd4a3SBenjamin Herrenschmidt return pe; 1060184cd4a3SBenjamin Herrenschmidt } 1061184cd4a3SBenjamin Herrenschmidt 1062184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1063184cd4a3SBenjamin Herrenschmidt { 1064184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1065184cd4a3SBenjamin Herrenschmidt 1066184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1067b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1068184cd4a3SBenjamin Herrenschmidt 1069184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1070184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1071184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1072184cd4a3SBenjamin Herrenschmidt continue; 1073184cd4a3SBenjamin Herrenschmidt } 1074ccd1c191SGavin Shan 1075ccd1c191SGavin Shan /* 1076ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1077ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1078ccd1c191SGavin Shan * again. 1079ccd1c191SGavin Shan */ 1080ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1081ccd1c191SGavin Shan continue; 1082ccd1c191SGavin Shan 1083c5f7700bSGavin Shan pe->device_count++; 108494973b24SAlistair Popple pdn->pcidev = dev; 1085184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1086fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1087184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1088184cd4a3SBenjamin Herrenschmidt } 1089184cd4a3SBenjamin Herrenschmidt } 1090184cd4a3SBenjamin Herrenschmidt 1091fb446ad0SGavin Shan /* 1092fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1093fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1094fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1095fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1096fb446ad0SGavin Shan */ 10971e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1098184cd4a3SBenjamin Herrenschmidt { 1099fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1100184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11011e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1102ccd1c191SGavin Shan unsigned int pe_num; 1103ccd1c191SGavin Shan 1104ccd1c191SGavin Shan /* 1105ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1106ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1107ccd1c191SGavin Shan */ 1108ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1109ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1110ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1111ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1112ccd1c191SGavin Shan return NULL; 1113ccd1c191SGavin Shan } 1114184cd4a3SBenjamin Herrenschmidt 111563803c39SGavin Shan /* PE number for root bus should have been reserved */ 111663803c39SGavin Shan if (pci_is_root_bus(bus) && 111763803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 111863803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 111963803c39SGavin Shan 1120262af557SGuo Chao /* Check if PE is determined by M64 */ 112163803c39SGavin Shan if (!pe && phb->pick_m64_pe) 11221e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1123262af557SGuo Chao 1124262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11251e916772SGavin Shan if (!pe) 11261e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1127262af557SGuo Chao 11281e916772SGavin Shan if (!pe) { 1129fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1130fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11311e916772SGavin Shan return NULL; 1132184cd4a3SBenjamin Herrenschmidt } 1133184cd4a3SBenjamin Herrenschmidt 1134262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1135184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1136184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1137184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1138b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1139184cd4a3SBenjamin Herrenschmidt 1140fb446ad0SGavin Shan if (all) 1141fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 11421e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1143fb446ad0SGavin Shan else 1144fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 11451e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1146184cd4a3SBenjamin Herrenschmidt 1147184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1148184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11491e916772SGavin Shan pnv_ioda_free_pe(pe); 1150184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11511e916772SGavin Shan return NULL; 1152184cd4a3SBenjamin Herrenschmidt } 1153184cd4a3SBenjamin Herrenschmidt 1154184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1155184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1156184cd4a3SBenjamin Herrenschmidt 11577ebdf956SGavin Shan /* Put PE to the list */ 11587ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11591e916772SGavin Shan 11601e916772SGavin Shan return pe; 1161184cd4a3SBenjamin Herrenschmidt } 1162184cd4a3SBenjamin Herrenschmidt 1163b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11645d2aa710SAlistair Popple { 1165b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1166b521549aSAlistair Popple long rid; 1167b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1168b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1169b521549aSAlistair Popple struct pci_dn *npu_pdn; 1170b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1171b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1172b521549aSAlistair Popple 1173b521549aSAlistair Popple /* 1174b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1175b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1176b521549aSAlistair Popple * which need to be assigned to four links, implying some 1177b521549aSAlistair Popple * links must share PEs. 1178b521549aSAlistair Popple * 1179b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1180b521549aSAlistair Popple * same GPU get assigned the same PE. 1181b521549aSAlistair Popple */ 1182b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 118392b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1184b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1185b521549aSAlistair Popple if (!pe->pdev) 1186b521549aSAlistair Popple continue; 1187b521549aSAlistair Popple 1188b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1189b521549aSAlistair Popple /* 1190b521549aSAlistair Popple * This device has the same peer GPU so should 1191b521549aSAlistair Popple * be assigned the same PE as the existing 1192b521549aSAlistair Popple * peer NPU. 1193b521549aSAlistair Popple */ 1194b521549aSAlistair Popple dev_info(&npu_pdev->dev, 1195b521549aSAlistair Popple "Associating to existing PE %d\n", pe_num); 1196b521549aSAlistair Popple pci_dev_get(npu_pdev); 1197b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1198b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1199b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1200b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1201b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1202b521549aSAlistair Popple 1203b521549aSAlistair Popple /* Map the PE to this link */ 1204b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1205b521549aSAlistair Popple OpalPciBusAll, 1206b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1207b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1208b521549aSAlistair Popple OPAL_MAP_PE); 1209b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1210b521549aSAlistair Popple found_pe = true; 1211b521549aSAlistair Popple break; 1212b521549aSAlistair Popple } 1213b521549aSAlistair Popple } 1214b521549aSAlistair Popple 1215b521549aSAlistair Popple if (!found_pe) 1216b521549aSAlistair Popple /* 1217b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1218b521549aSAlistair Popple * one. 1219b521549aSAlistair Popple */ 1220b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1221b521549aSAlistair Popple else 1222b521549aSAlistair Popple return pe; 1223b521549aSAlistair Popple } 1224b521549aSAlistair Popple 1225b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1226b521549aSAlistair Popple { 12275d2aa710SAlistair Popple struct pci_dev *pdev; 12285d2aa710SAlistair Popple 12295d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1230b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12315d2aa710SAlistair Popple } 12325d2aa710SAlistair Popple 1233cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1234fb446ad0SGavin Shan { 1235fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1236262af557SGuo Chao struct pnv_phb *phb; 1237fb446ad0SGavin Shan 1238fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1239262af557SGuo Chao phb = hose->private_data; 124008f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 124108f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 124208f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1243b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 1244ccd1c191SGavin Shan } 1245fb446ad0SGavin Shan } 1246fb446ad0SGavin Shan } 1247184cd4a3SBenjamin Herrenschmidt 1248a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1249ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1250781a868fSWei Yang { 1251781a868fSWei Yang struct pci_bus *bus; 1252781a868fSWei Yang struct pci_controller *hose; 1253781a868fSWei Yang struct pnv_phb *phb; 1254781a868fSWei Yang struct pci_dn *pdn; 125502639b0eSWei Yang int i, j; 1256ee8222feSWei Yang int m64_bars; 1257781a868fSWei Yang 1258781a868fSWei Yang bus = pdev->bus; 1259781a868fSWei Yang hose = pci_bus_to_host(bus); 1260781a868fSWei Yang phb = hose->private_data; 1261781a868fSWei Yang pdn = pci_get_pdn(pdev); 1262781a868fSWei Yang 1263ee8222feSWei Yang if (pdn->m64_single_mode) 1264ee8222feSWei Yang m64_bars = num_vfs; 1265ee8222feSWei Yang else 1266ee8222feSWei Yang m64_bars = 1; 1267ee8222feSWei Yang 126802639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1269ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1270ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1271781a868fSWei Yang continue; 1272781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1273ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1274ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1275ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1276781a868fSWei Yang } 1277781a868fSWei Yang 1278ee8222feSWei Yang kfree(pdn->m64_map); 1279781a868fSWei Yang return 0; 1280781a868fSWei Yang } 1281781a868fSWei Yang 128202639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1283781a868fSWei Yang { 1284781a868fSWei Yang struct pci_bus *bus; 1285781a868fSWei Yang struct pci_controller *hose; 1286781a868fSWei Yang struct pnv_phb *phb; 1287781a868fSWei Yang struct pci_dn *pdn; 1288781a868fSWei Yang unsigned int win; 1289781a868fSWei Yang struct resource *res; 129002639b0eSWei Yang int i, j; 1291781a868fSWei Yang int64_t rc; 129202639b0eSWei Yang int total_vfs; 129302639b0eSWei Yang resource_size_t size, start; 129402639b0eSWei Yang int pe_num; 1295ee8222feSWei Yang int m64_bars; 1296781a868fSWei Yang 1297781a868fSWei Yang bus = pdev->bus; 1298781a868fSWei Yang hose = pci_bus_to_host(bus); 1299781a868fSWei Yang phb = hose->private_data; 1300781a868fSWei Yang pdn = pci_get_pdn(pdev); 130102639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1302781a868fSWei Yang 1303ee8222feSWei Yang if (pdn->m64_single_mode) 1304ee8222feSWei Yang m64_bars = num_vfs; 1305ee8222feSWei Yang else 1306ee8222feSWei Yang m64_bars = 1; 130702639b0eSWei Yang 1308ee8222feSWei Yang pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1309ee8222feSWei Yang if (!pdn->m64_map) 1310ee8222feSWei Yang return -ENOMEM; 1311ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1312ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1313ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1314ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1315ee8222feSWei Yang 1316781a868fSWei Yang 1317781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1318781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1319781a868fSWei Yang if (!res->flags || !res->parent) 1320781a868fSWei Yang continue; 1321781a868fSWei Yang 1322ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1323781a868fSWei Yang do { 1324781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1325781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1326781a868fSWei Yang 1327781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1328781a868fSWei Yang goto m64_failed; 1329781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1330781a868fSWei Yang 1331ee8222feSWei Yang pdn->m64_map[j][i] = win; 133202639b0eSWei Yang 1333ee8222feSWei Yang if (pdn->m64_single_mode) { 133402639b0eSWei Yang size = pci_iov_resource_size(pdev, 133502639b0eSWei Yang PCI_IOV_RESOURCES + i); 133602639b0eSWei Yang start = res->start + size * j; 133702639b0eSWei Yang } else { 133802639b0eSWei Yang size = resource_size(res); 133902639b0eSWei Yang start = res->start; 134002639b0eSWei Yang } 1341781a868fSWei Yang 1342781a868fSWei Yang /* Map the M64 here */ 1343ee8222feSWei Yang if (pdn->m64_single_mode) { 1344be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 134502639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 134602639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1347ee8222feSWei Yang pdn->m64_map[j][i], 0); 134802639b0eSWei Yang } 134902639b0eSWei Yang 1350781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1351781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1352ee8222feSWei Yang pdn->m64_map[j][i], 135302639b0eSWei Yang start, 1354781a868fSWei Yang 0, /* unused */ 135502639b0eSWei Yang size); 135602639b0eSWei Yang 135702639b0eSWei Yang 1358781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1359781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1360781a868fSWei Yang win, rc); 1361781a868fSWei Yang goto m64_failed; 1362781a868fSWei Yang } 1363781a868fSWei Yang 1364ee8222feSWei Yang if (pdn->m64_single_mode) 1365781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1366ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 136702639b0eSWei Yang else 136802639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1369ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 137002639b0eSWei Yang 1371781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1372781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1373781a868fSWei Yang win, rc); 1374781a868fSWei Yang goto m64_failed; 1375781a868fSWei Yang } 1376781a868fSWei Yang } 137702639b0eSWei Yang } 1378781a868fSWei Yang return 0; 1379781a868fSWei Yang 1380781a868fSWei Yang m64_failed: 1381ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1382781a868fSWei Yang return -EBUSY; 1383781a868fSWei Yang } 1384781a868fSWei Yang 1385c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1386c035e37bSAlexey Kardashevskiy int num); 1387c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1388c035e37bSAlexey Kardashevskiy 1389781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1390781a868fSWei Yang { 1391781a868fSWei Yang struct iommu_table *tbl; 1392781a868fSWei Yang int64_t rc; 1393781a868fSWei Yang 1394b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1395c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1396781a868fSWei Yang if (rc) 1397781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1398781a868fSWei Yang 1399c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14000eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14010eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14020eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1403ac9a5889SAlexey Kardashevskiy } 1404aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1405781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1406781a868fSWei Yang } 1407781a868fSWei Yang 1408ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1409781a868fSWei Yang { 1410781a868fSWei Yang struct pci_bus *bus; 1411781a868fSWei Yang struct pci_controller *hose; 1412781a868fSWei Yang struct pnv_phb *phb; 1413781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1414781a868fSWei Yang struct pci_dn *pdn; 1415781a868fSWei Yang 1416781a868fSWei Yang bus = pdev->bus; 1417781a868fSWei Yang hose = pci_bus_to_host(bus); 1418781a868fSWei Yang phb = hose->private_data; 141902639b0eSWei Yang pdn = pci_get_pdn(pdev); 1420781a868fSWei Yang 1421781a868fSWei Yang if (!pdev->is_physfn) 1422781a868fSWei Yang return; 1423781a868fSWei Yang 1424781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1425781a868fSWei Yang if (pe->parent_dev != pdev) 1426781a868fSWei Yang continue; 1427781a868fSWei Yang 1428781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1429781a868fSWei Yang 1430781a868fSWei Yang /* Remove from list */ 1431781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1432781a868fSWei Yang list_del(&pe->list); 1433781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1434781a868fSWei Yang 1435781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1436781a868fSWei Yang 14371e916772SGavin Shan pnv_ioda_free_pe(pe); 1438781a868fSWei Yang } 1439781a868fSWei Yang } 1440781a868fSWei Yang 1441781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1442781a868fSWei Yang { 1443781a868fSWei Yang struct pci_bus *bus; 1444781a868fSWei Yang struct pci_controller *hose; 1445781a868fSWei Yang struct pnv_phb *phb; 14461e916772SGavin Shan struct pnv_ioda_pe *pe; 1447781a868fSWei Yang struct pci_dn *pdn; 1448781a868fSWei Yang struct pci_sriov *iov; 1449be283eebSWei Yang u16 num_vfs, i; 1450781a868fSWei Yang 1451781a868fSWei Yang bus = pdev->bus; 1452781a868fSWei Yang hose = pci_bus_to_host(bus); 1453781a868fSWei Yang phb = hose->private_data; 1454781a868fSWei Yang pdn = pci_get_pdn(pdev); 1455781a868fSWei Yang iov = pdev->sriov; 1456781a868fSWei Yang num_vfs = pdn->num_vfs; 1457781a868fSWei Yang 1458781a868fSWei Yang /* Release VF PEs */ 1459ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1460781a868fSWei Yang 1461781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1462ee8222feSWei Yang if (!pdn->m64_single_mode) 1463be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1464781a868fSWei Yang 1465781a868fSWei Yang /* Release M64 windows */ 1466ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1467781a868fSWei Yang 1468781a868fSWei Yang /* Release PE numbers */ 1469be283eebSWei Yang if (pdn->m64_single_mode) { 1470be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 14711e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 14721e916772SGavin Shan continue; 14731e916772SGavin Shan 14741e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 14751e916772SGavin Shan pnv_ioda_free_pe(pe); 1476be283eebSWei Yang } 1477be283eebSWei Yang } else 1478be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1479be283eebSWei Yang /* Releasing pe_num_map */ 1480be283eebSWei Yang kfree(pdn->pe_num_map); 1481781a868fSWei Yang } 1482781a868fSWei Yang } 1483781a868fSWei Yang 1484781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1485781a868fSWei Yang struct pnv_ioda_pe *pe); 1486781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1487781a868fSWei Yang { 1488781a868fSWei Yang struct pci_bus *bus; 1489781a868fSWei Yang struct pci_controller *hose; 1490781a868fSWei Yang struct pnv_phb *phb; 1491781a868fSWei Yang struct pnv_ioda_pe *pe; 1492781a868fSWei Yang int pe_num; 1493781a868fSWei Yang u16 vf_index; 1494781a868fSWei Yang struct pci_dn *pdn; 1495781a868fSWei Yang 1496781a868fSWei Yang bus = pdev->bus; 1497781a868fSWei Yang hose = pci_bus_to_host(bus); 1498781a868fSWei Yang phb = hose->private_data; 1499781a868fSWei Yang pdn = pci_get_pdn(pdev); 1500781a868fSWei Yang 1501781a868fSWei Yang if (!pdev->is_physfn) 1502781a868fSWei Yang return; 1503781a868fSWei Yang 1504781a868fSWei Yang /* Reserve PE for each VF */ 1505781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1506be283eebSWei Yang if (pdn->m64_single_mode) 1507be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1508be283eebSWei Yang else 1509be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1510781a868fSWei Yang 1511781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1512781a868fSWei Yang pe->pe_number = pe_num; 1513781a868fSWei Yang pe->phb = phb; 1514781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1515781a868fSWei Yang pe->pbus = NULL; 1516781a868fSWei Yang pe->parent_dev = pdev; 1517781a868fSWei Yang pe->mve_number = -1; 1518781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1519781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1520781a868fSWei Yang 1521781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1522781a868fSWei Yang hose->global_number, pdev->bus->number, 1523781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1524781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1525781a868fSWei Yang 1526781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1527781a868fSWei Yang /* XXX What do we do here ? */ 15281e916772SGavin Shan pnv_ioda_free_pe(pe); 1529781a868fSWei Yang pe->pdev = NULL; 1530781a868fSWei Yang continue; 1531781a868fSWei Yang } 1532781a868fSWei Yang 1533781a868fSWei Yang /* Put PE to the list */ 1534781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1535781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1536781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1537781a868fSWei Yang 1538781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1539781a868fSWei Yang } 1540781a868fSWei Yang } 1541781a868fSWei Yang 1542781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1543781a868fSWei Yang { 1544781a868fSWei Yang struct pci_bus *bus; 1545781a868fSWei Yang struct pci_controller *hose; 1546781a868fSWei Yang struct pnv_phb *phb; 15471e916772SGavin Shan struct pnv_ioda_pe *pe; 1548781a868fSWei Yang struct pci_dn *pdn; 1549781a868fSWei Yang int ret; 1550be283eebSWei Yang u16 i; 1551781a868fSWei Yang 1552781a868fSWei Yang bus = pdev->bus; 1553781a868fSWei Yang hose = pci_bus_to_host(bus); 1554781a868fSWei Yang phb = hose->private_data; 1555781a868fSWei Yang pdn = pci_get_pdn(pdev); 1556781a868fSWei Yang 1557781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1558b0331854SWei Yang if (!pdn->vfs_expanded) { 1559b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1560b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1561b0331854SWei Yang return -ENOSPC; 1562b0331854SWei Yang } 1563b0331854SWei Yang 1564ee8222feSWei Yang /* 1565ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1566ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1567ee8222feSWei Yang */ 1568ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1569ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1570ee8222feSWei Yang return -EBUSY; 1571ee8222feSWei Yang } 1572ee8222feSWei Yang 1573be283eebSWei Yang /* Allocating pe_num_map */ 1574be283eebSWei Yang if (pdn->m64_single_mode) 1575be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1576be283eebSWei Yang GFP_KERNEL); 1577be283eebSWei Yang else 1578be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1579be283eebSWei Yang 1580be283eebSWei Yang if (!pdn->pe_num_map) 1581be283eebSWei Yang return -ENOMEM; 1582be283eebSWei Yang 1583be283eebSWei Yang if (pdn->m64_single_mode) 1584be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1585be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1586be283eebSWei Yang 1587781a868fSWei Yang /* Calculate available PE for required VFs */ 1588be283eebSWei Yang if (pdn->m64_single_mode) { 1589be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15901e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 15911e916772SGavin Shan if (!pe) { 1592be283eebSWei Yang ret = -EBUSY; 1593be283eebSWei Yang goto m64_failed; 1594be283eebSWei Yang } 15951e916772SGavin Shan 15961e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1597be283eebSWei Yang } 1598be283eebSWei Yang } else { 1599781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1600be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 160192b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1602781a868fSWei Yang 0, num_vfs, 0); 160392b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1604781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1605781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1606be283eebSWei Yang kfree(pdn->pe_num_map); 1607781a868fSWei Yang return -EBUSY; 1608781a868fSWei Yang } 1609be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1610781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1611be283eebSWei Yang } 1612be283eebSWei Yang pdn->num_vfs = num_vfs; 1613781a868fSWei Yang 1614781a868fSWei Yang /* Assign M64 window accordingly */ 161502639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1616781a868fSWei Yang if (ret) { 1617781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1618781a868fSWei Yang goto m64_failed; 1619781a868fSWei Yang } 1620781a868fSWei Yang 1621781a868fSWei Yang /* 1622781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1623781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1624781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1625781a868fSWei Yang */ 1626ee8222feSWei Yang if (!pdn->m64_single_mode) { 1627be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1628781a868fSWei Yang if (ret) 1629781a868fSWei Yang goto m64_failed; 1630781a868fSWei Yang } 163102639b0eSWei Yang } 1632781a868fSWei Yang 1633781a868fSWei Yang /* Setup VF PEs */ 1634781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1635781a868fSWei Yang 1636781a868fSWei Yang return 0; 1637781a868fSWei Yang 1638781a868fSWei Yang m64_failed: 1639be283eebSWei Yang if (pdn->m64_single_mode) { 1640be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16411e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16421e916772SGavin Shan continue; 16431e916772SGavin Shan 16441e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16451e916772SGavin Shan pnv_ioda_free_pe(pe); 1646be283eebSWei Yang } 1647be283eebSWei Yang } else 1648be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1649be283eebSWei Yang 1650be283eebSWei Yang /* Releasing pe_num_map */ 1651be283eebSWei Yang kfree(pdn->pe_num_map); 1652781a868fSWei Yang 1653781a868fSWei Yang return ret; 1654781a868fSWei Yang } 1655781a868fSWei Yang 1656a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1657a8b2f828SGavin Shan { 1658781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1659781a868fSWei Yang 1660a8b2f828SGavin Shan /* Release PCI data */ 1661a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1662a8b2f828SGavin Shan return 0; 1663a8b2f828SGavin Shan } 1664a8b2f828SGavin Shan 1665a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1666a8b2f828SGavin Shan { 1667a8b2f828SGavin Shan /* Allocate PCI data */ 1668a8b2f828SGavin Shan add_dev_pci_data(pdev); 1669781a868fSWei Yang 1670ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1671a8b2f828SGavin Shan } 1672a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1673a8b2f828SGavin Shan 1674959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1675184cd4a3SBenjamin Herrenschmidt { 1676b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1677959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1678184cd4a3SBenjamin Herrenschmidt 1679959c9bddSGavin Shan /* 1680959c9bddSGavin Shan * The function can be called while the PE# 1681959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1682959c9bddSGavin Shan * case. 1683959c9bddSGavin Shan */ 1684959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1685959c9bddSGavin Shan return; 1686184cd4a3SBenjamin Herrenschmidt 1687959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1688cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 16890e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1690b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 16914617082eSAlexey Kardashevskiy /* 16924617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 16934617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 16944617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 16954617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 16964617082eSAlexey Kardashevskiy */ 1697184cd4a3SBenjamin Herrenschmidt } 1698184cd4a3SBenjamin Herrenschmidt 1699763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1700cd15b048SBenjamin Herrenschmidt { 1701763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1702763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1703cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1704cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1705cd15b048SBenjamin Herrenschmidt uint64_t top; 1706cd15b048SBenjamin Herrenschmidt bool bypass = false; 1707cd15b048SBenjamin Herrenschmidt 1708cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1709cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1710cd15b048SBenjamin Herrenschmidt 1711cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1712cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1713cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1714cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1715cd15b048SBenjamin Herrenschmidt } 1716cd15b048SBenjamin Herrenschmidt 1717cd15b048SBenjamin Herrenschmidt if (bypass) { 1718cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1719cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1720cd15b048SBenjamin Herrenschmidt } else { 1721cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1722cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1723cd15b048SBenjamin Herrenschmidt } 1724a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 17255d2aa710SAlistair Popple 17265d2aa710SAlistair Popple /* Update peer npu devices */ 1727f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 17285d2aa710SAlistair Popple 1729cd15b048SBenjamin Herrenschmidt return 0; 1730cd15b048SBenjamin Herrenschmidt } 1731cd15b048SBenjamin Herrenschmidt 173253522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1733fe7e85c6SGavin Shan { 173453522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 173553522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1736fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1737fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1738fe7e85c6SGavin Shan u64 end, mask; 1739fe7e85c6SGavin Shan 1740fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1741fe7e85c6SGavin Shan return 0; 1742fe7e85c6SGavin Shan 1743fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1744fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1745fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1746fe7e85c6SGavin Shan 1747fe7e85c6SGavin Shan 1748fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1749fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1750fe7e85c6SGavin Shan mask += mask - 1; 1751fe7e85c6SGavin Shan 1752fe7e85c6SGavin Shan return mask; 1753fe7e85c6SGavin Shan } 1754fe7e85c6SGavin Shan 1755dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1756ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 175774251fe2SBenjamin Herrenschmidt { 175874251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 175974251fe2SBenjamin Herrenschmidt 176074251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1761b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1762e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 17634617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1764dff4a39eSGavin Shan 17655c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1766ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 176774251fe2SBenjamin Herrenschmidt } 176874251fe2SBenjamin Herrenschmidt } 176974251fe2SBenjamin Herrenschmidt 1770fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1771fd141d1aSBenjamin Herrenschmidt bool real_mode) 1772fd141d1aSBenjamin Herrenschmidt { 1773fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1774fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1775fd141d1aSBenjamin Herrenschmidt } 1776fd141d1aSBenjamin Herrenschmidt 1777a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1778decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 17794cce9550SGavin Shan { 17800eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 17810eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 17820eaf4defSAlexey Kardashevskiy next); 17830eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1784b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1785fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 17864cce9550SGavin Shan unsigned long start, end, inc; 17874cce9550SGavin Shan 1788decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1789decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1790decbda25SAlexey Kardashevskiy npages - 1); 17914cce9550SGavin Shan 17924cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 17934cce9550SGavin Shan start |= (1ull << 63); 17944cce9550SGavin Shan end |= (1ull << 63); 17954cce9550SGavin Shan inc = 16; 17964cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17974cce9550SGavin Shan 17984cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17994cce9550SGavin Shan while (start <= end) { 18008e0a1611SAlexey Kardashevskiy if (rm) 18013ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18028e0a1611SAlexey Kardashevskiy else 18033a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18044cce9550SGavin Shan start += inc; 18054cce9550SGavin Shan } 18064cce9550SGavin Shan 18074cce9550SGavin Shan /* 18084cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 18094cce9550SGavin Shan * and we don't care on free() 18104cce9550SGavin Shan */ 18114cce9550SGavin Shan } 18124cce9550SGavin Shan 1813decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1814decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1815decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 181600085f1eSKrzysztof Kozlowski unsigned long attrs) 1817decbda25SAlexey Kardashevskiy { 1818decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1819decbda25SAlexey Kardashevskiy attrs); 1820decbda25SAlexey Kardashevskiy 182108acce1cSBenjamin Herrenschmidt if (!ret) 1822a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1823decbda25SAlexey Kardashevskiy 1824decbda25SAlexey Kardashevskiy return ret; 1825decbda25SAlexey Kardashevskiy } 1826decbda25SAlexey Kardashevskiy 182705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 182805c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 182905c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 183005c6cfb9SAlexey Kardashevskiy { 183105c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 183205c6cfb9SAlexey Kardashevskiy 183308acce1cSBenjamin Herrenschmidt if (!ret) 1834a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 183505c6cfb9SAlexey Kardashevskiy 183605c6cfb9SAlexey Kardashevskiy return ret; 183705c6cfb9SAlexey Kardashevskiy } 183805c6cfb9SAlexey Kardashevskiy #endif 183905c6cfb9SAlexey Kardashevskiy 1840decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1841decbda25SAlexey Kardashevskiy long npages) 1842decbda25SAlexey Kardashevskiy { 1843decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1844decbda25SAlexey Kardashevskiy 1845a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1846decbda25SAlexey Kardashevskiy } 1847decbda25SAlexey Kardashevskiy 1848da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1849decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 185005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 185105c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 185205c6cfb9SAlexey Kardashevskiy #endif 1853decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1854da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1855da004c36SAlexey Kardashevskiy }; 1856da004c36SAlexey Kardashevskiy 1857a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1858a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1859a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1860bef9253fSAlexey Kardashevskiy 1861a34ab7c3SBenjamin Herrenschmidt void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 18620bbcdb43SAlexey Kardashevskiy { 1863fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1864a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 18650bbcdb43SAlexey Kardashevskiy 18660bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 18670bbcdb43SAlexey Kardashevskiy if (rm) 1868fd141d1aSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(val), invalidate); 18690bbcdb43SAlexey Kardashevskiy else 1870fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 18710bbcdb43SAlexey Kardashevskiy } 18720bbcdb43SAlexey Kardashevskiy 1873a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 18745780fb04SAlexey Kardashevskiy { 18755780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1876fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1877a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 18785780fb04SAlexey Kardashevskiy 18795780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1880fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 18815780fb04SAlexey Kardashevskiy } 18825780fb04SAlexey Kardashevskiy 1883fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1884fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1885fd141d1aSBenjamin Herrenschmidt unsigned long npages) 18864cce9550SGavin Shan { 18874d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 18884cce9550SGavin Shan unsigned long start, end, inc; 18894cce9550SGavin Shan 18904cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1891a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1892fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 18934cce9550SGavin Shan end = start; 18944cce9550SGavin Shan 18954cce9550SGavin Shan /* Figure out the start, end and step */ 1896decbda25SAlexey Kardashevskiy start |= (index << shift); 1897decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1898b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 18994cce9550SGavin Shan mb(); 19004cce9550SGavin Shan 19014cce9550SGavin Shan while (start <= end) { 19028e0a1611SAlexey Kardashevskiy if (rm) 19033ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 19048e0a1611SAlexey Kardashevskiy else 19053a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 19064cce9550SGavin Shan start += inc; 19074cce9550SGavin Shan } 19084cce9550SGavin Shan } 19094cce9550SGavin Shan 1910f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1911f0228c41SBenjamin Herrenschmidt { 1912f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1913f0228c41SBenjamin Herrenschmidt 1914f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1915f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1916f0228c41SBenjamin Herrenschmidt else 1917f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1918f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1919f0228c41SBenjamin Herrenschmidt } 1920f0228c41SBenjamin Herrenschmidt 1921e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1922e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1923e57080f1SAlexey Kardashevskiy { 1924e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1925e57080f1SAlexey Kardashevskiy 1926e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1927e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1928e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1929f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1930f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1931f0228c41SBenjamin Herrenschmidt 1932f0228c41SBenjamin Herrenschmidt if (phb->type == PNV_PHB_NPU) { 19330bbcdb43SAlexey Kardashevskiy /* 19340bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 19350bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 19360bbcdb43SAlexey Kardashevskiy * the entire cache for it. 19370bbcdb43SAlexey Kardashevskiy */ 1938f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 19395d2aa710SAlistair Popple continue; 19405d2aa710SAlistair Popple } 1941f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1942f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 194385674868SAlexey Kardashevskiy index, npages); 1944f0228c41SBenjamin Herrenschmidt else if (rm) 1945f0228c41SBenjamin Herrenschmidt opal_rm_pci_tce_kill(phb->opal_id, 1946f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1947f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1948f0228c41SBenjamin Herrenschmidt index << shift, npages); 1949f0228c41SBenjamin Herrenschmidt else 1950f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 1951f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1952f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1953f0228c41SBenjamin Herrenschmidt index << shift, npages); 1954e57080f1SAlexey Kardashevskiy } 1955e57080f1SAlexey Kardashevskiy } 1956e57080f1SAlexey Kardashevskiy 1957decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1958decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1959decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 196000085f1eSKrzysztof Kozlowski unsigned long attrs) 19614cce9550SGavin Shan { 1962decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1963decbda25SAlexey Kardashevskiy attrs); 19644cce9550SGavin Shan 196508acce1cSBenjamin Herrenschmidt if (!ret) 1966decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1967decbda25SAlexey Kardashevskiy 1968decbda25SAlexey Kardashevskiy return ret; 1969decbda25SAlexey Kardashevskiy } 1970decbda25SAlexey Kardashevskiy 197105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 197205c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 197305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 197405c6cfb9SAlexey Kardashevskiy { 197505c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 197605c6cfb9SAlexey Kardashevskiy 197708acce1cSBenjamin Herrenschmidt if (!ret) 197805c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 197905c6cfb9SAlexey Kardashevskiy 198005c6cfb9SAlexey Kardashevskiy return ret; 198105c6cfb9SAlexey Kardashevskiy } 198205c6cfb9SAlexey Kardashevskiy #endif 198305c6cfb9SAlexey Kardashevskiy 1984decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1985decbda25SAlexey Kardashevskiy long npages) 1986decbda25SAlexey Kardashevskiy { 1987decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1988decbda25SAlexey Kardashevskiy 1989decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 19904cce9550SGavin Shan } 19914cce9550SGavin Shan 19924793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 19934793d65dSAlexey Kardashevskiy { 19944793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 19954793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19964793d65dSAlexey Kardashevskiy } 19974793d65dSAlexey Kardashevskiy 1998da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1999decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 200005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 200105c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 200205c6cfb9SAlexey Kardashevskiy #endif 2003decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2004da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 20054793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 2006da004c36SAlexey Kardashevskiy }; 2007da004c36SAlexey Kardashevskiy 2008801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2009801846d1SGavin Shan { 2010801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2011801846d1SGavin Shan 2012801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2013801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2014801846d1SGavin Shan */ 2015801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2016801846d1SGavin Shan return 0; 2017801846d1SGavin Shan 2018801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2019801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2020801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2021801846d1SGavin Shan *weight += 3; 2022801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2023801846d1SGavin Shan *weight += 15; 2024801846d1SGavin Shan else 2025801846d1SGavin Shan *weight += 10; 2026801846d1SGavin Shan 2027801846d1SGavin Shan return 0; 2028801846d1SGavin Shan } 2029801846d1SGavin Shan 2030801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2031801846d1SGavin Shan { 2032801846d1SGavin Shan unsigned int weight = 0; 2033801846d1SGavin Shan 2034801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2035801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2036801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2037801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2038801846d1SGavin Shan return weight; 2039801846d1SGavin Shan } 2040801846d1SGavin Shan #endif 2041801846d1SGavin Shan 2042801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2043801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2044801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2045801846d1SGavin Shan struct pci_dev *pdev; 2046801846d1SGavin Shan 2047801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2048801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2049801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2050801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2051801846d1SGavin Shan } 2052801846d1SGavin Shan 2053801846d1SGavin Shan return weight; 2054801846d1SGavin Shan } 2055801846d1SGavin Shan 2056b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 20572b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2058184cd4a3SBenjamin Herrenschmidt { 2059184cd4a3SBenjamin Herrenschmidt 2060184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2061184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 20622b923ed1SGavin Shan unsigned int weight, total_weight = 0; 20632b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2064184cd4a3SBenjamin Herrenschmidt int64_t rc; 2065184cd4a3SBenjamin Herrenschmidt void *addr; 2066184cd4a3SBenjamin Herrenschmidt 2067184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2068184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2069184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 20702b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 20712b923ed1SGavin Shan if (!weight) 20722b923ed1SGavin Shan return; 2073184cd4a3SBenjamin Herrenschmidt 20742b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 20752b923ed1SGavin Shan &total_weight); 20762b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 20772b923ed1SGavin Shan if (!segs) 20782b923ed1SGavin Shan segs = 1; 20792b923ed1SGavin Shan 20802b923ed1SGavin Shan /* 20812b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 20822b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 20832b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 20842b923ed1SGavin Shan * is allocated successfully. 20852b923ed1SGavin Shan */ 20862b923ed1SGavin Shan do { 20872b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 20882b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 20892b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 20902b923ed1SGavin Shan IODA_INVALID_PE) 20912b923ed1SGavin Shan avail++; 20922b923ed1SGavin Shan } 20932b923ed1SGavin Shan 20942b923ed1SGavin Shan if (avail == segs) 20952b923ed1SGavin Shan goto found; 20962b923ed1SGavin Shan } 20972b923ed1SGavin Shan } while (--segs); 20982b923ed1SGavin Shan 20992b923ed1SGavin Shan if (!segs) { 21002b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 21012b923ed1SGavin Shan return; 21022b923ed1SGavin Shan } 21032b923ed1SGavin Shan 21042b923ed1SGavin Shan found: 21050eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 2106b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2107b348aa65SAlexey Kardashevskiy pe->pe_number); 21080eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2109c5773822SAlexey Kardashevskiy 2110184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 21112b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 21122b923ed1SGavin Shan weight, total_weight, base, segs); 2113184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2114acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2115acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2116184cd4a3SBenjamin Herrenschmidt 2117184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2118184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2119184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2120184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2121acce971cSGavin Shan * 2122acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2123acce971cSGavin Shan * bytes 2124184cd4a3SBenjamin Herrenschmidt */ 2125acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2126184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2127acce971cSGavin Shan get_order(tce32_segsz * segs)); 2128184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2129184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2130184cd4a3SBenjamin Herrenschmidt goto fail; 2131184cd4a3SBenjamin Herrenschmidt } 2132184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2133acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2134184cd4a3SBenjamin Herrenschmidt 2135184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2136184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2137184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2138184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2139184cd4a3SBenjamin Herrenschmidt base + i, 1, 2140acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2141acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2142184cd4a3SBenjamin Herrenschmidt if (rc) { 2143184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2144184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2145184cd4a3SBenjamin Herrenschmidt goto fail; 2146184cd4a3SBenjamin Herrenschmidt } 2147184cd4a3SBenjamin Herrenschmidt } 2148184cd4a3SBenjamin Herrenschmidt 21492b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 21502b923ed1SGavin Shan for (i = base; i < base + segs; i++) 21512b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 21522b923ed1SGavin Shan 2153184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2154acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2155acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2156acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2157184cd4a3SBenjamin Herrenschmidt 2158da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 21594793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 21604793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2161184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2162184cd4a3SBenjamin Herrenschmidt 2163781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 21644617082eSAlexey Kardashevskiy /* 21654617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 21664617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 21674617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 21684617082eSAlexey Kardashevskiy */ 21694617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 21704617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2171c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2172ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 217374251fe2SBenjamin Herrenschmidt 2174184cd4a3SBenjamin Herrenschmidt return; 2175184cd4a3SBenjamin Herrenschmidt fail: 2176184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2177184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2178acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 21790eaf4defSAlexey Kardashevskiy if (tbl) { 21800eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 21810eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 21820eaf4defSAlexey Kardashevskiy } 2183184cd4a3SBenjamin Herrenschmidt } 2184184cd4a3SBenjamin Herrenschmidt 218543cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 218643cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 218743cb60abSAlexey Kardashevskiy { 218843cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 218943cb60abSAlexey Kardashevskiy table_group); 219043cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 219143cb60abSAlexey Kardashevskiy int64_t rc; 2192bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2193bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 219443cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 219543cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 219643cb60abSAlexey Kardashevskiy 21974793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 219843cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 219943cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 220043cb60abSAlexey Kardashevskiy 220143cb60abSAlexey Kardashevskiy /* 220243cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 220343cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 220443cb60abSAlexey Kardashevskiy */ 220543cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 220643cb60abSAlexey Kardashevskiy pe->pe_number, 22074793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2208bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 220943cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2210bbb845c4SAlexey Kardashevskiy size << 3, 221143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 221243cb60abSAlexey Kardashevskiy if (rc) { 221343cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 221443cb60abSAlexey Kardashevskiy return rc; 221543cb60abSAlexey Kardashevskiy } 221643cb60abSAlexey Kardashevskiy 221743cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 221843cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2219a34ab7c3SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 222043cb60abSAlexey Kardashevskiy 222143cb60abSAlexey Kardashevskiy return 0; 222243cb60abSAlexey Kardashevskiy } 222343cb60abSAlexey Kardashevskiy 2224f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2225cd15b048SBenjamin Herrenschmidt { 2226cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2227cd15b048SBenjamin Herrenschmidt int64_t rc; 2228cd15b048SBenjamin Herrenschmidt 2229cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2230cd15b048SBenjamin Herrenschmidt if (enable) { 2231cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2232cd15b048SBenjamin Herrenschmidt 2233cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2234cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2235cd15b048SBenjamin Herrenschmidt pe->pe_number, 2236cd15b048SBenjamin Herrenschmidt window_id, 2237cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2238cd15b048SBenjamin Herrenschmidt top); 2239cd15b048SBenjamin Herrenschmidt } else { 2240cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2241cd15b048SBenjamin Herrenschmidt pe->pe_number, 2242cd15b048SBenjamin Herrenschmidt window_id, 2243cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2244cd15b048SBenjamin Herrenschmidt 0); 2245cd15b048SBenjamin Herrenschmidt } 2246cd15b048SBenjamin Herrenschmidt if (rc) 2247cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2248cd15b048SBenjamin Herrenschmidt else 2249cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2250cd15b048SBenjamin Herrenschmidt } 2251cd15b048SBenjamin Herrenschmidt 22524793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 22534793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 22544793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 22554793d65dSAlexey Kardashevskiy 22564793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 22574793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 22584793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 22594793d65dSAlexey Kardashevskiy { 22604793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 22614793d65dSAlexey Kardashevskiy table_group); 22624793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 22634793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 22644793d65dSAlexey Kardashevskiy long ret; 22654793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 22664793d65dSAlexey Kardashevskiy 22674793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 22684793d65dSAlexey Kardashevskiy if (!tbl) 22694793d65dSAlexey Kardashevskiy return -ENOMEM; 22704793d65dSAlexey Kardashevskiy 22714793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 22724793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 22734793d65dSAlexey Kardashevskiy levels, tbl); 22744793d65dSAlexey Kardashevskiy if (ret) { 22754793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 22764793d65dSAlexey Kardashevskiy return ret; 22774793d65dSAlexey Kardashevskiy } 22784793d65dSAlexey Kardashevskiy 22794793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 22804793d65dSAlexey Kardashevskiy 22814793d65dSAlexey Kardashevskiy *ptbl = tbl; 22824793d65dSAlexey Kardashevskiy 22834793d65dSAlexey Kardashevskiy return 0; 22844793d65dSAlexey Kardashevskiy } 22854793d65dSAlexey Kardashevskiy 228646d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 228746d3e1e1SAlexey Kardashevskiy { 228846d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 228946d3e1e1SAlexey Kardashevskiy long rc; 229046d3e1e1SAlexey Kardashevskiy 2291bb005455SNishanth Aravamudan /* 2292fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2293fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2294fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2295fa144869SNishanth Aravamudan */ 2296fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2297fa144869SNishanth Aravamudan 2298fa144869SNishanth Aravamudan /* 2299bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2300bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2301bb005455SNishanth Aravamudan * cause errors later. 2302bb005455SNishanth Aravamudan */ 2303fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2304bb005455SNishanth Aravamudan 230546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 230646d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2307bb005455SNishanth Aravamudan window_size, 230846d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 230946d3e1e1SAlexey Kardashevskiy if (rc) { 231046d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 231146d3e1e1SAlexey Kardashevskiy rc); 231246d3e1e1SAlexey Kardashevskiy return rc; 231346d3e1e1SAlexey Kardashevskiy } 231446d3e1e1SAlexey Kardashevskiy 231546d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 231646d3e1e1SAlexey Kardashevskiy 231746d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 231846d3e1e1SAlexey Kardashevskiy if (rc) { 231946d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 232046d3e1e1SAlexey Kardashevskiy rc); 232146d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 232246d3e1e1SAlexey Kardashevskiy return rc; 232346d3e1e1SAlexey Kardashevskiy } 232446d3e1e1SAlexey Kardashevskiy 232546d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 232646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 232746d3e1e1SAlexey Kardashevskiy 232846d3e1e1SAlexey Kardashevskiy /* 232946d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 233046d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 233146d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 233246d3e1e1SAlexey Kardashevskiy */ 233346d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 233446d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 233546d3e1e1SAlexey Kardashevskiy 233646d3e1e1SAlexey Kardashevskiy return 0; 233746d3e1e1SAlexey Kardashevskiy } 233846d3e1e1SAlexey Kardashevskiy 2339b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2340b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2341b5926430SAlexey Kardashevskiy int num) 2342b5926430SAlexey Kardashevskiy { 2343b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2344b5926430SAlexey Kardashevskiy table_group); 2345b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2346b5926430SAlexey Kardashevskiy long ret; 2347b5926430SAlexey Kardashevskiy 2348b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2349b5926430SAlexey Kardashevskiy 2350b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2351b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2352b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2353b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2354b5926430SAlexey Kardashevskiy if (ret) 2355b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2356b5926430SAlexey Kardashevskiy else 2357a34ab7c3SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2358b5926430SAlexey Kardashevskiy 2359b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2360b5926430SAlexey Kardashevskiy 2361b5926430SAlexey Kardashevskiy return ret; 2362b5926430SAlexey Kardashevskiy } 2363b5926430SAlexey Kardashevskiy #endif 2364b5926430SAlexey Kardashevskiy 2365f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 236600547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 236700547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 236800547193SAlexey Kardashevskiy { 236900547193SAlexey Kardashevskiy unsigned long bytes = 0; 237000547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 237100547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 237200547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 237300547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 237400547193SAlexey Kardashevskiy unsigned long direct_table_size; 237500547193SAlexey Kardashevskiy 237600547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 237700547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 237800547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 237900547193SAlexey Kardashevskiy return 0; 238000547193SAlexey Kardashevskiy 238100547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 238200547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 238300547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 238400547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 238500547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 238600547193SAlexey Kardashevskiy 238700547193SAlexey Kardashevskiy for ( ; levels; --levels) { 238800547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 238900547193SAlexey Kardashevskiy 239000547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 239100547193SAlexey Kardashevskiy tce_table_size <<= 3; 239200547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 239300547193SAlexey Kardashevskiy } 239400547193SAlexey Kardashevskiy 239500547193SAlexey Kardashevskiy return bytes; 239600547193SAlexey Kardashevskiy } 239700547193SAlexey Kardashevskiy 2398f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2399cd15b048SBenjamin Herrenschmidt { 2400f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2401f87a8864SAlexey Kardashevskiy table_group); 240246d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 240346d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2404cd15b048SBenjamin Herrenschmidt 2405f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 240646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 240746d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2408cd15b048SBenjamin Herrenschmidt } 2409cd15b048SBenjamin Herrenschmidt 2410f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2411f87a8864SAlexey Kardashevskiy { 2412f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2413f87a8864SAlexey Kardashevskiy table_group); 2414f87a8864SAlexey Kardashevskiy 241546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2416f87a8864SAlexey Kardashevskiy } 2417f87a8864SAlexey Kardashevskiy 2418f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 241900547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 24204793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 24214793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 24224793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2423f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2424f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2425f87a8864SAlexey Kardashevskiy }; 2426b5cb9ab1SAlexey Kardashevskiy 2427b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2428b5cb9ab1SAlexey Kardashevskiy { 2429b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2430b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2431b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2432b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2433b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2434b5cb9ab1SAlexey Kardashevskiy 2435b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2436b5cb9ab1SAlexey Kardashevskiy return 0; 2437b5cb9ab1SAlexey Kardashevskiy 2438b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2439b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2440b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2441b5cb9ab1SAlexey Kardashevskiy return 0; 2442b5cb9ab1SAlexey Kardashevskiy 2443b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2444b5cb9ab1SAlexey Kardashevskiy 2445b5cb9ab1SAlexey Kardashevskiy return 1; 2446b5cb9ab1SAlexey Kardashevskiy } 2447b5cb9ab1SAlexey Kardashevskiy 2448b5cb9ab1SAlexey Kardashevskiy /* 2449b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2450b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2451b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2452b5cb9ab1SAlexey Kardashevskiy */ 2453b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2454b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2455b5cb9ab1SAlexey Kardashevskiy { 2456b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2457b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2458b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2459b5cb9ab1SAlexey Kardashevskiy 2460b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2461b5cb9ab1SAlexey Kardashevskiy 2462b5cb9ab1SAlexey Kardashevskiy return npe; 2463b5cb9ab1SAlexey Kardashevskiy } 2464b5cb9ab1SAlexey Kardashevskiy 2465b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2466b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2467b5cb9ab1SAlexey Kardashevskiy { 2468b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2469b5cb9ab1SAlexey Kardashevskiy 2470b5cb9ab1SAlexey Kardashevskiy if (ret) 2471b5cb9ab1SAlexey Kardashevskiy return ret; 2472b5cb9ab1SAlexey Kardashevskiy 2473b5cb9ab1SAlexey Kardashevskiy ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2474b5cb9ab1SAlexey Kardashevskiy if (ret) 2475b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2476b5cb9ab1SAlexey Kardashevskiy 2477b5cb9ab1SAlexey Kardashevskiy return ret; 2478b5cb9ab1SAlexey Kardashevskiy } 2479b5cb9ab1SAlexey Kardashevskiy 2480b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2481b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2482b5cb9ab1SAlexey Kardashevskiy int num) 2483b5cb9ab1SAlexey Kardashevskiy { 2484b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2485b5cb9ab1SAlexey Kardashevskiy 2486b5cb9ab1SAlexey Kardashevskiy if (ret) 2487b5cb9ab1SAlexey Kardashevskiy return ret; 2488b5cb9ab1SAlexey Kardashevskiy 2489b5cb9ab1SAlexey Kardashevskiy return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2490b5cb9ab1SAlexey Kardashevskiy } 2491b5cb9ab1SAlexey Kardashevskiy 2492b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2493b5cb9ab1SAlexey Kardashevskiy { 2494b5cb9ab1SAlexey Kardashevskiy /* 2495b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2496b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2497b5cb9ab1SAlexey Kardashevskiy */ 2498b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2499b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2500b5cb9ab1SAlexey Kardashevskiy } 2501b5cb9ab1SAlexey Kardashevskiy 2502b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2503b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2504b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2505b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2506b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2507b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2508b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2509b5cb9ab1SAlexey Kardashevskiy }; 2510b5cb9ab1SAlexey Kardashevskiy 2511b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2512b5cb9ab1SAlexey Kardashevskiy { 2513b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2514b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2515b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2516b5cb9ab1SAlexey Kardashevskiy 2517b5cb9ab1SAlexey Kardashevskiy /* 2518b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2519b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2520b5cb9ab1SAlexey Kardashevskiy */ 2521b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2522b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2523b5cb9ab1SAlexey Kardashevskiy 2524b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2525b5cb9ab1SAlexey Kardashevskiy continue; 2526b5cb9ab1SAlexey Kardashevskiy 2527b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2528b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2529b5cb9ab1SAlexey Kardashevskiy if (gpe) 2530b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2531b5cb9ab1SAlexey Kardashevskiy } 2532b5cb9ab1SAlexey Kardashevskiy } 2533b5cb9ab1SAlexey Kardashevskiy } 2534b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2535b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2536f87a8864SAlexey Kardashevskiy #endif 2537f87a8864SAlexey Kardashevskiy 2538bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2539bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 25403ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2541aca6913fSAlexey Kardashevskiy { 2542aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2543bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2544aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2545bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2546bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2547bbb845c4SAlexey Kardashevskiy long i; 2548aca6913fSAlexey Kardashevskiy 2549aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2550aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2551aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2552aca6913fSAlexey Kardashevskiy return NULL; 2553aca6913fSAlexey Kardashevskiy } 2554aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2555bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 25563ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2557bbb845c4SAlexey Kardashevskiy 2558bbb845c4SAlexey Kardashevskiy --levels; 2559bbb845c4SAlexey Kardashevskiy if (!levels) { 2560bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2561bbb845c4SAlexey Kardashevskiy return addr; 2562bbb845c4SAlexey Kardashevskiy } 2563bbb845c4SAlexey Kardashevskiy 2564bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2565bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 25663ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2567bbb845c4SAlexey Kardashevskiy if (!tmp) 2568bbb845c4SAlexey Kardashevskiy break; 2569bbb845c4SAlexey Kardashevskiy 2570bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2571bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2572bbb845c4SAlexey Kardashevskiy 2573bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2574bbb845c4SAlexey Kardashevskiy break; 2575bbb845c4SAlexey Kardashevskiy } 2576aca6913fSAlexey Kardashevskiy 2577aca6913fSAlexey Kardashevskiy return addr; 2578aca6913fSAlexey Kardashevskiy } 2579aca6913fSAlexey Kardashevskiy 2580bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2581bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2582bbb845c4SAlexey Kardashevskiy 2583aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2584bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2585bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2586aca6913fSAlexey Kardashevskiy { 2587aca6913fSAlexey Kardashevskiy void *addr; 25883ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2589aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2590aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2591aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2592aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2593aca6913fSAlexey Kardashevskiy 2594bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2595bbb845c4SAlexey Kardashevskiy return -EINVAL; 2596bbb845c4SAlexey Kardashevskiy 2597aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2598aca6913fSAlexey Kardashevskiy return -EINVAL; 2599aca6913fSAlexey Kardashevskiy 2600bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2601bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2602bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2603bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2604bbb845c4SAlexey Kardashevskiy 2605aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2606bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 26073ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2608bbb845c4SAlexey Kardashevskiy 2609bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2610aca6913fSAlexey Kardashevskiy if (!addr) 2611aca6913fSAlexey Kardashevskiy return -ENOMEM; 2612aca6913fSAlexey Kardashevskiy 2613bbb845c4SAlexey Kardashevskiy /* 2614bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2615bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2616bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2617bbb845c4SAlexey Kardashevskiy */ 2618bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2619bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2620bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2621bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2622bbb845c4SAlexey Kardashevskiy } 2623bbb845c4SAlexey Kardashevskiy 2624aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2625aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2626aca6913fSAlexey Kardashevskiy page_shift); 2627bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2628bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 26293ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2630aca6913fSAlexey Kardashevskiy 2631aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2632aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2633aca6913fSAlexey Kardashevskiy 2634aca6913fSAlexey Kardashevskiy return 0; 2635aca6913fSAlexey Kardashevskiy } 2636aca6913fSAlexey Kardashevskiy 2637bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2638bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2639bbb845c4SAlexey Kardashevskiy { 2640bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2641bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2642bbb845c4SAlexey Kardashevskiy 2643bbb845c4SAlexey Kardashevskiy if (level) { 2644bbb845c4SAlexey Kardashevskiy long i; 2645bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2646bbb845c4SAlexey Kardashevskiy 2647bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2648bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2649bbb845c4SAlexey Kardashevskiy 2650bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2651bbb845c4SAlexey Kardashevskiy continue; 2652bbb845c4SAlexey Kardashevskiy 2653bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2654bbb845c4SAlexey Kardashevskiy level - 1); 2655bbb845c4SAlexey Kardashevskiy } 2656bbb845c4SAlexey Kardashevskiy } 2657bbb845c4SAlexey Kardashevskiy 2658bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2659bbb845c4SAlexey Kardashevskiy } 2660bbb845c4SAlexey Kardashevskiy 2661aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2662aca6913fSAlexey Kardashevskiy { 2663bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2664bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2665bbb845c4SAlexey Kardashevskiy 2666aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2667aca6913fSAlexey Kardashevskiy return; 2668aca6913fSAlexey Kardashevskiy 2669bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2670bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2671aca6913fSAlexey Kardashevskiy } 2672aca6913fSAlexey Kardashevskiy 2673373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2674373f5657SGavin Shan struct pnv_ioda_pe *pe) 2675373f5657SGavin Shan { 2676373f5657SGavin Shan int64_t rc; 2677373f5657SGavin Shan 2678ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2679ccd1c191SGavin Shan return; 2680ccd1c191SGavin Shan 2681f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2682f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2683f87a8864SAlexey Kardashevskiy 2684b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2685b348aa65SAlexey Kardashevskiy pe->pe_number); 2686c5773822SAlexey Kardashevskiy 2687373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2688373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2689aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2690373f5657SGavin Shan 2691e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 26924793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 26934793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 26944793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 26954793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 26964793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 26974793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2698e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2699e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2700e5aad1e6SAlexey Kardashevskiy #endif 2701e5aad1e6SAlexey Kardashevskiy 270246d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2703801846d1SGavin Shan if (rc) 270446d3e1e1SAlexey Kardashevskiy return; 270546d3e1e1SAlexey Kardashevskiy 270646d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 270746d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 270846d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 270946d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2710373f5657SGavin Shan } 2711373f5657SGavin Shan 2712184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 27134ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2714137436c9SGavin Shan { 2715137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2716137436c9SGavin Shan ioda.irq_chip); 2717137436c9SGavin Shan 27184ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 27194ee11c1aSSuresh Warrier } 27204ee11c1aSSuresh Warrier 27214ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 27224ee11c1aSSuresh Warrier { 27234ee11c1aSSuresh Warrier int64_t rc; 27244ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 27254ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 27264ee11c1aSSuresh Warrier 27274ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2728137436c9SGavin Shan WARN_ON_ONCE(rc); 2729137436c9SGavin Shan 2730137436c9SGavin Shan icp_native_eoi(d); 2731137436c9SGavin Shan } 2732137436c9SGavin Shan 2733fd9a1c26SIan Munsie 2734f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2735fd9a1c26SIan Munsie { 2736fd9a1c26SIan Munsie struct irq_data *idata; 2737fd9a1c26SIan Munsie struct irq_chip *ichip; 2738fd9a1c26SIan Munsie 2739fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2740fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2741fd9a1c26SIan Munsie return; 2742fd9a1c26SIan Munsie 2743fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2744fd9a1c26SIan Munsie /* 2745fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2746fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2747fd9a1c26SIan Munsie */ 2748fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2749fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2750fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2751fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2752fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2753fd9a1c26SIan Munsie } 2754fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2755fd9a1c26SIan Munsie } 2756fd9a1c26SIan Munsie 27574ee11c1aSSuresh Warrier /* 27584ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 27594ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 27604ee11c1aSSuresh Warrier */ 27614ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 27624ee11c1aSSuresh Warrier { 27634ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 27644ee11c1aSSuresh Warrier } 27654ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 27664ee11c1aSSuresh Warrier 2767184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2768137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2769137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2770184cd4a3SBenjamin Herrenschmidt { 2771184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2772184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 27733a1a4661SBenjamin Herrenschmidt __be32 data; 2774184cd4a3SBenjamin Herrenschmidt int rc; 2775184cd4a3SBenjamin Herrenschmidt 2776184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2777184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2778184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2779184cd4a3SBenjamin Herrenschmidt 2780184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2781184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2782184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2783184cd4a3SBenjamin Herrenschmidt 2784b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 278536074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2786b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2787b72c1f65SBenjamin Herrenschmidt 2788184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2789184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2790184cd4a3SBenjamin Herrenschmidt if (rc) { 2791184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2792184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2793184cd4a3SBenjamin Herrenschmidt return -EIO; 2794184cd4a3SBenjamin Herrenschmidt } 2795184cd4a3SBenjamin Herrenschmidt 2796184cd4a3SBenjamin Herrenschmidt if (is_64) { 27973a1a4661SBenjamin Herrenschmidt __be64 addr64; 27983a1a4661SBenjamin Herrenschmidt 2799184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2800184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2801184cd4a3SBenjamin Herrenschmidt if (rc) { 2802184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2803184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2804184cd4a3SBenjamin Herrenschmidt return -EIO; 2805184cd4a3SBenjamin Herrenschmidt } 28063a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28073a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2808184cd4a3SBenjamin Herrenschmidt } else { 28093a1a4661SBenjamin Herrenschmidt __be32 addr32; 28103a1a4661SBenjamin Herrenschmidt 2811184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2812184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2813184cd4a3SBenjamin Herrenschmidt if (rc) { 2814184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2815184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2816184cd4a3SBenjamin Herrenschmidt return -EIO; 2817184cd4a3SBenjamin Herrenschmidt } 2818184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28193a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2820184cd4a3SBenjamin Herrenschmidt } 28213a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2822184cd4a3SBenjamin Herrenschmidt 2823f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2824137436c9SGavin Shan 2825184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2826184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2827184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2828184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2829184cd4a3SBenjamin Herrenschmidt 2830184cd4a3SBenjamin Herrenschmidt return 0; 2831184cd4a3SBenjamin Herrenschmidt } 2832184cd4a3SBenjamin Herrenschmidt 2833184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2834184cd4a3SBenjamin Herrenschmidt { 2835fb1b55d6SGavin Shan unsigned int count; 2836184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2837184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2838184cd4a3SBenjamin Herrenschmidt if (!prop) { 2839184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2840184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2841184cd4a3SBenjamin Herrenschmidt } 2842184cd4a3SBenjamin Herrenschmidt if (!prop) 2843184cd4a3SBenjamin Herrenschmidt return; 2844184cd4a3SBenjamin Herrenschmidt 2845184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2846fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2847fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2848184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2849184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2850184cd4a3SBenjamin Herrenschmidt return; 2851184cd4a3SBenjamin Herrenschmidt } 2852fb1b55d6SGavin Shan 2853184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2854184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2855184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2856fb1b55d6SGavin Shan count, phb->msi_base); 2857184cd4a3SBenjamin Herrenschmidt } 2858184cd4a3SBenjamin Herrenschmidt #else 2859184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2860184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2861184cd4a3SBenjamin Herrenschmidt 28626e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 28636e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 28646e628c7dSWei Yang { 2865f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2866f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2867f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 28686e628c7dSWei Yang struct resource *res; 28696e628c7dSWei Yang int i; 2870dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 28716e628c7dSWei Yang struct pci_dn *pdn; 28725b88ec22SWei Yang int mul, total_vfs; 28736e628c7dSWei Yang 28746e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 28756e628c7dSWei Yang return; 28766e628c7dSWei Yang 28776e628c7dSWei Yang pdn = pci_get_pdn(pdev); 28786e628c7dSWei Yang pdn->vfs_expanded = 0; 2879ee8222feSWei Yang pdn->m64_single_mode = false; 28806e628c7dSWei Yang 28815b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 288292b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2883dfcc8d45SWei Yang total_vf_bar_sz = 0; 28845b88ec22SWei Yang 28855b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 28865b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 28875b88ec22SWei Yang if (!res->flags || res->parent) 28885b88ec22SWei Yang continue; 28895958d19aSBenjamin Herrenschmidt if (!pnv_pci_is_m64(phb, res)) { 2890b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2891b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 28925b88ec22SWei Yang i, res); 2893b0331854SWei Yang goto truncate_iov; 28945b88ec22SWei Yang } 28955b88ec22SWei Yang 2896dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2897dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 28985b88ec22SWei Yang 2899f2dd0afeSWei Yang /* 2900f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2901f2dd0afeSWei Yang * power of two. 2902f2dd0afeSWei Yang * 2903f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2904f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2905f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2906f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2907f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2908f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2909f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2910f2dd0afeSWei Yang */ 2911dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29125b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2913dfcc8d45SWei Yang dev_info(&pdev->dev, 2914dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2915dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2916ee8222feSWei Yang pdn->m64_single_mode = true; 29175b88ec22SWei Yang break; 29185b88ec22SWei Yang } 29195b88ec22SWei Yang } 29205b88ec22SWei Yang 29216e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29226e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29236e628c7dSWei Yang if (!res->flags || res->parent) 29246e628c7dSWei Yang continue; 29256e628c7dSWei Yang 29266e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2927ee8222feSWei Yang /* 2928ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2929ee8222feSWei Yang * mode is 32MB. 2930ee8222feSWei Yang */ 2931ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2932ee8222feSWei Yang goto truncate_iov; 2933ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29345b88ec22SWei Yang res->end = res->start + size * mul - 1; 29356e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 29366e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 29375b88ec22SWei Yang i, res, mul); 29386e628c7dSWei Yang } 29395b88ec22SWei Yang pdn->vfs_expanded = mul; 2940b0331854SWei Yang 2941b0331854SWei Yang return; 2942b0331854SWei Yang 2943b0331854SWei Yang truncate_iov: 2944b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2945b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2946b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2947b0331854SWei Yang res->flags = 0; 2948b0331854SWei Yang res->end = res->start - 1; 2949b0331854SWei Yang } 29506e628c7dSWei Yang } 29516e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 29526e628c7dSWei Yang 295323e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 295423e79425SGavin Shan struct resource *res) 295511685becSGavin Shan { 295623e79425SGavin Shan struct pnv_phb *phb = pe->phb; 295711685becSGavin Shan struct pci_bus_region region; 295823e79425SGavin Shan int index; 295923e79425SGavin Shan int64_t rc; 296011685becSGavin Shan 296123e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 296223e79425SGavin Shan return; 296311685becSGavin Shan 296411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 296511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 296611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 296711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 296811685becSGavin Shan 296992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 297011685becSGavin Shan region.start <= region.end) { 297111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 297211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 297311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 297411685becSGavin Shan if (rc != OPAL_SUCCESS) { 297523e79425SGavin Shan pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 297611685becSGavin Shan __func__, rc, index, pe->pe_number); 297711685becSGavin Shan break; 297811685becSGavin Shan } 297911685becSGavin Shan 298011685becSGavin Shan region.start += phb->ioda.io_segsize; 298111685becSGavin Shan index++; 298211685becSGavin Shan } 2983027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 29845958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 298511685becSGavin Shan region.start = res->start - 298623e79425SGavin Shan phb->hose->mem_offset[0] - 298711685becSGavin Shan phb->ioda.m32_pci_base; 298811685becSGavin Shan region.end = res->end - 298923e79425SGavin Shan phb->hose->mem_offset[0] - 299011685becSGavin Shan phb->ioda.m32_pci_base; 299111685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 299211685becSGavin Shan 299392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 299411685becSGavin Shan region.start <= region.end) { 299511685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 299611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 299711685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 299811685becSGavin Shan if (rc != OPAL_SUCCESS) { 299923e79425SGavin Shan pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 300011685becSGavin Shan __func__, rc, index, pe->pe_number); 300111685becSGavin Shan break; 300211685becSGavin Shan } 300311685becSGavin Shan 300411685becSGavin Shan region.start += phb->ioda.m32_segsize; 300511685becSGavin Shan index++; 300611685becSGavin Shan } 300711685becSGavin Shan } 300811685becSGavin Shan } 300923e79425SGavin Shan 301023e79425SGavin Shan /* 301123e79425SGavin Shan * This function is supposed to be called on basis of PE from top 301223e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 301323e79425SGavin Shan * parent PE could be overrided by its child PEs if necessary. 301423e79425SGavin Shan */ 301523e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 301623e79425SGavin Shan { 301769d733e7SGavin Shan struct pci_dev *pdev; 301823e79425SGavin Shan int i; 301923e79425SGavin Shan 302023e79425SGavin Shan /* 302123e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 302223e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 302323e79425SGavin Shan * be figured out later. 302423e79425SGavin Shan */ 302523e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 302623e79425SGavin Shan 302769d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 302869d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 302969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 303069d733e7SGavin Shan 303169d733e7SGavin Shan /* 303269d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 303369d733e7SGavin Shan * windows of the child bridges should be mapped to 303469d733e7SGavin Shan * the PE as well. 303569d733e7SGavin Shan */ 303669d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 303769d733e7SGavin Shan continue; 303869d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 303969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 304069d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 304169d733e7SGavin Shan } 304211685becSGavin Shan } 304311685becSGavin Shan 304437c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 304537c367f2SGavin Shan { 304637c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 304737c367f2SGavin Shan struct pci_controller *hose, *tmp; 304837c367f2SGavin Shan struct pnv_phb *phb; 304937c367f2SGavin Shan char name[16]; 305037c367f2SGavin Shan 305137c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 305237c367f2SGavin Shan phb = hose->private_data; 305337c367f2SGavin Shan 3054ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3055ccd1c191SGavin Shan phb->initialized = 1; 3056ccd1c191SGavin Shan 305737c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 305837c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 305937c367f2SGavin Shan if (!phb->dbgfs) 306037c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 306137c367f2SGavin Shan __func__, hose->global_number); 306237c367f2SGavin Shan } 306337c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 306437c367f2SGavin Shan } 306537c367f2SGavin Shan 3066cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3067fb446ad0SGavin Shan { 3068fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3069ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 307037c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 307137c367f2SGavin Shan 3072e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3073e9cc17d4SGavin Shan eeh_init(); 3074dadcd6d6SMike Qiu eeh_addr_cache_build(); 3075e9cc17d4SGavin Shan #endif 3076fb446ad0SGavin Shan } 3077fb446ad0SGavin Shan 3078271fd03aSGavin Shan /* 3079271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3080271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3081271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3082271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3083271fd03aSGavin Shan * 1MiB for memory) will be returned. 3084271fd03aSGavin Shan * 3085271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3086271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3087271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3088271fd03aSGavin Shan * resources. 3089271fd03aSGavin Shan */ 3090271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3091271fd03aSGavin Shan unsigned long type) 3092271fd03aSGavin Shan { 3093271fd03aSGavin Shan struct pci_dev *bridge; 3094271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3095271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3096271fd03aSGavin Shan int num_pci_bridges = 0; 3097271fd03aSGavin Shan 3098271fd03aSGavin Shan bridge = bus->self; 3099271fd03aSGavin Shan while (bridge) { 3100271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3101271fd03aSGavin Shan num_pci_bridges++; 3102271fd03aSGavin Shan if (num_pci_bridges >= 2) 3103271fd03aSGavin Shan return 1; 3104271fd03aSGavin Shan } 3105271fd03aSGavin Shan 3106271fd03aSGavin Shan bridge = bridge->bus->self; 3107271fd03aSGavin Shan } 3108271fd03aSGavin Shan 31095958d19aSBenjamin Herrenschmidt /* 31105958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 31115958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 31125958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 31135958d19aSBenjamin Herrenschmidt */ 31145958d19aSBenjamin Herrenschmidt if (phb->ioda.m64_segsize && (type & IORESOURCE_MEM_64)) 3115262af557SGuo Chao return phb->ioda.m64_segsize; 3116271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3117271fd03aSGavin Shan return phb->ioda.m32_segsize; 3118271fd03aSGavin Shan 3119271fd03aSGavin Shan return phb->ioda.io_segsize; 3120271fd03aSGavin Shan } 3121271fd03aSGavin Shan 312240e2a47eSGavin Shan /* 312340e2a47eSGavin Shan * We are updating root port or the upstream port of the 312440e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 312540e2a47eSGavin Shan * to accommodate the changes on required resources during 312640e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 312740e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 312840e2a47eSGavin Shan * root port. 312940e2a47eSGavin Shan */ 313040e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 313140e2a47eSGavin Shan unsigned long type) 313240e2a47eSGavin Shan { 313340e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 313440e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 313540e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 313640e2a47eSGavin Shan struct resource *r, *w; 313740e2a47eSGavin Shan bool msi_region = false; 313840e2a47eSGavin Shan int i; 313940e2a47eSGavin Shan 314040e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 314140e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 314240e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 314340e2a47eSGavin Shan return; 314440e2a47eSGavin Shan 314540e2a47eSGavin Shan /* Fixup the resources */ 314640e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 314740e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 314840e2a47eSGavin Shan if (!r->flags || !r->parent) 314940e2a47eSGavin Shan continue; 315040e2a47eSGavin Shan 315140e2a47eSGavin Shan w = NULL; 315240e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 315340e2a47eSGavin Shan w = &hose->io_resource; 31545958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 315540e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 315640e2a47eSGavin Shan phb->ioda.m64_segsize) 315740e2a47eSGavin Shan w = &hose->mem_resources[1]; 315840e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 315940e2a47eSGavin Shan w = &hose->mem_resources[0]; 316040e2a47eSGavin Shan msi_region = true; 316140e2a47eSGavin Shan } 316240e2a47eSGavin Shan 316340e2a47eSGavin Shan r->start = w->start; 316440e2a47eSGavin Shan r->end = w->end; 316540e2a47eSGavin Shan 316640e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 316740e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 316840e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 316940e2a47eSGavin Shan * 317040e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 317140e2a47eSGavin Shan * 32-bits bridge window. 317240e2a47eSGavin Shan */ 317340e2a47eSGavin Shan if (msi_region) { 317440e2a47eSGavin Shan r->end += 0x10000; 317540e2a47eSGavin Shan r->end -= 0x100000; 317640e2a47eSGavin Shan } 317740e2a47eSGavin Shan } 317840e2a47eSGavin Shan } 317940e2a47eSGavin Shan 3180ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3181ccd1c191SGavin Shan { 3182ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3183ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3184ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3185ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3186ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3187ccd1c191SGavin Shan 318840e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 318940e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 319040e2a47eSGavin Shan 319163803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 319263803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 319363803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 319463803c39SGavin Shan if (pe) { 319563803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 319663803c39SGavin Shan phb->ioda.root_pe_populated = true; 319763803c39SGavin Shan } 319863803c39SGavin Shan } 319963803c39SGavin Shan 3200ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3201ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3202ccd1c191SGavin Shan return; 3203ccd1c191SGavin Shan 3204ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3205ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3206ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3207ccd1c191SGavin Shan 3208ccd1c191SGavin Shan /* 3209ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3210ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3211ccd1c191SGavin Shan * not allocate resources again. 3212ccd1c191SGavin Shan */ 3213ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3214ccd1c191SGavin Shan if (!pe) 3215ccd1c191SGavin Shan return; 3216ccd1c191SGavin Shan 3217ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3218ccd1c191SGavin Shan switch (phb->type) { 3219ccd1c191SGavin Shan case PNV_PHB_IODA1: 3220ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3221ccd1c191SGavin Shan break; 3222ccd1c191SGavin Shan case PNV_PHB_IODA2: 3223ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3224ccd1c191SGavin Shan break; 3225ccd1c191SGavin Shan default: 3226ccd1c191SGavin Shan pr_warn("%s: No DMA for PHB#%d (type %d)\n", 3227ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3228ccd1c191SGavin Shan } 3229ccd1c191SGavin Shan } 3230ccd1c191SGavin Shan 32315350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 32325350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 32335350ab3fSWei Yang int resno) 32345350ab3fSWei Yang { 3235ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3236ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 32375350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 32387fbe7a93SWei Yang resource_size_t align; 32395350ab3fSWei Yang 32407fbe7a93SWei Yang /* 32417fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 32427fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 32437fbe7a93SWei Yang * BAR should be size aligned. 32447fbe7a93SWei Yang * 3245ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3246ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3247ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3248ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3249ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3250ee8222feSWei Yang * m64_segsize. 3251ee8222feSWei Yang * 32527fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 32537fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3254ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3255ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 32567fbe7a93SWei Yang */ 32575350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 32587fbe7a93SWei Yang if (!pdn->vfs_expanded) 32595350ab3fSWei Yang return align; 3260ee8222feSWei Yang if (pdn->m64_single_mode) 3261ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 32627fbe7a93SWei Yang 32637fbe7a93SWei Yang return pdn->vfs_expanded * align; 32645350ab3fSWei Yang } 32655350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 32665350ab3fSWei Yang 3267184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3268184cd4a3SBenjamin Herrenschmidt * assign a PE 3269184cd4a3SBenjamin Herrenschmidt */ 32704361b034SIan Munsie bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3271184cd4a3SBenjamin Herrenschmidt { 3272db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3273db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3274db1266c8SGavin Shan struct pci_dn *pdn; 3275184cd4a3SBenjamin Herrenschmidt 3276db1266c8SGavin Shan /* The function is probably called while the PEs have 3277db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3278db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3279db1266c8SGavin Shan * PEs isn't ready. 3280db1266c8SGavin Shan */ 3281db1266c8SGavin Shan if (!phb->initialized) 3282c88c2a18SDaniel Axtens return true; 3283db1266c8SGavin Shan 3284b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3285184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3286c88c2a18SDaniel Axtens return false; 3287db1266c8SGavin Shan 3288c88c2a18SDaniel Axtens return true; 3289184cd4a3SBenjamin Herrenschmidt } 3290184cd4a3SBenjamin Herrenschmidt 3291c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3292c5f7700bSGavin Shan int num) 3293c5f7700bSGavin Shan { 3294c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3295c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3296c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3297c5f7700bSGavin Shan unsigned int idx; 3298c5f7700bSGavin Shan long rc; 3299c5f7700bSGavin Shan 3300c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3301c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3302c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3303c5f7700bSGavin Shan continue; 3304c5f7700bSGavin Shan 3305c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3306c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3307c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3308c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3309c5f7700bSGavin Shan rc, idx); 3310c5f7700bSGavin Shan return rc; 3311c5f7700bSGavin Shan } 3312c5f7700bSGavin Shan 3313c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3314c5f7700bSGavin Shan } 3315c5f7700bSGavin Shan 3316c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3317c5f7700bSGavin Shan return OPAL_SUCCESS; 3318c5f7700bSGavin Shan } 3319c5f7700bSGavin Shan 3320c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3321c5f7700bSGavin Shan { 3322c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3323c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3324c5f7700bSGavin Shan int64_t rc; 3325c5f7700bSGavin Shan 3326c5f7700bSGavin Shan if (!weight) 3327c5f7700bSGavin Shan return; 3328c5f7700bSGavin Shan 3329c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3330c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3331c5f7700bSGavin Shan return; 3332c5f7700bSGavin Shan 3333a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3334c5f7700bSGavin Shan if (pe->table_group.group) { 3335c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3336c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3337c5f7700bSGavin Shan } 3338c5f7700bSGavin Shan 3339c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3340c5f7700bSGavin Shan iommu_free_table(tbl, "pnv"); 3341c5f7700bSGavin Shan } 3342c5f7700bSGavin Shan 3343c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3344c5f7700bSGavin Shan { 3345c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3346c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3347c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3348c5f7700bSGavin Shan int64_t rc; 3349c5f7700bSGavin Shan #endif 3350c5f7700bSGavin Shan 3351c5f7700bSGavin Shan if (!weight) 3352c5f7700bSGavin Shan return; 3353c5f7700bSGavin Shan 3354c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3355c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3356c5f7700bSGavin Shan if (rc) 3357c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3358c5f7700bSGavin Shan #endif 3359c5f7700bSGavin Shan 3360c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3361c5f7700bSGavin Shan if (pe->table_group.group) { 3362c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3363c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3364c5f7700bSGavin Shan } 3365c5f7700bSGavin Shan 3366c5f7700bSGavin Shan pnv_pci_ioda2_table_free_pages(tbl); 3367c5f7700bSGavin Shan iommu_free_table(tbl, "pnv"); 3368c5f7700bSGavin Shan } 3369c5f7700bSGavin Shan 3370c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3371c5f7700bSGavin Shan unsigned short win, 3372c5f7700bSGavin Shan unsigned int *map) 3373c5f7700bSGavin Shan { 3374c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3375c5f7700bSGavin Shan int idx; 3376c5f7700bSGavin Shan int64_t rc; 3377c5f7700bSGavin Shan 3378c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3379c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3380c5f7700bSGavin Shan continue; 3381c5f7700bSGavin Shan 3382c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3383c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3384c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3385c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3386c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3387c5f7700bSGavin Shan else 3388c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3389c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3390c5f7700bSGavin Shan 3391c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3392c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3393c5f7700bSGavin Shan rc, win, idx); 3394c5f7700bSGavin Shan 3395c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3396c5f7700bSGavin Shan } 3397c5f7700bSGavin Shan } 3398c5f7700bSGavin Shan 3399c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3400c5f7700bSGavin Shan { 3401c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3402c5f7700bSGavin Shan 3403c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3404c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3405c5f7700bSGavin Shan phb->ioda.io_segmap); 3406c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3407c5f7700bSGavin Shan phb->ioda.m32_segmap); 3408c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3409c5f7700bSGavin Shan phb->ioda.m64_segmap); 3410c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3411c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3412c5f7700bSGavin Shan phb->ioda.m32_segmap); 3413c5f7700bSGavin Shan } 3414c5f7700bSGavin Shan } 3415c5f7700bSGavin Shan 3416c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3417c5f7700bSGavin Shan { 3418c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3419c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3420c5f7700bSGavin Shan 3421c5f7700bSGavin Shan /* Release slave PEs in compound PE */ 3422c5f7700bSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3423c5f7700bSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) 3424c5f7700bSGavin Shan pnv_ioda_release_pe(slave); 3425c5f7700bSGavin Shan } 3426c5f7700bSGavin Shan 3427c5f7700bSGavin Shan list_del(&pe->list); 3428c5f7700bSGavin Shan switch (phb->type) { 3429c5f7700bSGavin Shan case PNV_PHB_IODA1: 3430c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3431c5f7700bSGavin Shan break; 3432c5f7700bSGavin Shan case PNV_PHB_IODA2: 3433c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3434c5f7700bSGavin Shan break; 3435c5f7700bSGavin Shan default: 3436c5f7700bSGavin Shan WARN_ON(1); 3437c5f7700bSGavin Shan } 3438c5f7700bSGavin Shan 3439c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3440c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3441c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3442c5f7700bSGavin Shan } 3443c5f7700bSGavin Shan 3444c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3445c5f7700bSGavin Shan { 3446c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3447c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3448c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3449c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3450c5f7700bSGavin Shan 3451c5f7700bSGavin Shan if (pdev->is_virtfn) 3452c5f7700bSGavin Shan return; 3453c5f7700bSGavin Shan 3454c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3455c5f7700bSGavin Shan return; 3456c5f7700bSGavin Shan 3457c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 3458c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3459c5f7700bSGavin Shan if (pe->device_count == 0) 3460c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3461c5f7700bSGavin Shan } 3462c5f7700bSGavin Shan 34637a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 346473ed148aSBenjamin Herrenschmidt { 34657a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 34667a8e6bbfSMichael Neuling 3467d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 346873ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 346973ed148aSBenjamin Herrenschmidt } 347073ed148aSBenjamin Herrenschmidt 347192ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 347292ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 34731bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 347492ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 347592ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 347692ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 347792ae0353SDaniel Axtens #endif 347892ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3479c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 348092ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3481ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 348292ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3483763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 348453522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 34857a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 348692ae0353SDaniel Axtens }; 348792ae0353SDaniel Axtens 3488f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3489f9f83456SAlexey Kardashevskiy { 3490f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3491f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3492f9f83456SAlexey Kardashevskiy __func__); 3493f9f83456SAlexey Kardashevskiy return -EPERM; 3494f9f83456SAlexey Kardashevskiy } 3495f9f83456SAlexey Kardashevskiy 34965d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 34975d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 34985d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 34995d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 35005d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 35015d2aa710SAlistair Popple #endif 35025d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 35035d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 35045d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35055d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 35065d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 35075d2aa710SAlistair Popple }; 35085d2aa710SAlistair Popple 35094361b034SIan Munsie #ifdef CONFIG_CXL_BASE 35104361b034SIan Munsie const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 35114361b034SIan Munsie .dma_dev_setup = pnv_pci_dma_dev_setup, 35124361b034SIan Munsie .dma_bus_setup = pnv_pci_dma_bus_setup, 3513a2f67d5eSIan Munsie #ifdef CONFIG_PCI_MSI 3514a2f67d5eSIan Munsie .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3515a2f67d5eSIan Munsie .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3516a2f67d5eSIan Munsie #endif 35174361b034SIan Munsie .enable_device_hook = pnv_cxl_enable_device_hook, 35184361b034SIan Munsie .disable_device = pnv_cxl_disable_device, 35194361b034SIan Munsie .release_device = pnv_pci_release_device, 35204361b034SIan Munsie .window_alignment = pnv_pci_window_alignment, 35214361b034SIan Munsie .setup_bridge = pnv_pci_setup_bridge, 35224361b034SIan Munsie .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35234361b034SIan Munsie .dma_set_mask = pnv_pci_ioda_dma_set_mask, 35244361b034SIan Munsie .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 35254361b034SIan Munsie .shutdown = pnv_pci_ioda_shutdown, 35264361b034SIan Munsie }; 35274361b034SIan Munsie #endif 35284361b034SIan Munsie 3529e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3530e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3531184cd4a3SBenjamin Herrenschmidt { 3532184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3533184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 35342b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 35352b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3536fd141d1aSBenjamin Herrenschmidt struct resource r; 3537c681b93cSAlistair Popple const __be64 *prop64; 35383a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3539f1b7cc3eSGavin Shan int len; 35403fa23ff8SGavin Shan unsigned int segno; 3541184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3542184cd4a3SBenjamin Herrenschmidt void *aux; 3543184cd4a3SBenjamin Herrenschmidt long rc; 3544184cd4a3SBenjamin Herrenschmidt 354508a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 354608a45b32SBenjamin Herrenschmidt return; 354708a45b32SBenjamin Herrenschmidt 35489497a1c1SGavin Shan pr_info("Initializing %s PHB (%s)\n", 35499497a1c1SGavin Shan pnv_phb_names[ioda_type], of_node_full_name(np)); 3550184cd4a3SBenjamin Herrenschmidt 3551184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3552184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3553184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3554184cd4a3SBenjamin Herrenschmidt return; 3555184cd4a3SBenjamin Herrenschmidt } 3556184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3557184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3558184cd4a3SBenjamin Herrenschmidt 3559e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 356058d714ecSGavin Shan 356158d714ecSGavin Shan /* Allocate PCI controller */ 3562184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 356358d714ecSGavin Shan if (!phb->hose) { 356458d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3565184cd4a3SBenjamin Herrenschmidt np->full_name); 3566e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3567184cd4a3SBenjamin Herrenschmidt return; 3568184cd4a3SBenjamin Herrenschmidt } 3569184cd4a3SBenjamin Herrenschmidt 3570184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3571f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3572f1b7cc3eSGavin Shan if (prop32 && len == 8) { 35733a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 35743a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3575f1b7cc3eSGavin Shan } else { 3576f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3577184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3578184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3579f1b7cc3eSGavin Shan } 3580184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3581e9cc17d4SGavin Shan phb->hub_id = hub_id; 3582184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3583aa0c033fSGavin Shan phb->type = ioda_type; 3584781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3585184cd4a3SBenjamin Herrenschmidt 3586cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3587cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3588cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3589f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3590aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 35915d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 35925d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3593cee72d5bSBenjamin Herrenschmidt else 3594cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3595cee72d5bSBenjamin Herrenschmidt 3596aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 35972f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3598184cd4a3SBenjamin Herrenschmidt 3599aa0c033fSGavin Shan /* Get registers */ 3600fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3601fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3602fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3603184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3604184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3605fd141d1aSBenjamin Herrenschmidt } 3606577c8c88SGavin Shan 3607184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 360892b8f137SGavin Shan phb->ioda.total_pe_num = 1; 360936954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 361036954dc7SGavin Shan if (prop32) 361192b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 361236954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 361336954dc7SGavin Shan if (prop32) 361492b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3615262af557SGuo Chao 3616c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3617c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3618c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3619c127562aSGavin Shan 3620262af557SGuo Chao /* Parse 64-bit MMIO range */ 3621262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3622262af557SGuo Chao 3623184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3624aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3625184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3626184cd4a3SBenjamin Herrenschmidt 362792b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 36283fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3629184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 363092b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3631184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3632184cd4a3SBenjamin Herrenschmidt 36332b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 36342b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 36352b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 36362b923ed1SGavin Shan 3637c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 363892a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 363992a86756SAlexey Kardashevskiy sizeof(unsigned long)); 364093289d8cSGavin Shan m64map_off = size; 364193289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3642184cd4a3SBenjamin Herrenschmidt m32map_off = size; 364392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3644c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3645c35d2a8cSGavin Shan iomap_off = size; 364692b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 36472b923ed1SGavin Shan dma32map_off = size; 36482b923ed1SGavin Shan size += phb->ioda.dma32_count * 36492b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3650c35d2a8cSGavin Shan } 3651184cd4a3SBenjamin Herrenschmidt pemap_off = size; 365292b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3653e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3654184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 365593289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3656184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 365793289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 365893289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 36593fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 366093289d8cSGavin Shan } 36613fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3662184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 36633fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 36643fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 36652b923ed1SGavin Shan 36662b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 36672b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 36682b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 36693fa23ff8SGavin Shan } 3670184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 367163803c39SGavin Shan 367263803c39SGavin Shan /* 367363803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 367463803c39SGavin Shan * M64 resources consumed by its child devices. To pick 367563803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 367663803c39SGavin Shan */ 367763803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 367863803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 367963803c39SGavin Shan phb->ioda.root_pe_idx = 1; 368063803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 368163803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 368263803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 368363803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 368463803c39SGavin Shan } else { 368563803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 368663803c39SGavin Shan } 3687184cd4a3SBenjamin Herrenschmidt 3688184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3689781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3690184cd4a3SBenjamin Herrenschmidt 3691184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 36922b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3693acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3694184cd4a3SBenjamin Herrenschmidt 3695aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3696184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3697184cd4a3SBenjamin Herrenschmidt window_type, 3698184cd4a3SBenjamin Herrenschmidt window_num, 3699184cd4a3SBenjamin Herrenschmidt starting_real_address, 3700184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3701184cd4a3SBenjamin Herrenschmidt segment_size); 3702184cd4a3SBenjamin Herrenschmidt #endif 3703184cd4a3SBenjamin Herrenschmidt 3704262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 370592b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3706262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3707262af557SGuo Chao if (phb->ioda.m64_size) 3708262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3709262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3710262af557SGuo Chao if (phb->ioda.io_size) 3711262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3712184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3713184cd4a3SBenjamin Herrenschmidt 3714262af557SGuo Chao 3715184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 371649dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 371749dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 371849dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3719184cd4a3SBenjamin Herrenschmidt 3720184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3721184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3722184cd4a3SBenjamin Herrenschmidt 3723c40a4210SGavin Shan /* 3724c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3725c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3726c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3727c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3728c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3729184cd4a3SBenjamin Herrenschmidt */ 3730fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 37315d2aa710SAlistair Popple 3732f9f83456SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU) { 37335d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 3734f9f83456SAlexey Kardashevskiy } else { 3735f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 373692ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3737f9f83456SAlexey Kardashevskiy } 3738ad30cb99SMichael Ellerman 37396e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 37406e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 37415350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3742ad30cb99SMichael Ellerman #endif 3743ad30cb99SMichael Ellerman 3744c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3745184cd4a3SBenjamin Herrenschmidt 3746184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3747d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3748184cd4a3SBenjamin Herrenschmidt if (rc) 3749f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3750361f2a2aSGavin Shan 3751361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3752361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3753361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3754361f2a2aSGavin Shan * transactions from previous kerenl. 3755361f2a2aSGavin Shan */ 3756361f2a2aSGavin Shan if (is_kdump_kernel()) { 3757361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3758cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3759cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3760361f2a2aSGavin Shan } 3761262af557SGuo Chao 37629e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 37639e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3764262af557SGuo Chao hose->mem_resources[1].flags = 0; 3765184cd4a3SBenjamin Herrenschmidt } 3766184cd4a3SBenjamin Herrenschmidt 376767975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3768aa0c033fSGavin Shan { 3769e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3770aa0c033fSGavin Shan } 3771aa0c033fSGavin Shan 37725d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 37735d2aa710SAlistair Popple { 37745d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 37755d2aa710SAlistair Popple } 37765d2aa710SAlistair Popple 3777184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3778184cd4a3SBenjamin Herrenschmidt { 3779184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3780c681b93cSAlistair Popple const __be64 *prop64; 3781184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3782184cd4a3SBenjamin Herrenschmidt 3783184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3784184cd4a3SBenjamin Herrenschmidt 3785184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3786184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3787184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3788184cd4a3SBenjamin Herrenschmidt return; 3789184cd4a3SBenjamin Herrenschmidt } 3790184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3791184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3792184cd4a3SBenjamin Herrenschmidt 3793184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3794184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3795184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3796184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3797e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3798184cd4a3SBenjamin Herrenschmidt } 3799184cd4a3SBenjamin Herrenschmidt } 3800