1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 35184cd4a3SBenjamin Herrenschmidt 36184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 37184cd4a3SBenjamin Herrenschmidt #include "pci.h" 38184cd4a3SBenjamin Herrenschmidt 39184cd4a3SBenjamin Herrenschmidt #define define_pe_printk_level(func, kern_level) \ 40184cd4a3SBenjamin Herrenschmidt static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ 41184cd4a3SBenjamin Herrenschmidt { \ 42184cd4a3SBenjamin Herrenschmidt struct va_format vaf; \ 43184cd4a3SBenjamin Herrenschmidt va_list args; \ 44490e078dSGavin Shan char pfix[32]; \ 45184cd4a3SBenjamin Herrenschmidt int r; \ 46184cd4a3SBenjamin Herrenschmidt \ 47184cd4a3SBenjamin Herrenschmidt va_start(args, fmt); \ 48184cd4a3SBenjamin Herrenschmidt \ 49184cd4a3SBenjamin Herrenschmidt vaf.fmt = fmt; \ 50184cd4a3SBenjamin Herrenschmidt vaf.va = &args; \ 51184cd4a3SBenjamin Herrenschmidt \ 52490e078dSGavin Shan if (pe->pdev) \ 53490e078dSGavin Shan strlcpy(pfix, dev_name(&pe->pdev->dev), \ 54490e078dSGavin Shan sizeof(pfix)); \ 55490e078dSGavin Shan else \ 56490e078dSGavin Shan sprintf(pfix, "%04x:%02x ", \ 57490e078dSGavin Shan pci_domain_nr(pe->pbus), \ 58490e078dSGavin Shan pe->pbus->number); \ 59490e078dSGavin Shan r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ 60490e078dSGavin Shan pfix, pe->pe_number, &vaf); \ 61490e078dSGavin Shan \ 62184cd4a3SBenjamin Herrenschmidt va_end(args); \ 63184cd4a3SBenjamin Herrenschmidt \ 64184cd4a3SBenjamin Herrenschmidt return r; \ 65184cd4a3SBenjamin Herrenschmidt } \ 66184cd4a3SBenjamin Herrenschmidt 67184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_err, KERN_ERR); 68184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_warn, KERN_WARNING); 69184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_info, KERN_INFO); 70184cd4a3SBenjamin Herrenschmidt 71cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 72184cd4a3SBenjamin Herrenschmidt { 73184cd4a3SBenjamin Herrenschmidt unsigned long pe; 74184cd4a3SBenjamin Herrenschmidt 75184cd4a3SBenjamin Herrenschmidt do { 76184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 77184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 78184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 79184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 80184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 81184cd4a3SBenjamin Herrenschmidt 824cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 83184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 84184cd4a3SBenjamin Herrenschmidt return pe; 85184cd4a3SBenjamin Herrenschmidt } 86184cd4a3SBenjamin Herrenschmidt 87cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 88184cd4a3SBenjamin Herrenschmidt { 89184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 90184cd4a3SBenjamin Herrenschmidt 91184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 92184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 93184cd4a3SBenjamin Herrenschmidt } 94184cd4a3SBenjamin Herrenschmidt 95184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 96184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 97184cd4a3SBenjamin Herrenschmidt */ 98184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 99cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 100184cd4a3SBenjamin Herrenschmidt { 101184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 102184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 103b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 104184cd4a3SBenjamin Herrenschmidt 105184cd4a3SBenjamin Herrenschmidt if (!pdn) 106184cd4a3SBenjamin Herrenschmidt return NULL; 107184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 108184cd4a3SBenjamin Herrenschmidt return NULL; 109184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 110184cd4a3SBenjamin Herrenschmidt } 111184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 112184cd4a3SBenjamin Herrenschmidt 113cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 114184cd4a3SBenjamin Herrenschmidt { 115184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 116184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 117184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 118184cd4a3SBenjamin Herrenschmidt 119184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 120184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 121184cd4a3SBenjamin Herrenschmidt int count; 122184cd4a3SBenjamin Herrenschmidt 123184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 124184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 125184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 126fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 127b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 128fb446ad0SGavin Shan else 129fb446ad0SGavin Shan count = 1; 130fb446ad0SGavin Shan 131184cd4a3SBenjamin Herrenschmidt switch(count) { 132184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 133184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 134184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 135184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 136184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 137184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 138184cd4a3SBenjamin Herrenschmidt default: 139184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 140184cd4a3SBenjamin Herrenschmidt " unsupported\n", 141184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 142184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 143184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 144184cd4a3SBenjamin Herrenschmidt } 145184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 146184cd4a3SBenjamin Herrenschmidt } else { 147184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 148184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 149184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 150184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 151184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 152184cd4a3SBenjamin Herrenschmidt } 153184cd4a3SBenjamin Herrenschmidt 154184cd4a3SBenjamin Herrenschmidt /* Associate PE in PELT */ 155184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 156184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 157184cd4a3SBenjamin Herrenschmidt if (rc) { 158184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 159184cd4a3SBenjamin Herrenschmidt return -ENXIO; 160184cd4a3SBenjamin Herrenschmidt } 161184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 162184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 163184cd4a3SBenjamin Herrenschmidt 164184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 165184cd4a3SBenjamin Herrenschmidt while (parent) { 166b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(parent); 167184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 168184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 169cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 170184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 171184cd4a3SBenjamin Herrenschmidt } 172184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 173184cd4a3SBenjamin Herrenschmidt } 174184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 175184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 176184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 177184cd4a3SBenjamin Herrenschmidt 178184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 179184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 180184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 181184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 182184cd4a3SBenjamin Herrenschmidt pe->pe_number); 183184cd4a3SBenjamin Herrenschmidt if (rc) { 184184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 185184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 186184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 187184cd4a3SBenjamin Herrenschmidt } else { 188184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 189cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 190184cd4a3SBenjamin Herrenschmidt if (rc) { 191184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 192184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 193184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 194184cd4a3SBenjamin Herrenschmidt } 195184cd4a3SBenjamin Herrenschmidt } 196184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 197184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 198184cd4a3SBenjamin Herrenschmidt 199184cd4a3SBenjamin Herrenschmidt return 0; 200184cd4a3SBenjamin Herrenschmidt } 201184cd4a3SBenjamin Herrenschmidt 202cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 203184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 204184cd4a3SBenjamin Herrenschmidt { 205184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 206184cd4a3SBenjamin Herrenschmidt 2077ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 208184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 2097ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 210184cd4a3SBenjamin Herrenschmidt return; 211184cd4a3SBenjamin Herrenschmidt } 212184cd4a3SBenjamin Herrenschmidt } 2137ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 214184cd4a3SBenjamin Herrenschmidt } 215184cd4a3SBenjamin Herrenschmidt 216184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 217184cd4a3SBenjamin Herrenschmidt { 218184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 219184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 220184cd4a3SBenjamin Herrenschmidt */ 221184cd4a3SBenjamin Herrenschmidt 222184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 223184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 224184cd4a3SBenjamin Herrenschmidt return 0; 225184cd4a3SBenjamin Herrenschmidt 226184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 227184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 228184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 229184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 230184cd4a3SBenjamin Herrenschmidt return 3; 231184cd4a3SBenjamin Herrenschmidt 232184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 233184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 234184cd4a3SBenjamin Herrenschmidt return 15; 235184cd4a3SBenjamin Herrenschmidt 236184cd4a3SBenjamin Herrenschmidt /* Default */ 237184cd4a3SBenjamin Herrenschmidt return 10; 238184cd4a3SBenjamin Herrenschmidt } 239184cd4a3SBenjamin Herrenschmidt 240fb446ad0SGavin Shan #if 0 241cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 242184cd4a3SBenjamin Herrenschmidt { 243184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 244184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 245b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 246184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 247184cd4a3SBenjamin Herrenschmidt int pe_num; 248184cd4a3SBenjamin Herrenschmidt 249184cd4a3SBenjamin Herrenschmidt if (!pdn) { 250184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 251184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 252184cd4a3SBenjamin Herrenschmidt return NULL; 253184cd4a3SBenjamin Herrenschmidt } 254184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 255184cd4a3SBenjamin Herrenschmidt return NULL; 256184cd4a3SBenjamin Herrenschmidt 257184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 258184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 259184cd4a3SBenjamin Herrenschmidt pe_num = 0; 260184cd4a3SBenjamin Herrenschmidt else 261184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 262184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 263184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 264184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 265184cd4a3SBenjamin Herrenschmidt return NULL; 266184cd4a3SBenjamin Herrenschmidt } 267184cd4a3SBenjamin Herrenschmidt 268184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 269184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 270184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 271184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 272184cd4a3SBenjamin Herrenschmidt * 273184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 274184cd4a3SBenjamin Herrenschmidt */ 275184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 276184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 277184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 278184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 279184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 280184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 281184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 282184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 283184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 284184cd4a3SBenjamin Herrenschmidt 285184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 286184cd4a3SBenjamin Herrenschmidt 287184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 288184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 289184cd4a3SBenjamin Herrenschmidt if (pe_num) 290184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 291184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 292184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 293184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 294184cd4a3SBenjamin Herrenschmidt return NULL; 295184cd4a3SBenjamin Herrenschmidt } 296184cd4a3SBenjamin Herrenschmidt 297184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 298184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 299184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 300184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 301184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 302184cd4a3SBenjamin Herrenschmidt } 303184cd4a3SBenjamin Herrenschmidt 304184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 305184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 306184cd4a3SBenjamin Herrenschmidt 307184cd4a3SBenjamin Herrenschmidt return pe; 308184cd4a3SBenjamin Herrenschmidt } 309fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 310184cd4a3SBenjamin Herrenschmidt 311184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 312184cd4a3SBenjamin Herrenschmidt { 313184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 314184cd4a3SBenjamin Herrenschmidt 315184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 316b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 317184cd4a3SBenjamin Herrenschmidt 318184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 319184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 320184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 321184cd4a3SBenjamin Herrenschmidt continue; 322184cd4a3SBenjamin Herrenschmidt } 323184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 324184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 325184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 326184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 327fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 328184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 329184cd4a3SBenjamin Herrenschmidt } 330184cd4a3SBenjamin Herrenschmidt } 331184cd4a3SBenjamin Herrenschmidt 332fb446ad0SGavin Shan /* 333fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 334fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 335fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 336fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 337fb446ad0SGavin Shan */ 338cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 339184cd4a3SBenjamin Herrenschmidt { 340fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 341184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 342184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 343184cd4a3SBenjamin Herrenschmidt int pe_num; 344184cd4a3SBenjamin Herrenschmidt 345184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 346184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 347fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 348fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 349184cd4a3SBenjamin Herrenschmidt return; 350184cd4a3SBenjamin Herrenschmidt } 351184cd4a3SBenjamin Herrenschmidt 352184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 353fb446ad0SGavin Shan pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 354184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 355184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 356184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 357184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 358b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 359184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 360184cd4a3SBenjamin Herrenschmidt 361fb446ad0SGavin Shan if (all) 362fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 363fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 364fb446ad0SGavin Shan else 365fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 366fb446ad0SGavin Shan bus->busn_res.start, pe_num); 367184cd4a3SBenjamin Herrenschmidt 368184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 369184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 370184cd4a3SBenjamin Herrenschmidt if (pe_num) 371184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 372184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 373184cd4a3SBenjamin Herrenschmidt return; 374184cd4a3SBenjamin Herrenschmidt } 375184cd4a3SBenjamin Herrenschmidt 376184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 377184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 378184cd4a3SBenjamin Herrenschmidt 3797ebdf956SGavin Shan /* Put PE to the list */ 3807ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 3817ebdf956SGavin Shan 382184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 383184cd4a3SBenjamin Herrenschmidt * below the bridge 384184cd4a3SBenjamin Herrenschmidt */ 385184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 386184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 387184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 388184cd4a3SBenjamin Herrenschmidt } 389184cd4a3SBenjamin Herrenschmidt 390184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 391184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 392184cd4a3SBenjamin Herrenschmidt } 393184cd4a3SBenjamin Herrenschmidt 394cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 395184cd4a3SBenjamin Herrenschmidt { 396184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 397fb446ad0SGavin Shan 398fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 399184cd4a3SBenjamin Herrenschmidt 400184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 401fb446ad0SGavin Shan if (dev->subordinate) { 40262f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 403fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 404fb446ad0SGavin Shan else 405184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 406184cd4a3SBenjamin Herrenschmidt } 407184cd4a3SBenjamin Herrenschmidt } 408fb446ad0SGavin Shan } 409fb446ad0SGavin Shan 410fb446ad0SGavin Shan /* 411fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 412fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 413fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 414fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 415fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 416fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 417fb446ad0SGavin Shan */ 418cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 419fb446ad0SGavin Shan { 420fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 421fb446ad0SGavin Shan 422fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 423fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 424fb446ad0SGavin Shan } 425fb446ad0SGavin Shan } 426184cd4a3SBenjamin Herrenschmidt 427959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 428184cd4a3SBenjamin Herrenschmidt { 429b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 430959c9bddSGavin Shan struct pnv_ioda_pe *pe; 431184cd4a3SBenjamin Herrenschmidt 432959c9bddSGavin Shan /* 433959c9bddSGavin Shan * The function can be called while the PE# 434959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 435959c9bddSGavin Shan * case. 436959c9bddSGavin Shan */ 437959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 438959c9bddSGavin Shan return; 439184cd4a3SBenjamin Herrenschmidt 440959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 441959c9bddSGavin Shan set_iommu_table_base(&pdev->dev, &pe->tce32_table); 442184cd4a3SBenjamin Herrenschmidt } 443184cd4a3SBenjamin Herrenschmidt 4444cce9550SGavin Shan static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 4454cce9550SGavin Shan u64 *startp, u64 *endp) 4464cce9550SGavin Shan { 4474cce9550SGavin Shan u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; 4484cce9550SGavin Shan unsigned long start, end, inc; 4494cce9550SGavin Shan 4504cce9550SGavin Shan start = __pa(startp); 4514cce9550SGavin Shan end = __pa(endp); 4524cce9550SGavin Shan 4534cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 4544cce9550SGavin Shan if (tbl->it_busno) { 4554cce9550SGavin Shan start <<= 12; 4564cce9550SGavin Shan end <<= 12; 4574cce9550SGavin Shan inc = 128 << 12; 4584cce9550SGavin Shan start |= tbl->it_busno; 4594cce9550SGavin Shan end |= tbl->it_busno; 4604cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 4614cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 4624cce9550SGavin Shan start |= (1ull << 63); 4634cce9550SGavin Shan end |= (1ull << 63); 4644cce9550SGavin Shan inc = 16; 4654cce9550SGavin Shan } else { 4664cce9550SGavin Shan /* Default (older HW) */ 4674cce9550SGavin Shan inc = 128; 4684cce9550SGavin Shan } 4694cce9550SGavin Shan 4704cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 4714cce9550SGavin Shan 4724cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 4734cce9550SGavin Shan while (start <= end) { 4744cce9550SGavin Shan __raw_writeq(start, invalidate); 4754cce9550SGavin Shan start += inc; 4764cce9550SGavin Shan } 4774cce9550SGavin Shan 4784cce9550SGavin Shan /* 4794cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 4804cce9550SGavin Shan * and we don't care on free() 4814cce9550SGavin Shan */ 4824cce9550SGavin Shan } 4834cce9550SGavin Shan 4844cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 4854cce9550SGavin Shan struct iommu_table *tbl, 4864cce9550SGavin Shan u64 *startp, u64 *endp) 4874cce9550SGavin Shan { 4884cce9550SGavin Shan unsigned long start, end, inc; 4894cce9550SGavin Shan u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; 4904cce9550SGavin Shan 4914cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 4924cce9550SGavin Shan start = 0x2ul << 60; 4934cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 4944cce9550SGavin Shan end = start; 4954cce9550SGavin Shan 4964cce9550SGavin Shan /* Figure out the start, end and step */ 4974cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 4984cce9550SGavin Shan start |= (inc << 12); 4994cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 5004cce9550SGavin Shan end |= (inc << 12); 5014cce9550SGavin Shan inc = (0x1ul << 12); 5024cce9550SGavin Shan mb(); 5034cce9550SGavin Shan 5044cce9550SGavin Shan while (start <= end) { 5054cce9550SGavin Shan __raw_writeq(start, invalidate); 5064cce9550SGavin Shan start += inc; 5074cce9550SGavin Shan } 5084cce9550SGavin Shan } 5094cce9550SGavin Shan 5104cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 5114cce9550SGavin Shan u64 *startp, u64 *endp) 5124cce9550SGavin Shan { 5134cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 5144cce9550SGavin Shan tce32_table); 5154cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 5164cce9550SGavin Shan 5174cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 5184cce9550SGavin Shan pnv_pci_ioda1_tce_invalidate(tbl, startp, endp); 5194cce9550SGavin Shan else 5204cce9550SGavin Shan pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp); 5214cce9550SGavin Shan } 5224cce9550SGavin Shan 523cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 524cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 525184cd4a3SBenjamin Herrenschmidt unsigned int segs) 526184cd4a3SBenjamin Herrenschmidt { 527184cd4a3SBenjamin Herrenschmidt 528184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 529184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 530184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 531184cd4a3SBenjamin Herrenschmidt unsigned int i; 532184cd4a3SBenjamin Herrenschmidt int64_t rc; 533184cd4a3SBenjamin Herrenschmidt void *addr; 534184cd4a3SBenjamin Herrenschmidt 535184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 536184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 537184cd4a3SBenjamin Herrenschmidt 538184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 539184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 540184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 541184cd4a3SBenjamin Herrenschmidt 542184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 543184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 544184cd4a3SBenjamin Herrenschmidt return; 545184cd4a3SBenjamin Herrenschmidt 546184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 547184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 548184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 549184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 550184cd4a3SBenjamin Herrenschmidt 551184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 552184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 553184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 554184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 555184cd4a3SBenjamin Herrenschmidt */ 556184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 557184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 558184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 559184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 560184cd4a3SBenjamin Herrenschmidt goto fail; 561184cd4a3SBenjamin Herrenschmidt } 562184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 563184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 564184cd4a3SBenjamin Herrenschmidt 565184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 566184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 567184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 568184cd4a3SBenjamin Herrenschmidt pe->pe_number, 569184cd4a3SBenjamin Herrenschmidt base + i, 1, 570184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 571184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 572184cd4a3SBenjamin Herrenschmidt if (rc) { 573184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 574184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 575184cd4a3SBenjamin Herrenschmidt goto fail; 576184cd4a3SBenjamin Herrenschmidt } 577184cd4a3SBenjamin Herrenschmidt } 578184cd4a3SBenjamin Herrenschmidt 579184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 580184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 581184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 582184cd4a3SBenjamin Herrenschmidt base << 28); 583184cd4a3SBenjamin Herrenschmidt 584184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 585184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 586184cd4a3SBenjamin Herrenschmidt if (swinvp) { 587184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 588184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 589184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 590184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 591184cd4a3SBenjamin Herrenschmidt */ 592184cd4a3SBenjamin Herrenschmidt tbl->it_busno = 0; 593184cd4a3SBenjamin Herrenschmidt tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 594373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE | 595373f5657SGavin Shan TCE_PCI_SWINV_PAIR; 596184cd4a3SBenjamin Herrenschmidt } 597184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 5984e13c1acSAlexey Kardashevskiy iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number); 599184cd4a3SBenjamin Herrenschmidt 600184cd4a3SBenjamin Herrenschmidt return; 601184cd4a3SBenjamin Herrenschmidt fail: 602184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 603184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 604184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 605184cd4a3SBenjamin Herrenschmidt if (tce_mem) 606184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 607184cd4a3SBenjamin Herrenschmidt } 608184cd4a3SBenjamin Herrenschmidt 609373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 610373f5657SGavin Shan struct pnv_ioda_pe *pe) 611373f5657SGavin Shan { 612373f5657SGavin Shan struct page *tce_mem = NULL; 613373f5657SGavin Shan void *addr; 614373f5657SGavin Shan const __be64 *swinvp; 615373f5657SGavin Shan struct iommu_table *tbl; 616373f5657SGavin Shan unsigned int tce_table_size, end; 617373f5657SGavin Shan int64_t rc; 618373f5657SGavin Shan 619373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 620373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 621373f5657SGavin Shan return; 622373f5657SGavin Shan 623373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 624373f5657SGavin Shan pe->tce32_seg = 0; 625373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 626373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 627373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 628373f5657SGavin Shan end); 629373f5657SGavin Shan 630373f5657SGavin Shan /* Allocate TCE table */ 631373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 632373f5657SGavin Shan get_order(tce_table_size)); 633373f5657SGavin Shan if (!tce_mem) { 634373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 635373f5657SGavin Shan goto fail; 636373f5657SGavin Shan } 637373f5657SGavin Shan addr = page_address(tce_mem); 638373f5657SGavin Shan memset(addr, 0, tce_table_size); 639373f5657SGavin Shan 640373f5657SGavin Shan /* 641373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 642373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 643373f5657SGavin Shan */ 644373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 645373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 646373f5657SGavin Shan tce_table_size, 0x1000); 647373f5657SGavin Shan if (rc) { 648373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 649373f5657SGavin Shan " err %ld\n", rc); 650373f5657SGavin Shan goto fail; 651373f5657SGavin Shan } 652373f5657SGavin Shan 653373f5657SGavin Shan /* Setup linux iommu table */ 654373f5657SGavin Shan tbl = &pe->tce32_table; 655373f5657SGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0); 656373f5657SGavin Shan 657373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 658373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 659373f5657SGavin Shan if (swinvp) { 660373f5657SGavin Shan /* We need a couple more fields -- an address and a data 661373f5657SGavin Shan * to or. Since the bus is only printed out on table free 662373f5657SGavin Shan * errors, and on the first pass the data will be a relative 663373f5657SGavin Shan * bus number, print that out instead. 664373f5657SGavin Shan */ 665373f5657SGavin Shan tbl->it_busno = 0; 666373f5657SGavin Shan tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 667373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; 668373f5657SGavin Shan } 669373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 670373f5657SGavin Shan 671373f5657SGavin Shan return; 672373f5657SGavin Shan fail: 673373f5657SGavin Shan if (pe->tce32_seg >= 0) 674373f5657SGavin Shan pe->tce32_seg = -1; 675373f5657SGavin Shan if (tce_mem) 676373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 677373f5657SGavin Shan } 678373f5657SGavin Shan 679cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 680184cd4a3SBenjamin Herrenschmidt { 681184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 682184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 683184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 684184cd4a3SBenjamin Herrenschmidt 685184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 686184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 687184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 688184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 689184cd4a3SBenjamin Herrenschmidt */ 690184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 691184cd4a3SBenjamin Herrenschmidt residual = 0; 692184cd4a3SBenjamin Herrenschmidt else 693184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 694184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 695184cd4a3SBenjamin Herrenschmidt 696184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 697184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 698184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 699184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 700184cd4a3SBenjamin Herrenschmidt 701184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 702184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 703184cd4a3SBenjamin Herrenschmidt * weight 704184cd4a3SBenjamin Herrenschmidt */ 705184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 706184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 707184cd4a3SBenjamin Herrenschmidt base = 0; 7087ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 709184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 710184cd4a3SBenjamin Herrenschmidt continue; 711184cd4a3SBenjamin Herrenschmidt if (!remaining) { 712184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 713184cd4a3SBenjamin Herrenschmidt continue; 714184cd4a3SBenjamin Herrenschmidt } 715184cd4a3SBenjamin Herrenschmidt segs = 1; 716184cd4a3SBenjamin Herrenschmidt if (residual) { 717184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 718184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 719184cd4a3SBenjamin Herrenschmidt segs = remaining; 720184cd4a3SBenjamin Herrenschmidt } 721373f5657SGavin Shan 722373f5657SGavin Shan /* 723373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 724373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 725373f5657SGavin Shan * the specific PE. 726373f5657SGavin Shan */ 727373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 728184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 729184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 730184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 731373f5657SGavin Shan } else { 732373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 733373f5657SGavin Shan segs = 0; 734373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 735373f5657SGavin Shan } 736373f5657SGavin Shan 737184cd4a3SBenjamin Herrenschmidt remaining -= segs; 738184cd4a3SBenjamin Herrenschmidt base += segs; 739184cd4a3SBenjamin Herrenschmidt } 740184cd4a3SBenjamin Herrenschmidt } 741184cd4a3SBenjamin Herrenschmidt 742184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 743137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 744137436c9SGavin Shan { 745137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 746137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 747137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 748137436c9SGavin Shan ioda.irq_chip); 749137436c9SGavin Shan int64_t rc; 750137436c9SGavin Shan 751137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 752137436c9SGavin Shan WARN_ON_ONCE(rc); 753137436c9SGavin Shan 754137436c9SGavin Shan icp_native_eoi(d); 755137436c9SGavin Shan } 756137436c9SGavin Shan 757184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 758137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 759137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 760184cd4a3SBenjamin Herrenschmidt { 761184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 762b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 763137436c9SGavin Shan struct irq_data *idata; 764137436c9SGavin Shan struct irq_chip *ichip; 765184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 766184cd4a3SBenjamin Herrenschmidt uint64_t addr64; 767184cd4a3SBenjamin Herrenschmidt uint32_t addr32, data; 768184cd4a3SBenjamin Herrenschmidt int rc; 769184cd4a3SBenjamin Herrenschmidt 770184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 771184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 772184cd4a3SBenjamin Herrenschmidt return -ENXIO; 773184cd4a3SBenjamin Herrenschmidt 774184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 775184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 776184cd4a3SBenjamin Herrenschmidt return -ENXIO; 777184cd4a3SBenjamin Herrenschmidt 778b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 779b72c1f65SBenjamin Herrenschmidt if (pdn && pdn->force_32bit_msi) 780b72c1f65SBenjamin Herrenschmidt is_64 = 0; 781b72c1f65SBenjamin Herrenschmidt 782184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 783184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 784184cd4a3SBenjamin Herrenschmidt if (rc) { 785184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 786184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 787184cd4a3SBenjamin Herrenschmidt return -EIO; 788184cd4a3SBenjamin Herrenschmidt } 789184cd4a3SBenjamin Herrenschmidt 790184cd4a3SBenjamin Herrenschmidt if (is_64) { 791184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 792184cd4a3SBenjamin Herrenschmidt &addr64, &data); 793184cd4a3SBenjamin Herrenschmidt if (rc) { 794184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 795184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 796184cd4a3SBenjamin Herrenschmidt return -EIO; 797184cd4a3SBenjamin Herrenschmidt } 798184cd4a3SBenjamin Herrenschmidt msg->address_hi = addr64 >> 32; 799184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr64 & 0xfffffffful; 800184cd4a3SBenjamin Herrenschmidt } else { 801184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 802184cd4a3SBenjamin Herrenschmidt &addr32, &data); 803184cd4a3SBenjamin Herrenschmidt if (rc) { 804184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 805184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 806184cd4a3SBenjamin Herrenschmidt return -EIO; 807184cd4a3SBenjamin Herrenschmidt } 808184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 809184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr32; 810184cd4a3SBenjamin Herrenschmidt } 811184cd4a3SBenjamin Herrenschmidt msg->data = data; 812184cd4a3SBenjamin Herrenschmidt 813137436c9SGavin Shan /* 814137436c9SGavin Shan * Change the IRQ chip for the MSI interrupts on PHB3. 815137436c9SGavin Shan * The corresponding IRQ chip should be populated for 816137436c9SGavin Shan * the first time. 817137436c9SGavin Shan */ 818137436c9SGavin Shan if (phb->type == PNV_PHB_IODA2) { 819137436c9SGavin Shan if (!phb->ioda.irq_chip_init) { 820137436c9SGavin Shan idata = irq_get_irq_data(virq); 821137436c9SGavin Shan ichip = irq_data_get_irq_chip(idata); 822137436c9SGavin Shan phb->ioda.irq_chip_init = 1; 823137436c9SGavin Shan phb->ioda.irq_chip = *ichip; 824137436c9SGavin Shan phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 825137436c9SGavin Shan } 826137436c9SGavin Shan 827137436c9SGavin Shan irq_set_chip(virq, &phb->ioda.irq_chip); 828137436c9SGavin Shan } 829137436c9SGavin Shan 830184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 831184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 832184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 833184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 834184cd4a3SBenjamin Herrenschmidt 835184cd4a3SBenjamin Herrenschmidt return 0; 836184cd4a3SBenjamin Herrenschmidt } 837184cd4a3SBenjamin Herrenschmidt 838184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 839184cd4a3SBenjamin Herrenschmidt { 840fb1b55d6SGavin Shan unsigned int count; 841184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 842184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 843184cd4a3SBenjamin Herrenschmidt if (!prop) { 844184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 845184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 846184cd4a3SBenjamin Herrenschmidt } 847184cd4a3SBenjamin Herrenschmidt if (!prop) 848184cd4a3SBenjamin Herrenschmidt return; 849184cd4a3SBenjamin Herrenschmidt 850184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 851fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 852fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 853184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 854184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 855184cd4a3SBenjamin Herrenschmidt return; 856184cd4a3SBenjamin Herrenschmidt } 857fb1b55d6SGavin Shan 858184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 859184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 860184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 861fb1b55d6SGavin Shan count, phb->msi_base); 862184cd4a3SBenjamin Herrenschmidt } 863184cd4a3SBenjamin Herrenschmidt #else 864184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 865184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 866184cd4a3SBenjamin Herrenschmidt 86711685becSGavin Shan /* 86811685becSGavin Shan * This function is supposed to be called on basis of PE from top 86911685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 87011685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 87111685becSGavin Shan */ 872cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 87311685becSGavin Shan struct pnv_ioda_pe *pe) 87411685becSGavin Shan { 87511685becSGavin Shan struct pnv_phb *phb = hose->private_data; 87611685becSGavin Shan struct pci_bus_region region; 87711685becSGavin Shan struct resource *res; 87811685becSGavin Shan int i, index; 87911685becSGavin Shan int rc; 88011685becSGavin Shan 88111685becSGavin Shan /* 88211685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 88311685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 88411685becSGavin Shan * be figured out later. 88511685becSGavin Shan */ 88611685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 88711685becSGavin Shan 88811685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 88911685becSGavin Shan if (!res || !res->flags || 89011685becSGavin Shan res->start > res->end) 89111685becSGavin Shan continue; 89211685becSGavin Shan 89311685becSGavin Shan if (res->flags & IORESOURCE_IO) { 89411685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 89511685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 89611685becSGavin Shan index = region.start / phb->ioda.io_segsize; 89711685becSGavin Shan 89811685becSGavin Shan while (index < phb->ioda.total_pe && 89911685becSGavin Shan region.start <= region.end) { 90011685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 90111685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 90211685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 90311685becSGavin Shan if (rc != OPAL_SUCCESS) { 90411685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 90511685becSGavin Shan "segment #%d to PE#%d\n", 90611685becSGavin Shan __func__, rc, index, pe->pe_number); 90711685becSGavin Shan break; 90811685becSGavin Shan } 90911685becSGavin Shan 91011685becSGavin Shan region.start += phb->ioda.io_segsize; 91111685becSGavin Shan index++; 91211685becSGavin Shan } 91311685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 9143fd47f06SBenjamin Herrenschmidt /* WARNING: Assumes M32 is mem region 0 in PHB. We need to 9153fd47f06SBenjamin Herrenschmidt * harden that algorithm when we start supporting M64 9163fd47f06SBenjamin Herrenschmidt */ 91711685becSGavin Shan region.start = res->start - 9183fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 91911685becSGavin Shan phb->ioda.m32_pci_base; 92011685becSGavin Shan region.end = res->end - 9213fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 92211685becSGavin Shan phb->ioda.m32_pci_base; 92311685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 92411685becSGavin Shan 92511685becSGavin Shan while (index < phb->ioda.total_pe && 92611685becSGavin Shan region.start <= region.end) { 92711685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 92811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 92911685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 93011685becSGavin Shan if (rc != OPAL_SUCCESS) { 93111685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 93211685becSGavin Shan "segment#%d to PE#%d", 93311685becSGavin Shan __func__, rc, index, pe->pe_number); 93411685becSGavin Shan break; 93511685becSGavin Shan } 93611685becSGavin Shan 93711685becSGavin Shan region.start += phb->ioda.m32_segsize; 93811685becSGavin Shan index++; 93911685becSGavin Shan } 94011685becSGavin Shan } 94111685becSGavin Shan } 94211685becSGavin Shan } 94311685becSGavin Shan 944cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 94511685becSGavin Shan { 94611685becSGavin Shan struct pci_controller *tmp, *hose; 94711685becSGavin Shan struct pnv_phb *phb; 94811685becSGavin Shan struct pnv_ioda_pe *pe; 94911685becSGavin Shan 95011685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 95111685becSGavin Shan phb = hose->private_data; 95211685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 95311685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 95411685becSGavin Shan } 95511685becSGavin Shan } 95611685becSGavin Shan } 95711685becSGavin Shan 958cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 95913395c48SGavin Shan { 96013395c48SGavin Shan struct pci_controller *hose, *tmp; 961db1266c8SGavin Shan struct pnv_phb *phb; 96213395c48SGavin Shan 96313395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 96413395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 965db1266c8SGavin Shan 966db1266c8SGavin Shan /* Mark the PHB initialization done */ 967db1266c8SGavin Shan phb = hose->private_data; 968db1266c8SGavin Shan phb->initialized = 1; 96913395c48SGavin Shan } 97013395c48SGavin Shan } 97113395c48SGavin Shan 972cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 973fb446ad0SGavin Shan { 974fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 97511685becSGavin Shan pnv_pci_ioda_setup_seg(); 97613395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 977fb446ad0SGavin Shan } 978fb446ad0SGavin Shan 979271fd03aSGavin Shan /* 980271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 981271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 982271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 983271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 984271fd03aSGavin Shan * 1MiB for memory) will be returned. 985271fd03aSGavin Shan * 986271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 987271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 988271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 989271fd03aSGavin Shan * resources. 990271fd03aSGavin Shan */ 991271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 992271fd03aSGavin Shan unsigned long type) 993271fd03aSGavin Shan { 994271fd03aSGavin Shan struct pci_dev *bridge; 995271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 996271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 997271fd03aSGavin Shan int num_pci_bridges = 0; 998271fd03aSGavin Shan 999271fd03aSGavin Shan bridge = bus->self; 1000271fd03aSGavin Shan while (bridge) { 1001271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1002271fd03aSGavin Shan num_pci_bridges++; 1003271fd03aSGavin Shan if (num_pci_bridges >= 2) 1004271fd03aSGavin Shan return 1; 1005271fd03aSGavin Shan } 1006271fd03aSGavin Shan 1007271fd03aSGavin Shan bridge = bridge->bus->self; 1008271fd03aSGavin Shan } 1009271fd03aSGavin Shan 1010271fd03aSGavin Shan /* We need support prefetchable memory window later */ 1011271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1012271fd03aSGavin Shan return phb->ioda.m32_segsize; 1013271fd03aSGavin Shan 1014271fd03aSGavin Shan return phb->ioda.io_segsize; 1015271fd03aSGavin Shan } 1016271fd03aSGavin Shan 1017184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1018184cd4a3SBenjamin Herrenschmidt * assign a PE 1019184cd4a3SBenjamin Herrenschmidt */ 1020cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1021184cd4a3SBenjamin Herrenschmidt { 1022db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1023db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1024db1266c8SGavin Shan struct pci_dn *pdn; 1025184cd4a3SBenjamin Herrenschmidt 1026db1266c8SGavin Shan /* The function is probably called while the PEs have 1027db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1028db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1029db1266c8SGavin Shan * PEs isn't ready. 1030db1266c8SGavin Shan */ 1031db1266c8SGavin Shan if (!phb->initialized) 1032db1266c8SGavin Shan return 0; 1033db1266c8SGavin Shan 1034b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1035184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1036184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1037db1266c8SGavin Shan 1038184cd4a3SBenjamin Herrenschmidt return 0; 1039184cd4a3SBenjamin Herrenschmidt } 1040184cd4a3SBenjamin Herrenschmidt 1041184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1042184cd4a3SBenjamin Herrenschmidt u32 devfn) 1043184cd4a3SBenjamin Herrenschmidt { 1044184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1045184cd4a3SBenjamin Herrenschmidt } 1046184cd4a3SBenjamin Herrenschmidt 104773ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 104873ed148aSBenjamin Herrenschmidt { 104973ed148aSBenjamin Herrenschmidt opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET, 105073ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 105173ed148aSBenjamin Herrenschmidt } 105273ed148aSBenjamin Herrenschmidt 1053aa0c033fSGavin Shan void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type) 1054184cd4a3SBenjamin Herrenschmidt { 1055184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1056184cd4a3SBenjamin Herrenschmidt static int primary = 1; 1057184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 1058184cd4a3SBenjamin Herrenschmidt unsigned long size, m32map_off, iomap_off, pemap_off; 1059184cd4a3SBenjamin Herrenschmidt const u64 *prop64; 1060aa0c033fSGavin Shan const u32 *prop32; 1061184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1062184cd4a3SBenjamin Herrenschmidt void *aux; 1063184cd4a3SBenjamin Herrenschmidt long rc; 1064184cd4a3SBenjamin Herrenschmidt 1065aa0c033fSGavin Shan pr_info(" Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1066184cd4a3SBenjamin Herrenschmidt 1067184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1068184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1069184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1070184cd4a3SBenjamin Herrenschmidt return; 1071184cd4a3SBenjamin Herrenschmidt } 1072184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1073184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1074184cd4a3SBenjamin Herrenschmidt 1075184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 1076184cd4a3SBenjamin Herrenschmidt if (phb) { 1077184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 1078184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 1079184cd4a3SBenjamin Herrenschmidt } 1080184cd4a3SBenjamin Herrenschmidt if (!phb || !phb->hose) { 1081184cd4a3SBenjamin Herrenschmidt pr_err("PCI: Failed to allocate PCI controller for %s\n", 1082184cd4a3SBenjamin Herrenschmidt np->full_name); 1083184cd4a3SBenjamin Herrenschmidt return; 1084184cd4a3SBenjamin Herrenschmidt } 1085184cd4a3SBenjamin Herrenschmidt 1086184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1087184cd4a3SBenjamin Herrenschmidt /* XXX Use device-tree */ 1088184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1089184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1090184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1091184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1092aa0c033fSGavin Shan phb->type = ioda_type; 1093184cd4a3SBenjamin Herrenschmidt 1094cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1095cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1096cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1097f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1098aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1099cee72d5bSBenjamin Herrenschmidt else 1100cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1101cee72d5bSBenjamin Herrenschmidt 1102aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 1103184cd4a3SBenjamin Herrenschmidt pci_process_bridge_OF_ranges(phb->hose, np, primary); 1104184cd4a3SBenjamin Herrenschmidt primary = 0; 1105184cd4a3SBenjamin Herrenschmidt 1106aa0c033fSGavin Shan /* Get registers */ 1107184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1108184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1109184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1110184cd4a3SBenjamin Herrenschmidt 1111184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1112aa0c033fSGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 1113aa0c033fSGavin Shan if (!prop32) 1114aa0c033fSGavin Shan phb->ioda.total_pe = 1; 1115aa0c033fSGavin Shan else 1116aa0c033fSGavin Shan phb->ioda.total_pe = *prop32; 1117184cd4a3SBenjamin Herrenschmidt 1118184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1119aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 1120184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 1121184cd4a3SBenjamin Herrenschmidt 1122184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 11233fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 1124184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 1125184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1126184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1127184cd4a3SBenjamin Herrenschmidt 1128aa0c033fSGavin Shan /* Allocate aux data & arrays 1129aa0c033fSGavin Shan * 1130aa0c033fSGavin Shan * XXX TODO: Don't allocate io segmap on PHB3 1131aa0c033fSGavin Shan */ 1132184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1133184cd4a3SBenjamin Herrenschmidt m32map_off = size; 1134e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 1135184cd4a3SBenjamin Herrenschmidt iomap_off = size; 1136e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 1137184cd4a3SBenjamin Herrenschmidt pemap_off = size; 1138184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1139184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 1140184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 1141184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 1142184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 1143184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 1144184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 1145184cd4a3SBenjamin Herrenschmidt set_bit(0, phb->ioda.pe_alloc); 1146184cd4a3SBenjamin Herrenschmidt 11477ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1148184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 1149184cd4a3SBenjamin Herrenschmidt 1150184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 1151184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1152184cd4a3SBenjamin Herrenschmidt 1153184cd4a3SBenjamin Herrenschmidt /* Clear unusable m64 */ 1154184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].flags = 0; 1155184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].start = 0; 1156184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].end = 0; 1157184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].flags = 0; 1158184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].start = 0; 1159184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].end = 0; 1160184cd4a3SBenjamin Herrenschmidt 1161aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 1162184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1163184cd4a3SBenjamin Herrenschmidt window_type, 1164184cd4a3SBenjamin Herrenschmidt window_num, 1165184cd4a3SBenjamin Herrenschmidt starting_real_address, 1166184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1167184cd4a3SBenjamin Herrenschmidt segment_size); 1168184cd4a3SBenjamin Herrenschmidt #endif 1169184cd4a3SBenjamin Herrenschmidt 1170184cd4a3SBenjamin Herrenschmidt pr_info(" %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n", 1171184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 1172184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size, phb->ioda.m32_segsize, 1173184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1174184cd4a3SBenjamin Herrenschmidt 1175184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 1176184cd4a3SBenjamin Herrenschmidt 1177184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1178184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1179184cd4a3SBenjamin Herrenschmidt 1180184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1181184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1182184cd4a3SBenjamin Herrenschmidt 118373ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 118473ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 118573ed148aSBenjamin Herrenschmidt 1186184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1187184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1188184cd4a3SBenjamin Herrenschmidt 1189c40a4210SGavin Shan /* 1190c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1191c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1192c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1193c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1194c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1195184cd4a3SBenjamin Herrenschmidt */ 1196fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1197184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1198271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1199c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1200184cd4a3SBenjamin Herrenschmidt 1201184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1202f11fe552SBenjamin Herrenschmidt rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); 1203184cd4a3SBenjamin Herrenschmidt if (rc) 1204f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1205aa0c033fSGavin Shan 1206aa0c033fSGavin Shan /* 1207aa0c033fSGavin Shan * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset 1208aa0c033fSGavin Shan * has cleared the RTT which has the same effect 1209aa0c033fSGavin Shan */ 1210aa0c033fSGavin Shan if (ioda_type == PNV_PHB_IODA1) 1211184cd4a3SBenjamin Herrenschmidt opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE); 1212184cd4a3SBenjamin Herrenschmidt } 1213184cd4a3SBenjamin Herrenschmidt 1214aa0c033fSGavin Shan void pnv_pci_init_ioda2_phb(struct device_node *np) 1215aa0c033fSGavin Shan { 1216aa0c033fSGavin Shan pnv_pci_init_ioda_phb(np, PNV_PHB_IODA2); 1217aa0c033fSGavin Shan } 1218aa0c033fSGavin Shan 1219184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 1220184cd4a3SBenjamin Herrenschmidt { 1221184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 1222184cd4a3SBenjamin Herrenschmidt const u64 *prop64; 1223184cd4a3SBenjamin Herrenschmidt u64 hub_id; 1224184cd4a3SBenjamin Herrenschmidt 1225184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1226184cd4a3SBenjamin Herrenschmidt 1227184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1228184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1229184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1230184cd4a3SBenjamin Herrenschmidt return; 1231184cd4a3SBenjamin Herrenschmidt } 1232184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 1233184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1234184cd4a3SBenjamin Herrenschmidt 1235184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 1236184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 1237184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 1238184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1239aa0c033fSGavin Shan pnv_pci_init_ioda_phb(phbn, PNV_PHB_IODA1); 1240184cd4a3SBenjamin Herrenschmidt } 1241184cd4a3SBenjamin Herrenschmidt } 1242