1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26184cd4a3SBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 32fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 37137436c9SGavin Shan #include <asm/xics.h> 3837c367f2SGavin Shan #include <asm/debug.h> 39262af557SGuo Chao #include <asm/firmware.h> 4080c49c7eSIan Munsie #include <asm/pnv-pci.h> 4180c49c7eSIan Munsie 4280c49c7eSIan Munsie #include <misc/cxl.h> 43184cd4a3SBenjamin Herrenschmidt 44184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 45184cd4a3SBenjamin Herrenschmidt #include "pci.h" 46184cd4a3SBenjamin Herrenschmidt 476d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 486d31c2faSJoe Perches const char *fmt, ...) 496d31c2faSJoe Perches { 506d31c2faSJoe Perches struct va_format vaf; 516d31c2faSJoe Perches va_list args; 526d31c2faSJoe Perches char pfix[32]; 53184cd4a3SBenjamin Herrenschmidt 546d31c2faSJoe Perches va_start(args, fmt); 556d31c2faSJoe Perches 566d31c2faSJoe Perches vaf.fmt = fmt; 576d31c2faSJoe Perches vaf.va = &args; 586d31c2faSJoe Perches 596d31c2faSJoe Perches if (pe->pdev) 606d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 616d31c2faSJoe Perches else 626d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 636d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 646d31c2faSJoe Perches 656d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 666d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 676d31c2faSJoe Perches 686d31c2faSJoe Perches va_end(args); 696d31c2faSJoe Perches } 706d31c2faSJoe Perches 716d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 726d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 736d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 746d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 756d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 766d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 77184cd4a3SBenjamin Herrenschmidt 788e0a1611SAlexey Kardashevskiy /* 798e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 808e0a1611SAlexey Kardashevskiy * the architecture spec 818e0a1611SAlexey Kardashevskiy */ 828e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 838e0a1611SAlexey Kardashevskiy { 848e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 858e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 868e0a1611SAlexey Kardashevskiy } 878e0a1611SAlexey Kardashevskiy 88262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 89262af557SGuo Chao { 90262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 91262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 92262af557SGuo Chao } 93262af557SGuo Chao 944b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 954b82ab18SGavin Shan { 964b82ab18SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { 974b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 984b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 994b82ab18SGavin Shan return; 1004b82ab18SGavin Shan } 1014b82ab18SGavin Shan 1024b82ab18SGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) { 1034b82ab18SGavin Shan pr_warn("%s: PE %d was assigned on PHB#%x\n", 1044b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1054b82ab18SGavin Shan return; 1064b82ab18SGavin Shan } 1074b82ab18SGavin Shan 1084b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1094b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1104b82ab18SGavin Shan } 1114b82ab18SGavin Shan 112cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 113184cd4a3SBenjamin Herrenschmidt { 114184cd4a3SBenjamin Herrenschmidt unsigned long pe; 115184cd4a3SBenjamin Herrenschmidt 116184cd4a3SBenjamin Herrenschmidt do { 117184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 118184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 119184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 120184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 121184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 122184cd4a3SBenjamin Herrenschmidt 1234cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 124184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 125184cd4a3SBenjamin Herrenschmidt return pe; 126184cd4a3SBenjamin Herrenschmidt } 127184cd4a3SBenjamin Herrenschmidt 128cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 129184cd4a3SBenjamin Herrenschmidt { 130184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 131184cd4a3SBenjamin Herrenschmidt 132184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 133184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 134184cd4a3SBenjamin Herrenschmidt } 135184cd4a3SBenjamin Herrenschmidt 136262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 137262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 138262af557SGuo Chao { 139262af557SGuo Chao const char *desc; 140262af557SGuo Chao struct resource *r; 141262af557SGuo Chao s64 rc; 142262af557SGuo Chao 143262af557SGuo Chao /* Configure the default M64 BAR */ 144262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 145262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 146262af557SGuo Chao phb->ioda.m64_bar_idx, 147262af557SGuo Chao phb->ioda.m64_base, 148262af557SGuo Chao 0, /* unused */ 149262af557SGuo Chao phb->ioda.m64_size); 150262af557SGuo Chao if (rc != OPAL_SUCCESS) { 151262af557SGuo Chao desc = "configuring"; 152262af557SGuo Chao goto fail; 153262af557SGuo Chao } 154262af557SGuo Chao 155262af557SGuo Chao /* Enable the default M64 BAR */ 156262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 157262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 158262af557SGuo Chao phb->ioda.m64_bar_idx, 159262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 160262af557SGuo Chao if (rc != OPAL_SUCCESS) { 161262af557SGuo Chao desc = "enabling"; 162262af557SGuo Chao goto fail; 163262af557SGuo Chao } 164262af557SGuo Chao 165262af557SGuo Chao /* Mark the M64 BAR assigned */ 166262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 167262af557SGuo Chao 168262af557SGuo Chao /* 169262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 170262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 171262af557SGuo Chao */ 172262af557SGuo Chao r = &phb->hose->mem_resources[1]; 173262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 174262af557SGuo Chao r->start += phb->ioda.m64_segsize; 175262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 176262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 177262af557SGuo Chao else 178262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 179262af557SGuo Chao phb->ioda.reserved_pe); 180262af557SGuo Chao 181262af557SGuo Chao return 0; 182262af557SGuo Chao 183262af557SGuo Chao fail: 184262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 185262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 186262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 187262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 188262af557SGuo Chao phb->ioda.m64_bar_idx, 189262af557SGuo Chao OPAL_DISABLE_M64); 190262af557SGuo Chao return -EIO; 191262af557SGuo Chao } 192262af557SGuo Chao 1935ef73567SGavin Shan static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) 194262af557SGuo Chao { 195262af557SGuo Chao resource_size_t sgsz = phb->ioda.m64_segsize; 196262af557SGuo Chao struct pci_dev *pdev; 197262af557SGuo Chao struct resource *r; 198262af557SGuo Chao int base, step, i; 199262af557SGuo Chao 200262af557SGuo Chao /* 201262af557SGuo Chao * Root bus always has full M64 range and root port has 202262af557SGuo Chao * M64 range used in reality. So we're checking root port 203262af557SGuo Chao * instead of root bus. 204262af557SGuo Chao */ 205262af557SGuo Chao list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { 2064b82ab18SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 2074b82ab18SGavin Shan r = &pdev->resource[PCI_BRIDGE_RESOURCES + i]; 208262af557SGuo Chao if (!r->parent || 209262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 210262af557SGuo Chao continue; 211262af557SGuo Chao 212262af557SGuo Chao base = (r->start - phb->ioda.m64_base) / sgsz; 213262af557SGuo Chao for (step = 0; step < resource_size(r) / sgsz; step++) 2144b82ab18SGavin Shan pnv_ioda_reserve_pe(phb, base + step); 215262af557SGuo Chao } 216262af557SGuo Chao } 217262af557SGuo Chao } 218262af557SGuo Chao 219262af557SGuo Chao static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 220262af557SGuo Chao struct pci_bus *bus, int all) 221262af557SGuo Chao { 222262af557SGuo Chao resource_size_t segsz = phb->ioda.m64_segsize; 223262af557SGuo Chao struct pci_dev *pdev; 224262af557SGuo Chao struct resource *r; 225262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 226262af557SGuo Chao unsigned long size, *pe_alloc; 227262af557SGuo Chao bool found; 228262af557SGuo Chao int start, i, j; 229262af557SGuo Chao 230262af557SGuo Chao /* Root bus shouldn't use M64 */ 231262af557SGuo Chao if (pci_is_root_bus(bus)) 232262af557SGuo Chao return IODA_INVALID_PE; 233262af557SGuo Chao 234262af557SGuo Chao /* We support only one M64 window on each bus */ 235262af557SGuo Chao found = false; 236262af557SGuo Chao pci_bus_for_each_resource(bus, r, i) { 237262af557SGuo Chao if (r && r->parent && 238262af557SGuo Chao pnv_pci_is_mem_pref_64(r->flags)) { 239262af557SGuo Chao found = true; 240262af557SGuo Chao break; 241262af557SGuo Chao } 242262af557SGuo Chao } 243262af557SGuo Chao 244262af557SGuo Chao /* No M64 window found ? */ 245262af557SGuo Chao if (!found) 246262af557SGuo Chao return IODA_INVALID_PE; 247262af557SGuo Chao 248262af557SGuo Chao /* Allocate bitmap */ 249262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 250262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 251262af557SGuo Chao if (!pe_alloc) { 252262af557SGuo Chao pr_warn("%s: Out of memory !\n", 253262af557SGuo Chao __func__); 254262af557SGuo Chao return IODA_INVALID_PE; 255262af557SGuo Chao } 256262af557SGuo Chao 257262af557SGuo Chao /* 258262af557SGuo Chao * Figure out reserved PE numbers by the PE 259262af557SGuo Chao * the its child PEs. 260262af557SGuo Chao */ 261262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 262262af557SGuo Chao for (i = 0; i < resource_size(r) / segsz; i++) 263262af557SGuo Chao set_bit(start + i, pe_alloc); 264262af557SGuo Chao 265262af557SGuo Chao if (all) 266262af557SGuo Chao goto done; 267262af557SGuo Chao 268262af557SGuo Chao /* 269262af557SGuo Chao * If the PE doesn't cover all subordinate buses, 270262af557SGuo Chao * we need subtract from reserved PEs for children. 271262af557SGuo Chao */ 272262af557SGuo Chao list_for_each_entry(pdev, &bus->devices, bus_list) { 273262af557SGuo Chao if (!pdev->subordinate) 274262af557SGuo Chao continue; 275262af557SGuo Chao 276262af557SGuo Chao pci_bus_for_each_resource(pdev->subordinate, r, i) { 277262af557SGuo Chao if (!r || !r->parent || 278262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 279262af557SGuo Chao continue; 280262af557SGuo Chao 281262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 282262af557SGuo Chao for (j = 0; j < resource_size(r) / segsz ; j++) 283262af557SGuo Chao clear_bit(start + j, pe_alloc); 284262af557SGuo Chao } 285262af557SGuo Chao } 286262af557SGuo Chao 287262af557SGuo Chao /* 288262af557SGuo Chao * the current bus might not own M64 window and that's all 289262af557SGuo Chao * contributed by its child buses. For the case, we needn't 290262af557SGuo Chao * pick M64 dependent PE#. 291262af557SGuo Chao */ 292262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 293262af557SGuo Chao kfree(pe_alloc); 294262af557SGuo Chao return IODA_INVALID_PE; 295262af557SGuo Chao } 296262af557SGuo Chao 297262af557SGuo Chao /* 298262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 299262af557SGuo Chao * PE's list to form compound PE. 300262af557SGuo Chao */ 301262af557SGuo Chao done: 302262af557SGuo Chao master_pe = NULL; 303262af557SGuo Chao i = -1; 304262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 305262af557SGuo Chao phb->ioda.total_pe) { 306262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 307262af557SGuo Chao 308262af557SGuo Chao if (!master_pe) { 309262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 310262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 311262af557SGuo Chao master_pe = pe; 312262af557SGuo Chao } else { 313262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 314262af557SGuo Chao pe->master = master_pe; 315262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 316262af557SGuo Chao } 317262af557SGuo Chao } 318262af557SGuo Chao 319262af557SGuo Chao kfree(pe_alloc); 320262af557SGuo Chao return master_pe->pe_number; 321262af557SGuo Chao } 322262af557SGuo Chao 323262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 324262af557SGuo Chao { 325262af557SGuo Chao struct pci_controller *hose = phb->hose; 326262af557SGuo Chao struct device_node *dn = hose->dn; 327262af557SGuo Chao struct resource *res; 328262af557SGuo Chao const u32 *r; 329262af557SGuo Chao u64 pci_addr; 330262af557SGuo Chao 3311665c4a8SGavin Shan /* FIXME: Support M64 for P7IOC */ 3321665c4a8SGavin Shan if (phb->type != PNV_PHB_IODA2) { 3331665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3341665c4a8SGavin Shan return; 3351665c4a8SGavin Shan } 3361665c4a8SGavin Shan 337262af557SGuo Chao if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 338262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 339262af557SGuo Chao return; 340262af557SGuo Chao } 341262af557SGuo Chao 342262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 343262af557SGuo Chao if (!r) { 344262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 345262af557SGuo Chao dn->full_name); 346262af557SGuo Chao return; 347262af557SGuo Chao } 348262af557SGuo Chao 349262af557SGuo Chao res = &hose->mem_resources[1]; 350262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 351262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 352262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 353262af557SGuo Chao pci_addr = of_read_number(r, 2); 354262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 355262af557SGuo Chao 356262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 357262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 358262af557SGuo Chao phb->ioda.m64_base = pci_addr; 359262af557SGuo Chao 360262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 361262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 362262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 3635ef73567SGavin Shan phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 364262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 365262af557SGuo Chao } 366262af557SGuo Chao 36749dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 36849dec922SGavin Shan { 36949dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 37049dec922SGavin Shan struct pnv_ioda_pe *slave; 37149dec922SGavin Shan s64 rc; 37249dec922SGavin Shan 37349dec922SGavin Shan /* Fetch master PE */ 37449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 37549dec922SGavin Shan pe = pe->master; 37649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 37749dec922SGavin Shan pe_no = pe->pe_number; 37849dec922SGavin Shan } 37949dec922SGavin Shan 38049dec922SGavin Shan /* Freeze master PE */ 38149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 38249dec922SGavin Shan pe_no, 38349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 38449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 38549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 38649dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 38749dec922SGavin Shan return; 38849dec922SGavin Shan } 38949dec922SGavin Shan 39049dec922SGavin Shan /* Freeze slave PEs */ 39149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 39249dec922SGavin Shan return; 39349dec922SGavin Shan 39449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 39549dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 39649dec922SGavin Shan slave->pe_number, 39749dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 39849dec922SGavin Shan if (rc != OPAL_SUCCESS) 39949dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 40049dec922SGavin Shan __func__, rc, phb->hose->global_number, 40149dec922SGavin Shan slave->pe_number); 40249dec922SGavin Shan } 40349dec922SGavin Shan } 40449dec922SGavin Shan 405e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 40649dec922SGavin Shan { 40749dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 40849dec922SGavin Shan s64 rc; 40949dec922SGavin Shan 41049dec922SGavin Shan /* Find master PE */ 41149dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 41249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 41349dec922SGavin Shan pe = pe->master; 41449dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 41549dec922SGavin Shan pe_no = pe->pe_number; 41649dec922SGavin Shan } 41749dec922SGavin Shan 41849dec922SGavin Shan /* Clear frozen state for master PE */ 41949dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 42049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 42149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 42249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 42349dec922SGavin Shan return -EIO; 42449dec922SGavin Shan } 42549dec922SGavin Shan 42649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 42749dec922SGavin Shan return 0; 42849dec922SGavin Shan 42949dec922SGavin Shan /* Clear frozen state for slave PEs */ 43049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 43149dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 43249dec922SGavin Shan slave->pe_number, 43349dec922SGavin Shan opt); 43449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 43549dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 43649dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 43749dec922SGavin Shan slave->pe_number); 43849dec922SGavin Shan return -EIO; 43949dec922SGavin Shan } 44049dec922SGavin Shan } 44149dec922SGavin Shan 44249dec922SGavin Shan return 0; 44349dec922SGavin Shan } 44449dec922SGavin Shan 44549dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 44649dec922SGavin Shan { 44749dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 44849dec922SGavin Shan u8 fstate, state; 44949dec922SGavin Shan __be16 pcierr; 45049dec922SGavin Shan s64 rc; 45149dec922SGavin Shan 45249dec922SGavin Shan /* Sanity check on PE number */ 45349dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 45449dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 45549dec922SGavin Shan 45649dec922SGavin Shan /* 45749dec922SGavin Shan * Fetch the master PE and the PE instance might be 45849dec922SGavin Shan * not initialized yet. 45949dec922SGavin Shan */ 46049dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 46149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 46249dec922SGavin Shan pe = pe->master; 46349dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 46449dec922SGavin Shan pe_no = pe->pe_number; 46549dec922SGavin Shan } 46649dec922SGavin Shan 46749dec922SGavin Shan /* Check the master PE */ 46849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 46949dec922SGavin Shan &state, &pcierr, NULL); 47049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47149dec922SGavin Shan pr_warn("%s: Failure %lld getting " 47249dec922SGavin Shan "PHB#%x-PE#%x state\n", 47349dec922SGavin Shan __func__, rc, 47449dec922SGavin Shan phb->hose->global_number, pe_no); 47549dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 47649dec922SGavin Shan } 47749dec922SGavin Shan 47849dec922SGavin Shan /* Check the slave PE */ 47949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 48049dec922SGavin Shan return state; 48149dec922SGavin Shan 48249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 48349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 48449dec922SGavin Shan slave->pe_number, 48549dec922SGavin Shan &fstate, 48649dec922SGavin Shan &pcierr, 48749dec922SGavin Shan NULL); 48849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 48949dec922SGavin Shan pr_warn("%s: Failure %lld getting " 49049dec922SGavin Shan "PHB#%x-PE#%x state\n", 49149dec922SGavin Shan __func__, rc, 49249dec922SGavin Shan phb->hose->global_number, slave->pe_number); 49349dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 49449dec922SGavin Shan } 49549dec922SGavin Shan 49649dec922SGavin Shan /* 49749dec922SGavin Shan * Override the result based on the ascending 49849dec922SGavin Shan * priority. 49949dec922SGavin Shan */ 50049dec922SGavin Shan if (fstate > state) 50149dec922SGavin Shan state = fstate; 50249dec922SGavin Shan } 50349dec922SGavin Shan 50449dec922SGavin Shan return state; 50549dec922SGavin Shan } 50649dec922SGavin Shan 507184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 508184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 509184cd4a3SBenjamin Herrenschmidt */ 510184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 511cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 512184cd4a3SBenjamin Herrenschmidt { 513184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 514184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 515b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 516184cd4a3SBenjamin Herrenschmidt 517184cd4a3SBenjamin Herrenschmidt if (!pdn) 518184cd4a3SBenjamin Herrenschmidt return NULL; 519184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 520184cd4a3SBenjamin Herrenschmidt return NULL; 521184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 522184cd4a3SBenjamin Herrenschmidt } 523184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 524184cd4a3SBenjamin Herrenschmidt 525cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 526184cd4a3SBenjamin Herrenschmidt { 527184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 528184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 529184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 530184cd4a3SBenjamin Herrenschmidt 531184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 532184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 533184cd4a3SBenjamin Herrenschmidt int count; 534184cd4a3SBenjamin Herrenschmidt 535184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 536184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 537184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 538fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 539b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 540fb446ad0SGavin Shan else 541fb446ad0SGavin Shan count = 1; 542fb446ad0SGavin Shan 543184cd4a3SBenjamin Herrenschmidt switch(count) { 544184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 545184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 546184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 547184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 548184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 549184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 550184cd4a3SBenjamin Herrenschmidt default: 551184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 552184cd4a3SBenjamin Herrenschmidt " unsupported\n", 553184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 554184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 555184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 556184cd4a3SBenjamin Herrenschmidt } 557184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 558184cd4a3SBenjamin Herrenschmidt } else { 559184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 560184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 561184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 562184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 563184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 564184cd4a3SBenjamin Herrenschmidt } 565184cd4a3SBenjamin Herrenschmidt 566631ad691SGavin Shan /* 567631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 568631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 569631ad691SGavin Shan * originated from the PE might contribute to other 570631ad691SGavin Shan * PEs. 571631ad691SGavin Shan */ 572184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 573184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 574184cd4a3SBenjamin Herrenschmidt if (rc) { 575184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 576184cd4a3SBenjamin Herrenschmidt return -ENXIO; 577184cd4a3SBenjamin Herrenschmidt } 578631ad691SGavin Shan 579631ad691SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 580631ad691SGavin Shan pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 581631ad691SGavin Shan if (rc) 582631ad691SGavin Shan pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc); 583184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 584184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 585184cd4a3SBenjamin Herrenschmidt 586184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 587184cd4a3SBenjamin Herrenschmidt while (parent) { 588b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(parent); 589184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 590184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 591cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 592184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 593184cd4a3SBenjamin Herrenschmidt } 594184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 595184cd4a3SBenjamin Herrenschmidt } 596184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 597184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 598184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 599184cd4a3SBenjamin Herrenschmidt 600184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 601184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 602184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 603184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 604184cd4a3SBenjamin Herrenschmidt pe->pe_number); 605184cd4a3SBenjamin Herrenschmidt if (rc) { 606184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 607184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 608184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 609184cd4a3SBenjamin Herrenschmidt } else { 610184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 611cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 612184cd4a3SBenjamin Herrenschmidt if (rc) { 613184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 614184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 615184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 616184cd4a3SBenjamin Herrenschmidt } 617184cd4a3SBenjamin Herrenschmidt } 618184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 619184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 620184cd4a3SBenjamin Herrenschmidt 621184cd4a3SBenjamin Herrenschmidt return 0; 622184cd4a3SBenjamin Herrenschmidt } 623184cd4a3SBenjamin Herrenschmidt 624cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 625184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 626184cd4a3SBenjamin Herrenschmidt { 627184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 628184cd4a3SBenjamin Herrenschmidt 6297ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 630184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 6317ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 632184cd4a3SBenjamin Herrenschmidt return; 633184cd4a3SBenjamin Herrenschmidt } 634184cd4a3SBenjamin Herrenschmidt } 6357ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 636184cd4a3SBenjamin Herrenschmidt } 637184cd4a3SBenjamin Herrenschmidt 638184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 639184cd4a3SBenjamin Herrenschmidt { 640184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 641184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 642184cd4a3SBenjamin Herrenschmidt */ 643184cd4a3SBenjamin Herrenschmidt 644184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 645184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 646184cd4a3SBenjamin Herrenschmidt return 0; 647184cd4a3SBenjamin Herrenschmidt 648184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 649184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 650184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 651184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 652184cd4a3SBenjamin Herrenschmidt return 3; 653184cd4a3SBenjamin Herrenschmidt 654184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 655184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 656184cd4a3SBenjamin Herrenschmidt return 15; 657184cd4a3SBenjamin Herrenschmidt 658184cd4a3SBenjamin Herrenschmidt /* Default */ 659184cd4a3SBenjamin Herrenschmidt return 10; 660184cd4a3SBenjamin Herrenschmidt } 661184cd4a3SBenjamin Herrenschmidt 662fb446ad0SGavin Shan #if 0 663cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 664184cd4a3SBenjamin Herrenschmidt { 665184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 666184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 667b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 668184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 669184cd4a3SBenjamin Herrenschmidt int pe_num; 670184cd4a3SBenjamin Herrenschmidt 671184cd4a3SBenjamin Herrenschmidt if (!pdn) { 672184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 673184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 674184cd4a3SBenjamin Herrenschmidt return NULL; 675184cd4a3SBenjamin Herrenschmidt } 676184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 677184cd4a3SBenjamin Herrenschmidt return NULL; 678184cd4a3SBenjamin Herrenschmidt 679184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 680184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 681184cd4a3SBenjamin Herrenschmidt pe_num = 0; 682184cd4a3SBenjamin Herrenschmidt else 683184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 684184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 685184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 686184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 687184cd4a3SBenjamin Herrenschmidt return NULL; 688184cd4a3SBenjamin Herrenschmidt } 689184cd4a3SBenjamin Herrenschmidt 690184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 691184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 692184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 693184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 694184cd4a3SBenjamin Herrenschmidt * 695184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 696184cd4a3SBenjamin Herrenschmidt */ 697184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 698184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 699184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 700184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 701184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 702184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 703184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 704184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 705184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 706184cd4a3SBenjamin Herrenschmidt 707184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 708184cd4a3SBenjamin Herrenschmidt 709184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 710184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 711184cd4a3SBenjamin Herrenschmidt if (pe_num) 712184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 713184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 714184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 715184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 716184cd4a3SBenjamin Herrenschmidt return NULL; 717184cd4a3SBenjamin Herrenschmidt } 718184cd4a3SBenjamin Herrenschmidt 719184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 720184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 721184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 722184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 723184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 724184cd4a3SBenjamin Herrenschmidt } 725184cd4a3SBenjamin Herrenschmidt 726184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 727184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 728184cd4a3SBenjamin Herrenschmidt 729184cd4a3SBenjamin Herrenschmidt return pe; 730184cd4a3SBenjamin Herrenschmidt } 731fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 732184cd4a3SBenjamin Herrenschmidt 733184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 734184cd4a3SBenjamin Herrenschmidt { 735184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 736184cd4a3SBenjamin Herrenschmidt 737184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 738b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 739184cd4a3SBenjamin Herrenschmidt 740184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 741184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 742184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 743184cd4a3SBenjamin Herrenschmidt continue; 744184cd4a3SBenjamin Herrenschmidt } 745184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 746184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 747184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 748fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 749184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 750184cd4a3SBenjamin Herrenschmidt } 751184cd4a3SBenjamin Herrenschmidt } 752184cd4a3SBenjamin Herrenschmidt 753fb446ad0SGavin Shan /* 754fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 755fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 756fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 757fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 758fb446ad0SGavin Shan */ 759cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 760184cd4a3SBenjamin Herrenschmidt { 761fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 762184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 763184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 764262af557SGuo Chao int pe_num = IODA_INVALID_PE; 765184cd4a3SBenjamin Herrenschmidt 766262af557SGuo Chao /* Check if PE is determined by M64 */ 767262af557SGuo Chao if (phb->pick_m64_pe) 768262af557SGuo Chao pe_num = phb->pick_m64_pe(phb, bus, all); 769262af557SGuo Chao 770262af557SGuo Chao /* The PE number isn't pinned by M64 */ 771262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 772184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 773262af557SGuo Chao 774184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 775fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 776fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 777184cd4a3SBenjamin Herrenschmidt return; 778184cd4a3SBenjamin Herrenschmidt } 779184cd4a3SBenjamin Herrenschmidt 780184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 781262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 782184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 783184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 784184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 785184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 786b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 787184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 788184cd4a3SBenjamin Herrenschmidt 789fb446ad0SGavin Shan if (all) 790fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 791fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 792fb446ad0SGavin Shan else 793fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 794fb446ad0SGavin Shan bus->busn_res.start, pe_num); 795184cd4a3SBenjamin Herrenschmidt 796184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 797184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 798184cd4a3SBenjamin Herrenschmidt if (pe_num) 799184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 800184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 801184cd4a3SBenjamin Herrenschmidt return; 802184cd4a3SBenjamin Herrenschmidt } 803184cd4a3SBenjamin Herrenschmidt 804184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 805184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 806184cd4a3SBenjamin Herrenschmidt 8077ebdf956SGavin Shan /* Put PE to the list */ 8087ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 8097ebdf956SGavin Shan 810184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 811184cd4a3SBenjamin Herrenschmidt * below the bridge 812184cd4a3SBenjamin Herrenschmidt */ 813184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 814184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 815184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 816184cd4a3SBenjamin Herrenschmidt } 817184cd4a3SBenjamin Herrenschmidt 818184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 819184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 820184cd4a3SBenjamin Herrenschmidt } 821184cd4a3SBenjamin Herrenschmidt 822cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 823184cd4a3SBenjamin Herrenschmidt { 824184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 825fb446ad0SGavin Shan 826fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 827184cd4a3SBenjamin Herrenschmidt 828184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 829fb446ad0SGavin Shan if (dev->subordinate) { 83062f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 831fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 832fb446ad0SGavin Shan else 833184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 834184cd4a3SBenjamin Herrenschmidt } 835184cd4a3SBenjamin Herrenschmidt } 836fb446ad0SGavin Shan } 837fb446ad0SGavin Shan 838fb446ad0SGavin Shan /* 839fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 840fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 841fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 842fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 843fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 844fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 845fb446ad0SGavin Shan */ 846cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 847fb446ad0SGavin Shan { 848fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 849262af557SGuo Chao struct pnv_phb *phb; 850fb446ad0SGavin Shan 851fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 852262af557SGuo Chao phb = hose->private_data; 853262af557SGuo Chao 854262af557SGuo Chao /* M64 layout might affect PE allocation */ 8555ef73567SGavin Shan if (phb->reserve_m64_pe) 8565ef73567SGavin Shan phb->reserve_m64_pe(phb); 857262af557SGuo Chao 858fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 859fb446ad0SGavin Shan } 860fb446ad0SGavin Shan } 861184cd4a3SBenjamin Herrenschmidt 862959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 863184cd4a3SBenjamin Herrenschmidt { 864b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 865959c9bddSGavin Shan struct pnv_ioda_pe *pe; 866184cd4a3SBenjamin Herrenschmidt 867959c9bddSGavin Shan /* 868959c9bddSGavin Shan * The function can be called while the PE# 869959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 870959c9bddSGavin Shan * case. 871959c9bddSGavin Shan */ 872959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 873959c9bddSGavin Shan return; 874184cd4a3SBenjamin Herrenschmidt 875959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 876cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 877763fe0adSGavin Shan set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); 878184cd4a3SBenjamin Herrenschmidt } 879184cd4a3SBenjamin Herrenschmidt 880cd15b048SBenjamin Herrenschmidt static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, 881cd15b048SBenjamin Herrenschmidt struct pci_dev *pdev, u64 dma_mask) 882cd15b048SBenjamin Herrenschmidt { 883cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 884cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 885cd15b048SBenjamin Herrenschmidt uint64_t top; 886cd15b048SBenjamin Herrenschmidt bool bypass = false; 887cd15b048SBenjamin Herrenschmidt 888cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 889cd15b048SBenjamin Herrenschmidt return -ENODEV;; 890cd15b048SBenjamin Herrenschmidt 891cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 892cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 893cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 894cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 895cd15b048SBenjamin Herrenschmidt } 896cd15b048SBenjamin Herrenschmidt 897cd15b048SBenjamin Herrenschmidt if (bypass) { 898cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 899cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 900cd15b048SBenjamin Herrenschmidt set_dma_offset(&pdev->dev, pe->tce_bypass_base); 901cd15b048SBenjamin Herrenschmidt } else { 902cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 903cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 904cd15b048SBenjamin Herrenschmidt set_iommu_table_base(&pdev->dev, &pe->tce32_table); 905cd15b048SBenjamin Herrenschmidt } 906a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 907cd15b048SBenjamin Herrenschmidt return 0; 908cd15b048SBenjamin Herrenschmidt } 909cd15b048SBenjamin Herrenschmidt 910fe7e85c6SGavin Shan static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, 911fe7e85c6SGavin Shan struct pci_dev *pdev) 912fe7e85c6SGavin Shan { 913fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 914fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 915fe7e85c6SGavin Shan u64 end, mask; 916fe7e85c6SGavin Shan 917fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 918fe7e85c6SGavin Shan return 0; 919fe7e85c6SGavin Shan 920fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 921fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 922fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 923fe7e85c6SGavin Shan 924fe7e85c6SGavin Shan 925fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 926fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 927fe7e85c6SGavin Shan mask += mask - 1; 928fe7e85c6SGavin Shan 929fe7e85c6SGavin Shan return mask; 930fe7e85c6SGavin Shan } 931fe7e85c6SGavin Shan 932dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 933dff4a39eSGavin Shan struct pci_bus *bus, 934dff4a39eSGavin Shan bool add_to_iommu_group) 93574251fe2SBenjamin Herrenschmidt { 93674251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 93774251fe2SBenjamin Herrenschmidt 93874251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 939dff4a39eSGavin Shan if (add_to_iommu_group) 940dff4a39eSGavin Shan set_iommu_table_base_and_group(&dev->dev, 941dff4a39eSGavin Shan &pe->tce32_table); 942dff4a39eSGavin Shan else 943dff4a39eSGavin Shan set_iommu_table_base(&dev->dev, &pe->tce32_table); 944dff4a39eSGavin Shan 94574251fe2SBenjamin Herrenschmidt if (dev->subordinate) 946dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, dev->subordinate, 947dff4a39eSGavin Shan add_to_iommu_group); 94874251fe2SBenjamin Herrenschmidt } 94974251fe2SBenjamin Herrenschmidt } 95074251fe2SBenjamin Herrenschmidt 9518e0a1611SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, 9528e0a1611SAlexey Kardashevskiy struct iommu_table *tbl, 9533ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 9544cce9550SGavin Shan { 9553ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 9563ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 9573ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 9584cce9550SGavin Shan unsigned long start, end, inc; 959b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 9604cce9550SGavin Shan 9614cce9550SGavin Shan start = __pa(startp); 9624cce9550SGavin Shan end = __pa(endp); 9634cce9550SGavin Shan 9644cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 9654cce9550SGavin Shan if (tbl->it_busno) { 966b0376c9bSAlexey Kardashevskiy start <<= shift; 967b0376c9bSAlexey Kardashevskiy end <<= shift; 968b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 9694cce9550SGavin Shan start |= tbl->it_busno; 9704cce9550SGavin Shan end |= tbl->it_busno; 9714cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 9724cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 9734cce9550SGavin Shan start |= (1ull << 63); 9744cce9550SGavin Shan end |= (1ull << 63); 9754cce9550SGavin Shan inc = 16; 9764cce9550SGavin Shan } else { 9774cce9550SGavin Shan /* Default (older HW) */ 9784cce9550SGavin Shan inc = 128; 9794cce9550SGavin Shan } 9804cce9550SGavin Shan 9814cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 9824cce9550SGavin Shan 9834cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 9844cce9550SGavin Shan while (start <= end) { 9858e0a1611SAlexey Kardashevskiy if (rm) 9863ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 9878e0a1611SAlexey Kardashevskiy else 9883a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 9894cce9550SGavin Shan start += inc; 9904cce9550SGavin Shan } 9914cce9550SGavin Shan 9924cce9550SGavin Shan /* 9934cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 9944cce9550SGavin Shan * and we don't care on free() 9954cce9550SGavin Shan */ 9964cce9550SGavin Shan } 9974cce9550SGavin Shan 9984cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 9994cce9550SGavin Shan struct iommu_table *tbl, 10003ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 10014cce9550SGavin Shan { 10024cce9550SGavin Shan unsigned long start, end, inc; 10033ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 10043ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 10053ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 1006b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 10074cce9550SGavin Shan 10084cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1009b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 10104cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 10114cce9550SGavin Shan end = start; 10124cce9550SGavin Shan 10134cce9550SGavin Shan /* Figure out the start, end and step */ 10144cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 1015b0376c9bSAlexey Kardashevskiy start |= (inc << shift); 10164cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 1017b0376c9bSAlexey Kardashevskiy end |= (inc << shift); 1018b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 10194cce9550SGavin Shan mb(); 10204cce9550SGavin Shan 10214cce9550SGavin Shan while (start <= end) { 10228e0a1611SAlexey Kardashevskiy if (rm) 10233ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 10248e0a1611SAlexey Kardashevskiy else 10253a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 10264cce9550SGavin Shan start += inc; 10274cce9550SGavin Shan } 10284cce9550SGavin Shan } 10294cce9550SGavin Shan 10304cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 10313ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 10324cce9550SGavin Shan { 10334cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 10344cce9550SGavin Shan tce32_table); 10354cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 10364cce9550SGavin Shan 10374cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 10388e0a1611SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); 10394cce9550SGavin Shan else 10408e0a1611SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); 10414cce9550SGavin Shan } 10424cce9550SGavin Shan 1043cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1044cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1045184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1046184cd4a3SBenjamin Herrenschmidt { 1047184cd4a3SBenjamin Herrenschmidt 1048184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1049184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 1050184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1051184cd4a3SBenjamin Herrenschmidt unsigned int i; 1052184cd4a3SBenjamin Herrenschmidt int64_t rc; 1053184cd4a3SBenjamin Herrenschmidt void *addr; 1054184cd4a3SBenjamin Herrenschmidt 1055184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 1056184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 1057184cd4a3SBenjamin Herrenschmidt 1058184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1059184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1060184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1061184cd4a3SBenjamin Herrenschmidt 1062184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1063184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1064184cd4a3SBenjamin Herrenschmidt return; 1065184cd4a3SBenjamin Herrenschmidt 1066184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1067184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1068184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1069184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1070184cd4a3SBenjamin Herrenschmidt 1071184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1072184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1073184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1074184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1075184cd4a3SBenjamin Herrenschmidt */ 1076184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1077184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1078184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1079184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1080184cd4a3SBenjamin Herrenschmidt goto fail; 1081184cd4a3SBenjamin Herrenschmidt } 1082184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1083184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1084184cd4a3SBenjamin Herrenschmidt 1085184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1086184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1087184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1088184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1089184cd4a3SBenjamin Herrenschmidt base + i, 1, 1090184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1091184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1092184cd4a3SBenjamin Herrenschmidt if (rc) { 1093184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1094184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1095184cd4a3SBenjamin Herrenschmidt goto fail; 1096184cd4a3SBenjamin Herrenschmidt } 1097184cd4a3SBenjamin Herrenschmidt } 1098184cd4a3SBenjamin Herrenschmidt 1099184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1100184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 1101184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 11028fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1103184cd4a3SBenjamin Herrenschmidt 1104184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 1105184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1106184cd4a3SBenjamin Herrenschmidt if (swinvp) { 1107184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 1108184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 1109184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 1110184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 1111184cd4a3SBenjamin Herrenschmidt */ 11128e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 11138e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 11148e0a1611SAlexey Kardashevskiy 8); 111565fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 111665fd766bSGavin Shan TCE_PCI_SWINV_FREE | 111765fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 1118184cd4a3SBenjamin Herrenschmidt } 1119184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1120e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1121184cd4a3SBenjamin Herrenschmidt 112274251fe2SBenjamin Herrenschmidt if (pe->pdev) 1123d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 112474251fe2SBenjamin Herrenschmidt else 1125dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 112674251fe2SBenjamin Herrenschmidt 1127184cd4a3SBenjamin Herrenschmidt return; 1128184cd4a3SBenjamin Herrenschmidt fail: 1129184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1130184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1131184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1132184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1133184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 1134184cd4a3SBenjamin Herrenschmidt } 1135184cd4a3SBenjamin Herrenschmidt 1136cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) 1137cd15b048SBenjamin Herrenschmidt { 1138cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 1139cd15b048SBenjamin Herrenschmidt tce32_table); 1140cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1141cd15b048SBenjamin Herrenschmidt int64_t rc; 1142cd15b048SBenjamin Herrenschmidt 1143cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1144cd15b048SBenjamin Herrenschmidt if (enable) { 1145cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1146cd15b048SBenjamin Herrenschmidt 1147cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1148cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1149cd15b048SBenjamin Herrenschmidt pe->pe_number, 1150cd15b048SBenjamin Herrenschmidt window_id, 1151cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1152cd15b048SBenjamin Herrenschmidt top); 1153cd15b048SBenjamin Herrenschmidt } else { 1154cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1155cd15b048SBenjamin Herrenschmidt pe->pe_number, 1156cd15b048SBenjamin Herrenschmidt window_id, 1157cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1158cd15b048SBenjamin Herrenschmidt 0); 1159cd15b048SBenjamin Herrenschmidt 1160cd15b048SBenjamin Herrenschmidt /* 1161dff4a39eSGavin Shan * EEH needs the mapping between IOMMU table and group 1162dff4a39eSGavin Shan * of those VFIO/KVM pass-through devices. We can postpone 1163dff4a39eSGavin Shan * resetting DMA ops until the DMA mask is configured in 1164dff4a39eSGavin Shan * host side. 1165cd15b048SBenjamin Herrenschmidt */ 1166dff4a39eSGavin Shan if (pe->pdev) 1167dff4a39eSGavin Shan set_iommu_table_base(&pe->pdev->dev, tbl); 1168dff4a39eSGavin Shan else 1169dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 1170cd15b048SBenjamin Herrenschmidt } 1171cd15b048SBenjamin Herrenschmidt if (rc) 1172cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1173cd15b048SBenjamin Herrenschmidt else 1174cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1175cd15b048SBenjamin Herrenschmidt } 1176cd15b048SBenjamin Herrenschmidt 1177cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, 1178cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 1179cd15b048SBenjamin Herrenschmidt { 1180cd15b048SBenjamin Herrenschmidt /* TVE #1 is selected by PCI address bit 59 */ 1181cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base = 1ull << 59; 1182cd15b048SBenjamin Herrenschmidt 1183cd15b048SBenjamin Herrenschmidt /* Install set_bypass callback for VFIO */ 1184cd15b048SBenjamin Herrenschmidt pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; 1185cd15b048SBenjamin Herrenschmidt 1186cd15b048SBenjamin Herrenschmidt /* Enable bypass by default */ 1187cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); 1188cd15b048SBenjamin Herrenschmidt } 1189cd15b048SBenjamin Herrenschmidt 1190373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1191373f5657SGavin Shan struct pnv_ioda_pe *pe) 1192373f5657SGavin Shan { 1193373f5657SGavin Shan struct page *tce_mem = NULL; 1194373f5657SGavin Shan void *addr; 1195373f5657SGavin Shan const __be64 *swinvp; 1196373f5657SGavin Shan struct iommu_table *tbl; 1197373f5657SGavin Shan unsigned int tce_table_size, end; 1198373f5657SGavin Shan int64_t rc; 1199373f5657SGavin Shan 1200373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 1201373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 1202373f5657SGavin Shan return; 1203373f5657SGavin Shan 1204373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1205373f5657SGavin Shan pe->tce32_seg = 0; 1206373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 1207373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 1208373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1209373f5657SGavin Shan end); 1210373f5657SGavin Shan 1211373f5657SGavin Shan /* Allocate TCE table */ 1212373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1213373f5657SGavin Shan get_order(tce_table_size)); 1214373f5657SGavin Shan if (!tce_mem) { 1215373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 1216373f5657SGavin Shan goto fail; 1217373f5657SGavin Shan } 1218373f5657SGavin Shan addr = page_address(tce_mem); 1219373f5657SGavin Shan memset(addr, 0, tce_table_size); 1220373f5657SGavin Shan 1221373f5657SGavin Shan /* 1222373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 1223373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 1224373f5657SGavin Shan */ 1225373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1226373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 1227373f5657SGavin Shan tce_table_size, 0x1000); 1228373f5657SGavin Shan if (rc) { 1229373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 1230373f5657SGavin Shan " err %ld\n", rc); 1231373f5657SGavin Shan goto fail; 1232373f5657SGavin Shan } 1233373f5657SGavin Shan 1234373f5657SGavin Shan /* Setup linux iommu table */ 1235373f5657SGavin Shan tbl = &pe->tce32_table; 12368fa5d454SAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, 12378fa5d454SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K); 1238373f5657SGavin Shan 1239373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 1240373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1241373f5657SGavin Shan if (swinvp) { 1242373f5657SGavin Shan /* We need a couple more fields -- an address and a data 1243373f5657SGavin Shan * to or. Since the bus is only printed out on table free 1244373f5657SGavin Shan * errors, and on the first pass the data will be a relative 1245373f5657SGavin Shan * bus number, print that out instead. 1246373f5657SGavin Shan */ 12478e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 12488e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 12498e0a1611SAlexey Kardashevskiy 8); 125065fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 1251373f5657SGavin Shan } 1252373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 1253e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1254373f5657SGavin Shan 125574251fe2SBenjamin Herrenschmidt if (pe->pdev) 1256d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 125774251fe2SBenjamin Herrenschmidt else 1258dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 125974251fe2SBenjamin Herrenschmidt 1260cd15b048SBenjamin Herrenschmidt /* Also create a bypass window */ 1261cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_setup_bypass_pe(phb, pe); 1262373f5657SGavin Shan return; 1263373f5657SGavin Shan fail: 1264373f5657SGavin Shan if (pe->tce32_seg >= 0) 1265373f5657SGavin Shan pe->tce32_seg = -1; 1266373f5657SGavin Shan if (tce_mem) 1267373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 1268373f5657SGavin Shan } 1269373f5657SGavin Shan 1270cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 1271184cd4a3SBenjamin Herrenschmidt { 1272184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 1273184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 1274184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1275184cd4a3SBenjamin Herrenschmidt 1276184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 1277184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 1278184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 1279184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 1280184cd4a3SBenjamin Herrenschmidt */ 1281184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 1282184cd4a3SBenjamin Herrenschmidt residual = 0; 1283184cd4a3SBenjamin Herrenschmidt else 1284184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 1285184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 1286184cd4a3SBenjamin Herrenschmidt 1287184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 1288184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 1289184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 1290184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 1291184cd4a3SBenjamin Herrenschmidt 1292184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 1293184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 1294184cd4a3SBenjamin Herrenschmidt * weight 1295184cd4a3SBenjamin Herrenschmidt */ 1296184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 1297184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 1298184cd4a3SBenjamin Herrenschmidt base = 0; 12997ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 1300184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 1301184cd4a3SBenjamin Herrenschmidt continue; 1302184cd4a3SBenjamin Herrenschmidt if (!remaining) { 1303184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 1304184cd4a3SBenjamin Herrenschmidt continue; 1305184cd4a3SBenjamin Herrenschmidt } 1306184cd4a3SBenjamin Herrenschmidt segs = 1; 1307184cd4a3SBenjamin Herrenschmidt if (residual) { 1308184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 1309184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 1310184cd4a3SBenjamin Herrenschmidt segs = remaining; 1311184cd4a3SBenjamin Herrenschmidt } 1312373f5657SGavin Shan 1313373f5657SGavin Shan /* 1314373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 1315373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 1316373f5657SGavin Shan * the specific PE. 1317373f5657SGavin Shan */ 1318373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 1319184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 1320184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 1321184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 1322373f5657SGavin Shan } else { 1323373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 1324373f5657SGavin Shan segs = 0; 1325373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 1326373f5657SGavin Shan } 1327373f5657SGavin Shan 1328184cd4a3SBenjamin Herrenschmidt remaining -= segs; 1329184cd4a3SBenjamin Herrenschmidt base += segs; 1330184cd4a3SBenjamin Herrenschmidt } 1331184cd4a3SBenjamin Herrenschmidt } 1332184cd4a3SBenjamin Herrenschmidt 1333184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 1334137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 1335137436c9SGavin Shan { 1336137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1337137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 1338137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 1339137436c9SGavin Shan ioda.irq_chip); 1340137436c9SGavin Shan int64_t rc; 1341137436c9SGavin Shan 1342137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1343137436c9SGavin Shan WARN_ON_ONCE(rc); 1344137436c9SGavin Shan 1345137436c9SGavin Shan icp_native_eoi(d); 1346137436c9SGavin Shan } 1347137436c9SGavin Shan 1348fd9a1c26SIan Munsie 1349fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 1350fd9a1c26SIan Munsie { 1351fd9a1c26SIan Munsie struct irq_data *idata; 1352fd9a1c26SIan Munsie struct irq_chip *ichip; 1353fd9a1c26SIan Munsie 1354fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 1355fd9a1c26SIan Munsie return; 1356fd9a1c26SIan Munsie 1357fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 1358fd9a1c26SIan Munsie /* 1359fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 1360fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 1361fd9a1c26SIan Munsie */ 1362fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 1363fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 1364fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 1365fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 1366fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 1367fd9a1c26SIan Munsie } 1368fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 1369fd9a1c26SIan Munsie } 1370fd9a1c26SIan Munsie 137180c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 137280c49c7eSIan Munsie 137380c49c7eSIan Munsie struct device_node *pnv_pci_to_phb_node(struct pci_dev *dev) 137480c49c7eSIan Munsie { 137580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 137680c49c7eSIan Munsie 137780c49c7eSIan Munsie return hose->dn; 137880c49c7eSIan Munsie } 137980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_pci_to_phb_node); 138080c49c7eSIan Munsie 138180c49c7eSIan Munsie int pnv_phb_to_cxl(struct pci_dev *dev) 138280c49c7eSIan Munsie { 138380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 138480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 138580c49c7eSIan Munsie struct pnv_ioda_pe *pe; 138680c49c7eSIan Munsie int rc; 138780c49c7eSIan Munsie 138880c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 138980c49c7eSIan Munsie if (!pe) 139080c49c7eSIan Munsie return -ENODEV; 139180c49c7eSIan Munsie 139280c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 139380c49c7eSIan Munsie 139480c49c7eSIan Munsie rc = opal_pci_set_phb_cxl_mode(phb->opal_id, 1, pe->pe_number); 139580c49c7eSIan Munsie if (rc) 139680c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 139780c49c7eSIan Munsie 139880c49c7eSIan Munsie return rc; 139980c49c7eSIan Munsie } 140080c49c7eSIan Munsie EXPORT_SYMBOL(pnv_phb_to_cxl); 140180c49c7eSIan Munsie 140280c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 140380c49c7eSIan Munsie * Returns the absolute hardware IRQ number 140480c49c7eSIan Munsie */ 140580c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 140680c49c7eSIan Munsie { 140780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 140880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 140980c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 141080c49c7eSIan Munsie 141180c49c7eSIan Munsie if (hwirq < 0) { 141280c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 141380c49c7eSIan Munsie return -ENOSPC; 141480c49c7eSIan Munsie } 141580c49c7eSIan Munsie 141680c49c7eSIan Munsie return phb->msi_base + hwirq; 141780c49c7eSIan Munsie } 141880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 141980c49c7eSIan Munsie 142080c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 142180c49c7eSIan Munsie { 142280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 142380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 142480c49c7eSIan Munsie 142580c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 142680c49c7eSIan Munsie } 142780c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 142880c49c7eSIan Munsie 142980c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 143080c49c7eSIan Munsie struct pci_dev *dev) 143180c49c7eSIan Munsie { 143280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 143380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 143480c49c7eSIan Munsie int i, hwirq; 143580c49c7eSIan Munsie 143680c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 143780c49c7eSIan Munsie if (!irqs->range[i]) 143880c49c7eSIan Munsie continue; 143980c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 144080c49c7eSIan Munsie i, irqs->offset[i], 144180c49c7eSIan Munsie irqs->range[i]); 144280c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 144380c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 144480c49c7eSIan Munsie irqs->range[i]); 144580c49c7eSIan Munsie } 144680c49c7eSIan Munsie } 144780c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 144880c49c7eSIan Munsie 144980c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 145080c49c7eSIan Munsie struct pci_dev *dev, int num) 145180c49c7eSIan Munsie { 145280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 145380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 145480c49c7eSIan Munsie int i, hwirq, try; 145580c49c7eSIan Munsie 145680c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 145780c49c7eSIan Munsie 145880c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 145980c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 146080c49c7eSIan Munsie try = num; 146180c49c7eSIan Munsie while (try) { 146280c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 146380c49c7eSIan Munsie if (hwirq >= 0) 146480c49c7eSIan Munsie break; 146580c49c7eSIan Munsie try /= 2; 146680c49c7eSIan Munsie } 146780c49c7eSIan Munsie if (!try) 146880c49c7eSIan Munsie goto fail; 146980c49c7eSIan Munsie 147080c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 147180c49c7eSIan Munsie irqs->range[i] = try; 147280c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 147380c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 147480c49c7eSIan Munsie num -= try; 147580c49c7eSIan Munsie } 147680c49c7eSIan Munsie if (num) 147780c49c7eSIan Munsie goto fail; 147880c49c7eSIan Munsie 147980c49c7eSIan Munsie return 0; 148080c49c7eSIan Munsie fail: 148180c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 148280c49c7eSIan Munsie return -ENOSPC; 148380c49c7eSIan Munsie } 148480c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 148580c49c7eSIan Munsie 148680c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 148780c49c7eSIan Munsie { 148880c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 148980c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 149080c49c7eSIan Munsie 149180c49c7eSIan Munsie return phb->msi_bmp.irq_count; 149280c49c7eSIan Munsie } 149380c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 149480c49c7eSIan Munsie 149580c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 149680c49c7eSIan Munsie unsigned int virq) 149780c49c7eSIan Munsie { 149880c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 149980c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 150080c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 150180c49c7eSIan Munsie struct pnv_ioda_pe *pe; 150280c49c7eSIan Munsie int rc; 150380c49c7eSIan Munsie 150480c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 150580c49c7eSIan Munsie return -ENODEV; 150680c49c7eSIan Munsie 150780c49c7eSIan Munsie /* Assign XIVE to PE */ 150880c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 150980c49c7eSIan Munsie if (rc) { 151080c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 151180c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 151280c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 151380c49c7eSIan Munsie return -EIO; 151480c49c7eSIan Munsie } 151580c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 151680c49c7eSIan Munsie 151780c49c7eSIan Munsie return 0; 151880c49c7eSIan Munsie } 151980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 152080c49c7eSIan Munsie #endif 152180c49c7eSIan Munsie 1522184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 1523137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 1524137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 1525184cd4a3SBenjamin Herrenschmidt { 1526184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 1527b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1528184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 15293a1a4661SBenjamin Herrenschmidt __be32 data; 1530184cd4a3SBenjamin Herrenschmidt int rc; 1531184cd4a3SBenjamin Herrenschmidt 1532184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 1533184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 1534184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1535184cd4a3SBenjamin Herrenschmidt 1536184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 1537184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 1538184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1539184cd4a3SBenjamin Herrenschmidt 1540b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 1541b72c1f65SBenjamin Herrenschmidt if (pdn && pdn->force_32bit_msi) 1542b72c1f65SBenjamin Herrenschmidt is_64 = 0; 1543b72c1f65SBenjamin Herrenschmidt 1544184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 1545184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 1546184cd4a3SBenjamin Herrenschmidt if (rc) { 1547184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 1548184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 1549184cd4a3SBenjamin Herrenschmidt return -EIO; 1550184cd4a3SBenjamin Herrenschmidt } 1551184cd4a3SBenjamin Herrenschmidt 1552184cd4a3SBenjamin Herrenschmidt if (is_64) { 15533a1a4661SBenjamin Herrenschmidt __be64 addr64; 15543a1a4661SBenjamin Herrenschmidt 1555184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 1556184cd4a3SBenjamin Herrenschmidt &addr64, &data); 1557184cd4a3SBenjamin Herrenschmidt if (rc) { 1558184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 1559184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1560184cd4a3SBenjamin Herrenschmidt return -EIO; 1561184cd4a3SBenjamin Herrenschmidt } 15623a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 15633a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 1564184cd4a3SBenjamin Herrenschmidt } else { 15653a1a4661SBenjamin Herrenschmidt __be32 addr32; 15663a1a4661SBenjamin Herrenschmidt 1567184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 1568184cd4a3SBenjamin Herrenschmidt &addr32, &data); 1569184cd4a3SBenjamin Herrenschmidt if (rc) { 1570184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 1571184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1572184cd4a3SBenjamin Herrenschmidt return -EIO; 1573184cd4a3SBenjamin Herrenschmidt } 1574184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 15753a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 1576184cd4a3SBenjamin Herrenschmidt } 15773a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 1578184cd4a3SBenjamin Herrenschmidt 1579fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 1580137436c9SGavin Shan 1581184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 1582184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 1583184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 1584184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 1585184cd4a3SBenjamin Herrenschmidt 1586184cd4a3SBenjamin Herrenschmidt return 0; 1587184cd4a3SBenjamin Herrenschmidt } 1588184cd4a3SBenjamin Herrenschmidt 1589184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 1590184cd4a3SBenjamin Herrenschmidt { 1591fb1b55d6SGavin Shan unsigned int count; 1592184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 1593184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 1594184cd4a3SBenjamin Herrenschmidt if (!prop) { 1595184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 1596184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 1597184cd4a3SBenjamin Herrenschmidt } 1598184cd4a3SBenjamin Herrenschmidt if (!prop) 1599184cd4a3SBenjamin Herrenschmidt return; 1600184cd4a3SBenjamin Herrenschmidt 1601184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 1602fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 1603fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 1604184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 1605184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 1606184cd4a3SBenjamin Herrenschmidt return; 1607184cd4a3SBenjamin Herrenschmidt } 1608fb1b55d6SGavin Shan 1609184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 1610184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 1611184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 1612fb1b55d6SGavin Shan count, phb->msi_base); 1613184cd4a3SBenjamin Herrenschmidt } 1614184cd4a3SBenjamin Herrenschmidt #else 1615184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 1616184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 1617184cd4a3SBenjamin Herrenschmidt 161811685becSGavin Shan /* 161911685becSGavin Shan * This function is supposed to be called on basis of PE from top 162011685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 162111685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 162211685becSGavin Shan */ 1623cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 162411685becSGavin Shan struct pnv_ioda_pe *pe) 162511685becSGavin Shan { 162611685becSGavin Shan struct pnv_phb *phb = hose->private_data; 162711685becSGavin Shan struct pci_bus_region region; 162811685becSGavin Shan struct resource *res; 162911685becSGavin Shan int i, index; 163011685becSGavin Shan int rc; 163111685becSGavin Shan 163211685becSGavin Shan /* 163311685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 163411685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 163511685becSGavin Shan * be figured out later. 163611685becSGavin Shan */ 163711685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 163811685becSGavin Shan 163911685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 164011685becSGavin Shan if (!res || !res->flags || 164111685becSGavin Shan res->start > res->end) 164211685becSGavin Shan continue; 164311685becSGavin Shan 164411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 164511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 164611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 164711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 164811685becSGavin Shan 164911685becSGavin Shan while (index < phb->ioda.total_pe && 165011685becSGavin Shan region.start <= region.end) { 165111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 165211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 165311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 165411685becSGavin Shan if (rc != OPAL_SUCCESS) { 165511685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 165611685becSGavin Shan "segment #%d to PE#%d\n", 165711685becSGavin Shan __func__, rc, index, pe->pe_number); 165811685becSGavin Shan break; 165911685becSGavin Shan } 166011685becSGavin Shan 166111685becSGavin Shan region.start += phb->ioda.io_segsize; 166211685becSGavin Shan index++; 166311685becSGavin Shan } 166411685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 166511685becSGavin Shan region.start = res->start - 16663fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 166711685becSGavin Shan phb->ioda.m32_pci_base; 166811685becSGavin Shan region.end = res->end - 16693fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 167011685becSGavin Shan phb->ioda.m32_pci_base; 167111685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 167211685becSGavin Shan 167311685becSGavin Shan while (index < phb->ioda.total_pe && 167411685becSGavin Shan region.start <= region.end) { 167511685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 167611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 167711685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 167811685becSGavin Shan if (rc != OPAL_SUCCESS) { 167911685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 168011685becSGavin Shan "segment#%d to PE#%d", 168111685becSGavin Shan __func__, rc, index, pe->pe_number); 168211685becSGavin Shan break; 168311685becSGavin Shan } 168411685becSGavin Shan 168511685becSGavin Shan region.start += phb->ioda.m32_segsize; 168611685becSGavin Shan index++; 168711685becSGavin Shan } 168811685becSGavin Shan } 168911685becSGavin Shan } 169011685becSGavin Shan } 169111685becSGavin Shan 1692cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 169311685becSGavin Shan { 169411685becSGavin Shan struct pci_controller *tmp, *hose; 169511685becSGavin Shan struct pnv_phb *phb; 169611685becSGavin Shan struct pnv_ioda_pe *pe; 169711685becSGavin Shan 169811685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 169911685becSGavin Shan phb = hose->private_data; 170011685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 170111685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 170211685becSGavin Shan } 170311685becSGavin Shan } 170411685becSGavin Shan } 170511685becSGavin Shan 1706cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 170713395c48SGavin Shan { 170813395c48SGavin Shan struct pci_controller *hose, *tmp; 1709db1266c8SGavin Shan struct pnv_phb *phb; 171013395c48SGavin Shan 171113395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 171213395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 1713db1266c8SGavin Shan 1714db1266c8SGavin Shan /* Mark the PHB initialization done */ 1715db1266c8SGavin Shan phb = hose->private_data; 1716db1266c8SGavin Shan phb->initialized = 1; 171713395c48SGavin Shan } 171813395c48SGavin Shan } 171913395c48SGavin Shan 172037c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 172137c367f2SGavin Shan { 172237c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 172337c367f2SGavin Shan struct pci_controller *hose, *tmp; 172437c367f2SGavin Shan struct pnv_phb *phb; 172537c367f2SGavin Shan char name[16]; 172637c367f2SGavin Shan 172737c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 172837c367f2SGavin Shan phb = hose->private_data; 172937c367f2SGavin Shan 173037c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 173137c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 173237c367f2SGavin Shan if (!phb->dbgfs) 173337c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 173437c367f2SGavin Shan __func__, hose->global_number); 173537c367f2SGavin Shan } 173637c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 173737c367f2SGavin Shan } 173837c367f2SGavin Shan 1739cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 1740fb446ad0SGavin Shan { 1741fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 174211685becSGavin Shan pnv_pci_ioda_setup_seg(); 174313395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 1744e9cc17d4SGavin Shan 174537c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 174637c367f2SGavin Shan 1747e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1748e9cc17d4SGavin Shan eeh_init(); 1749dadcd6d6SMike Qiu eeh_addr_cache_build(); 1750e9cc17d4SGavin Shan #endif 1751fb446ad0SGavin Shan } 1752fb446ad0SGavin Shan 1753271fd03aSGavin Shan /* 1754271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 1755271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 1756271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 1757271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 1758271fd03aSGavin Shan * 1MiB for memory) will be returned. 1759271fd03aSGavin Shan * 1760271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 1761271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 1762271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 1763271fd03aSGavin Shan * resources. 1764271fd03aSGavin Shan */ 1765271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1766271fd03aSGavin Shan unsigned long type) 1767271fd03aSGavin Shan { 1768271fd03aSGavin Shan struct pci_dev *bridge; 1769271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1770271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1771271fd03aSGavin Shan int num_pci_bridges = 0; 1772271fd03aSGavin Shan 1773271fd03aSGavin Shan bridge = bus->self; 1774271fd03aSGavin Shan while (bridge) { 1775271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1776271fd03aSGavin Shan num_pci_bridges++; 1777271fd03aSGavin Shan if (num_pci_bridges >= 2) 1778271fd03aSGavin Shan return 1; 1779271fd03aSGavin Shan } 1780271fd03aSGavin Shan 1781271fd03aSGavin Shan bridge = bridge->bus->self; 1782271fd03aSGavin Shan } 1783271fd03aSGavin Shan 1784262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 1785262af557SGuo Chao if (phb->ioda.m64_segsize && 1786262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 1787262af557SGuo Chao return phb->ioda.m64_segsize; 1788271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1789271fd03aSGavin Shan return phb->ioda.m32_segsize; 1790271fd03aSGavin Shan 1791271fd03aSGavin Shan return phb->ioda.io_segsize; 1792271fd03aSGavin Shan } 1793271fd03aSGavin Shan 1794184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1795184cd4a3SBenjamin Herrenschmidt * assign a PE 1796184cd4a3SBenjamin Herrenschmidt */ 1797cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1798184cd4a3SBenjamin Herrenschmidt { 1799db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1800db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1801db1266c8SGavin Shan struct pci_dn *pdn; 1802184cd4a3SBenjamin Herrenschmidt 1803db1266c8SGavin Shan /* The function is probably called while the PEs have 1804db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1805db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1806db1266c8SGavin Shan * PEs isn't ready. 1807db1266c8SGavin Shan */ 1808db1266c8SGavin Shan if (!phb->initialized) 1809db1266c8SGavin Shan return 0; 1810db1266c8SGavin Shan 1811b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1812184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1813184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1814db1266c8SGavin Shan 1815184cd4a3SBenjamin Herrenschmidt return 0; 1816184cd4a3SBenjamin Herrenschmidt } 1817184cd4a3SBenjamin Herrenschmidt 1818184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1819184cd4a3SBenjamin Herrenschmidt u32 devfn) 1820184cd4a3SBenjamin Herrenschmidt { 1821184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1822184cd4a3SBenjamin Herrenschmidt } 1823184cd4a3SBenjamin Herrenschmidt 182473ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 182573ed148aSBenjamin Herrenschmidt { 1826d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 182773ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 182873ed148aSBenjamin Herrenschmidt } 182973ed148aSBenjamin Herrenschmidt 1830e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 1831e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 1832184cd4a3SBenjamin Herrenschmidt { 1833184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1834184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 18358184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 1836c681b93cSAlistair Popple const __be64 *prop64; 18373a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 1838f1b7cc3eSGavin Shan int len; 1839184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1840184cd4a3SBenjamin Herrenschmidt void *aux; 1841184cd4a3SBenjamin Herrenschmidt long rc; 1842184cd4a3SBenjamin Herrenschmidt 1843aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1844184cd4a3SBenjamin Herrenschmidt 1845184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1846184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1847184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1848184cd4a3SBenjamin Herrenschmidt return; 1849184cd4a3SBenjamin Herrenschmidt } 1850184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1851184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1852184cd4a3SBenjamin Herrenschmidt 1853184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 185458d714ecSGavin Shan if (!phb) { 185558d714ecSGavin Shan pr_err(" Out of memory !\n"); 185658d714ecSGavin Shan return; 185758d714ecSGavin Shan } 185858d714ecSGavin Shan 185958d714ecSGavin Shan /* Allocate PCI controller */ 1860184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 1861184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 186258d714ecSGavin Shan if (!phb->hose) { 186358d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 1864184cd4a3SBenjamin Herrenschmidt np->full_name); 186558d714ecSGavin Shan free_bootmem((unsigned long)phb, sizeof(struct pnv_phb)); 1866184cd4a3SBenjamin Herrenschmidt return; 1867184cd4a3SBenjamin Herrenschmidt } 1868184cd4a3SBenjamin Herrenschmidt 1869184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1870f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 1871f1b7cc3eSGavin Shan if (prop32 && len == 8) { 18723a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 18733a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 1874f1b7cc3eSGavin Shan } else { 1875f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 1876184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1877184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1878f1b7cc3eSGavin Shan } 1879184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1880e9cc17d4SGavin Shan phb->hub_id = hub_id; 1881184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1882aa0c033fSGavin Shan phb->type = ioda_type; 1883184cd4a3SBenjamin Herrenschmidt 1884cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1885cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1886cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1887f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1888aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1889cee72d5bSBenjamin Herrenschmidt else 1890cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1891cee72d5bSBenjamin Herrenschmidt 1892aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 18932f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 1894184cd4a3SBenjamin Herrenschmidt 1895aa0c033fSGavin Shan /* Get registers */ 1896184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1897184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1898184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1899184cd4a3SBenjamin Herrenschmidt 1900184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1901aa0c033fSGavin Shan phb->ioda.total_pe = 1; 190236954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 190336954dc7SGavin Shan if (prop32) 19043a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 190536954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 190636954dc7SGavin Shan if (prop32) 190736954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 1908262af557SGuo Chao 1909262af557SGuo Chao /* Parse 64-bit MMIO range */ 1910262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 1911262af557SGuo Chao 1912184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1913aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 1914184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 1915184cd4a3SBenjamin Herrenschmidt 1916184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 19173fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 1918184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 1919184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1920184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1921184cd4a3SBenjamin Herrenschmidt 1922c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 1923184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1924184cd4a3SBenjamin Herrenschmidt m32map_off = size; 1925e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 1926c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 1927c35d2a8cSGavin Shan iomap_off = size; 1928e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 1929c35d2a8cSGavin Shan } 1930184cd4a3SBenjamin Herrenschmidt pemap_off = size; 1931184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1932184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 1933184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 1934184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 1935184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 1936c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 1937184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 1938184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 193936954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 1940184cd4a3SBenjamin Herrenschmidt 19417ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1942184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 1943184cd4a3SBenjamin Herrenschmidt 1944184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 1945184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1946184cd4a3SBenjamin Herrenschmidt 1947aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 1948184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1949184cd4a3SBenjamin Herrenschmidt window_type, 1950184cd4a3SBenjamin Herrenschmidt window_num, 1951184cd4a3SBenjamin Herrenschmidt starting_real_address, 1952184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1953184cd4a3SBenjamin Herrenschmidt segment_size); 1954184cd4a3SBenjamin Herrenschmidt #endif 1955184cd4a3SBenjamin Herrenschmidt 1956262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 1957262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 1958262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 1959262af557SGuo Chao if (phb->ioda.m64_size) 1960262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 1961262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 1962262af557SGuo Chao if (phb->ioda.io_size) 1963262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 1964184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1965184cd4a3SBenjamin Herrenschmidt 1966262af557SGuo Chao 1967184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 196849dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 196949dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 197049dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 1971e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1972e9cc17d4SGavin Shan phb->eeh_ops = &ioda_eeh_ops; 1973e9cc17d4SGavin Shan #endif 1974184cd4a3SBenjamin Herrenschmidt 1975184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1976184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1977184cd4a3SBenjamin Herrenschmidt 1978184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1979184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1980cd15b048SBenjamin Herrenschmidt phb->dma_set_mask = pnv_pci_ioda_dma_set_mask; 1981fe7e85c6SGavin Shan phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; 1982184cd4a3SBenjamin Herrenschmidt 198373ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 198473ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 198573ed148aSBenjamin Herrenschmidt 1986184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1987184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1988184cd4a3SBenjamin Herrenschmidt 1989c40a4210SGavin Shan /* 1990c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1991c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1992c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1993c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1994c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1995184cd4a3SBenjamin Herrenschmidt */ 1996fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1997184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1998271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1999d92a208dSGavin Shan ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus; 2000c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 2001184cd4a3SBenjamin Herrenschmidt 2002184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 2003d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 2004184cd4a3SBenjamin Herrenschmidt if (rc) 2005f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 2006361f2a2aSGavin Shan 2007361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 2008361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 2009361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 2010361f2a2aSGavin Shan * transactions from previous kerenl. 2011361f2a2aSGavin Shan */ 2012361f2a2aSGavin Shan if (is_kdump_kernel()) { 2013361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 2014361f2a2aSGavin Shan ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 2015361f2a2aSGavin Shan ioda_eeh_phb_reset(hose, OPAL_DEASSERT_RESET); 2016361f2a2aSGavin Shan } 2017262af557SGuo Chao 20189e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 20199e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 2020262af557SGuo Chao hose->mem_resources[1].flags = 0; 2021184cd4a3SBenjamin Herrenschmidt } 2022184cd4a3SBenjamin Herrenschmidt 202367975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 2024aa0c033fSGavin Shan { 2025e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 2026aa0c033fSGavin Shan } 2027aa0c033fSGavin Shan 2028184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 2029184cd4a3SBenjamin Herrenschmidt { 2030184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 2031c681b93cSAlistair Popple const __be64 *prop64; 2032184cd4a3SBenjamin Herrenschmidt u64 hub_id; 2033184cd4a3SBenjamin Herrenschmidt 2034184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 2035184cd4a3SBenjamin Herrenschmidt 2036184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 2037184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2038184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 2039184cd4a3SBenjamin Herrenschmidt return; 2040184cd4a3SBenjamin Herrenschmidt } 2041184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 2042184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 2043184cd4a3SBenjamin Herrenschmidt 2044184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 2045184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 2046184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 2047184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 2048e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 2049184cd4a3SBenjamin Herrenschmidt } 2050184cd4a3SBenjamin Herrenschmidt } 2051