1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 25ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 26e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 274793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 28184cd4a3SBenjamin Herrenschmidt 29184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 34fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 39137436c9SGavin Shan #include <asm/xics.h> 407644d581SMichael Ellerman #include <asm/debugfs.h> 41262af557SGuo Chao #include <asm/firmware.h> 4280c49c7eSIan Munsie #include <asm/pnv-pci.h> 43aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4480c49c7eSIan Munsie 45ec249dd8SMichael Neuling #include <misc/cxl-base.h> 46184cd4a3SBenjamin Herrenschmidt 47184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 48184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4944bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 50184cd4a3SBenjamin Herrenschmidt 5199451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5299451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54781a868fSWei Yang 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 57bbb845c4SAlexey Kardashevskiy 587f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 597f2c39e9SFrederic Barrat "NPU_OCAPI" }; 60aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 61aca6913fSAlexey Kardashevskiy 627d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 636d31c2faSJoe Perches const char *fmt, ...) 646d31c2faSJoe Perches { 656d31c2faSJoe Perches struct va_format vaf; 666d31c2faSJoe Perches va_list args; 676d31c2faSJoe Perches char pfix[32]; 68184cd4a3SBenjamin Herrenschmidt 696d31c2faSJoe Perches va_start(args, fmt); 706d31c2faSJoe Perches 716d31c2faSJoe Perches vaf.fmt = fmt; 726d31c2faSJoe Perches vaf.va = &args; 736d31c2faSJoe Perches 74781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 756d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 76781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 776d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 786d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 79781a868fSWei Yang #ifdef CONFIG_PCI_IOV 80781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 81781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 82781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 83781a868fSWei Yang (pe->rid & 0xff00) >> 8, 84781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 85781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 866d31c2faSJoe Perches 871f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 886d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 896d31c2faSJoe Perches 906d31c2faSJoe Perches va_end(args); 916d31c2faSJoe Perches } 926d31c2faSJoe Perches 934e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 9445baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 954e287840SThadeu Lima de Souza Cascardo 964e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 974e287840SThadeu Lima de Souza Cascardo { 984e287840SThadeu Lima de Souza Cascardo if (!str) 994e287840SThadeu Lima de Souza Cascardo return -EINVAL; 1004e287840SThadeu Lima de Souza Cascardo 1014e287840SThadeu Lima de Souza Cascardo while (*str) { 1024e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1034e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1044e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1054e287840SThadeu Lima de Souza Cascardo break; 1064e287840SThadeu Lima de Souza Cascardo } 1074e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1084e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1094e287840SThadeu Lima de Souza Cascardo str++; 1104e287840SThadeu Lima de Souza Cascardo } 1114e287840SThadeu Lima de Souza Cascardo 1124e287840SThadeu Lima de Souza Cascardo return 0; 1134e287840SThadeu Lima de Souza Cascardo } 1144e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1154e287840SThadeu Lima de Souza Cascardo 11645baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11745baee14SGuilherme G. Piccoli { 11845baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11945baee14SGuilherme G. Piccoli return 0; 12045baee14SGuilherme G. Piccoli } 12145baee14SGuilherme G. Piccoli 12245baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 12345baee14SGuilherme G. Piccoli 1245958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 125262af557SGuo Chao { 1265958d19aSBenjamin Herrenschmidt /* 1275958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1285958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1295958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1305958d19aSBenjamin Herrenschmidt * 1315958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1325958d19aSBenjamin Herrenschmidt */ 1335958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1345958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 135262af557SGuo Chao } 136262af557SGuo Chao 137b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 138b79331a5SRussell Currey { 139b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 140b79331a5SRussell Currey 141b79331a5SRussell Currey return (resource_flags & flags) == flags; 142b79331a5SRussell Currey } 143b79331a5SRussell Currey 1441e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1451e916772SGavin Shan { 146313483ddSGavin Shan s64 rc; 147313483ddSGavin Shan 1481e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1491e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1501e916772SGavin Shan 151313483ddSGavin Shan /* 152313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 153313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 154313483ddSGavin Shan * PE is already in unfrozen state. 155313483ddSGavin Shan */ 156313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 157313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 158d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1591f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 160313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 161313483ddSGavin Shan 1621e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1631e916772SGavin Shan } 1641e916772SGavin Shan 1654b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1664b82ab18SGavin Shan { 16792b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1681f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1694b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1704b82ab18SGavin Shan return; 1714b82ab18SGavin Shan } 1724b82ab18SGavin Shan 173e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1741f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1754b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1764b82ab18SGavin Shan 1771e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1784b82ab18SGavin Shan } 1794b82ab18SGavin Shan 1801e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 181184cd4a3SBenjamin Herrenschmidt { 18260964816SAndrzej Hajda long pe; 183184cd4a3SBenjamin Herrenschmidt 1849fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1859fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1861e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 187184cd4a3SBenjamin Herrenschmidt } 188184cd4a3SBenjamin Herrenschmidt 1899fcd6f4aSGavin Shan return NULL; 1909fcd6f4aSGavin Shan } 1919fcd6f4aSGavin Shan 1921e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 193184cd4a3SBenjamin Herrenschmidt { 1941e916772SGavin Shan struct pnv_phb *phb = pe->phb; 195caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 196184cd4a3SBenjamin Herrenschmidt 1971e916772SGavin Shan WARN_ON(pe->pdev); 1981e916772SGavin Shan 1991e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 200caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 201184cd4a3SBenjamin Herrenschmidt } 202184cd4a3SBenjamin Herrenschmidt 203262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 204262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 205262af557SGuo Chao { 206262af557SGuo Chao const char *desc; 207262af557SGuo Chao struct resource *r; 208262af557SGuo Chao s64 rc; 209262af557SGuo Chao 210262af557SGuo Chao /* Configure the default M64 BAR */ 211262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 212262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 213262af557SGuo Chao phb->ioda.m64_bar_idx, 214262af557SGuo Chao phb->ioda.m64_base, 215262af557SGuo Chao 0, /* unused */ 216262af557SGuo Chao phb->ioda.m64_size); 217262af557SGuo Chao if (rc != OPAL_SUCCESS) { 218262af557SGuo Chao desc = "configuring"; 219262af557SGuo Chao goto fail; 220262af557SGuo Chao } 221262af557SGuo Chao 222262af557SGuo Chao /* Enable the default M64 BAR */ 223262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 224262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 225262af557SGuo Chao phb->ioda.m64_bar_idx, 226262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 227262af557SGuo Chao if (rc != OPAL_SUCCESS) { 228262af557SGuo Chao desc = "enabling"; 229262af557SGuo Chao goto fail; 230262af557SGuo Chao } 231262af557SGuo Chao 232262af557SGuo Chao /* 23363803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23463803c39SGavin Shan * are first or last two PEs. 235262af557SGuo Chao */ 236262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23792b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23863803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23992b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 24063803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 241262af557SGuo Chao else 2421f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 24392b8f137SGavin Shan phb->ioda.reserved_pe_idx); 244262af557SGuo Chao 245262af557SGuo Chao return 0; 246262af557SGuo Chao 247262af557SGuo Chao fail: 248262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 249262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 250262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 251262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 252262af557SGuo Chao phb->ioda.m64_bar_idx, 253262af557SGuo Chao OPAL_DISABLE_M64); 254262af557SGuo Chao return -EIO; 255262af557SGuo Chao } 256262af557SGuo Chao 257c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25896a2f92bSGavin Shan unsigned long *pe_bitmap) 259262af557SGuo Chao { 26096a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 26196a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 262262af557SGuo Chao struct resource *r; 26396a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26496a2f92bSGavin Shan int segno, i; 265262af557SGuo Chao 26696a2f92bSGavin Shan base = phb->ioda.m64_base; 26796a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26896a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26996a2f92bSGavin Shan r = &pdev->resource[i]; 2705958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 271262af557SGuo Chao continue; 272262af557SGuo Chao 27396a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 27496a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 27596a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27696a2f92bSGavin Shan if (pe_bitmap) 27796a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27896a2f92bSGavin Shan else 27996a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 280262af557SGuo Chao } 281262af557SGuo Chao } 282262af557SGuo Chao } 283262af557SGuo Chao 28499451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28599451551SGavin Shan { 28699451551SGavin Shan struct resource *r; 28799451551SGavin Shan int index; 28899451551SGavin Shan 28999451551SGavin Shan /* 29099451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 29199451551SGavin Shan * there are as many M64 segments as the maximum number of 29299451551SGavin Shan * PEs, which is 128. 29399451551SGavin Shan */ 29499451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29599451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29699451551SGavin Shan int64_t rc; 29799451551SGavin Shan 29899451551SGavin Shan base = phb->ioda.m64_base + 29999451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 30099451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 30199451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 30299451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 30399451551SGavin Shan if (rc != OPAL_SUCCESS) { 3041f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30599451551SGavin Shan rc, phb->hose->global_number, index); 30699451551SGavin Shan goto fail; 30799451551SGavin Shan } 30899451551SGavin Shan 30999451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 31099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 31199451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 31299451551SGavin Shan if (rc != OPAL_SUCCESS) { 3131f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31499451551SGavin Shan rc, phb->hose->global_number, index); 31599451551SGavin Shan goto fail; 31699451551SGavin Shan } 31799451551SGavin Shan } 31899451551SGavin Shan 31999451551SGavin Shan /* 32063803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 32163803c39SGavin Shan * are first or last two PEs. 32299451551SGavin Shan */ 32399451551SGavin Shan r = &phb->hose->mem_resources[1]; 32499451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 32563803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32699451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32763803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32899451551SGavin Shan else 3291f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 33099451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 33199451551SGavin Shan 33299451551SGavin Shan return 0; 33399451551SGavin Shan 33499451551SGavin Shan fail: 33599451551SGavin Shan for ( ; index >= 0; index--) 33699451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33799451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33899451551SGavin Shan 33999451551SGavin Shan return -EIO; 34099451551SGavin Shan } 34199451551SGavin Shan 342c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 34396a2f92bSGavin Shan unsigned long *pe_bitmap, 34496a2f92bSGavin Shan bool all) 345262af557SGuo Chao { 346262af557SGuo Chao struct pci_dev *pdev; 34796a2f92bSGavin Shan 34896a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 349c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 35096a2f92bSGavin Shan 35196a2f92bSGavin Shan if (all && pdev->subordinate) 352c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 35396a2f92bSGavin Shan pe_bitmap, all); 35496a2f92bSGavin Shan } 35596a2f92bSGavin Shan } 35696a2f92bSGavin Shan 3571e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 358262af557SGuo Chao { 35926ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 36026ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 361262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 362262af557SGuo Chao unsigned long size, *pe_alloc; 36326ba248dSGavin Shan int i; 364262af557SGuo Chao 365262af557SGuo Chao /* Root bus shouldn't use M64 */ 366262af557SGuo Chao if (pci_is_root_bus(bus)) 3671e916772SGavin Shan return NULL; 368262af557SGuo Chao 369262af557SGuo Chao /* Allocate bitmap */ 37092b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 371262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 372262af557SGuo Chao if (!pe_alloc) { 373262af557SGuo Chao pr_warn("%s: Out of memory !\n", 374262af557SGuo Chao __func__); 3751e916772SGavin Shan return NULL; 376262af557SGuo Chao } 377262af557SGuo Chao 37826ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 379c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 380262af557SGuo Chao 381262af557SGuo Chao /* 382262af557SGuo Chao * the current bus might not own M64 window and that's all 383262af557SGuo Chao * contributed by its child buses. For the case, we needn't 384262af557SGuo Chao * pick M64 dependent PE#. 385262af557SGuo Chao */ 38692b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 387262af557SGuo Chao kfree(pe_alloc); 3881e916772SGavin Shan return NULL; 389262af557SGuo Chao } 390262af557SGuo Chao 391262af557SGuo Chao /* 392262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 393262af557SGuo Chao * PE's list to form compound PE. 394262af557SGuo Chao */ 395262af557SGuo Chao master_pe = NULL; 396262af557SGuo Chao i = -1; 39792b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39892b8f137SGavin Shan phb->ioda.total_pe_num) { 399262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 400262af557SGuo Chao 40193289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 402262af557SGuo Chao if (!master_pe) { 403262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 404262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 405262af557SGuo Chao master_pe = pe; 406262af557SGuo Chao } else { 407262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 408262af557SGuo Chao pe->master = master_pe; 409262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 410262af557SGuo Chao } 41199451551SGavin Shan 41299451551SGavin Shan /* 41399451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 41499451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 41599451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41699451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41799451551SGavin Shan * segment and PE# on P7IOC. 41899451551SGavin Shan */ 41999451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 42099451551SGavin Shan int64_t rc; 42199451551SGavin Shan 42299451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 42399451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 42499451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 42599451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42699451551SGavin Shan if (rc != OPAL_SUCCESS) 4271f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42899451551SGavin Shan __func__, rc, phb->hose->global_number, 42999451551SGavin Shan pe->pe_number); 43099451551SGavin Shan } 431262af557SGuo Chao } 432262af557SGuo Chao 433262af557SGuo Chao kfree(pe_alloc); 4341e916772SGavin Shan return master_pe; 435262af557SGuo Chao } 436262af557SGuo Chao 437262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 438262af557SGuo Chao { 439262af557SGuo Chao struct pci_controller *hose = phb->hose; 440262af557SGuo Chao struct device_node *dn = hose->dn; 441262af557SGuo Chao struct resource *res; 442a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4430e7736c6SGavin Shan const __be32 *r; 444262af557SGuo Chao u64 pci_addr; 445262af557SGuo Chao 44699451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4471665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4481665c4a8SGavin Shan return; 4491665c4a8SGavin Shan } 4501665c4a8SGavin Shan 451e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 452262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 453262af557SGuo Chao return; 454262af557SGuo Chao } 455262af557SGuo Chao 456262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 457262af557SGuo Chao if (!r) { 458b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 459b7c670d6SRob Herring dn); 460262af557SGuo Chao return; 461262af557SGuo Chao } 462262af557SGuo Chao 463a1339fafSBenjamin Herrenschmidt /* 464a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 465a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 466a1339fafSBenjamin Herrenschmidt */ 467a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 468a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 469a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 470a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 471a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 472a1339fafSBenjamin Herrenschmidt } 473a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 474a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 475a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 476a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 477a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 478a1339fafSBenjamin Herrenschmidt } 479a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 480a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 481a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 482a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 483a1339fafSBenjamin Herrenschmidt return; 484a1339fafSBenjamin Herrenschmidt } 485a1339fafSBenjamin Herrenschmidt 486a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 487262af557SGuo Chao res = &hose->mem_resources[1]; 488e80c4e7cSGavin Shan res->name = dn->full_name; 489262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 490262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 491262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 492262af557SGuo Chao pci_addr = of_read_number(r, 2); 493262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 494262af557SGuo Chao 495262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49692b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 497262af557SGuo Chao phb->ioda.m64_base = pci_addr; 498262af557SGuo Chao 499a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 500a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 501a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 502a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 503a1339fafSBenjamin Herrenschmidt 504a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 505a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 506e9863e68SWei Yang 507262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 508a1339fafSBenjamin Herrenschmidt m64_range[1]--; 509a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 510a1339fafSBenjamin Herrenschmidt 511a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 512a1339fafSBenjamin Herrenschmidt 513a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 514a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 515a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 516a1339fafSBenjamin Herrenschmidt 517a1339fafSBenjamin Herrenschmidt /* 518a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 519a1339fafSBenjamin Herrenschmidt * the IODA2 code. 520a1339fafSBenjamin Herrenschmidt */ 52199451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 52299451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 52399451551SGavin Shan else 524262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 525c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 526c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 527262af557SGuo Chao } 528262af557SGuo Chao 52949dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 53049dec922SGavin Shan { 53149dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 53249dec922SGavin Shan struct pnv_ioda_pe *slave; 53349dec922SGavin Shan s64 rc; 53449dec922SGavin Shan 53549dec922SGavin Shan /* Fetch master PE */ 53649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53749dec922SGavin Shan pe = pe->master; 538ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 539ec8e4e9dSGavin Shan return; 540ec8e4e9dSGavin Shan 54149dec922SGavin Shan pe_no = pe->pe_number; 54249dec922SGavin Shan } 54349dec922SGavin Shan 54449dec922SGavin Shan /* Freeze master PE */ 54549dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54649dec922SGavin Shan pe_no, 54749dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54949dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55049dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 55149dec922SGavin Shan return; 55249dec922SGavin Shan } 55349dec922SGavin Shan 55449dec922SGavin Shan /* Freeze slave PEs */ 55549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55649dec922SGavin Shan return; 55749dec922SGavin Shan 55849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55949dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 56049dec922SGavin Shan slave->pe_number, 56149dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 56249dec922SGavin Shan if (rc != OPAL_SUCCESS) 56349dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 56449dec922SGavin Shan __func__, rc, phb->hose->global_number, 56549dec922SGavin Shan slave->pe_number); 56649dec922SGavin Shan } 56749dec922SGavin Shan } 56849dec922SGavin Shan 569e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 57049dec922SGavin Shan { 57149dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 57249dec922SGavin Shan s64 rc; 57349dec922SGavin Shan 57449dec922SGavin Shan /* Find master PE */ 57549dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57749dec922SGavin Shan pe = pe->master; 57849dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57949dec922SGavin Shan pe_no = pe->pe_number; 58049dec922SGavin Shan } 58149dec922SGavin Shan 58249dec922SGavin Shan /* Clear frozen state for master PE */ 58349dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 58449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58549dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58649dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58749dec922SGavin Shan return -EIO; 58849dec922SGavin Shan } 58949dec922SGavin Shan 59049dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 59149dec922SGavin Shan return 0; 59249dec922SGavin Shan 59349dec922SGavin Shan /* Clear frozen state for slave PEs */ 59449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59549dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59649dec922SGavin Shan slave->pe_number, 59749dec922SGavin Shan opt); 59849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59949dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 60049dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 60149dec922SGavin Shan slave->pe_number); 60249dec922SGavin Shan return -EIO; 60349dec922SGavin Shan } 60449dec922SGavin Shan } 60549dec922SGavin Shan 60649dec922SGavin Shan return 0; 60749dec922SGavin Shan } 60849dec922SGavin Shan 60949dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 61049dec922SGavin Shan { 61149dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 61249dec922SGavin Shan u8 fstate, state; 61349dec922SGavin Shan __be16 pcierr; 61449dec922SGavin Shan s64 rc; 61549dec922SGavin Shan 61649dec922SGavin Shan /* Sanity check on PE number */ 61792b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61849dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61949dec922SGavin Shan 62049dec922SGavin Shan /* 62149dec922SGavin Shan * Fetch the master PE and the PE instance might be 62249dec922SGavin Shan * not initialized yet. 62349dec922SGavin Shan */ 62449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62649dec922SGavin Shan pe = pe->master; 62749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62849dec922SGavin Shan pe_no = pe->pe_number; 62949dec922SGavin Shan } 63049dec922SGavin Shan 63149dec922SGavin Shan /* Check the master PE */ 63249dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 63349dec922SGavin Shan &state, &pcierr, NULL); 63449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63549dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63649dec922SGavin Shan "PHB#%x-PE#%x state\n", 63749dec922SGavin Shan __func__, rc, 63849dec922SGavin Shan phb->hose->global_number, pe_no); 63949dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 64049dec922SGavin Shan } 64149dec922SGavin Shan 64249dec922SGavin Shan /* Check the slave PE */ 64349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 64449dec922SGavin Shan return state; 64549dec922SGavin Shan 64649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64749dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64849dec922SGavin Shan slave->pe_number, 64949dec922SGavin Shan &fstate, 65049dec922SGavin Shan &pcierr, 65149dec922SGavin Shan NULL); 65249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 65349dec922SGavin Shan pr_warn("%s: Failure %lld getting " 65449dec922SGavin Shan "PHB#%x-PE#%x state\n", 65549dec922SGavin Shan __func__, rc, 65649dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65749dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65849dec922SGavin Shan } 65949dec922SGavin Shan 66049dec922SGavin Shan /* 66149dec922SGavin Shan * Override the result based on the ascending 66249dec922SGavin Shan * priority. 66349dec922SGavin Shan */ 66449dec922SGavin Shan if (fstate > state) 66549dec922SGavin Shan state = fstate; 66649dec922SGavin Shan } 66749dec922SGavin Shan 66849dec922SGavin Shan return state; 66949dec922SGavin Shan } 67049dec922SGavin Shan 671184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 672184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 673184cd4a3SBenjamin Herrenschmidt */ 674184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 675f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 676184cd4a3SBenjamin Herrenschmidt { 677184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 678184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 679b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 680184cd4a3SBenjamin Herrenschmidt 681184cd4a3SBenjamin Herrenschmidt if (!pdn) 682184cd4a3SBenjamin Herrenschmidt return NULL; 683184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 684184cd4a3SBenjamin Herrenschmidt return NULL; 685184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 686184cd4a3SBenjamin Herrenschmidt } 687184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 688184cd4a3SBenjamin Herrenschmidt 689b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 690b131a842SGavin Shan struct pnv_ioda_pe *parent, 691b131a842SGavin Shan struct pnv_ioda_pe *child, 692b131a842SGavin Shan bool is_add) 693b131a842SGavin Shan { 694b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 695b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 696b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 697b131a842SGavin Shan struct pnv_ioda_pe *slave; 698b131a842SGavin Shan long rc; 699b131a842SGavin Shan 700b131a842SGavin Shan /* Parent PE affects child PE */ 701b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 702b131a842SGavin Shan child->pe_number, op); 703b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 704b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 705b131a842SGavin Shan rc, desc); 706b131a842SGavin Shan return -ENXIO; 707b131a842SGavin Shan } 708b131a842SGavin Shan 709b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 710b131a842SGavin Shan return 0; 711b131a842SGavin Shan 712b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 713b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 714b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 715b131a842SGavin Shan slave->pe_number, op); 716b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 717b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 718b131a842SGavin Shan rc, desc); 719b131a842SGavin Shan return -ENXIO; 720b131a842SGavin Shan } 721b131a842SGavin Shan } 722b131a842SGavin Shan 723b131a842SGavin Shan return 0; 724b131a842SGavin Shan } 725b131a842SGavin Shan 726b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 727b131a842SGavin Shan struct pnv_ioda_pe *pe, 728b131a842SGavin Shan bool is_add) 729b131a842SGavin Shan { 730b131a842SGavin Shan struct pnv_ioda_pe *slave; 731781a868fSWei Yang struct pci_dev *pdev = NULL; 732b131a842SGavin Shan int ret; 733b131a842SGavin Shan 734b131a842SGavin Shan /* 735b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 736b131a842SGavin Shan * clear slave PE frozen state as well. 737b131a842SGavin Shan */ 738b131a842SGavin Shan if (is_add) { 739b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 740b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 741b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 742b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 743b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 744b131a842SGavin Shan slave->pe_number, 745b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 746b131a842SGavin Shan } 747b131a842SGavin Shan } 748b131a842SGavin Shan 749b131a842SGavin Shan /* 750b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 751b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 752b131a842SGavin Shan * originated from the PE might contribute to other 753b131a842SGavin Shan * PEs. 754b131a842SGavin Shan */ 755b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 756b131a842SGavin Shan if (ret) 757b131a842SGavin Shan return ret; 758b131a842SGavin Shan 759b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 760b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 761b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 762b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 763b131a842SGavin Shan if (ret) 764b131a842SGavin Shan return ret; 765b131a842SGavin Shan } 766b131a842SGavin Shan } 767b131a842SGavin Shan 768b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 769b131a842SGavin Shan pdev = pe->pbus->self; 770781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 771b131a842SGavin Shan pdev = pe->pdev->bus->self; 772781a868fSWei Yang #ifdef CONFIG_PCI_IOV 773781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 774283e2d8aSGavin Shan pdev = pe->parent_dev; 775781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 776b131a842SGavin Shan while (pdev) { 777b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 778b131a842SGavin Shan struct pnv_ioda_pe *parent; 779b131a842SGavin Shan 780b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 781b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 782b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 783b131a842SGavin Shan if (ret) 784b131a842SGavin Shan return ret; 785b131a842SGavin Shan } 786b131a842SGavin Shan 787b131a842SGavin Shan pdev = pdev->bus->self; 788b131a842SGavin Shan } 789b131a842SGavin Shan 790b131a842SGavin Shan return 0; 791b131a842SGavin Shan } 792b131a842SGavin Shan 793781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 794781a868fSWei Yang { 795781a868fSWei Yang struct pci_dev *parent; 796781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 797781a868fSWei Yang int64_t rc; 798781a868fSWei Yang long rid_end, rid; 799781a868fSWei Yang 800781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 801781a868fSWei Yang if (pe->pbus) { 802781a868fSWei Yang int count; 803781a868fSWei Yang 804781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 805781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 806781a868fSWei Yang parent = pe->pbus->self; 807781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 808781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 809781a868fSWei Yang else 810781a868fSWei Yang count = 1; 811781a868fSWei Yang 812781a868fSWei Yang switch(count) { 813781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 814781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 815781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 816781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 817781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 818781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 819781a868fSWei Yang default: 820781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 821781a868fSWei Yang count); 822781a868fSWei Yang /* Do an exact match only */ 823781a868fSWei Yang bcomp = OpalPciBusAll; 824781a868fSWei Yang } 825781a868fSWei Yang rid_end = pe->rid + (count << 8); 826781a868fSWei Yang } else { 82793e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 828781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 829781a868fSWei Yang parent = pe->parent_dev; 830781a868fSWei Yang else 83193e01a50SGavin Shan #endif 832781a868fSWei Yang parent = pe->pdev->bus->self; 833781a868fSWei Yang bcomp = OpalPciBusAll; 834781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 835781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 836781a868fSWei Yang rid_end = pe->rid + 1; 837781a868fSWei Yang } 838781a868fSWei Yang 839781a868fSWei Yang /* Clear the reverse map */ 840781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 841c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 842781a868fSWei Yang 843781a868fSWei Yang /* Release from all parents PELT-V */ 844781a868fSWei Yang while (parent) { 845781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 846781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 847781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 848781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 849781a868fSWei Yang /* XXX What to do in case of error ? */ 850781a868fSWei Yang } 851781a868fSWei Yang parent = parent->bus->self; 852781a868fSWei Yang } 853781a868fSWei Yang 854f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 855781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 856781a868fSWei Yang 857781a868fSWei Yang /* Disassociate PE in PELT */ 858781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 859781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 860781a868fSWei Yang if (rc) 861781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 862781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 863781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 864781a868fSWei Yang if (rc) 865781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 866781a868fSWei Yang 867781a868fSWei Yang pe->pbus = NULL; 868781a868fSWei Yang pe->pdev = NULL; 86993e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 870781a868fSWei Yang pe->parent_dev = NULL; 87193e01a50SGavin Shan #endif 872781a868fSWei Yang 873781a868fSWei Yang return 0; 874781a868fSWei Yang } 875781a868fSWei Yang 876cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 877184cd4a3SBenjamin Herrenschmidt { 878184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 879184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 880184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 881184cd4a3SBenjamin Herrenschmidt 882184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 883184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 884184cd4a3SBenjamin Herrenschmidt int count; 885184cd4a3SBenjamin Herrenschmidt 886184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 887184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 888184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 889fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 890b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 891fb446ad0SGavin Shan else 892fb446ad0SGavin Shan count = 1; 893fb446ad0SGavin Shan 894184cd4a3SBenjamin Herrenschmidt switch(count) { 895184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 896184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 897184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 898184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 899184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 900184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 901184cd4a3SBenjamin Herrenschmidt default: 902781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 903781a868fSWei Yang count); 904184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 905184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 906184cd4a3SBenjamin Herrenschmidt } 907184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 908184cd4a3SBenjamin Herrenschmidt } else { 909781a868fSWei Yang #ifdef CONFIG_PCI_IOV 910781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 911781a868fSWei Yang parent = pe->parent_dev; 912781a868fSWei Yang else 913781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 914184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 915184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 916184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 917184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 918184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 919184cd4a3SBenjamin Herrenschmidt } 920184cd4a3SBenjamin Herrenschmidt 921631ad691SGavin Shan /* 922631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 923631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 924631ad691SGavin Shan * originated from the PE might contribute to other 925631ad691SGavin Shan * PEs. 926631ad691SGavin Shan */ 927184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 928184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 929184cd4a3SBenjamin Herrenschmidt if (rc) { 930184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 931184cd4a3SBenjamin Herrenschmidt return -ENXIO; 932184cd4a3SBenjamin Herrenschmidt } 933631ad691SGavin Shan 9345d2aa710SAlistair Popple /* 9355d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9365d2aa710SAlistair Popple * configuration on them. 9375d2aa710SAlistair Popple */ 9387f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 939b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 940184cd4a3SBenjamin Herrenschmidt 941184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 942184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 943184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 944184cd4a3SBenjamin Herrenschmidt 945184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9464773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9474773f76bSGavin Shan pe->mve_number = 0; 9484773f76bSGavin Shan goto out; 9494773f76bSGavin Shan } 9504773f76bSGavin Shan 951184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9524773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9534773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9541f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 955184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 956184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 957184cd4a3SBenjamin Herrenschmidt } else { 958184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 959cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 960184cd4a3SBenjamin Herrenschmidt if (rc) { 9611f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 962184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 963184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 964184cd4a3SBenjamin Herrenschmidt } 965184cd4a3SBenjamin Herrenschmidt } 966184cd4a3SBenjamin Herrenschmidt 9674773f76bSGavin Shan out: 968184cd4a3SBenjamin Herrenschmidt return 0; 969184cd4a3SBenjamin Herrenschmidt } 970184cd4a3SBenjamin Herrenschmidt 971781a868fSWei Yang #ifdef CONFIG_PCI_IOV 972781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 973781a868fSWei Yang { 974781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 975781a868fSWei Yang int i; 976781a868fSWei Yang struct resource *res, res2; 977781a868fSWei Yang resource_size_t size; 978781a868fSWei Yang u16 num_vfs; 979781a868fSWei Yang 980781a868fSWei Yang if (!dev->is_physfn) 981781a868fSWei Yang return -EINVAL; 982781a868fSWei Yang 983781a868fSWei Yang /* 984781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 985781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 986781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 987781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 988781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 989781a868fSWei Yang * range of PEs the VFs are in. 990781a868fSWei Yang */ 991781a868fSWei Yang num_vfs = pdn->num_vfs; 992781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 993781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 994781a868fSWei Yang if (!res->flags || !res->parent) 995781a868fSWei Yang continue; 996781a868fSWei Yang 997781a868fSWei Yang /* 998781a868fSWei Yang * The actual IOV BAR range is determined by the start address 999781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 1000781a868fSWei Yang * make sure that after shifting, the range will not overlap 1001781a868fSWei Yang * with another device. 1002781a868fSWei Yang */ 1003781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1004781a868fSWei Yang res2.flags = res->flags; 1005781a868fSWei Yang res2.start = res->start + (size * offset); 1006781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 1007781a868fSWei Yang 1008781a868fSWei Yang if (res2.end > res->end) { 1009781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1010781a868fSWei Yang i, &res2, res, num_vfs, offset); 1011781a868fSWei Yang return -EBUSY; 1012781a868fSWei Yang } 1013781a868fSWei Yang } 1014781a868fSWei Yang 1015781a868fSWei Yang /* 1016d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1017d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1018d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1019d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1020d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1021d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1022781a868fSWei Yang */ 1023781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1024781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1025781a868fSWei Yang if (!res->flags || !res->parent) 1026781a868fSWei Yang continue; 1027781a868fSWei Yang 1028781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1029781a868fSWei Yang res2 = *res; 1030781a868fSWei Yang res->start += size * offset; 1031781a868fSWei Yang 103274703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 103374703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 103474703cc4SWei Yang num_vfs, offset); 1035d6f934fdSAlexey Kardashevskiy 1036d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1037d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1038d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1039d6f934fdSAlexey Kardashevskiy } 1040d6f934fdSAlexey Kardashevskiy 1041781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1042d6f934fdSAlexey Kardashevskiy 1043d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1044d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1045d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1046d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1047d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1048d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1049d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1050d6f934fdSAlexey Kardashevskiy } 1051781a868fSWei Yang } 1052781a868fSWei Yang return 0; 1053781a868fSWei Yang } 1054781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1055781a868fSWei Yang 1056cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1057184cd4a3SBenjamin Herrenschmidt { 1058184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1059184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1060b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1061184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1062184cd4a3SBenjamin Herrenschmidt 1063184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1064184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1065184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1066184cd4a3SBenjamin Herrenschmidt return NULL; 1067184cd4a3SBenjamin Herrenschmidt } 1068184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1069184cd4a3SBenjamin Herrenschmidt return NULL; 1070184cd4a3SBenjamin Herrenschmidt 10711e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10721e916772SGavin Shan if (!pe) { 1073f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1074184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1075184cd4a3SBenjamin Herrenschmidt return NULL; 1076184cd4a3SBenjamin Herrenschmidt } 1077184cd4a3SBenjamin Herrenschmidt 1078184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1079184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1080184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1081184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1082184cd4a3SBenjamin Herrenschmidt * 1083184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1084184cd4a3SBenjamin Herrenschmidt */ 1085184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 10861e916772SGavin Shan pdn->pe_number = pe->pe_number; 10875d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1088184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1089184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1090184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1091184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1092184cd4a3SBenjamin Herrenschmidt 1093184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1094184cd4a3SBenjamin Herrenschmidt 1095184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1096184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10971e916772SGavin Shan pnv_ioda_free_pe(pe); 1098184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1099184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1100184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1101184cd4a3SBenjamin Herrenschmidt return NULL; 1102184cd4a3SBenjamin Herrenschmidt } 1103184cd4a3SBenjamin Herrenschmidt 11041d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 11051d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 11061d4e89cfSAlexey Kardashevskiy 1107184cd4a3SBenjamin Herrenschmidt return pe; 1108184cd4a3SBenjamin Herrenschmidt } 1109184cd4a3SBenjamin Herrenschmidt 1110184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1111184cd4a3SBenjamin Herrenschmidt { 1112184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1113184cd4a3SBenjamin Herrenschmidt 1114184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1115b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1116184cd4a3SBenjamin Herrenschmidt 1117184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1118184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1119184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1120184cd4a3SBenjamin Herrenschmidt continue; 1121184cd4a3SBenjamin Herrenschmidt } 1122ccd1c191SGavin Shan 1123ccd1c191SGavin Shan /* 1124ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1125ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1126ccd1c191SGavin Shan * again. 1127ccd1c191SGavin Shan */ 1128ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1129ccd1c191SGavin Shan continue; 1130ccd1c191SGavin Shan 1131c5f7700bSGavin Shan pe->device_count++; 1132184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1133fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1134184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1135184cd4a3SBenjamin Herrenschmidt } 1136184cd4a3SBenjamin Herrenschmidt } 1137184cd4a3SBenjamin Herrenschmidt 1138fb446ad0SGavin Shan /* 1139fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1140fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1141fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1142fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1143fb446ad0SGavin Shan */ 11441e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1145184cd4a3SBenjamin Herrenschmidt { 1146fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1147184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11481e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1149ccd1c191SGavin Shan unsigned int pe_num; 1150ccd1c191SGavin Shan 1151ccd1c191SGavin Shan /* 1152ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1153ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1154ccd1c191SGavin Shan */ 1155ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1156ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1157ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1158ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1159ccd1c191SGavin Shan return NULL; 1160ccd1c191SGavin Shan } 1161184cd4a3SBenjamin Herrenschmidt 116263803c39SGavin Shan /* PE number for root bus should have been reserved */ 116363803c39SGavin Shan if (pci_is_root_bus(bus) && 116463803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 116563803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 116663803c39SGavin Shan 1167262af557SGuo Chao /* Check if PE is determined by M64 */ 116863803c39SGavin Shan if (!pe && phb->pick_m64_pe) 11691e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1170262af557SGuo Chao 1171262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11721e916772SGavin Shan if (!pe) 11731e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1174262af557SGuo Chao 11751e916772SGavin Shan if (!pe) { 1176f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1177fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11781e916772SGavin Shan return NULL; 1179184cd4a3SBenjamin Herrenschmidt } 1180184cd4a3SBenjamin Herrenschmidt 1181262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1182184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1183184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1184184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1185b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1186184cd4a3SBenjamin Herrenschmidt 1187fb446ad0SGavin Shan if (all) 11881f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11891e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1190fb446ad0SGavin Shan else 11911f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11921e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1193184cd4a3SBenjamin Herrenschmidt 1194184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1195184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11961e916772SGavin Shan pnv_ioda_free_pe(pe); 1197184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11981e916772SGavin Shan return NULL; 1199184cd4a3SBenjamin Herrenschmidt } 1200184cd4a3SBenjamin Herrenschmidt 1201184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1202184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1203184cd4a3SBenjamin Herrenschmidt 12047ebdf956SGavin Shan /* Put PE to the list */ 12057ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 12061e916772SGavin Shan 12071e916772SGavin Shan return pe; 1208184cd4a3SBenjamin Herrenschmidt } 1209184cd4a3SBenjamin Herrenschmidt 1210b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 12115d2aa710SAlistair Popple { 1212b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1213b521549aSAlistair Popple long rid; 1214b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1215b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1216b521549aSAlistair Popple struct pci_dn *npu_pdn; 1217b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1218b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1219b521549aSAlistair Popple 1220b521549aSAlistair Popple /* 1221b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1222b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1223b521549aSAlistair Popple * which need to be assigned to four links, implying some 1224b521549aSAlistair Popple * links must share PEs. 1225b521549aSAlistair Popple * 1226b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1227b521549aSAlistair Popple * same GPU get assigned the same PE. 1228b521549aSAlistair Popple */ 1229b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 123092b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1231b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1232b521549aSAlistair Popple if (!pe->pdev) 1233b521549aSAlistair Popple continue; 1234b521549aSAlistair Popple 1235b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1236b521549aSAlistair Popple /* 1237b521549aSAlistair Popple * This device has the same peer GPU so should 1238b521549aSAlistair Popple * be assigned the same PE as the existing 1239b521549aSAlistair Popple * peer NPU. 1240b521549aSAlistair Popple */ 1241b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12421f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1243b521549aSAlistair Popple pci_dev_get(npu_pdev); 1244b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1245b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1246b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1247b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1248b521549aSAlistair Popple 1249b521549aSAlistair Popple /* Map the PE to this link */ 1250b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1251b521549aSAlistair Popple OpalPciBusAll, 1252b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1253b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1254b521549aSAlistair Popple OPAL_MAP_PE); 1255b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1256b521549aSAlistair Popple found_pe = true; 1257b521549aSAlistair Popple break; 1258b521549aSAlistair Popple } 1259b521549aSAlistair Popple } 1260b521549aSAlistair Popple 1261b521549aSAlistair Popple if (!found_pe) 1262b521549aSAlistair Popple /* 1263b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1264b521549aSAlistair Popple * one. 1265b521549aSAlistair Popple */ 1266b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1267b521549aSAlistair Popple else 1268b521549aSAlistair Popple return pe; 1269b521549aSAlistair Popple } 1270b521549aSAlistair Popple 1271b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1272b521549aSAlistair Popple { 12735d2aa710SAlistair Popple struct pci_dev *pdev; 12745d2aa710SAlistair Popple 12755d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1276b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12775d2aa710SAlistair Popple } 12785d2aa710SAlistair Popple 1279cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1280fb446ad0SGavin Shan { 1281fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1282262af557SGuo Chao struct pnv_phb *phb; 12837f2c39e9SFrederic Barrat struct pci_bus *bus; 12847f2c39e9SFrederic Barrat struct pci_dev *pdev; 1285fb446ad0SGavin Shan 1286fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1287262af557SGuo Chao phb = hose->private_data; 12887f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 128908f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 129008f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1291b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12921ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12931ab66d1fSAlistair Popple pnv_npu2_init(phb); 1294ccd1c191SGavin Shan } 12957f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_OCAPI) { 12967f2c39e9SFrederic Barrat bus = hose->bus; 12977f2c39e9SFrederic Barrat list_for_each_entry(pdev, &bus->devices, bus_list) 12987f2c39e9SFrederic Barrat pnv_ioda_setup_dev_PE(pdev); 12997f2c39e9SFrederic Barrat } 1300fb446ad0SGavin Shan } 1301fb446ad0SGavin Shan } 1302184cd4a3SBenjamin Herrenschmidt 1303a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1304ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1305781a868fSWei Yang { 1306781a868fSWei Yang struct pci_bus *bus; 1307781a868fSWei Yang struct pci_controller *hose; 1308781a868fSWei Yang struct pnv_phb *phb; 1309781a868fSWei Yang struct pci_dn *pdn; 131002639b0eSWei Yang int i, j; 1311ee8222feSWei Yang int m64_bars; 1312781a868fSWei Yang 1313781a868fSWei Yang bus = pdev->bus; 1314781a868fSWei Yang hose = pci_bus_to_host(bus); 1315781a868fSWei Yang phb = hose->private_data; 1316781a868fSWei Yang pdn = pci_get_pdn(pdev); 1317781a868fSWei Yang 1318ee8222feSWei Yang if (pdn->m64_single_mode) 1319ee8222feSWei Yang m64_bars = num_vfs; 1320ee8222feSWei Yang else 1321ee8222feSWei Yang m64_bars = 1; 1322ee8222feSWei Yang 132302639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1324ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1325ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1326781a868fSWei Yang continue; 1327781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1328ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1329ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1330ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1331781a868fSWei Yang } 1332781a868fSWei Yang 1333ee8222feSWei Yang kfree(pdn->m64_map); 1334781a868fSWei Yang return 0; 1335781a868fSWei Yang } 1336781a868fSWei Yang 133702639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1338781a868fSWei Yang { 1339781a868fSWei Yang struct pci_bus *bus; 1340781a868fSWei Yang struct pci_controller *hose; 1341781a868fSWei Yang struct pnv_phb *phb; 1342781a868fSWei Yang struct pci_dn *pdn; 1343781a868fSWei Yang unsigned int win; 1344781a868fSWei Yang struct resource *res; 134502639b0eSWei Yang int i, j; 1346781a868fSWei Yang int64_t rc; 134702639b0eSWei Yang int total_vfs; 134802639b0eSWei Yang resource_size_t size, start; 134902639b0eSWei Yang int pe_num; 1350ee8222feSWei Yang int m64_bars; 1351781a868fSWei Yang 1352781a868fSWei Yang bus = pdev->bus; 1353781a868fSWei Yang hose = pci_bus_to_host(bus); 1354781a868fSWei Yang phb = hose->private_data; 1355781a868fSWei Yang pdn = pci_get_pdn(pdev); 135602639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1357781a868fSWei Yang 1358ee8222feSWei Yang if (pdn->m64_single_mode) 1359ee8222feSWei Yang m64_bars = num_vfs; 1360ee8222feSWei Yang else 1361ee8222feSWei Yang m64_bars = 1; 136202639b0eSWei Yang 1363fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1364fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1365fb37e128SMarkus Elfring GFP_KERNEL); 1366ee8222feSWei Yang if (!pdn->m64_map) 1367ee8222feSWei Yang return -ENOMEM; 1368ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1369ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1370ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1371ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1372ee8222feSWei Yang 1373781a868fSWei Yang 1374781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1375781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1376781a868fSWei Yang if (!res->flags || !res->parent) 1377781a868fSWei Yang continue; 1378781a868fSWei Yang 1379ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1380781a868fSWei Yang do { 1381781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1382781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1383781a868fSWei Yang 1384781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1385781a868fSWei Yang goto m64_failed; 1386781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1387781a868fSWei Yang 1388ee8222feSWei Yang pdn->m64_map[j][i] = win; 138902639b0eSWei Yang 1390ee8222feSWei Yang if (pdn->m64_single_mode) { 139102639b0eSWei Yang size = pci_iov_resource_size(pdev, 139202639b0eSWei Yang PCI_IOV_RESOURCES + i); 139302639b0eSWei Yang start = res->start + size * j; 139402639b0eSWei Yang } else { 139502639b0eSWei Yang size = resource_size(res); 139602639b0eSWei Yang start = res->start; 139702639b0eSWei Yang } 1398781a868fSWei Yang 1399781a868fSWei Yang /* Map the M64 here */ 1400ee8222feSWei Yang if (pdn->m64_single_mode) { 1401be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 140202639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 140302639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1404ee8222feSWei Yang pdn->m64_map[j][i], 0); 140502639b0eSWei Yang } 140602639b0eSWei Yang 1407781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1408781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1409ee8222feSWei Yang pdn->m64_map[j][i], 141002639b0eSWei Yang start, 1411781a868fSWei Yang 0, /* unused */ 141202639b0eSWei Yang size); 141302639b0eSWei Yang 141402639b0eSWei Yang 1415781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1416781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1417781a868fSWei Yang win, rc); 1418781a868fSWei Yang goto m64_failed; 1419781a868fSWei Yang } 1420781a868fSWei Yang 1421ee8222feSWei Yang if (pdn->m64_single_mode) 1422781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1423ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 142402639b0eSWei Yang else 142502639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1426ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 142702639b0eSWei Yang 1428781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1429781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1430781a868fSWei Yang win, rc); 1431781a868fSWei Yang goto m64_failed; 1432781a868fSWei Yang } 1433781a868fSWei Yang } 143402639b0eSWei Yang } 1435781a868fSWei Yang return 0; 1436781a868fSWei Yang 1437781a868fSWei Yang m64_failed: 1438ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1439781a868fSWei Yang return -EBUSY; 1440781a868fSWei Yang } 1441781a868fSWei Yang 1442c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1443c035e37bSAlexey Kardashevskiy int num); 1444c035e37bSAlexey Kardashevskiy 1445781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1446781a868fSWei Yang { 1447781a868fSWei Yang struct iommu_table *tbl; 1448781a868fSWei Yang int64_t rc; 1449781a868fSWei Yang 1450b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1451c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1452781a868fSWei Yang if (rc) 1453781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1454781a868fSWei Yang 1455c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14560eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14570eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14580eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1459ac9a5889SAlexey Kardashevskiy } 1460e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1461781a868fSWei Yang } 1462781a868fSWei Yang 1463ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1464781a868fSWei Yang { 1465781a868fSWei Yang struct pci_bus *bus; 1466781a868fSWei Yang struct pci_controller *hose; 1467781a868fSWei Yang struct pnv_phb *phb; 1468781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1469781a868fSWei Yang struct pci_dn *pdn; 1470781a868fSWei Yang 1471781a868fSWei Yang bus = pdev->bus; 1472781a868fSWei Yang hose = pci_bus_to_host(bus); 1473781a868fSWei Yang phb = hose->private_data; 147402639b0eSWei Yang pdn = pci_get_pdn(pdev); 1475781a868fSWei Yang 1476781a868fSWei Yang if (!pdev->is_physfn) 1477781a868fSWei Yang return; 1478781a868fSWei Yang 1479781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1480781a868fSWei Yang if (pe->parent_dev != pdev) 1481781a868fSWei Yang continue; 1482781a868fSWei Yang 1483781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1484781a868fSWei Yang 1485781a868fSWei Yang /* Remove from list */ 1486781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1487781a868fSWei Yang list_del(&pe->list); 1488781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1489781a868fSWei Yang 1490781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1491781a868fSWei Yang 14921e916772SGavin Shan pnv_ioda_free_pe(pe); 1493781a868fSWei Yang } 1494781a868fSWei Yang } 1495781a868fSWei Yang 1496781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1497781a868fSWei Yang { 1498781a868fSWei Yang struct pci_bus *bus; 1499781a868fSWei Yang struct pci_controller *hose; 1500781a868fSWei Yang struct pnv_phb *phb; 15011e916772SGavin Shan struct pnv_ioda_pe *pe; 1502781a868fSWei Yang struct pci_dn *pdn; 1503be283eebSWei Yang u16 num_vfs, i; 1504781a868fSWei Yang 1505781a868fSWei Yang bus = pdev->bus; 1506781a868fSWei Yang hose = pci_bus_to_host(bus); 1507781a868fSWei Yang phb = hose->private_data; 1508781a868fSWei Yang pdn = pci_get_pdn(pdev); 1509781a868fSWei Yang num_vfs = pdn->num_vfs; 1510781a868fSWei Yang 1511781a868fSWei Yang /* Release VF PEs */ 1512ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1513781a868fSWei Yang 1514781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1515ee8222feSWei Yang if (!pdn->m64_single_mode) 1516be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1517781a868fSWei Yang 1518781a868fSWei Yang /* Release M64 windows */ 1519ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1520781a868fSWei Yang 1521781a868fSWei Yang /* Release PE numbers */ 1522be283eebSWei Yang if (pdn->m64_single_mode) { 1523be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15241e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15251e916772SGavin Shan continue; 15261e916772SGavin Shan 15271e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15281e916772SGavin Shan pnv_ioda_free_pe(pe); 1529be283eebSWei Yang } 1530be283eebSWei Yang } else 1531be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1532be283eebSWei Yang /* Releasing pe_num_map */ 1533be283eebSWei Yang kfree(pdn->pe_num_map); 1534781a868fSWei Yang } 1535781a868fSWei Yang } 1536781a868fSWei Yang 1537781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1538781a868fSWei Yang struct pnv_ioda_pe *pe); 1539781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1540781a868fSWei Yang { 1541781a868fSWei Yang struct pci_bus *bus; 1542781a868fSWei Yang struct pci_controller *hose; 1543781a868fSWei Yang struct pnv_phb *phb; 1544781a868fSWei Yang struct pnv_ioda_pe *pe; 1545781a868fSWei Yang int pe_num; 1546781a868fSWei Yang u16 vf_index; 1547781a868fSWei Yang struct pci_dn *pdn; 1548781a868fSWei Yang 1549781a868fSWei Yang bus = pdev->bus; 1550781a868fSWei Yang hose = pci_bus_to_host(bus); 1551781a868fSWei Yang phb = hose->private_data; 1552781a868fSWei Yang pdn = pci_get_pdn(pdev); 1553781a868fSWei Yang 1554781a868fSWei Yang if (!pdev->is_physfn) 1555781a868fSWei Yang return; 1556781a868fSWei Yang 1557781a868fSWei Yang /* Reserve PE for each VF */ 1558781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1559be283eebSWei Yang if (pdn->m64_single_mode) 1560be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1561be283eebSWei Yang else 1562be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1563781a868fSWei Yang 1564781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1565781a868fSWei Yang pe->pe_number = pe_num; 1566781a868fSWei Yang pe->phb = phb; 1567781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1568781a868fSWei Yang pe->pbus = NULL; 1569781a868fSWei Yang pe->parent_dev = pdev; 1570781a868fSWei Yang pe->mve_number = -1; 1571781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1572781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1573781a868fSWei Yang 15741f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1575781a868fSWei Yang hose->global_number, pdev->bus->number, 1576781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1577781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1578781a868fSWei Yang 1579781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1580781a868fSWei Yang /* XXX What do we do here ? */ 15811e916772SGavin Shan pnv_ioda_free_pe(pe); 1582781a868fSWei Yang pe->pdev = NULL; 1583781a868fSWei Yang continue; 1584781a868fSWei Yang } 1585781a868fSWei Yang 1586781a868fSWei Yang /* Put PE to the list */ 1587781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1588781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1589781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1590781a868fSWei Yang 1591781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1592781a868fSWei Yang } 1593781a868fSWei Yang } 1594781a868fSWei Yang 1595781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1596781a868fSWei Yang { 1597781a868fSWei Yang struct pci_bus *bus; 1598781a868fSWei Yang struct pci_controller *hose; 1599781a868fSWei Yang struct pnv_phb *phb; 16001e916772SGavin Shan struct pnv_ioda_pe *pe; 1601781a868fSWei Yang struct pci_dn *pdn; 1602781a868fSWei Yang int ret; 1603be283eebSWei Yang u16 i; 1604781a868fSWei Yang 1605781a868fSWei Yang bus = pdev->bus; 1606781a868fSWei Yang hose = pci_bus_to_host(bus); 1607781a868fSWei Yang phb = hose->private_data; 1608781a868fSWei Yang pdn = pci_get_pdn(pdev); 1609781a868fSWei Yang 1610781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1611b0331854SWei Yang if (!pdn->vfs_expanded) { 1612b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1613b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1614b0331854SWei Yang return -ENOSPC; 1615b0331854SWei Yang } 1616b0331854SWei Yang 1617ee8222feSWei Yang /* 1618ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1619ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1620ee8222feSWei Yang */ 1621ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1622ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1623ee8222feSWei Yang return -EBUSY; 1624ee8222feSWei Yang } 1625ee8222feSWei Yang 1626be283eebSWei Yang /* Allocating pe_num_map */ 1627be283eebSWei Yang if (pdn->m64_single_mode) 1628fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1629fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1630be283eebSWei Yang GFP_KERNEL); 1631be283eebSWei Yang else 1632be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1633be283eebSWei Yang 1634be283eebSWei Yang if (!pdn->pe_num_map) 1635be283eebSWei Yang return -ENOMEM; 1636be283eebSWei Yang 1637be283eebSWei Yang if (pdn->m64_single_mode) 1638be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1639be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1640be283eebSWei Yang 1641781a868fSWei Yang /* Calculate available PE for required VFs */ 1642be283eebSWei Yang if (pdn->m64_single_mode) { 1643be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16441e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16451e916772SGavin Shan if (!pe) { 1646be283eebSWei Yang ret = -EBUSY; 1647be283eebSWei Yang goto m64_failed; 1648be283eebSWei Yang } 16491e916772SGavin Shan 16501e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1651be283eebSWei Yang } 1652be283eebSWei Yang } else { 1653781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1654be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 165592b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1656781a868fSWei Yang 0, num_vfs, 0); 165792b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1658781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1659781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1660be283eebSWei Yang kfree(pdn->pe_num_map); 1661781a868fSWei Yang return -EBUSY; 1662781a868fSWei Yang } 1663be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1664781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1665be283eebSWei Yang } 1666be283eebSWei Yang pdn->num_vfs = num_vfs; 1667781a868fSWei Yang 1668781a868fSWei Yang /* Assign M64 window accordingly */ 166902639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1670781a868fSWei Yang if (ret) { 1671781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1672781a868fSWei Yang goto m64_failed; 1673781a868fSWei Yang } 1674781a868fSWei Yang 1675781a868fSWei Yang /* 1676781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1677781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1678781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1679781a868fSWei Yang */ 1680ee8222feSWei Yang if (!pdn->m64_single_mode) { 1681be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1682781a868fSWei Yang if (ret) 1683781a868fSWei Yang goto m64_failed; 1684781a868fSWei Yang } 168502639b0eSWei Yang } 1686781a868fSWei Yang 1687781a868fSWei Yang /* Setup VF PEs */ 1688781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1689781a868fSWei Yang 1690781a868fSWei Yang return 0; 1691781a868fSWei Yang 1692781a868fSWei Yang m64_failed: 1693be283eebSWei Yang if (pdn->m64_single_mode) { 1694be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16951e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16961e916772SGavin Shan continue; 16971e916772SGavin Shan 16981e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16991e916772SGavin Shan pnv_ioda_free_pe(pe); 1700be283eebSWei Yang } 1701be283eebSWei Yang } else 1702be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1703be283eebSWei Yang 1704be283eebSWei Yang /* Releasing pe_num_map */ 1705be283eebSWei Yang kfree(pdn->pe_num_map); 1706781a868fSWei Yang 1707781a868fSWei Yang return ret; 1708781a868fSWei Yang } 1709781a868fSWei Yang 1710988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1711a8b2f828SGavin Shan { 1712781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1713781a868fSWei Yang 1714a8b2f828SGavin Shan /* Release PCI data */ 1715a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1716a8b2f828SGavin Shan return 0; 1717a8b2f828SGavin Shan } 1718a8b2f828SGavin Shan 1719988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1720a8b2f828SGavin Shan { 1721a8b2f828SGavin Shan /* Allocate PCI data */ 1722a8b2f828SGavin Shan add_dev_pci_data(pdev); 1723781a868fSWei Yang 1724ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1725a8b2f828SGavin Shan } 1726a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1727a8b2f828SGavin Shan 1728959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1729184cd4a3SBenjamin Herrenschmidt { 1730b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1731959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1732184cd4a3SBenjamin Herrenschmidt 1733959c9bddSGavin Shan /* 1734959c9bddSGavin Shan * The function can be called while the PE# 1735959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1736959c9bddSGavin Shan * case. 1737959c9bddSGavin Shan */ 1738959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1739959c9bddSGavin Shan return; 1740184cd4a3SBenjamin Herrenschmidt 1741959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1742cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17430e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1744b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17454617082eSAlexey Kardashevskiy /* 17464617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17474617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17484617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17494617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17504617082eSAlexey Kardashevskiy */ 1751184cd4a3SBenjamin Herrenschmidt } 1752184cd4a3SBenjamin Herrenschmidt 1753a0f98629SRussell Currey static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1754a0f98629SRussell Currey { 1755a0f98629SRussell Currey unsigned short vendor = 0; 1756a0f98629SRussell Currey struct pci_dev *pdev; 1757a0f98629SRussell Currey 1758a0f98629SRussell Currey if (pe->device_count == 1) 1759a0f98629SRussell Currey return true; 1760a0f98629SRussell Currey 1761a0f98629SRussell Currey /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1762a0f98629SRussell Currey if (!pe->pbus) 1763a0f98629SRussell Currey return true; 1764a0f98629SRussell Currey 1765a0f98629SRussell Currey list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1766a0f98629SRussell Currey if (!vendor) { 1767a0f98629SRussell Currey vendor = pdev->vendor; 1768a0f98629SRussell Currey continue; 1769a0f98629SRussell Currey } 1770a0f98629SRussell Currey 1771a0f98629SRussell Currey if (pdev->vendor != vendor) 1772a0f98629SRussell Currey return false; 1773a0f98629SRussell Currey } 1774a0f98629SRussell Currey 1775a0f98629SRussell Currey return true; 1776a0f98629SRussell Currey } 1777a0f98629SRussell Currey 17788e3f1b1dSRussell Currey /* 17798e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17808e3f1b1dSRussell Currey * 17818e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17828e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17838e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17848e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17858e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17868e3f1b1dSRussell Currey * devices in TVE#0. 17878e3f1b1dSRussell Currey * 17888e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17898e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17908e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17918e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17928e3f1b1dSRussell Currey * 17938e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17948e3f1b1dSRussell Currey */ 17958e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17968e3f1b1dSRussell Currey { 17978e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17988e3f1b1dSRussell Currey struct page *table_pages; 17998e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 18008e3f1b1dSRussell Currey __be64 *tces; 18018e3f1b1dSRussell Currey s64 rc; 18028e3f1b1dSRussell Currey 18038e3f1b1dSRussell Currey /* 18048e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 18058e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 18068e3f1b1dSRussell Currey */ 18078e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 18088e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 18098e3f1b1dSRussell Currey table_size = tce_count << 3; 18108e3f1b1dSRussell Currey 18118e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 18128e3f1b1dSRussell Currey table_size = PAGE_SIZE; 18138e3f1b1dSRussell Currey 18148e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 18158e3f1b1dSRussell Currey get_order(table_size)); 18168e3f1b1dSRussell Currey if (!table_pages) 18178e3f1b1dSRussell Currey goto err; 18188e3f1b1dSRussell Currey 18198e3f1b1dSRussell Currey tces = page_address(table_pages); 18208e3f1b1dSRussell Currey if (!tces) 18218e3f1b1dSRussell Currey goto err; 18228e3f1b1dSRussell Currey 18238e3f1b1dSRussell Currey memset(tces, 0, table_size); 18248e3f1b1dSRussell Currey 18258e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18268e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18278e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18288e3f1b1dSRussell Currey } 18298e3f1b1dSRussell Currey 18308e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18318e3f1b1dSRussell Currey pe->pe_number, 18328e3f1b1dSRussell Currey /* reconfigure window 0 */ 18338e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18348e3f1b1dSRussell Currey 1, 18358e3f1b1dSRussell Currey __pa(tces), 18368e3f1b1dSRussell Currey table_size, 18378e3f1b1dSRussell Currey 1 << tce_order); 18388e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18398e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18408e3f1b1dSRussell Currey return 0; 18418e3f1b1dSRussell Currey } 18428e3f1b1dSRussell Currey err: 18438e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18448e3f1b1dSRussell Currey return -EIO; 18458e3f1b1dSRussell Currey } 18468e3f1b1dSRussell Currey 1847763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1848cd15b048SBenjamin Herrenschmidt { 1849763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1850763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1851cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1852cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1853cd15b048SBenjamin Herrenschmidt uint64_t top; 1854cd15b048SBenjamin Herrenschmidt bool bypass = false; 18558e3f1b1dSRussell Currey s64 rc; 1856cd15b048SBenjamin Herrenschmidt 1857cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1858ed7158baSIngo Molnar return -ENODEV; 1859cd15b048SBenjamin Herrenschmidt 1860cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1861cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1862cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1863cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1864cd15b048SBenjamin Herrenschmidt } 1865cd15b048SBenjamin Herrenschmidt 1866cd15b048SBenjamin Herrenschmidt if (bypass) { 1867cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 18682d9d6f6cSChristoph Hellwig set_dma_ops(&pdev->dev, &dma_nommu_ops); 1869cd15b048SBenjamin Herrenschmidt } else { 18708e3f1b1dSRussell Currey /* 18718e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18728e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18738e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18748e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18758e3f1b1dSRussell Currey */ 18768e3f1b1dSRussell Currey if (dma_mask >> 32 && 18778e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 18788e3f1b1dSRussell Currey pnv_pci_ioda_pe_single_vendor(pe) && 18798e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18808e3f1b1dSRussell Currey /* Configure the bypass mode */ 18818e3f1b1dSRussell Currey rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18828e3f1b1dSRussell Currey if (rc) 18838e3f1b1dSRussell Currey return rc; 18848e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18858e3f1b1dSRussell Currey set_dma_offset(&pdev->dev, (1ULL << 32)); 18862d9d6f6cSChristoph Hellwig set_dma_ops(&pdev->dev, &dma_nommu_ops); 1887253fd51eSAlistair Popple } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1888253fd51eSAlistair Popple /* 1889253fd51eSAlistair Popple * Fail the request if a DMA mask between 32 and 64 bits 1890253fd51eSAlistair Popple * was requested but couldn't be fulfilled. Ideally we 1891253fd51eSAlistair Popple * would do this for 64-bits but historically we have 1892253fd51eSAlistair Popple * always fallen back to 32-bits. 1893253fd51eSAlistair Popple */ 1894253fd51eSAlistair Popple return -ENOMEM; 18958e3f1b1dSRussell Currey } else { 1896cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1897cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1898cd15b048SBenjamin Herrenschmidt } 18998e3f1b1dSRussell Currey } 1900a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 19015d2aa710SAlistair Popple 19025d2aa710SAlistair Popple /* Update peer npu devices */ 1903f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 19045d2aa710SAlistair Popple 1905cd15b048SBenjamin Herrenschmidt return 0; 1906cd15b048SBenjamin Herrenschmidt } 1907cd15b048SBenjamin Herrenschmidt 190853522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1909fe7e85c6SGavin Shan { 191053522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 191153522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1912fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1913fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1914fe7e85c6SGavin Shan u64 end, mask; 1915fe7e85c6SGavin Shan 1916fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1917fe7e85c6SGavin Shan return 0; 1918fe7e85c6SGavin Shan 1919fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1920fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1921fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1922fe7e85c6SGavin Shan 1923fe7e85c6SGavin Shan 1924fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1925fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1926fe7e85c6SGavin Shan mask += mask - 1; 1927fe7e85c6SGavin Shan 1928fe7e85c6SGavin Shan return mask; 1929fe7e85c6SGavin Shan } 1930fe7e85c6SGavin Shan 1931dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1932db08e1d5SAlexey Kardashevskiy struct pci_bus *bus, 1933db08e1d5SAlexey Kardashevskiy bool add_to_group) 193474251fe2SBenjamin Herrenschmidt { 193574251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 193674251fe2SBenjamin Herrenschmidt 193774251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1938b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1939e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 1940db08e1d5SAlexey Kardashevskiy if (add_to_group) 19414617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1942dff4a39eSGavin Shan 19435c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1944db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1945db08e1d5SAlexey Kardashevskiy add_to_group); 194674251fe2SBenjamin Herrenschmidt } 194774251fe2SBenjamin Herrenschmidt } 194874251fe2SBenjamin Herrenschmidt 1949fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1950fd141d1aSBenjamin Herrenschmidt bool real_mode) 1951fd141d1aSBenjamin Herrenschmidt { 1952fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1953fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1954fd141d1aSBenjamin Herrenschmidt } 1955fd141d1aSBenjamin Herrenschmidt 1956a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1957decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19584cce9550SGavin Shan { 19590eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19600eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19610eaf4defSAlexey Kardashevskiy next); 19620eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1963b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1964fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19654cce9550SGavin Shan unsigned long start, end, inc; 19664cce9550SGavin Shan 1967decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1968decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1969decbda25SAlexey Kardashevskiy npages - 1); 19704cce9550SGavin Shan 19714cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19724cce9550SGavin Shan start |= (1ull << 63); 19734cce9550SGavin Shan end |= (1ull << 63); 19744cce9550SGavin Shan inc = 16; 19754cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19764cce9550SGavin Shan 19774cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19784cce9550SGavin Shan while (start <= end) { 19798e0a1611SAlexey Kardashevskiy if (rm) 1980001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19818e0a1611SAlexey Kardashevskiy else 1982001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1983001ff2eeSMichael Ellerman 19844cce9550SGavin Shan start += inc; 19854cce9550SGavin Shan } 19864cce9550SGavin Shan 19874cce9550SGavin Shan /* 19884cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19894cce9550SGavin Shan * and we don't care on free() 19904cce9550SGavin Shan */ 19914cce9550SGavin Shan } 19924cce9550SGavin Shan 1993decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1994decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1995decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 199600085f1eSKrzysztof Kozlowski unsigned long attrs) 1997decbda25SAlexey Kardashevskiy { 1998decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1999decbda25SAlexey Kardashevskiy attrs); 2000decbda25SAlexey Kardashevskiy 200108acce1cSBenjamin Herrenschmidt if (!ret) 2002a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2003decbda25SAlexey Kardashevskiy 2004decbda25SAlexey Kardashevskiy return ret; 2005decbda25SAlexey Kardashevskiy } 2006decbda25SAlexey Kardashevskiy 200705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 200805c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 200905c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 201005c6cfb9SAlexey Kardashevskiy { 201105c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 201205c6cfb9SAlexey Kardashevskiy 201308acce1cSBenjamin Herrenschmidt if (!ret) 2014a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 201505c6cfb9SAlexey Kardashevskiy 201605c6cfb9SAlexey Kardashevskiy return ret; 201705c6cfb9SAlexey Kardashevskiy } 2018a540aa56SAlexey Kardashevskiy 2019a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 2020a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2021a540aa56SAlexey Kardashevskiy { 2022a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2023a540aa56SAlexey Kardashevskiy 2024a540aa56SAlexey Kardashevskiy if (!ret) 2025a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 2026a540aa56SAlexey Kardashevskiy 2027a540aa56SAlexey Kardashevskiy return ret; 2028a540aa56SAlexey Kardashevskiy } 202905c6cfb9SAlexey Kardashevskiy #endif 203005c6cfb9SAlexey Kardashevskiy 2031decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 2032decbda25SAlexey Kardashevskiy long npages) 2033decbda25SAlexey Kardashevskiy { 2034decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2035decbda25SAlexey Kardashevskiy 2036a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2037decbda25SAlexey Kardashevskiy } 2038decbda25SAlexey Kardashevskiy 2039da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2040decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 204105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 204205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 2043a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 204405c6cfb9SAlexey Kardashevskiy #endif 2045decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 2046da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2047da004c36SAlexey Kardashevskiy }; 2048da004c36SAlexey Kardashevskiy 2049a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2050a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2051a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2052bef9253fSAlexey Kardashevskiy 20536b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20540bbcdb43SAlexey Kardashevskiy { 2055fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2056a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 20570bbcdb43SAlexey Kardashevskiy 20580bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 20590bbcdb43SAlexey Kardashevskiy if (rm) 2060001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 20610bbcdb43SAlexey Kardashevskiy else 2062001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20630bbcdb43SAlexey Kardashevskiy } 20640bbcdb43SAlexey Kardashevskiy 2065a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20665780fb04SAlexey Kardashevskiy { 20675780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2068fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2069a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20705780fb04SAlexey Kardashevskiy 20715780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2072001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20735780fb04SAlexey Kardashevskiy } 20745780fb04SAlexey Kardashevskiy 2075fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2076fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2077fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20784cce9550SGavin Shan { 20794d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20804cce9550SGavin Shan unsigned long start, end, inc; 20814cce9550SGavin Shan 20824cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2083a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2084fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20854cce9550SGavin Shan end = start; 20864cce9550SGavin Shan 20874cce9550SGavin Shan /* Figure out the start, end and step */ 2088decbda25SAlexey Kardashevskiy start |= (index << shift); 2089decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2090b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20914cce9550SGavin Shan mb(); 20924cce9550SGavin Shan 20934cce9550SGavin Shan while (start <= end) { 20948e0a1611SAlexey Kardashevskiy if (rm) 2095001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 20968e0a1611SAlexey Kardashevskiy else 2097001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 20984cce9550SGavin Shan start += inc; 20994cce9550SGavin Shan } 21004cce9550SGavin Shan } 21014cce9550SGavin Shan 2102f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2103f0228c41SBenjamin Herrenschmidt { 2104f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2105f0228c41SBenjamin Herrenschmidt 2106f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2107f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2108f0228c41SBenjamin Herrenschmidt else 2109f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2110f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2111f0228c41SBenjamin Herrenschmidt } 2112f0228c41SBenjamin Herrenschmidt 2113e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2114e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2115e57080f1SAlexey Kardashevskiy { 2116e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2117e57080f1SAlexey Kardashevskiy 2118a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2119e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2120e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2121f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2122f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2123f0228c41SBenjamin Herrenschmidt 2124616badd2SAlistair Popple /* 2125616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2126616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2127616badd2SAlistair Popple * should go via the OPAL call. 2128616badd2SAlistair Popple */ 2129616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 21300bbcdb43SAlexey Kardashevskiy /* 21310bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 21320bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 21330bbcdb43SAlexey Kardashevskiy * the entire cache for it. 21340bbcdb43SAlexey Kardashevskiy */ 2135f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21365d2aa710SAlistair Popple continue; 21375d2aa710SAlistair Popple } 2138f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2139f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 214085674868SAlexey Kardashevskiy index, npages); 2141f0228c41SBenjamin Herrenschmidt else 2142f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2143f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2144f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2145f0228c41SBenjamin Herrenschmidt index << shift, npages); 2146e57080f1SAlexey Kardashevskiy } 2147e57080f1SAlexey Kardashevskiy } 2148e57080f1SAlexey Kardashevskiy 21496b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 21506b3d12a9SAlistair Popple { 21516b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 21526b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21536b3d12a9SAlistair Popple else 21546b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 21556b3d12a9SAlistair Popple } 21566b3d12a9SAlistair Popple 2157decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2158decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2159decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 216000085f1eSKrzysztof Kozlowski unsigned long attrs) 21614cce9550SGavin Shan { 2162decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2163decbda25SAlexey Kardashevskiy attrs); 21644cce9550SGavin Shan 216508acce1cSBenjamin Herrenschmidt if (!ret) 2166decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2167decbda25SAlexey Kardashevskiy 2168decbda25SAlexey Kardashevskiy return ret; 2169decbda25SAlexey Kardashevskiy } 2170decbda25SAlexey Kardashevskiy 217105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 217205c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 217305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 217405c6cfb9SAlexey Kardashevskiy { 217505c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 217605c6cfb9SAlexey Kardashevskiy 217708acce1cSBenjamin Herrenschmidt if (!ret) 217805c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 217905c6cfb9SAlexey Kardashevskiy 218005c6cfb9SAlexey Kardashevskiy return ret; 218105c6cfb9SAlexey Kardashevskiy } 2182a540aa56SAlexey Kardashevskiy 2183a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2184a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2185a540aa56SAlexey Kardashevskiy { 2186a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2187a540aa56SAlexey Kardashevskiy 2188a540aa56SAlexey Kardashevskiy if (!ret) 2189a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2190a540aa56SAlexey Kardashevskiy 2191a540aa56SAlexey Kardashevskiy return ret; 2192a540aa56SAlexey Kardashevskiy } 219305c6cfb9SAlexey Kardashevskiy #endif 219405c6cfb9SAlexey Kardashevskiy 2195decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2196decbda25SAlexey Kardashevskiy long npages) 2197decbda25SAlexey Kardashevskiy { 2198decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2199decbda25SAlexey Kardashevskiy 2200decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 22014cce9550SGavin Shan } 22024cce9550SGavin Shan 22034793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 22044793d65dSAlexey Kardashevskiy { 22054793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 22064793d65dSAlexey Kardashevskiy } 22074793d65dSAlexey Kardashevskiy 2208da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2209decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 221005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 221105c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2212a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 221305c6cfb9SAlexey Kardashevskiy #endif 2214decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2215da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 22164793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 2217da004c36SAlexey Kardashevskiy }; 2218da004c36SAlexey Kardashevskiy 2219801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2220801846d1SGavin Shan { 2221801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2222801846d1SGavin Shan 2223801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2224801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2225801846d1SGavin Shan */ 2226801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2227801846d1SGavin Shan return 0; 2228801846d1SGavin Shan 2229801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2230801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2231801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2232801846d1SGavin Shan *weight += 3; 2233801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2234801846d1SGavin Shan *weight += 15; 2235801846d1SGavin Shan else 2236801846d1SGavin Shan *weight += 10; 2237801846d1SGavin Shan 2238801846d1SGavin Shan return 0; 2239801846d1SGavin Shan } 2240801846d1SGavin Shan 2241801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2242801846d1SGavin Shan { 2243801846d1SGavin Shan unsigned int weight = 0; 2244801846d1SGavin Shan 2245801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2246801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2247801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2248801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2249801846d1SGavin Shan return weight; 2250801846d1SGavin Shan } 2251801846d1SGavin Shan #endif 2252801846d1SGavin Shan 2253801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2254801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2255801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2256801846d1SGavin Shan struct pci_dev *pdev; 2257801846d1SGavin Shan 2258801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2259801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2260801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2261801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2262801846d1SGavin Shan } 2263801846d1SGavin Shan 2264801846d1SGavin Shan return weight; 2265801846d1SGavin Shan } 2266801846d1SGavin Shan 2267b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 22682b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2269184cd4a3SBenjamin Herrenschmidt { 2270184cd4a3SBenjamin Herrenschmidt 2271184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2272184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22732b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22742b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2275184cd4a3SBenjamin Herrenschmidt int64_t rc; 2276184cd4a3SBenjamin Herrenschmidt void *addr; 2277184cd4a3SBenjamin Herrenschmidt 2278184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2279184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2280184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22812b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22822b923ed1SGavin Shan if (!weight) 22832b923ed1SGavin Shan return; 2284184cd4a3SBenjamin Herrenschmidt 22852b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22862b923ed1SGavin Shan &total_weight); 22872b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22882b923ed1SGavin Shan if (!segs) 22892b923ed1SGavin Shan segs = 1; 22902b923ed1SGavin Shan 22912b923ed1SGavin Shan /* 22922b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22932b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22942b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22952b923ed1SGavin Shan * is allocated successfully. 22962b923ed1SGavin Shan */ 22972b923ed1SGavin Shan do { 22982b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22992b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 23002b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 23012b923ed1SGavin Shan IODA_INVALID_PE) 23022b923ed1SGavin Shan avail++; 23032b923ed1SGavin Shan } 23042b923ed1SGavin Shan 23052b923ed1SGavin Shan if (avail == segs) 23062b923ed1SGavin Shan goto found; 23072b923ed1SGavin Shan } 23082b923ed1SGavin Shan } while (--segs); 23092b923ed1SGavin Shan 23102b923ed1SGavin Shan if (!segs) { 23112b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 23122b923ed1SGavin Shan return; 23132b923ed1SGavin Shan } 23142b923ed1SGavin Shan 23152b923ed1SGavin Shan found: 23160eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 231782eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 231882eae1afSAlexey Kardashevskiy return; 231982eae1afSAlexey Kardashevskiy 2320b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2321b348aa65SAlexey Kardashevskiy pe->pe_number); 23220eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2323c5773822SAlexey Kardashevskiy 2324184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 23252b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 23262b923ed1SGavin Shan weight, total_weight, base, segs); 2327184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2328acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2329acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2330184cd4a3SBenjamin Herrenschmidt 2331184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2332184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2333184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2334184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2335acce971cSGavin Shan * 2336acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2337acce971cSGavin Shan * bytes 2338184cd4a3SBenjamin Herrenschmidt */ 2339acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2340184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2341acce971cSGavin Shan get_order(tce32_segsz * segs)); 2342184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2343184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2344184cd4a3SBenjamin Herrenschmidt goto fail; 2345184cd4a3SBenjamin Herrenschmidt } 2346184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2347acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2348184cd4a3SBenjamin Herrenschmidt 2349184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2350184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2351184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2352184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2353184cd4a3SBenjamin Herrenschmidt base + i, 1, 2354acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2355acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2356184cd4a3SBenjamin Herrenschmidt if (rc) { 2357184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2358184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2359184cd4a3SBenjamin Herrenschmidt goto fail; 2360184cd4a3SBenjamin Herrenschmidt } 2361184cd4a3SBenjamin Herrenschmidt } 2362184cd4a3SBenjamin Herrenschmidt 23632b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 23642b923ed1SGavin Shan for (i = base; i < base + segs; i++) 23652b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 23662b923ed1SGavin Shan 2367184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2368acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2369acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2370acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2371184cd4a3SBenjamin Herrenschmidt 2372da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23734793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23744793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2375184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2376184cd4a3SBenjamin Herrenschmidt 2377781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 23784617082eSAlexey Kardashevskiy /* 23794617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 23804617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 23814617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 23824617082eSAlexey Kardashevskiy */ 23834617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 23844617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2385c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2386db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 238774251fe2SBenjamin Herrenschmidt 2388184cd4a3SBenjamin Herrenschmidt return; 2389184cd4a3SBenjamin Herrenschmidt fail: 2390184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2391184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2392acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23930eaf4defSAlexey Kardashevskiy if (tbl) { 23940eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2395e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23960eaf4defSAlexey Kardashevskiy } 2397184cd4a3SBenjamin Herrenschmidt } 2398184cd4a3SBenjamin Herrenschmidt 239943cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 240043cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 240143cb60abSAlexey Kardashevskiy { 240243cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 240343cb60abSAlexey Kardashevskiy table_group); 240443cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 240543cb60abSAlexey Kardashevskiy int64_t rc; 2406bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2407bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 240843cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 240943cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 241043cb60abSAlexey Kardashevskiy 24114793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 241243cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 241343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 241443cb60abSAlexey Kardashevskiy 241543cb60abSAlexey Kardashevskiy /* 241643cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 241743cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 241843cb60abSAlexey Kardashevskiy */ 241943cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 242043cb60abSAlexey Kardashevskiy pe->pe_number, 24214793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2422bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 242343cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2424bbb845c4SAlexey Kardashevskiy size << 3, 242543cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 242643cb60abSAlexey Kardashevskiy if (rc) { 242743cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 242843cb60abSAlexey Kardashevskiy return rc; 242943cb60abSAlexey Kardashevskiy } 243043cb60abSAlexey Kardashevskiy 243143cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 243243cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2433ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 243443cb60abSAlexey Kardashevskiy 243543cb60abSAlexey Kardashevskiy return 0; 243643cb60abSAlexey Kardashevskiy } 243743cb60abSAlexey Kardashevskiy 243825529100SFrederic Barrat void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2439cd15b048SBenjamin Herrenschmidt { 2440cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2441cd15b048SBenjamin Herrenschmidt int64_t rc; 2442cd15b048SBenjamin Herrenschmidt 2443cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2444cd15b048SBenjamin Herrenschmidt if (enable) { 2445cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2446cd15b048SBenjamin Herrenschmidt 2447cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2448cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2449cd15b048SBenjamin Herrenschmidt pe->pe_number, 2450cd15b048SBenjamin Herrenschmidt window_id, 2451cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2452cd15b048SBenjamin Herrenschmidt top); 2453cd15b048SBenjamin Herrenschmidt } else { 2454cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2455cd15b048SBenjamin Herrenschmidt pe->pe_number, 2456cd15b048SBenjamin Herrenschmidt window_id, 2457cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2458cd15b048SBenjamin Herrenschmidt 0); 2459cd15b048SBenjamin Herrenschmidt } 2460cd15b048SBenjamin Herrenschmidt if (rc) 2461cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2462cd15b048SBenjamin Herrenschmidt else 2463cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2464cd15b048SBenjamin Herrenschmidt } 2465cd15b048SBenjamin Herrenschmidt 24664793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 24674793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 24684793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 24694793d65dSAlexey Kardashevskiy 24704793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 24714793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 24724793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 24734793d65dSAlexey Kardashevskiy { 24744793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 24754793d65dSAlexey Kardashevskiy table_group); 24764793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 24774793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 24784793d65dSAlexey Kardashevskiy long ret; 24794793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 24804793d65dSAlexey Kardashevskiy 24814793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24824793d65dSAlexey Kardashevskiy if (!tbl) 24834793d65dSAlexey Kardashevskiy return -ENOMEM; 24844793d65dSAlexey Kardashevskiy 248511edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 248611edf116SAlexey Kardashevskiy 24874793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24884793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 24894793d65dSAlexey Kardashevskiy levels, tbl); 24904793d65dSAlexey Kardashevskiy if (ret) { 2491e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24924793d65dSAlexey Kardashevskiy return ret; 24934793d65dSAlexey Kardashevskiy } 24944793d65dSAlexey Kardashevskiy 24954793d65dSAlexey Kardashevskiy *ptbl = tbl; 24964793d65dSAlexey Kardashevskiy 24974793d65dSAlexey Kardashevskiy return 0; 24984793d65dSAlexey Kardashevskiy } 24994793d65dSAlexey Kardashevskiy 250046d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 250146d3e1e1SAlexey Kardashevskiy { 250246d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 250346d3e1e1SAlexey Kardashevskiy long rc; 250446d3e1e1SAlexey Kardashevskiy 2505bb005455SNishanth Aravamudan /* 2506fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2507fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2508fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2509fa144869SNishanth Aravamudan */ 2510fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2511fa144869SNishanth Aravamudan 2512fa144869SNishanth Aravamudan /* 2513bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2514bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2515bb005455SNishanth Aravamudan * cause errors later. 2516bb005455SNishanth Aravamudan */ 2517fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2518bb005455SNishanth Aravamudan 251946d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 252046d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2521bb005455SNishanth Aravamudan window_size, 252246d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 252346d3e1e1SAlexey Kardashevskiy if (rc) { 252446d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 252546d3e1e1SAlexey Kardashevskiy rc); 252646d3e1e1SAlexey Kardashevskiy return rc; 252746d3e1e1SAlexey Kardashevskiy } 252846d3e1e1SAlexey Kardashevskiy 252946d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 253046d3e1e1SAlexey Kardashevskiy 253146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 253246d3e1e1SAlexey Kardashevskiy if (rc) { 253346d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 253446d3e1e1SAlexey Kardashevskiy rc); 2535e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 253646d3e1e1SAlexey Kardashevskiy return rc; 253746d3e1e1SAlexey Kardashevskiy } 253846d3e1e1SAlexey Kardashevskiy 253946d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 254046d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 254146d3e1e1SAlexey Kardashevskiy 254246d3e1e1SAlexey Kardashevskiy /* 254346d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 254446d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 254546d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 254646d3e1e1SAlexey Kardashevskiy */ 254746d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 254846d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 254946d3e1e1SAlexey Kardashevskiy 255046d3e1e1SAlexey Kardashevskiy return 0; 255146d3e1e1SAlexey Kardashevskiy } 255246d3e1e1SAlexey Kardashevskiy 2553b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2554b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2555b5926430SAlexey Kardashevskiy int num) 2556b5926430SAlexey Kardashevskiy { 2557b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2558b5926430SAlexey Kardashevskiy table_group); 2559b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2560b5926430SAlexey Kardashevskiy long ret; 2561b5926430SAlexey Kardashevskiy 2562b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2563b5926430SAlexey Kardashevskiy 2564b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2565b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2566b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2567b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2568b5926430SAlexey Kardashevskiy if (ret) 2569b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2570b5926430SAlexey Kardashevskiy else 2571ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2572b5926430SAlexey Kardashevskiy 2573b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2574b5926430SAlexey Kardashevskiy 2575b5926430SAlexey Kardashevskiy return ret; 2576b5926430SAlexey Kardashevskiy } 2577b5926430SAlexey Kardashevskiy #endif 2578b5926430SAlexey Kardashevskiy 2579f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 258000547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 258100547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 258200547193SAlexey Kardashevskiy { 258300547193SAlexey Kardashevskiy unsigned long bytes = 0; 258400547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 258500547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 258600547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 258700547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 258800547193SAlexey Kardashevskiy unsigned long direct_table_size; 258900547193SAlexey Kardashevskiy 259000547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 259100547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 259200547193SAlexey Kardashevskiy return 0; 259300547193SAlexey Kardashevskiy 259400547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 259500547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 259600547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 259700547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 259800547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 259900547193SAlexey Kardashevskiy 260000547193SAlexey Kardashevskiy for ( ; levels; --levels) { 260100547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 260200547193SAlexey Kardashevskiy 260300547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 260400547193SAlexey Kardashevskiy tce_table_size <<= 3; 2605e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2606e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 260700547193SAlexey Kardashevskiy } 260800547193SAlexey Kardashevskiy 260900547193SAlexey Kardashevskiy return bytes; 261000547193SAlexey Kardashevskiy } 261100547193SAlexey Kardashevskiy 2612f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2613cd15b048SBenjamin Herrenschmidt { 2614f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2615f87a8864SAlexey Kardashevskiy table_group); 261646d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 261746d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2618cd15b048SBenjamin Herrenschmidt 2619f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 262046d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2621db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2622db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2623e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2624cd15b048SBenjamin Herrenschmidt } 2625cd15b048SBenjamin Herrenschmidt 2626f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2627f87a8864SAlexey Kardashevskiy { 2628f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2629f87a8864SAlexey Kardashevskiy table_group); 2630f87a8864SAlexey Kardashevskiy 263146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2632db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2633db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2634f87a8864SAlexey Kardashevskiy } 2635f87a8864SAlexey Kardashevskiy 2636f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 263700547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 26384793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 26394793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 26404793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2641f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2642f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2643f87a8864SAlexey Kardashevskiy }; 2644b5cb9ab1SAlexey Kardashevskiy 2645b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2646b5cb9ab1SAlexey Kardashevskiy { 2647b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2648b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2649b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2650b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2651b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2652b5cb9ab1SAlexey Kardashevskiy 2653b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2654b5cb9ab1SAlexey Kardashevskiy return 0; 2655b5cb9ab1SAlexey Kardashevskiy 2656b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2657b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 26587f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2659b5cb9ab1SAlexey Kardashevskiy return 0; 2660b5cb9ab1SAlexey Kardashevskiy 2661b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2662b5cb9ab1SAlexey Kardashevskiy 2663b5cb9ab1SAlexey Kardashevskiy return 1; 2664b5cb9ab1SAlexey Kardashevskiy } 2665b5cb9ab1SAlexey Kardashevskiy 2666b5cb9ab1SAlexey Kardashevskiy /* 2667b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2668b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2669b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2670b5cb9ab1SAlexey Kardashevskiy */ 2671b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2672b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2673b5cb9ab1SAlexey Kardashevskiy { 2674b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2675b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2676b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2677b5cb9ab1SAlexey Kardashevskiy 2678b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2679b5cb9ab1SAlexey Kardashevskiy 2680b5cb9ab1SAlexey Kardashevskiy return npe; 2681b5cb9ab1SAlexey Kardashevskiy } 2682b5cb9ab1SAlexey Kardashevskiy 2683b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2684b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2685b5cb9ab1SAlexey Kardashevskiy { 2686d41ce7b1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2687d41ce7b1SAlexey Kardashevskiy int num2 = (num == 0) ? 1 : 0; 2688b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2689b5cb9ab1SAlexey Kardashevskiy 2690b5cb9ab1SAlexey Kardashevskiy if (ret) 2691b5cb9ab1SAlexey Kardashevskiy return ret; 2692b5cb9ab1SAlexey Kardashevskiy 2693d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2694d41ce7b1SAlexey Kardashevskiy pnv_npu_unset_window(npe, num2); 2695d41ce7b1SAlexey Kardashevskiy 2696d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_set_window(npe, num, tbl); 2697d41ce7b1SAlexey Kardashevskiy if (ret) { 2698b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2699d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2700d41ce7b1SAlexey Kardashevskiy pnv_npu_set_window(npe, num2, 2701d41ce7b1SAlexey Kardashevskiy table_group->tables[num2]); 2702d41ce7b1SAlexey Kardashevskiy } 2703b5cb9ab1SAlexey Kardashevskiy 2704b5cb9ab1SAlexey Kardashevskiy return ret; 2705b5cb9ab1SAlexey Kardashevskiy } 2706b5cb9ab1SAlexey Kardashevskiy 2707b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2708b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2709b5cb9ab1SAlexey Kardashevskiy int num) 2710b5cb9ab1SAlexey Kardashevskiy { 2711d41ce7b1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2712d41ce7b1SAlexey Kardashevskiy int num2 = (num == 0) ? 1 : 0; 2713b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2714b5cb9ab1SAlexey Kardashevskiy 2715b5cb9ab1SAlexey Kardashevskiy if (ret) 2716b5cb9ab1SAlexey Kardashevskiy return ret; 2717b5cb9ab1SAlexey Kardashevskiy 2718d41ce7b1SAlexey Kardashevskiy if (!npe->table_group.tables[num]) 2719d41ce7b1SAlexey Kardashevskiy return 0; 2720d41ce7b1SAlexey Kardashevskiy 2721d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_unset_window(npe, num); 2722d41ce7b1SAlexey Kardashevskiy if (ret) 2723d41ce7b1SAlexey Kardashevskiy return ret; 2724d41ce7b1SAlexey Kardashevskiy 2725d41ce7b1SAlexey Kardashevskiy if (table_group->tables[num2]) 2726d41ce7b1SAlexey Kardashevskiy ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]); 2727d41ce7b1SAlexey Kardashevskiy 2728d41ce7b1SAlexey Kardashevskiy return ret; 2729b5cb9ab1SAlexey Kardashevskiy } 2730b5cb9ab1SAlexey Kardashevskiy 2731b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2732b5cb9ab1SAlexey Kardashevskiy { 2733b5cb9ab1SAlexey Kardashevskiy /* 2734b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2735b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2736b5cb9ab1SAlexey Kardashevskiy */ 2737b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2738b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2739b5cb9ab1SAlexey Kardashevskiy } 2740b5cb9ab1SAlexey Kardashevskiy 2741b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2742b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2743b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2744b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2745b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2746b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2747b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2748b5cb9ab1SAlexey Kardashevskiy }; 2749b5cb9ab1SAlexey Kardashevskiy 2750b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2751b5cb9ab1SAlexey Kardashevskiy { 2752b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2753b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2754b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2755b5cb9ab1SAlexey Kardashevskiy 2756b5cb9ab1SAlexey Kardashevskiy /* 2757b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2758b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2759b5cb9ab1SAlexey Kardashevskiy */ 2760b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2761b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2762b5cb9ab1SAlexey Kardashevskiy 27637f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2764b5cb9ab1SAlexey Kardashevskiy continue; 2765b5cb9ab1SAlexey Kardashevskiy 2766b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2767b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2768b5cb9ab1SAlexey Kardashevskiy if (gpe) 2769b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2770b5cb9ab1SAlexey Kardashevskiy } 2771b5cb9ab1SAlexey Kardashevskiy } 2772b5cb9ab1SAlexey Kardashevskiy } 2773b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2774b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2775f87a8864SAlexey Kardashevskiy #endif 2776f87a8864SAlexey Kardashevskiy 2777bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2778bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 27793ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2780aca6913fSAlexey Kardashevskiy { 2781aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2782bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2783aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2784bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2785bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2786bbb845c4SAlexey Kardashevskiy long i; 2787aca6913fSAlexey Kardashevskiy 2788aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2789aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2790aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2791aca6913fSAlexey Kardashevskiy return NULL; 2792aca6913fSAlexey Kardashevskiy } 2793aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2794bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 27953ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2796bbb845c4SAlexey Kardashevskiy 2797bbb845c4SAlexey Kardashevskiy --levels; 2798bbb845c4SAlexey Kardashevskiy if (!levels) { 2799bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2800bbb845c4SAlexey Kardashevskiy return addr; 2801bbb845c4SAlexey Kardashevskiy } 2802bbb845c4SAlexey Kardashevskiy 2803bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2804bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 28053ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2806bbb845c4SAlexey Kardashevskiy if (!tmp) 2807bbb845c4SAlexey Kardashevskiy break; 2808bbb845c4SAlexey Kardashevskiy 2809bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2810bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2811bbb845c4SAlexey Kardashevskiy 2812bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2813bbb845c4SAlexey Kardashevskiy break; 2814bbb845c4SAlexey Kardashevskiy } 2815aca6913fSAlexey Kardashevskiy 2816aca6913fSAlexey Kardashevskiy return addr; 2817aca6913fSAlexey Kardashevskiy } 2818aca6913fSAlexey Kardashevskiy 2819bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2820bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2821bbb845c4SAlexey Kardashevskiy 2822aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2823bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2824bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2825aca6913fSAlexey Kardashevskiy { 2826aca6913fSAlexey Kardashevskiy void *addr; 28273ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2828aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2829aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2830aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2831aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2832aca6913fSAlexey Kardashevskiy 2833bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2834bbb845c4SAlexey Kardashevskiy return -EINVAL; 2835bbb845c4SAlexey Kardashevskiy 28369003a249SAlexey Kardashevskiy if (!is_power_of_2(window_size)) 2837aca6913fSAlexey Kardashevskiy return -EINVAL; 2838aca6913fSAlexey Kardashevskiy 2839bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2840bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2841bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2842bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2843bbb845c4SAlexey Kardashevskiy 28447aafac11SAlexey Kardashevskiy if ((level_shift - 3) * levels + page_shift >= 60) 28457aafac11SAlexey Kardashevskiy return -EINVAL; 28467aafac11SAlexey Kardashevskiy 2847aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2848bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 28493ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2850bbb845c4SAlexey Kardashevskiy 2851bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2852aca6913fSAlexey Kardashevskiy if (!addr) 2853aca6913fSAlexey Kardashevskiy return -ENOMEM; 2854aca6913fSAlexey Kardashevskiy 2855bbb845c4SAlexey Kardashevskiy /* 2856bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2857bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2858bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2859bbb845c4SAlexey Kardashevskiy */ 2860bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2861bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2862bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2863bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2864bbb845c4SAlexey Kardashevskiy } 2865bbb845c4SAlexey Kardashevskiy 2866aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2867aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2868aca6913fSAlexey Kardashevskiy page_shift); 2869bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2870bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 28713ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2872aca6913fSAlexey Kardashevskiy 2873aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2874aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2875aca6913fSAlexey Kardashevskiy 2876aca6913fSAlexey Kardashevskiy return 0; 2877aca6913fSAlexey Kardashevskiy } 2878aca6913fSAlexey Kardashevskiy 2879bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2880bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2881bbb845c4SAlexey Kardashevskiy { 2882bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2883bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2884bbb845c4SAlexey Kardashevskiy 2885bbb845c4SAlexey Kardashevskiy if (level) { 2886bbb845c4SAlexey Kardashevskiy long i; 2887bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2888bbb845c4SAlexey Kardashevskiy 2889bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2890bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2891bbb845c4SAlexey Kardashevskiy 2892bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2893bbb845c4SAlexey Kardashevskiy continue; 2894bbb845c4SAlexey Kardashevskiy 2895bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2896bbb845c4SAlexey Kardashevskiy level - 1); 2897bbb845c4SAlexey Kardashevskiy } 2898bbb845c4SAlexey Kardashevskiy } 2899bbb845c4SAlexey Kardashevskiy 2900bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2901bbb845c4SAlexey Kardashevskiy } 2902bbb845c4SAlexey Kardashevskiy 2903aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2904aca6913fSAlexey Kardashevskiy { 2905bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2906bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2907bbb845c4SAlexey Kardashevskiy 2908aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2909aca6913fSAlexey Kardashevskiy return; 2910aca6913fSAlexey Kardashevskiy 2911bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2912bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2913aca6913fSAlexey Kardashevskiy } 2914aca6913fSAlexey Kardashevskiy 29157ef73cd3SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 29167ef73cd3SAlexey Kardashevskiy { 29177ef73cd3SAlexey Kardashevskiy struct pci_controller *hose = phb->hose; 29187ef73cd3SAlexey Kardashevskiy struct device_node *dn = hose->dn; 29197ef73cd3SAlexey Kardashevskiy unsigned long mask = 0; 29207ef73cd3SAlexey Kardashevskiy int i, rc, count; 29217ef73cd3SAlexey Kardashevskiy u32 val; 29227ef73cd3SAlexey Kardashevskiy 29237ef73cd3SAlexey Kardashevskiy count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 29247ef73cd3SAlexey Kardashevskiy if (count <= 0) { 29257ef73cd3SAlexey Kardashevskiy mask = SZ_4K | SZ_64K; 29267ef73cd3SAlexey Kardashevskiy /* Add 16M for POWER8 by default */ 29277ef73cd3SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_ARCH_207S) && 29287ef73cd3SAlexey Kardashevskiy !cpu_has_feature(CPU_FTR_ARCH_300)) 29297ef73cd3SAlexey Kardashevskiy mask |= SZ_16M; 29307ef73cd3SAlexey Kardashevskiy return mask; 29317ef73cd3SAlexey Kardashevskiy } 29327ef73cd3SAlexey Kardashevskiy 29337ef73cd3SAlexey Kardashevskiy for (i = 0; i < count; i++) { 29347ef73cd3SAlexey Kardashevskiy rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 29357ef73cd3SAlexey Kardashevskiy i, &val); 29367ef73cd3SAlexey Kardashevskiy if (rc == 0) 29377ef73cd3SAlexey Kardashevskiy mask |= 1ULL << val; 29387ef73cd3SAlexey Kardashevskiy } 29397ef73cd3SAlexey Kardashevskiy 29407ef73cd3SAlexey Kardashevskiy return mask; 29417ef73cd3SAlexey Kardashevskiy } 29427ef73cd3SAlexey Kardashevskiy 2943373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2944373f5657SGavin Shan struct pnv_ioda_pe *pe) 2945373f5657SGavin Shan { 2946373f5657SGavin Shan int64_t rc; 2947373f5657SGavin Shan 2948ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2949ccd1c191SGavin Shan return; 2950ccd1c191SGavin Shan 2951f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2952f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2953f87a8864SAlexey Kardashevskiy 2954b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2955b348aa65SAlexey Kardashevskiy pe->pe_number); 2956c5773822SAlexey Kardashevskiy 2957373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2958373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2959aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2960373f5657SGavin Shan 2961e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 29624793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 29634793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 29644793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 29654793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 29664793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 29677ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2968e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2969e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2970e5aad1e6SAlexey Kardashevskiy #endif 2971e5aad1e6SAlexey Kardashevskiy 297246d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2973801846d1SGavin Shan if (rc) 297446d3e1e1SAlexey Kardashevskiy return; 297546d3e1e1SAlexey Kardashevskiy 297620f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2977db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2978373f5657SGavin Shan } 2979373f5657SGavin Shan 2980184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 29814ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2982137436c9SGavin Shan { 2983137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2984137436c9SGavin Shan ioda.irq_chip); 2985137436c9SGavin Shan 29864ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 29874ee11c1aSSuresh Warrier } 29884ee11c1aSSuresh Warrier 29894ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 29904ee11c1aSSuresh Warrier { 29914ee11c1aSSuresh Warrier int64_t rc; 29924ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 29934ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 29944ee11c1aSSuresh Warrier 29954ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2996137436c9SGavin Shan WARN_ON_ONCE(rc); 2997137436c9SGavin Shan 2998137436c9SGavin Shan icp_native_eoi(d); 2999137436c9SGavin Shan } 3000137436c9SGavin Shan 3001fd9a1c26SIan Munsie 3002f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 3003fd9a1c26SIan Munsie { 3004fd9a1c26SIan Munsie struct irq_data *idata; 3005fd9a1c26SIan Munsie struct irq_chip *ichip; 3006fd9a1c26SIan Munsie 3007fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 3008fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 3009fd9a1c26SIan Munsie return; 3010fd9a1c26SIan Munsie 3011fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 3012fd9a1c26SIan Munsie /* 3013fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 3014fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 3015fd9a1c26SIan Munsie */ 3016fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 3017fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 3018fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 3019fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 3020fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 3021fd9a1c26SIan Munsie } 3022fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 3023fd9a1c26SIan Munsie } 3024fd9a1c26SIan Munsie 30254ee11c1aSSuresh Warrier /* 30264ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 30274ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 30284ee11c1aSSuresh Warrier */ 30294ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 30304ee11c1aSSuresh Warrier { 30314ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 30324ee11c1aSSuresh Warrier } 30334ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 30344ee11c1aSSuresh Warrier 3035184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 3036137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 3037137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 3038184cd4a3SBenjamin Herrenschmidt { 3039184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 3040184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 30413a1a4661SBenjamin Herrenschmidt __be32 data; 3042184cd4a3SBenjamin Herrenschmidt int rc; 3043184cd4a3SBenjamin Herrenschmidt 3044184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 3045184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 3046184cd4a3SBenjamin Herrenschmidt return -ENXIO; 3047184cd4a3SBenjamin Herrenschmidt 3048184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 3049184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 3050184cd4a3SBenjamin Herrenschmidt return -ENXIO; 3051184cd4a3SBenjamin Herrenschmidt 3052b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 305336074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 3054b72c1f65SBenjamin Herrenschmidt is_64 = 0; 3055b72c1f65SBenjamin Herrenschmidt 3056184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 3057184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 3058184cd4a3SBenjamin Herrenschmidt if (rc) { 3059184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 3060184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 3061184cd4a3SBenjamin Herrenschmidt return -EIO; 3062184cd4a3SBenjamin Herrenschmidt } 3063184cd4a3SBenjamin Herrenschmidt 3064184cd4a3SBenjamin Herrenschmidt if (is_64) { 30653a1a4661SBenjamin Herrenschmidt __be64 addr64; 30663a1a4661SBenjamin Herrenschmidt 3067184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 3068184cd4a3SBenjamin Herrenschmidt &addr64, &data); 3069184cd4a3SBenjamin Herrenschmidt if (rc) { 3070184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 3071184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 3072184cd4a3SBenjamin Herrenschmidt return -EIO; 3073184cd4a3SBenjamin Herrenschmidt } 30743a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 30753a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 3076184cd4a3SBenjamin Herrenschmidt } else { 30773a1a4661SBenjamin Herrenschmidt __be32 addr32; 30783a1a4661SBenjamin Herrenschmidt 3079184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 3080184cd4a3SBenjamin Herrenschmidt &addr32, &data); 3081184cd4a3SBenjamin Herrenschmidt if (rc) { 3082184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 3083184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 3084184cd4a3SBenjamin Herrenschmidt return -EIO; 3085184cd4a3SBenjamin Herrenschmidt } 3086184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 30873a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 3088184cd4a3SBenjamin Herrenschmidt } 30893a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 3090184cd4a3SBenjamin Herrenschmidt 3091f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 3092137436c9SGavin Shan 3093184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 30941f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 3095184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 3096184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 3097184cd4a3SBenjamin Herrenschmidt 3098184cd4a3SBenjamin Herrenschmidt return 0; 3099184cd4a3SBenjamin Herrenschmidt } 3100184cd4a3SBenjamin Herrenschmidt 3101184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 3102184cd4a3SBenjamin Herrenschmidt { 3103fb1b55d6SGavin Shan unsigned int count; 3104184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 3105184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 3106184cd4a3SBenjamin Herrenschmidt if (!prop) { 3107184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 3108184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 3109184cd4a3SBenjamin Herrenschmidt } 3110184cd4a3SBenjamin Herrenschmidt if (!prop) 3111184cd4a3SBenjamin Herrenschmidt return; 3112184cd4a3SBenjamin Herrenschmidt 3113184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 3114fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 3115fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3116184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3117184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 3118184cd4a3SBenjamin Herrenschmidt return; 3119184cd4a3SBenjamin Herrenschmidt } 3120fb1b55d6SGavin Shan 3121184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 3122184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 3123184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3124fb1b55d6SGavin Shan count, phb->msi_base); 3125184cd4a3SBenjamin Herrenschmidt } 3126184cd4a3SBenjamin Herrenschmidt #else 3127184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 3128184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 3129184cd4a3SBenjamin Herrenschmidt 31306e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 31316e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 31326e628c7dSWei Yang { 3133f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3134f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 3135f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 31366e628c7dSWei Yang struct resource *res; 31376e628c7dSWei Yang int i; 3138dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 31396e628c7dSWei Yang struct pci_dn *pdn; 31405b88ec22SWei Yang int mul, total_vfs; 31416e628c7dSWei Yang 314244bda4b7SHari Vyas if (!pdev->is_physfn || pci_dev_is_added(pdev)) 31436e628c7dSWei Yang return; 31446e628c7dSWei Yang 31456e628c7dSWei Yang pdn = pci_get_pdn(pdev); 31466e628c7dSWei Yang pdn->vfs_expanded = 0; 3147ee8222feSWei Yang pdn->m64_single_mode = false; 31486e628c7dSWei Yang 31495b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 315092b8f137SGavin Shan mul = phb->ioda.total_pe_num; 3151dfcc8d45SWei Yang total_vf_bar_sz = 0; 31525b88ec22SWei Yang 31535b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 31545b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 31555b88ec22SWei Yang if (!res->flags || res->parent) 31565b88ec22SWei Yang continue; 3157b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 3158b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 3159b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 31605b88ec22SWei Yang i, res); 3161b0331854SWei Yang goto truncate_iov; 31625b88ec22SWei Yang } 31635b88ec22SWei Yang 3164dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 3165dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 31665b88ec22SWei Yang 3167f2dd0afeSWei Yang /* 3168f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 3169f2dd0afeSWei Yang * power of two. 3170f2dd0afeSWei Yang * 3171f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3172f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 3173f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3174f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 3175f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 3176f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 3177f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 3178f2dd0afeSWei Yang */ 3179dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 31805b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 3181dfcc8d45SWei Yang dev_info(&pdev->dev, 3182dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3183dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 3184ee8222feSWei Yang pdn->m64_single_mode = true; 31855b88ec22SWei Yang break; 31865b88ec22SWei Yang } 31875b88ec22SWei Yang } 31885b88ec22SWei Yang 31896e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 31906e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 31916e628c7dSWei Yang if (!res->flags || res->parent) 31926e628c7dSWei Yang continue; 31936e628c7dSWei Yang 31946e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3195ee8222feSWei Yang /* 3196ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 3197ee8222feSWei Yang * mode is 32MB. 3198ee8222feSWei Yang */ 3199ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3200ee8222feSWei Yang goto truncate_iov; 3201ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 32025b88ec22SWei Yang res->end = res->start + size * mul - 1; 32036e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 32046e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 32055b88ec22SWei Yang i, res, mul); 32066e628c7dSWei Yang } 32075b88ec22SWei Yang pdn->vfs_expanded = mul; 3208b0331854SWei Yang 3209b0331854SWei Yang return; 3210b0331854SWei Yang 3211b0331854SWei Yang truncate_iov: 3212b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3213b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3214b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3215b0331854SWei Yang res->flags = 0; 3216b0331854SWei Yang res->end = res->start - 1; 3217b0331854SWei Yang } 32186e628c7dSWei Yang } 32196e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 32206e628c7dSWei Yang 322123e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 322223e79425SGavin Shan struct resource *res) 322311685becSGavin Shan { 322423e79425SGavin Shan struct pnv_phb *phb = pe->phb; 322511685becSGavin Shan struct pci_bus_region region; 322623e79425SGavin Shan int index; 322723e79425SGavin Shan int64_t rc; 322811685becSGavin Shan 322923e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 323023e79425SGavin Shan return; 323111685becSGavin Shan 323211685becSGavin Shan if (res->flags & IORESOURCE_IO) { 323311685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 323411685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 323511685becSGavin Shan index = region.start / phb->ioda.io_segsize; 323611685becSGavin Shan 323792b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 323811685becSGavin Shan region.start <= region.end) { 323911685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 324011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 324111685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 324211685becSGavin Shan if (rc != OPAL_SUCCESS) { 32431f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 324411685becSGavin Shan __func__, rc, index, pe->pe_number); 324511685becSGavin Shan break; 324611685becSGavin Shan } 324711685becSGavin Shan 324811685becSGavin Shan region.start += phb->ioda.io_segsize; 324911685becSGavin Shan index++; 325011685becSGavin Shan } 3251027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 32525958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 325311685becSGavin Shan region.start = res->start - 325423e79425SGavin Shan phb->hose->mem_offset[0] - 325511685becSGavin Shan phb->ioda.m32_pci_base; 325611685becSGavin Shan region.end = res->end - 325723e79425SGavin Shan phb->hose->mem_offset[0] - 325811685becSGavin Shan phb->ioda.m32_pci_base; 325911685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 326011685becSGavin Shan 326192b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 326211685becSGavin Shan region.start <= region.end) { 326311685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 326411685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 326511685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 326611685becSGavin Shan if (rc != OPAL_SUCCESS) { 32671f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 326811685becSGavin Shan __func__, rc, index, pe->pe_number); 326911685becSGavin Shan break; 327011685becSGavin Shan } 327111685becSGavin Shan 327211685becSGavin Shan region.start += phb->ioda.m32_segsize; 327311685becSGavin Shan index++; 327411685becSGavin Shan } 327511685becSGavin Shan } 327611685becSGavin Shan } 327723e79425SGavin Shan 327823e79425SGavin Shan /* 327923e79425SGavin Shan * This function is supposed to be called on basis of PE from top 328023e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 328103671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 328223e79425SGavin Shan */ 328323e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 328423e79425SGavin Shan { 328569d733e7SGavin Shan struct pci_dev *pdev; 328623e79425SGavin Shan int i; 328723e79425SGavin Shan 328823e79425SGavin Shan /* 328923e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 329023e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 329123e79425SGavin Shan * be figured out later. 329223e79425SGavin Shan */ 329323e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 329423e79425SGavin Shan 329569d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 329669d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 329769d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 329869d733e7SGavin Shan 329969d733e7SGavin Shan /* 330069d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 330169d733e7SGavin Shan * windows of the child bridges should be mapped to 330269d733e7SGavin Shan * the PE as well. 330369d733e7SGavin Shan */ 330469d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 330569d733e7SGavin Shan continue; 330669d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 330769d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 330869d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 330969d733e7SGavin Shan } 331011685becSGavin Shan } 331111685becSGavin Shan 331298b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 331398b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 331498b665daSRussell Currey { 331598b665daSRussell Currey struct pci_controller *hose; 331698b665daSRussell Currey struct pnv_phb *phb; 331798b665daSRussell Currey s64 ret; 331898b665daSRussell Currey 331998b665daSRussell Currey if (val != 1ULL) 332098b665daSRussell Currey return -EINVAL; 332198b665daSRussell Currey 332298b665daSRussell Currey hose = (struct pci_controller *)data; 332398b665daSRussell Currey if (!hose || !hose->private_data) 332498b665daSRussell Currey return -ENODEV; 332598b665daSRussell Currey 332698b665daSRussell Currey phb = hose->private_data; 332798b665daSRussell Currey 332898b665daSRussell Currey /* Retrieve the diag data from firmware */ 33295cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 33305cb1f8fdSRussell Currey phb->diag_data_size); 333198b665daSRussell Currey if (ret != OPAL_SUCCESS) 333298b665daSRussell Currey return -EIO; 333398b665daSRussell Currey 333498b665daSRussell Currey /* Print the diag data to the kernel log */ 33355cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 333698b665daSRussell Currey return 0; 333798b665daSRussell Currey } 333898b665daSRussell Currey 333998b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 334098b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 334198b665daSRussell Currey 334298b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 334398b665daSRussell Currey 334437c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 334537c367f2SGavin Shan { 334637c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 334737c367f2SGavin Shan struct pci_controller *hose, *tmp; 334837c367f2SGavin Shan struct pnv_phb *phb; 334937c367f2SGavin Shan char name[16]; 335037c367f2SGavin Shan 335137c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 335237c367f2SGavin Shan phb = hose->private_data; 335337c367f2SGavin Shan 3354ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3355ccd1c191SGavin Shan phb->initialized = 1; 3356ccd1c191SGavin Shan 335737c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 335837c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 335998b665daSRussell Currey if (!phb->dbgfs) { 3360f2c2cbccSJoe Perches pr_warn("%s: Error on creating debugfs on PHB#%x\n", 336137c367f2SGavin Shan __func__, hose->global_number); 336298b665daSRussell Currey continue; 336398b665daSRussell Currey } 336498b665daSRussell Currey 336598b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 336698b665daSRussell Currey &pnv_pci_diag_data_fops); 336737c367f2SGavin Shan } 336837c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 336937c367f2SGavin Shan } 337037c367f2SGavin Shan 3371cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3372fb446ad0SGavin Shan { 3373fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3374ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 337537c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 337637c367f2SGavin Shan 3377e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3378b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3379e9cc17d4SGavin Shan #endif 3380fb446ad0SGavin Shan } 3381fb446ad0SGavin Shan 3382271fd03aSGavin Shan /* 3383271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3384271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3385271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3386271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3387271fd03aSGavin Shan * 1MiB for memory) will be returned. 3388271fd03aSGavin Shan * 3389271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3390271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3391271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3392271fd03aSGavin Shan * resources. 3393271fd03aSGavin Shan */ 3394271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3395271fd03aSGavin Shan unsigned long type) 3396271fd03aSGavin Shan { 3397271fd03aSGavin Shan struct pci_dev *bridge; 3398271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3399271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3400271fd03aSGavin Shan int num_pci_bridges = 0; 3401271fd03aSGavin Shan 3402271fd03aSGavin Shan bridge = bus->self; 3403271fd03aSGavin Shan while (bridge) { 3404271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3405271fd03aSGavin Shan num_pci_bridges++; 3406271fd03aSGavin Shan if (num_pci_bridges >= 2) 3407271fd03aSGavin Shan return 1; 3408271fd03aSGavin Shan } 3409271fd03aSGavin Shan 3410271fd03aSGavin Shan bridge = bridge->bus->self; 3411271fd03aSGavin Shan } 3412271fd03aSGavin Shan 34135958d19aSBenjamin Herrenschmidt /* 34145958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 34155958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 34165958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 34175958d19aSBenjamin Herrenschmidt */ 3418b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3419262af557SGuo Chao return phb->ioda.m64_segsize; 3420271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3421271fd03aSGavin Shan return phb->ioda.m32_segsize; 3422271fd03aSGavin Shan 3423271fd03aSGavin Shan return phb->ioda.io_segsize; 3424271fd03aSGavin Shan } 3425271fd03aSGavin Shan 342640e2a47eSGavin Shan /* 342740e2a47eSGavin Shan * We are updating root port or the upstream port of the 342840e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 342940e2a47eSGavin Shan * to accommodate the changes on required resources during 343040e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 343140e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 343240e2a47eSGavin Shan * root port. 343340e2a47eSGavin Shan */ 343440e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 343540e2a47eSGavin Shan unsigned long type) 343640e2a47eSGavin Shan { 343740e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 343840e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 343940e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 344040e2a47eSGavin Shan struct resource *r, *w; 344140e2a47eSGavin Shan bool msi_region = false; 344240e2a47eSGavin Shan int i; 344340e2a47eSGavin Shan 344440e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 344540e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 344640e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 344740e2a47eSGavin Shan return; 344840e2a47eSGavin Shan 344940e2a47eSGavin Shan /* Fixup the resources */ 345040e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 345140e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 345240e2a47eSGavin Shan if (!r->flags || !r->parent) 345340e2a47eSGavin Shan continue; 345440e2a47eSGavin Shan 345540e2a47eSGavin Shan w = NULL; 345640e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 345740e2a47eSGavin Shan w = &hose->io_resource; 34585958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 345940e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 346040e2a47eSGavin Shan phb->ioda.m64_segsize) 346140e2a47eSGavin Shan w = &hose->mem_resources[1]; 346240e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 346340e2a47eSGavin Shan w = &hose->mem_resources[0]; 346440e2a47eSGavin Shan msi_region = true; 346540e2a47eSGavin Shan } 346640e2a47eSGavin Shan 346740e2a47eSGavin Shan r->start = w->start; 346840e2a47eSGavin Shan r->end = w->end; 346940e2a47eSGavin Shan 347040e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 347140e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 347240e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 347340e2a47eSGavin Shan * 347440e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 347540e2a47eSGavin Shan * 32-bits bridge window. 347640e2a47eSGavin Shan */ 347740e2a47eSGavin Shan if (msi_region) { 347840e2a47eSGavin Shan r->end += 0x10000; 347940e2a47eSGavin Shan r->end -= 0x100000; 348040e2a47eSGavin Shan } 348140e2a47eSGavin Shan } 348240e2a47eSGavin Shan } 348340e2a47eSGavin Shan 3484ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3485ccd1c191SGavin Shan { 3486ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3487ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3488ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3489ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3490ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3491ccd1c191SGavin Shan 349240e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 349340e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 349440e2a47eSGavin Shan 349563803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 349663803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 349763803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 349863803c39SGavin Shan if (pe) { 349963803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 350063803c39SGavin Shan phb->ioda.root_pe_populated = true; 350163803c39SGavin Shan } 350263803c39SGavin Shan } 350363803c39SGavin Shan 3504ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3505ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3506ccd1c191SGavin Shan return; 3507ccd1c191SGavin Shan 3508ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3509ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3510ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3511ccd1c191SGavin Shan 3512ccd1c191SGavin Shan /* 3513ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3514ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3515ccd1c191SGavin Shan * not allocate resources again. 3516ccd1c191SGavin Shan */ 3517ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3518ccd1c191SGavin Shan if (!pe) 3519ccd1c191SGavin Shan return; 3520ccd1c191SGavin Shan 3521ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3522ccd1c191SGavin Shan switch (phb->type) { 3523ccd1c191SGavin Shan case PNV_PHB_IODA1: 3524ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3525ccd1c191SGavin Shan break; 3526ccd1c191SGavin Shan case PNV_PHB_IODA2: 3527ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3528ccd1c191SGavin Shan break; 3529ccd1c191SGavin Shan default: 35301f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3531ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3532ccd1c191SGavin Shan } 3533ccd1c191SGavin Shan } 3534ccd1c191SGavin Shan 353538274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 353638274637SYongji Xie { 353738274637SYongji Xie return PAGE_SIZE; 353838274637SYongji Xie } 353938274637SYongji Xie 35405350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 35415350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 35425350ab3fSWei Yang int resno) 35435350ab3fSWei Yang { 3544ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3545ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 35465350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 35477fbe7a93SWei Yang resource_size_t align; 35485350ab3fSWei Yang 35497fbe7a93SWei Yang /* 35507fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 35517fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 35527fbe7a93SWei Yang * BAR should be size aligned. 35537fbe7a93SWei Yang * 3554ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3555ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3556ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3557ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3558ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3559ee8222feSWei Yang * m64_segsize. 3560ee8222feSWei Yang * 35617fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 35627fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3563ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3564ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 35657fbe7a93SWei Yang */ 35665350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 35677fbe7a93SWei Yang if (!pdn->vfs_expanded) 35685350ab3fSWei Yang return align; 3569ee8222feSWei Yang if (pdn->m64_single_mode) 3570ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 35717fbe7a93SWei Yang 35727fbe7a93SWei Yang return pdn->vfs_expanded * align; 35735350ab3fSWei Yang } 35745350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 35755350ab3fSWei Yang 3576184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3577184cd4a3SBenjamin Herrenschmidt * assign a PE 3578184cd4a3SBenjamin Herrenschmidt */ 35794361b034SIan Munsie bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3580184cd4a3SBenjamin Herrenschmidt { 3581db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3582db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3583db1266c8SGavin Shan struct pci_dn *pdn; 3584184cd4a3SBenjamin Herrenschmidt 3585db1266c8SGavin Shan /* The function is probably called while the PEs have 3586db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3587db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3588db1266c8SGavin Shan * PEs isn't ready. 3589db1266c8SGavin Shan */ 3590db1266c8SGavin Shan if (!phb->initialized) 3591c88c2a18SDaniel Axtens return true; 3592db1266c8SGavin Shan 3593b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3594184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3595c88c2a18SDaniel Axtens return false; 3596db1266c8SGavin Shan 3597c88c2a18SDaniel Axtens return true; 3598184cd4a3SBenjamin Herrenschmidt } 3599184cd4a3SBenjamin Herrenschmidt 3600c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3601c5f7700bSGavin Shan int num) 3602c5f7700bSGavin Shan { 3603c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3604c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3605c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3606c5f7700bSGavin Shan unsigned int idx; 3607c5f7700bSGavin Shan long rc; 3608c5f7700bSGavin Shan 3609c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3610c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3611c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3612c5f7700bSGavin Shan continue; 3613c5f7700bSGavin Shan 3614c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3615c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3616c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3617c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3618c5f7700bSGavin Shan rc, idx); 3619c5f7700bSGavin Shan return rc; 3620c5f7700bSGavin Shan } 3621c5f7700bSGavin Shan 3622c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3623c5f7700bSGavin Shan } 3624c5f7700bSGavin Shan 3625c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3626c5f7700bSGavin Shan return OPAL_SUCCESS; 3627c5f7700bSGavin Shan } 3628c5f7700bSGavin Shan 3629c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3630c5f7700bSGavin Shan { 3631c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3632c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3633c5f7700bSGavin Shan int64_t rc; 3634c5f7700bSGavin Shan 3635c5f7700bSGavin Shan if (!weight) 3636c5f7700bSGavin Shan return; 3637c5f7700bSGavin Shan 3638c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3639c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3640c5f7700bSGavin Shan return; 3641c5f7700bSGavin Shan 3642a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3643c5f7700bSGavin Shan if (pe->table_group.group) { 3644c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3645c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3646c5f7700bSGavin Shan } 3647c5f7700bSGavin Shan 3648c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3649e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3650c5f7700bSGavin Shan } 3651c5f7700bSGavin Shan 3652c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3653c5f7700bSGavin Shan { 3654c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3655c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3656c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3657c5f7700bSGavin Shan int64_t rc; 3658c5f7700bSGavin Shan #endif 3659c5f7700bSGavin Shan 3660c5f7700bSGavin Shan if (!weight) 3661c5f7700bSGavin Shan return; 3662c5f7700bSGavin Shan 3663c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3664c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3665c5f7700bSGavin Shan if (rc) 3666c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3667c5f7700bSGavin Shan #endif 3668c5f7700bSGavin Shan 3669c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3670c5f7700bSGavin Shan if (pe->table_group.group) { 3671c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3672c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3673c5f7700bSGavin Shan } 3674c5f7700bSGavin Shan 3675e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3676c5f7700bSGavin Shan } 3677c5f7700bSGavin Shan 3678c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3679c5f7700bSGavin Shan unsigned short win, 3680c5f7700bSGavin Shan unsigned int *map) 3681c5f7700bSGavin Shan { 3682c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3683c5f7700bSGavin Shan int idx; 3684c5f7700bSGavin Shan int64_t rc; 3685c5f7700bSGavin Shan 3686c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3687c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3688c5f7700bSGavin Shan continue; 3689c5f7700bSGavin Shan 3690c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3691c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3692c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3693c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3694c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3695c5f7700bSGavin Shan else 3696c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3697c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3698c5f7700bSGavin Shan 3699c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3700c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3701c5f7700bSGavin Shan rc, win, idx); 3702c5f7700bSGavin Shan 3703c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3704c5f7700bSGavin Shan } 3705c5f7700bSGavin Shan } 3706c5f7700bSGavin Shan 3707c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3708c5f7700bSGavin Shan { 3709c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3710c5f7700bSGavin Shan 3711c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3712c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3713c5f7700bSGavin Shan phb->ioda.io_segmap); 3714c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3715c5f7700bSGavin Shan phb->ioda.m32_segmap); 3716c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3717c5f7700bSGavin Shan phb->ioda.m64_segmap); 3718c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3719c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3720c5f7700bSGavin Shan phb->ioda.m32_segmap); 3721c5f7700bSGavin Shan } 3722c5f7700bSGavin Shan } 3723c5f7700bSGavin Shan 3724c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3725c5f7700bSGavin Shan { 3726c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3727c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3728c5f7700bSGavin Shan 3729c5f7700bSGavin Shan list_del(&pe->list); 3730c5f7700bSGavin Shan switch (phb->type) { 3731c5f7700bSGavin Shan case PNV_PHB_IODA1: 3732c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3733c5f7700bSGavin Shan break; 3734c5f7700bSGavin Shan case PNV_PHB_IODA2: 3735c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3736c5f7700bSGavin Shan break; 3737c5f7700bSGavin Shan default: 3738c5f7700bSGavin Shan WARN_ON(1); 3739c5f7700bSGavin Shan } 3740c5f7700bSGavin Shan 3741c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3742c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3743b314427aSGavin Shan 3744b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3745b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3746b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3747b314427aSGavin Shan list_del(&slave->list); 3748b314427aSGavin Shan pnv_ioda_free_pe(slave); 3749b314427aSGavin Shan } 3750b314427aSGavin Shan } 3751b314427aSGavin Shan 37526eaed166SGavin Shan /* 37536eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 37546eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 37556eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 37566eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 37576eaed166SGavin Shan */ 37586eaed166SGavin Shan if (phb->ioda.root_pe_populated && 37596eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 37606eaed166SGavin Shan phb->ioda.root_pe_populated = false; 37616eaed166SGavin Shan else 3762c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3763c5f7700bSGavin Shan } 3764c5f7700bSGavin Shan 3765c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3766c5f7700bSGavin Shan { 3767c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3768c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3769c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3770c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3771c5f7700bSGavin Shan 3772c5f7700bSGavin Shan if (pdev->is_virtfn) 3773c5f7700bSGavin Shan return; 3774c5f7700bSGavin Shan 3775c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3776c5f7700bSGavin Shan return; 3777c5f7700bSGavin Shan 377829bf282dSGavin Shan /* 377929bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 378029bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 378129bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 378229bf282dSGavin Shan * device count is decreased on removing devices while failing to 378329bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 378429bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 378529bf282dSGavin Shan */ 3786c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 378729bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 378829bf282dSGavin Shan 3789c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3790c5f7700bSGavin Shan if (pe->device_count == 0) 3791c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3792c5f7700bSGavin Shan } 3793c5f7700bSGavin Shan 37947a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 379573ed148aSBenjamin Herrenschmidt { 37967a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 37977a8e6bbfSMichael Neuling 3798d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 379973ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 380073ed148aSBenjamin Herrenschmidt } 380173ed148aSBenjamin Herrenschmidt 380292ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 380392ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 38041bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 380592ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 380692ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 380792ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 380892ae0353SDaniel Axtens #endif 380992ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3810c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 381192ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3812ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 381392ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3814763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 381553522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 38167a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 381792ae0353SDaniel Axtens }; 381892ae0353SDaniel Axtens 3819f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3820f9f83456SAlexey Kardashevskiy { 3821f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3822f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3823f9f83456SAlexey Kardashevskiy __func__); 3824f9f83456SAlexey Kardashevskiy return -EPERM; 3825f9f83456SAlexey Kardashevskiy } 3826f9f83456SAlexey Kardashevskiy 38275d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 38285d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 38295d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 38305d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 38315d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 38325d2aa710SAlistair Popple #endif 38335d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 38345d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 38355d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 38365d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 38375d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 38385d2aa710SAlistair Popple }; 38395d2aa710SAlistair Popple 38407f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 38417f2c39e9SFrederic Barrat .enable_device_hook = pnv_pci_enable_device_hook, 38427f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 38437f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 38447f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 38457f2c39e9SFrederic Barrat }; 38467f2c39e9SFrederic Barrat 38474361b034SIan Munsie #ifdef CONFIG_CXL_BASE 38484361b034SIan Munsie const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 38494361b034SIan Munsie .dma_dev_setup = pnv_pci_dma_dev_setup, 38504361b034SIan Munsie .dma_bus_setup = pnv_pci_dma_bus_setup, 3851a2f67d5eSIan Munsie #ifdef CONFIG_PCI_MSI 3852a2f67d5eSIan Munsie .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3853a2f67d5eSIan Munsie .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3854a2f67d5eSIan Munsie #endif 38554361b034SIan Munsie .enable_device_hook = pnv_cxl_enable_device_hook, 38564361b034SIan Munsie .disable_device = pnv_cxl_disable_device, 38574361b034SIan Munsie .release_device = pnv_pci_release_device, 38584361b034SIan Munsie .window_alignment = pnv_pci_window_alignment, 38594361b034SIan Munsie .setup_bridge = pnv_pci_setup_bridge, 38604361b034SIan Munsie .reset_secondary_bus = pnv_pci_reset_secondary_bus, 38614361b034SIan Munsie .dma_set_mask = pnv_pci_ioda_dma_set_mask, 38624361b034SIan Munsie .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 38634361b034SIan Munsie .shutdown = pnv_pci_ioda_shutdown, 38644361b034SIan Munsie }; 38654361b034SIan Munsie #endif 38664361b034SIan Munsie 3867e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3868e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3869184cd4a3SBenjamin Herrenschmidt { 3870184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3871184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 38722b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 38732b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3874fd141d1aSBenjamin Herrenschmidt struct resource r; 3875c681b93cSAlistair Popple const __be64 *prop64; 38763a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3877f1b7cc3eSGavin Shan int len; 38783fa23ff8SGavin Shan unsigned int segno; 3879184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3880184cd4a3SBenjamin Herrenschmidt void *aux; 3881184cd4a3SBenjamin Herrenschmidt long rc; 3882184cd4a3SBenjamin Herrenschmidt 388308a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 388408a45b32SBenjamin Herrenschmidt return; 388508a45b32SBenjamin Herrenschmidt 3886b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3887184cd4a3SBenjamin Herrenschmidt 3888184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3889184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3890184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3891184cd4a3SBenjamin Herrenschmidt return; 3892184cd4a3SBenjamin Herrenschmidt } 3893184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3894184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3895184cd4a3SBenjamin Herrenschmidt 3896a0828cf5SMarkus Elfring phb = memblock_virt_alloc(sizeof(*phb), 0); 389758d714ecSGavin Shan 389858d714ecSGavin Shan /* Allocate PCI controller */ 3899184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 390058d714ecSGavin Shan if (!phb->hose) { 3901b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3902b7c670d6SRob Herring np); 3903e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3904184cd4a3SBenjamin Herrenschmidt return; 3905184cd4a3SBenjamin Herrenschmidt } 3906184cd4a3SBenjamin Herrenschmidt 3907184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3908f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3909f1b7cc3eSGavin Shan if (prop32 && len == 8) { 39103a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 39113a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3912f1b7cc3eSGavin Shan } else { 3913b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3914184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3915184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3916f1b7cc3eSGavin Shan } 3917184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3918e9cc17d4SGavin Shan phb->hub_id = hub_id; 3919184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3920aa0c033fSGavin Shan phb->type = ioda_type; 3921781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3922184cd4a3SBenjamin Herrenschmidt 3923cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3924cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3925cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3926f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3927aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 39285d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 39295d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3930616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3931616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3932cee72d5bSBenjamin Herrenschmidt else 3933cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3934cee72d5bSBenjamin Herrenschmidt 39355cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 39365cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 39375cb1f8fdSRussell Currey if (prop32) 39385cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 39395cb1f8fdSRussell Currey else 39405cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 39415cb1f8fdSRussell Currey 39425cb1f8fdSRussell Currey phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); 39435cb1f8fdSRussell Currey 3944aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 39452f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3946184cd4a3SBenjamin Herrenschmidt 3947aa0c033fSGavin Shan /* Get registers */ 3948fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3949fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3950fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3951184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3952184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3953fd141d1aSBenjamin Herrenschmidt } 3954577c8c88SGavin Shan 3955184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 395692b8f137SGavin Shan phb->ioda.total_pe_num = 1; 395736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 395836954dc7SGavin Shan if (prop32) 395992b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 396036954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 396136954dc7SGavin Shan if (prop32) 396292b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3963262af557SGuo Chao 3964c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3965c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3966c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3967c127562aSGavin Shan 3968262af557SGuo Chao /* Parse 64-bit MMIO range */ 3969262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3970262af557SGuo Chao 3971184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3972aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3973184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3974184cd4a3SBenjamin Herrenschmidt 397592b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 39763fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3977184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 397892b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3979184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3980184cd4a3SBenjamin Herrenschmidt 39812b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 39822b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 39832b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 39842b923ed1SGavin Shan 3985c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 398692a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 398792a86756SAlexey Kardashevskiy sizeof(unsigned long)); 398893289d8cSGavin Shan m64map_off = size; 398993289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3990184cd4a3SBenjamin Herrenschmidt m32map_off = size; 399192b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3992c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3993c35d2a8cSGavin Shan iomap_off = size; 399492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 39952b923ed1SGavin Shan dma32map_off = size; 39962b923ed1SGavin Shan size += phb->ioda.dma32_count * 39972b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3998c35d2a8cSGavin Shan } 3999184cd4a3SBenjamin Herrenschmidt pemap_off = size; 400092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 4001e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 4002184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 400393289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 4004184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 400593289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 400693289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 40073fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 400893289d8cSGavin Shan } 40093fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 4010184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 40113fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 40123fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 40132b923ed1SGavin Shan 40142b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 40152b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 40162b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 40173fa23ff8SGavin Shan } 4018184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 401963803c39SGavin Shan 402063803c39SGavin Shan /* 402163803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 402263803c39SGavin Shan * M64 resources consumed by its child devices. To pick 402363803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 402463803c39SGavin Shan */ 402563803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 402663803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 402763803c39SGavin Shan phb->ioda.root_pe_idx = 1; 402863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 402963803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 403063803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 403163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 403263803c39SGavin Shan } else { 403363803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 403463803c39SGavin Shan } 4035184cd4a3SBenjamin Herrenschmidt 4036184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 4037781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 4038184cd4a3SBenjamin Herrenschmidt 4039184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 40402b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 4041acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 4042184cd4a3SBenjamin Herrenschmidt 4043aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 4044184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 4045184cd4a3SBenjamin Herrenschmidt window_type, 4046184cd4a3SBenjamin Herrenschmidt window_num, 4047184cd4a3SBenjamin Herrenschmidt starting_real_address, 4048184cd4a3SBenjamin Herrenschmidt starting_pci_address, 4049184cd4a3SBenjamin Herrenschmidt segment_size); 4050184cd4a3SBenjamin Herrenschmidt #endif 4051184cd4a3SBenjamin Herrenschmidt 4052262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 405392b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 4054262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 4055262af557SGuo Chao if (phb->ioda.m64_size) 4056262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 4057262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 4058262af557SGuo Chao if (phb->ioda.io_size) 4059262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 4060184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 4061184cd4a3SBenjamin Herrenschmidt 4062262af557SGuo Chao 4063184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 406449dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 406549dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 406649dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 4067184cd4a3SBenjamin Herrenschmidt 4068184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 4069184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 4070184cd4a3SBenjamin Herrenschmidt 4071c40a4210SGavin Shan /* 4072c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 4073c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 4074c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 4075c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 4076c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 4077184cd4a3SBenjamin Herrenschmidt */ 4078fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 40795d2aa710SAlistair Popple 40807f2c39e9SFrederic Barrat switch (phb->type) { 40817f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 40825d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 40837f2c39e9SFrederic Barrat break; 40847f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 40857f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 40867f2c39e9SFrederic Barrat break; 40877f2c39e9SFrederic Barrat default: 4088f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 408992ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 4090f9f83456SAlexey Kardashevskiy } 4091ad30cb99SMichael Ellerman 409238274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 409338274637SYongji Xie 40946e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 40956e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 40965350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 4097988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 4098988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 4099ad30cb99SMichael Ellerman #endif 4100ad30cb99SMichael Ellerman 4101c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 4102184cd4a3SBenjamin Herrenschmidt 4103184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 4104d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 4105184cd4a3SBenjamin Herrenschmidt if (rc) 4106f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 4107361f2a2aSGavin Shan 41086060e9eaSAndrew Donnellan /* 41096060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 4110361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 4111361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 411245baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 411345baee14SGuilherme G. Piccoli * kernel parameter will force this reset too. 4114361f2a2aSGavin Shan */ 411545baee14SGuilherme G. Piccoli if (is_kdump_kernel() || pci_reset_phbs) { 4116361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 4117cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 4118cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 4119361f2a2aSGavin Shan } 4120262af557SGuo Chao 41219e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 41229e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 4123262af557SGuo Chao hose->mem_resources[1].flags = 0; 4124184cd4a3SBenjamin Herrenschmidt } 4125184cd4a3SBenjamin Herrenschmidt 412667975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4127aa0c033fSGavin Shan { 4128e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4129aa0c033fSGavin Shan } 4130aa0c033fSGavin Shan 41315d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 41325d2aa710SAlistair Popple { 41337f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 41345d2aa710SAlistair Popple } 41355d2aa710SAlistair Popple 41367f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 41377f2c39e9SFrederic Barrat { 41387f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 4139184cd4a3SBenjamin Herrenschmidt } 4140184cd4a3SBenjamin Herrenschmidt 4141228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 4142228c2f41SAndrew Donnellan { 4143228c2f41SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(dev->bus); 4144228c2f41SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 4145228c2f41SAndrew Donnellan 4146228c2f41SAndrew Donnellan if (!machine_is(powernv)) 4147228c2f41SAndrew Donnellan return; 4148228c2f41SAndrew Donnellan 4149228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 4150228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4151228c2f41SAndrew Donnellan } 4152228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 4153228c2f41SAndrew Donnellan 4154184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 4155184cd4a3SBenjamin Herrenschmidt { 4156184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 4157184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 4158184cd4a3SBenjamin Herrenschmidt u64 hub_id; 4159184cd4a3SBenjamin Herrenschmidt 4160b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 4161184cd4a3SBenjamin Herrenschmidt 4162184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4163184cd4a3SBenjamin Herrenschmidt if (!prop64) { 4164184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4165184cd4a3SBenjamin Herrenschmidt return; 4166184cd4a3SBenjamin Herrenschmidt } 4167184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 4168184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4169184cd4a3SBenjamin Herrenschmidt 4170184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 4171184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 4172184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 4173184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4174184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4175184cd4a3SBenjamin Herrenschmidt } 4176184cd4a3SBenjamin Herrenschmidt } 4177