1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 35184cd4a3SBenjamin Herrenschmidt 36184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 37184cd4a3SBenjamin Herrenschmidt #include "pci.h" 38184cd4a3SBenjamin Herrenschmidt 39184cd4a3SBenjamin Herrenschmidt #define define_pe_printk_level(func, kern_level) \ 40184cd4a3SBenjamin Herrenschmidt static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ 41184cd4a3SBenjamin Herrenschmidt { \ 42184cd4a3SBenjamin Herrenschmidt struct va_format vaf; \ 43184cd4a3SBenjamin Herrenschmidt va_list args; \ 44490e078dSGavin Shan char pfix[32]; \ 45184cd4a3SBenjamin Herrenschmidt int r; \ 46184cd4a3SBenjamin Herrenschmidt \ 47184cd4a3SBenjamin Herrenschmidt va_start(args, fmt); \ 48184cd4a3SBenjamin Herrenschmidt \ 49184cd4a3SBenjamin Herrenschmidt vaf.fmt = fmt; \ 50184cd4a3SBenjamin Herrenschmidt vaf.va = &args; \ 51184cd4a3SBenjamin Herrenschmidt \ 52490e078dSGavin Shan if (pe->pdev) \ 53490e078dSGavin Shan strlcpy(pfix, dev_name(&pe->pdev->dev), \ 54490e078dSGavin Shan sizeof(pfix)); \ 55490e078dSGavin Shan else \ 56490e078dSGavin Shan sprintf(pfix, "%04x:%02x ", \ 57490e078dSGavin Shan pci_domain_nr(pe->pbus), \ 58490e078dSGavin Shan pe->pbus->number); \ 59490e078dSGavin Shan r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ 60490e078dSGavin Shan pfix, pe->pe_number, &vaf); \ 61490e078dSGavin Shan \ 62184cd4a3SBenjamin Herrenschmidt va_end(args); \ 63184cd4a3SBenjamin Herrenschmidt \ 64184cd4a3SBenjamin Herrenschmidt return r; \ 65184cd4a3SBenjamin Herrenschmidt } \ 66184cd4a3SBenjamin Herrenschmidt 67184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_err, KERN_ERR); 68184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_warn, KERN_WARNING); 69184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_info, KERN_INFO); 70184cd4a3SBenjamin Herrenschmidt 71184cd4a3SBenjamin Herrenschmidt static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev) 72184cd4a3SBenjamin Herrenschmidt { 73184cd4a3SBenjamin Herrenschmidt struct device_node *np; 74184cd4a3SBenjamin Herrenschmidt 75184cd4a3SBenjamin Herrenschmidt np = pci_device_to_OF_node(dev); 76184cd4a3SBenjamin Herrenschmidt if (!np) 77184cd4a3SBenjamin Herrenschmidt return NULL; 78184cd4a3SBenjamin Herrenschmidt return PCI_DN(np); 79184cd4a3SBenjamin Herrenschmidt } 80184cd4a3SBenjamin Herrenschmidt 81cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 82184cd4a3SBenjamin Herrenschmidt { 83184cd4a3SBenjamin Herrenschmidt unsigned long pe; 84184cd4a3SBenjamin Herrenschmidt 85184cd4a3SBenjamin Herrenschmidt do { 86184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 87184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 88184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 89184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 90184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 91184cd4a3SBenjamin Herrenschmidt 924cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 93184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 94184cd4a3SBenjamin Herrenschmidt return pe; 95184cd4a3SBenjamin Herrenschmidt } 96184cd4a3SBenjamin Herrenschmidt 97cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 98184cd4a3SBenjamin Herrenschmidt { 99184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 100184cd4a3SBenjamin Herrenschmidt 101184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 102184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 103184cd4a3SBenjamin Herrenschmidt } 104184cd4a3SBenjamin Herrenschmidt 105184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 106184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 107184cd4a3SBenjamin Herrenschmidt */ 108184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 109cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 110184cd4a3SBenjamin Herrenschmidt { 111184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 112184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 113184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 114184cd4a3SBenjamin Herrenschmidt 115184cd4a3SBenjamin Herrenschmidt if (!pdn) 116184cd4a3SBenjamin Herrenschmidt return NULL; 117184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 118184cd4a3SBenjamin Herrenschmidt return NULL; 119184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 120184cd4a3SBenjamin Herrenschmidt } 121184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 122184cd4a3SBenjamin Herrenschmidt 123cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 124184cd4a3SBenjamin Herrenschmidt { 125184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 126184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 127184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 128184cd4a3SBenjamin Herrenschmidt 129184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 130184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 131184cd4a3SBenjamin Herrenschmidt int count; 132184cd4a3SBenjamin Herrenschmidt 133184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 134184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 135184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 136fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 137b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 138fb446ad0SGavin Shan else 139fb446ad0SGavin Shan count = 1; 140fb446ad0SGavin Shan 141184cd4a3SBenjamin Herrenschmidt switch(count) { 142184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 143184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 144184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 145184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 146184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 147184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 148184cd4a3SBenjamin Herrenschmidt default: 149184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 150184cd4a3SBenjamin Herrenschmidt " unsupported\n", 151184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 152184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 153184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 154184cd4a3SBenjamin Herrenschmidt } 155184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 156184cd4a3SBenjamin Herrenschmidt } else { 157184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 158184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 159184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 160184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 161184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 162184cd4a3SBenjamin Herrenschmidt } 163184cd4a3SBenjamin Herrenschmidt 164184cd4a3SBenjamin Herrenschmidt /* Associate PE in PELT */ 165184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 166184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 167184cd4a3SBenjamin Herrenschmidt if (rc) { 168184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 169184cd4a3SBenjamin Herrenschmidt return -ENXIO; 170184cd4a3SBenjamin Herrenschmidt } 171184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 172184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 173184cd4a3SBenjamin Herrenschmidt 174184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 175184cd4a3SBenjamin Herrenschmidt while (parent) { 176184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(parent); 177184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 178184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 179cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 180184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 181184cd4a3SBenjamin Herrenschmidt } 182184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 183184cd4a3SBenjamin Herrenschmidt } 184184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 185184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 186184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 187184cd4a3SBenjamin Herrenschmidt 188184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 189184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 190184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 191184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 192184cd4a3SBenjamin Herrenschmidt pe->pe_number); 193184cd4a3SBenjamin Herrenschmidt if (rc) { 194184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 195184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 196184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 197184cd4a3SBenjamin Herrenschmidt } else { 198184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 199cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 200184cd4a3SBenjamin Herrenschmidt if (rc) { 201184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 202184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 203184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 204184cd4a3SBenjamin Herrenschmidt } 205184cd4a3SBenjamin Herrenschmidt } 206184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 207184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 208184cd4a3SBenjamin Herrenschmidt 209184cd4a3SBenjamin Herrenschmidt return 0; 210184cd4a3SBenjamin Herrenschmidt } 211184cd4a3SBenjamin Herrenschmidt 212cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 213184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 214184cd4a3SBenjamin Herrenschmidt { 215184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 216184cd4a3SBenjamin Herrenschmidt 2177ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 218184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 2197ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 220184cd4a3SBenjamin Herrenschmidt return; 221184cd4a3SBenjamin Herrenschmidt } 222184cd4a3SBenjamin Herrenschmidt } 2237ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 224184cd4a3SBenjamin Herrenschmidt } 225184cd4a3SBenjamin Herrenschmidt 226184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 227184cd4a3SBenjamin Herrenschmidt { 228184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 229184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 230184cd4a3SBenjamin Herrenschmidt */ 231184cd4a3SBenjamin Herrenschmidt 232184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 233184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 234184cd4a3SBenjamin Herrenschmidt return 0; 235184cd4a3SBenjamin Herrenschmidt 236184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 237184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 238184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 239184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 240184cd4a3SBenjamin Herrenschmidt return 3; 241184cd4a3SBenjamin Herrenschmidt 242184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 243184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 244184cd4a3SBenjamin Herrenschmidt return 15; 245184cd4a3SBenjamin Herrenschmidt 246184cd4a3SBenjamin Herrenschmidt /* Default */ 247184cd4a3SBenjamin Herrenschmidt return 10; 248184cd4a3SBenjamin Herrenschmidt } 249184cd4a3SBenjamin Herrenschmidt 250fb446ad0SGavin Shan #if 0 251cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 252184cd4a3SBenjamin Herrenschmidt { 253184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 254184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 255184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 256184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 257184cd4a3SBenjamin Herrenschmidt int pe_num; 258184cd4a3SBenjamin Herrenschmidt 259184cd4a3SBenjamin Herrenschmidt if (!pdn) { 260184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 261184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 262184cd4a3SBenjamin Herrenschmidt return NULL; 263184cd4a3SBenjamin Herrenschmidt } 264184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 265184cd4a3SBenjamin Herrenschmidt return NULL; 266184cd4a3SBenjamin Herrenschmidt 267184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 268184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 269184cd4a3SBenjamin Herrenschmidt pe_num = 0; 270184cd4a3SBenjamin Herrenschmidt else 271184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 272184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 273184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 274184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 275184cd4a3SBenjamin Herrenschmidt return NULL; 276184cd4a3SBenjamin Herrenschmidt } 277184cd4a3SBenjamin Herrenschmidt 278184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 279184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 280184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 281184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 282184cd4a3SBenjamin Herrenschmidt * 283184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 284184cd4a3SBenjamin Herrenschmidt */ 285184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 286184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 287184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 288184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 289184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 290184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 291184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 292184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 293184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 294184cd4a3SBenjamin Herrenschmidt 295184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 296184cd4a3SBenjamin Herrenschmidt 297184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 298184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 299184cd4a3SBenjamin Herrenschmidt if (pe_num) 300184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 301184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 302184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 303184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 304184cd4a3SBenjamin Herrenschmidt return NULL; 305184cd4a3SBenjamin Herrenschmidt } 306184cd4a3SBenjamin Herrenschmidt 307184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 308184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 309184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 310184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 311184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 312184cd4a3SBenjamin Herrenschmidt } 313184cd4a3SBenjamin Herrenschmidt 314184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 315184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 316184cd4a3SBenjamin Herrenschmidt 317184cd4a3SBenjamin Herrenschmidt return pe; 318184cd4a3SBenjamin Herrenschmidt } 319fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 320184cd4a3SBenjamin Herrenschmidt 321184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 322184cd4a3SBenjamin Herrenschmidt { 323184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 324184cd4a3SBenjamin Herrenschmidt 325184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 326184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 327184cd4a3SBenjamin Herrenschmidt 328184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 329184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 330184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 331184cd4a3SBenjamin Herrenschmidt continue; 332184cd4a3SBenjamin Herrenschmidt } 333184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 334184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 335184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 336184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 337fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 338184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 339184cd4a3SBenjamin Herrenschmidt } 340184cd4a3SBenjamin Herrenschmidt } 341184cd4a3SBenjamin Herrenschmidt 342fb446ad0SGavin Shan /* 343fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 344fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 345fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 346fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 347fb446ad0SGavin Shan */ 348cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 349184cd4a3SBenjamin Herrenschmidt { 350fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 351184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 352184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 353184cd4a3SBenjamin Herrenschmidt int pe_num; 354184cd4a3SBenjamin Herrenschmidt 355184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 356184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 357fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 358fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 359184cd4a3SBenjamin Herrenschmidt return; 360184cd4a3SBenjamin Herrenschmidt } 361184cd4a3SBenjamin Herrenschmidt 362184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 363fb446ad0SGavin Shan pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 364184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 365184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 366184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 367184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 368b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 369184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 370184cd4a3SBenjamin Herrenschmidt 371fb446ad0SGavin Shan if (all) 372fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 373fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 374fb446ad0SGavin Shan else 375fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 376fb446ad0SGavin Shan bus->busn_res.start, pe_num); 377184cd4a3SBenjamin Herrenschmidt 378184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 379184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 380184cd4a3SBenjamin Herrenschmidt if (pe_num) 381184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 382184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 383184cd4a3SBenjamin Herrenschmidt return; 384184cd4a3SBenjamin Herrenschmidt } 385184cd4a3SBenjamin Herrenschmidt 386184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 387184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 388184cd4a3SBenjamin Herrenschmidt 3897ebdf956SGavin Shan /* Put PE to the list */ 3907ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 3917ebdf956SGavin Shan 392184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 393184cd4a3SBenjamin Herrenschmidt * below the bridge 394184cd4a3SBenjamin Herrenschmidt */ 395184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 396184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 397184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 398184cd4a3SBenjamin Herrenschmidt } 399184cd4a3SBenjamin Herrenschmidt 400184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 401184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 402184cd4a3SBenjamin Herrenschmidt } 403184cd4a3SBenjamin Herrenschmidt 404cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 405184cd4a3SBenjamin Herrenschmidt { 406184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 407fb446ad0SGavin Shan 408fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 409184cd4a3SBenjamin Herrenschmidt 410184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 411fb446ad0SGavin Shan if (dev->subordinate) { 41262f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 413fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 414fb446ad0SGavin Shan else 415184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 416184cd4a3SBenjamin Herrenschmidt } 417184cd4a3SBenjamin Herrenschmidt } 418fb446ad0SGavin Shan } 419fb446ad0SGavin Shan 420fb446ad0SGavin Shan /* 421fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 422fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 423fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 424fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 425fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 426fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 427fb446ad0SGavin Shan */ 428cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 429fb446ad0SGavin Shan { 430fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 431fb446ad0SGavin Shan 432fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 433fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 434fb446ad0SGavin Shan } 435fb446ad0SGavin Shan } 436184cd4a3SBenjamin Herrenschmidt 437959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 438184cd4a3SBenjamin Herrenschmidt { 439959c9bddSGavin Shan struct pci_dn *pdn = pnv_ioda_get_pdn(pdev); 440959c9bddSGavin Shan struct pnv_ioda_pe *pe; 441184cd4a3SBenjamin Herrenschmidt 442959c9bddSGavin Shan /* 443959c9bddSGavin Shan * The function can be called while the PE# 444959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 445959c9bddSGavin Shan * case. 446959c9bddSGavin Shan */ 447959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 448959c9bddSGavin Shan return; 449184cd4a3SBenjamin Herrenschmidt 450959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 451959c9bddSGavin Shan set_iommu_table_base(&pdev->dev, &pe->tce32_table); 452184cd4a3SBenjamin Herrenschmidt } 453184cd4a3SBenjamin Herrenschmidt 4544cce9550SGavin Shan static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 4554cce9550SGavin Shan u64 *startp, u64 *endp) 4564cce9550SGavin Shan { 4574cce9550SGavin Shan u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; 4584cce9550SGavin Shan unsigned long start, end, inc; 4594cce9550SGavin Shan 4604cce9550SGavin Shan start = __pa(startp); 4614cce9550SGavin Shan end = __pa(endp); 4624cce9550SGavin Shan 4634cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 4644cce9550SGavin Shan if (tbl->it_busno) { 4654cce9550SGavin Shan start <<= 12; 4664cce9550SGavin Shan end <<= 12; 4674cce9550SGavin Shan inc = 128 << 12; 4684cce9550SGavin Shan start |= tbl->it_busno; 4694cce9550SGavin Shan end |= tbl->it_busno; 4704cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 4714cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 4724cce9550SGavin Shan start |= (1ull << 63); 4734cce9550SGavin Shan end |= (1ull << 63); 4744cce9550SGavin Shan inc = 16; 4754cce9550SGavin Shan } else { 4764cce9550SGavin Shan /* Default (older HW) */ 4774cce9550SGavin Shan inc = 128; 4784cce9550SGavin Shan } 4794cce9550SGavin Shan 4804cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 4814cce9550SGavin Shan 4824cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 4834cce9550SGavin Shan while (start <= end) { 4844cce9550SGavin Shan __raw_writeq(start, invalidate); 4854cce9550SGavin Shan start += inc; 4864cce9550SGavin Shan } 4874cce9550SGavin Shan 4884cce9550SGavin Shan /* 4894cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 4904cce9550SGavin Shan * and we don't care on free() 4914cce9550SGavin Shan */ 4924cce9550SGavin Shan } 4934cce9550SGavin Shan 4944cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 4954cce9550SGavin Shan struct iommu_table *tbl, 4964cce9550SGavin Shan u64 *startp, u64 *endp) 4974cce9550SGavin Shan { 4984cce9550SGavin Shan unsigned long start, end, inc; 4994cce9550SGavin Shan u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; 5004cce9550SGavin Shan 5014cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 5024cce9550SGavin Shan start = 0x2ul << 60; 5034cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 5044cce9550SGavin Shan end = start; 5054cce9550SGavin Shan 5064cce9550SGavin Shan /* Figure out the start, end and step */ 5074cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 5084cce9550SGavin Shan start |= (inc << 12); 5094cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 5104cce9550SGavin Shan end |= (inc << 12); 5114cce9550SGavin Shan inc = (0x1ul << 12); 5124cce9550SGavin Shan mb(); 5134cce9550SGavin Shan 5144cce9550SGavin Shan while (start <= end) { 5154cce9550SGavin Shan __raw_writeq(start, invalidate); 5164cce9550SGavin Shan start += inc; 5174cce9550SGavin Shan } 5184cce9550SGavin Shan } 5194cce9550SGavin Shan 5204cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 5214cce9550SGavin Shan u64 *startp, u64 *endp) 5224cce9550SGavin Shan { 5234cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 5244cce9550SGavin Shan tce32_table); 5254cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 5264cce9550SGavin Shan 5274cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 5284cce9550SGavin Shan pnv_pci_ioda1_tce_invalidate(tbl, startp, endp); 5294cce9550SGavin Shan else 5304cce9550SGavin Shan pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp); 5314cce9550SGavin Shan } 5324cce9550SGavin Shan 533cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 534cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 535184cd4a3SBenjamin Herrenschmidt unsigned int segs) 536184cd4a3SBenjamin Herrenschmidt { 537184cd4a3SBenjamin Herrenschmidt 538184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 539184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 540184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 541184cd4a3SBenjamin Herrenschmidt unsigned int i; 542184cd4a3SBenjamin Herrenschmidt int64_t rc; 543184cd4a3SBenjamin Herrenschmidt void *addr; 544184cd4a3SBenjamin Herrenschmidt 545184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 546184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 547184cd4a3SBenjamin Herrenschmidt 548184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 549184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 550184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 551184cd4a3SBenjamin Herrenschmidt 552184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 553184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 554184cd4a3SBenjamin Herrenschmidt return; 555184cd4a3SBenjamin Herrenschmidt 556184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 557184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 558184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 559184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 560184cd4a3SBenjamin Herrenschmidt 561184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 562184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 563184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 564184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 565184cd4a3SBenjamin Herrenschmidt */ 566184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 567184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 568184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 569184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 570184cd4a3SBenjamin Herrenschmidt goto fail; 571184cd4a3SBenjamin Herrenschmidt } 572184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 573184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 574184cd4a3SBenjamin Herrenschmidt 575184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 576184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 577184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 578184cd4a3SBenjamin Herrenschmidt pe->pe_number, 579184cd4a3SBenjamin Herrenschmidt base + i, 1, 580184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 581184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 582184cd4a3SBenjamin Herrenschmidt if (rc) { 583184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 584184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 585184cd4a3SBenjamin Herrenschmidt goto fail; 586184cd4a3SBenjamin Herrenschmidt } 587184cd4a3SBenjamin Herrenschmidt } 588184cd4a3SBenjamin Herrenschmidt 589184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 590184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 591184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 592184cd4a3SBenjamin Herrenschmidt base << 28); 593184cd4a3SBenjamin Herrenschmidt 594184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 595184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 596184cd4a3SBenjamin Herrenschmidt if (swinvp) { 597184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 598184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 599184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 600184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 601184cd4a3SBenjamin Herrenschmidt */ 602184cd4a3SBenjamin Herrenschmidt tbl->it_busno = 0; 603184cd4a3SBenjamin Herrenschmidt tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 604373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE | 605373f5657SGavin Shan TCE_PCI_SWINV_PAIR; 606184cd4a3SBenjamin Herrenschmidt } 607184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 608184cd4a3SBenjamin Herrenschmidt 609184cd4a3SBenjamin Herrenschmidt return; 610184cd4a3SBenjamin Herrenschmidt fail: 611184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 612184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 613184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 614184cd4a3SBenjamin Herrenschmidt if (tce_mem) 615184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 616184cd4a3SBenjamin Herrenschmidt } 617184cd4a3SBenjamin Herrenschmidt 618373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 619373f5657SGavin Shan struct pnv_ioda_pe *pe) 620373f5657SGavin Shan { 621373f5657SGavin Shan struct page *tce_mem = NULL; 622373f5657SGavin Shan void *addr; 623373f5657SGavin Shan const __be64 *swinvp; 624373f5657SGavin Shan struct iommu_table *tbl; 625373f5657SGavin Shan unsigned int tce_table_size, end; 626373f5657SGavin Shan int64_t rc; 627373f5657SGavin Shan 628373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 629373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 630373f5657SGavin Shan return; 631373f5657SGavin Shan 632373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 633373f5657SGavin Shan pe->tce32_seg = 0; 634373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 635373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 636373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 637373f5657SGavin Shan end); 638373f5657SGavin Shan 639373f5657SGavin Shan /* Allocate TCE table */ 640373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 641373f5657SGavin Shan get_order(tce_table_size)); 642373f5657SGavin Shan if (!tce_mem) { 643373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 644373f5657SGavin Shan goto fail; 645373f5657SGavin Shan } 646373f5657SGavin Shan addr = page_address(tce_mem); 647373f5657SGavin Shan memset(addr, 0, tce_table_size); 648373f5657SGavin Shan 649373f5657SGavin Shan /* 650373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 651373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 652373f5657SGavin Shan */ 653373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 654373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 655373f5657SGavin Shan tce_table_size, 0x1000); 656373f5657SGavin Shan if (rc) { 657373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 658373f5657SGavin Shan " err %ld\n", rc); 659373f5657SGavin Shan goto fail; 660373f5657SGavin Shan } 661373f5657SGavin Shan 662373f5657SGavin Shan /* Setup linux iommu table */ 663373f5657SGavin Shan tbl = &pe->tce32_table; 664373f5657SGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0); 665373f5657SGavin Shan 666373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 667373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 668373f5657SGavin Shan if (swinvp) { 669373f5657SGavin Shan /* We need a couple more fields -- an address and a data 670373f5657SGavin Shan * to or. Since the bus is only printed out on table free 671373f5657SGavin Shan * errors, and on the first pass the data will be a relative 672373f5657SGavin Shan * bus number, print that out instead. 673373f5657SGavin Shan */ 674373f5657SGavin Shan tbl->it_busno = 0; 675373f5657SGavin Shan tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 676373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; 677373f5657SGavin Shan } 678373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 679373f5657SGavin Shan 680373f5657SGavin Shan return; 681373f5657SGavin Shan fail: 682373f5657SGavin Shan if (pe->tce32_seg >= 0) 683373f5657SGavin Shan pe->tce32_seg = -1; 684373f5657SGavin Shan if (tce_mem) 685373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 686373f5657SGavin Shan } 687373f5657SGavin Shan 688cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 689184cd4a3SBenjamin Herrenschmidt { 690184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 691184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 692184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 693184cd4a3SBenjamin Herrenschmidt 694184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 695184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 696184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 697184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 698184cd4a3SBenjamin Herrenschmidt */ 699184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 700184cd4a3SBenjamin Herrenschmidt residual = 0; 701184cd4a3SBenjamin Herrenschmidt else 702184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 703184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 704184cd4a3SBenjamin Herrenschmidt 705184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 706184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 707184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 708184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 709184cd4a3SBenjamin Herrenschmidt 710184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 711184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 712184cd4a3SBenjamin Herrenschmidt * weight 713184cd4a3SBenjamin Herrenschmidt */ 714184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 715184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 716184cd4a3SBenjamin Herrenschmidt base = 0; 7177ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 718184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 719184cd4a3SBenjamin Herrenschmidt continue; 720184cd4a3SBenjamin Herrenschmidt if (!remaining) { 721184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 722184cd4a3SBenjamin Herrenschmidt continue; 723184cd4a3SBenjamin Herrenschmidt } 724184cd4a3SBenjamin Herrenschmidt segs = 1; 725184cd4a3SBenjamin Herrenschmidt if (residual) { 726184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 727184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 728184cd4a3SBenjamin Herrenschmidt segs = remaining; 729184cd4a3SBenjamin Herrenschmidt } 730373f5657SGavin Shan 731373f5657SGavin Shan /* 732373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 733373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 734373f5657SGavin Shan * the specific PE. 735373f5657SGavin Shan */ 736373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 737184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 738184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 739184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 740373f5657SGavin Shan } else { 741373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 742373f5657SGavin Shan segs = 0; 743373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 744373f5657SGavin Shan } 745373f5657SGavin Shan 746184cd4a3SBenjamin Herrenschmidt remaining -= segs; 747184cd4a3SBenjamin Herrenschmidt base += segs; 748184cd4a3SBenjamin Herrenschmidt } 749184cd4a3SBenjamin Herrenschmidt } 750184cd4a3SBenjamin Herrenschmidt 751184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 752137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 753137436c9SGavin Shan { 754137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 755137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 756137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 757137436c9SGavin Shan ioda.irq_chip); 758137436c9SGavin Shan int64_t rc; 759137436c9SGavin Shan 760137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 761137436c9SGavin Shan WARN_ON_ONCE(rc); 762137436c9SGavin Shan 763137436c9SGavin Shan icp_native_eoi(d); 764137436c9SGavin Shan } 765137436c9SGavin Shan 766184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 767137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 768137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 769184cd4a3SBenjamin Herrenschmidt { 770184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 771137436c9SGavin Shan struct irq_data *idata; 772137436c9SGavin Shan struct irq_chip *ichip; 773184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 774184cd4a3SBenjamin Herrenschmidt uint64_t addr64; 775184cd4a3SBenjamin Herrenschmidt uint32_t addr32, data; 776184cd4a3SBenjamin Herrenschmidt int rc; 777184cd4a3SBenjamin Herrenschmidt 778184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 779184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 780184cd4a3SBenjamin Herrenschmidt return -ENXIO; 781184cd4a3SBenjamin Herrenschmidt 782184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 783184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 784184cd4a3SBenjamin Herrenschmidt return -ENXIO; 785184cd4a3SBenjamin Herrenschmidt 786184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 787184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 788184cd4a3SBenjamin Herrenschmidt if (rc) { 789184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 790184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 791184cd4a3SBenjamin Herrenschmidt return -EIO; 792184cd4a3SBenjamin Herrenschmidt } 793184cd4a3SBenjamin Herrenschmidt 794184cd4a3SBenjamin Herrenschmidt if (is_64) { 795184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 796184cd4a3SBenjamin Herrenschmidt &addr64, &data); 797184cd4a3SBenjamin Herrenschmidt if (rc) { 798184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 799184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 800184cd4a3SBenjamin Herrenschmidt return -EIO; 801184cd4a3SBenjamin Herrenschmidt } 802184cd4a3SBenjamin Herrenschmidt msg->address_hi = addr64 >> 32; 803184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr64 & 0xfffffffful; 804184cd4a3SBenjamin Herrenschmidt } else { 805184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 806184cd4a3SBenjamin Herrenschmidt &addr32, &data); 807184cd4a3SBenjamin Herrenschmidt if (rc) { 808184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 809184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 810184cd4a3SBenjamin Herrenschmidt return -EIO; 811184cd4a3SBenjamin Herrenschmidt } 812184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 813184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr32; 814184cd4a3SBenjamin Herrenschmidt } 815184cd4a3SBenjamin Herrenschmidt msg->data = data; 816184cd4a3SBenjamin Herrenschmidt 817137436c9SGavin Shan /* 818137436c9SGavin Shan * Change the IRQ chip for the MSI interrupts on PHB3. 819137436c9SGavin Shan * The corresponding IRQ chip should be populated for 820137436c9SGavin Shan * the first time. 821137436c9SGavin Shan */ 822137436c9SGavin Shan if (phb->type == PNV_PHB_IODA2) { 823137436c9SGavin Shan if (!phb->ioda.irq_chip_init) { 824137436c9SGavin Shan idata = irq_get_irq_data(virq); 825137436c9SGavin Shan ichip = irq_data_get_irq_chip(idata); 826137436c9SGavin Shan phb->ioda.irq_chip_init = 1; 827137436c9SGavin Shan phb->ioda.irq_chip = *ichip; 828137436c9SGavin Shan phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 829137436c9SGavin Shan } 830137436c9SGavin Shan 831137436c9SGavin Shan irq_set_chip(virq, &phb->ioda.irq_chip); 832137436c9SGavin Shan } 833137436c9SGavin Shan 834184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 835184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 836184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 837184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 838184cd4a3SBenjamin Herrenschmidt 839184cd4a3SBenjamin Herrenschmidt return 0; 840184cd4a3SBenjamin Herrenschmidt } 841184cd4a3SBenjamin Herrenschmidt 842184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 843184cd4a3SBenjamin Herrenschmidt { 844fb1b55d6SGavin Shan unsigned int count; 845184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 846184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 847184cd4a3SBenjamin Herrenschmidt if (!prop) { 848184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 849184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 850184cd4a3SBenjamin Herrenschmidt } 851184cd4a3SBenjamin Herrenschmidt if (!prop) 852184cd4a3SBenjamin Herrenschmidt return; 853184cd4a3SBenjamin Herrenschmidt 854184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 855fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 856fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 857184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 858184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 859184cd4a3SBenjamin Herrenschmidt return; 860184cd4a3SBenjamin Herrenschmidt } 861fb1b55d6SGavin Shan 862184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 863184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 864184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 865fb1b55d6SGavin Shan count, phb->msi_base); 866184cd4a3SBenjamin Herrenschmidt } 867184cd4a3SBenjamin Herrenschmidt #else 868184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 869184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 870184cd4a3SBenjamin Herrenschmidt 87111685becSGavin Shan /* 87211685becSGavin Shan * This function is supposed to be called on basis of PE from top 87311685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 87411685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 87511685becSGavin Shan */ 876cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 87711685becSGavin Shan struct pnv_ioda_pe *pe) 87811685becSGavin Shan { 87911685becSGavin Shan struct pnv_phb *phb = hose->private_data; 88011685becSGavin Shan struct pci_bus_region region; 88111685becSGavin Shan struct resource *res; 88211685becSGavin Shan int i, index; 88311685becSGavin Shan int rc; 88411685becSGavin Shan 88511685becSGavin Shan /* 88611685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 88711685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 88811685becSGavin Shan * be figured out later. 88911685becSGavin Shan */ 89011685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 89111685becSGavin Shan 89211685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 89311685becSGavin Shan if (!res || !res->flags || 89411685becSGavin Shan res->start > res->end) 89511685becSGavin Shan continue; 89611685becSGavin Shan 89711685becSGavin Shan if (res->flags & IORESOURCE_IO) { 89811685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 89911685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 90011685becSGavin Shan index = region.start / phb->ioda.io_segsize; 90111685becSGavin Shan 90211685becSGavin Shan while (index < phb->ioda.total_pe && 90311685becSGavin Shan region.start <= region.end) { 90411685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 90511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 90611685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 90711685becSGavin Shan if (rc != OPAL_SUCCESS) { 90811685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 90911685becSGavin Shan "segment #%d to PE#%d\n", 91011685becSGavin Shan __func__, rc, index, pe->pe_number); 91111685becSGavin Shan break; 91211685becSGavin Shan } 91311685becSGavin Shan 91411685becSGavin Shan region.start += phb->ioda.io_segsize; 91511685becSGavin Shan index++; 91611685becSGavin Shan } 91711685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 9183fd47f06SBenjamin Herrenschmidt /* WARNING: Assumes M32 is mem region 0 in PHB. We need to 9193fd47f06SBenjamin Herrenschmidt * harden that algorithm when we start supporting M64 9203fd47f06SBenjamin Herrenschmidt */ 92111685becSGavin Shan region.start = res->start - 9223fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 92311685becSGavin Shan phb->ioda.m32_pci_base; 92411685becSGavin Shan region.end = res->end - 9253fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 92611685becSGavin Shan phb->ioda.m32_pci_base; 92711685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 92811685becSGavin Shan 92911685becSGavin Shan while (index < phb->ioda.total_pe && 93011685becSGavin Shan region.start <= region.end) { 93111685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 93211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 93311685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 93411685becSGavin Shan if (rc != OPAL_SUCCESS) { 93511685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 93611685becSGavin Shan "segment#%d to PE#%d", 93711685becSGavin Shan __func__, rc, index, pe->pe_number); 93811685becSGavin Shan break; 93911685becSGavin Shan } 94011685becSGavin Shan 94111685becSGavin Shan region.start += phb->ioda.m32_segsize; 94211685becSGavin Shan index++; 94311685becSGavin Shan } 94411685becSGavin Shan } 94511685becSGavin Shan } 94611685becSGavin Shan } 94711685becSGavin Shan 948cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 94911685becSGavin Shan { 95011685becSGavin Shan struct pci_controller *tmp, *hose; 95111685becSGavin Shan struct pnv_phb *phb; 95211685becSGavin Shan struct pnv_ioda_pe *pe; 95311685becSGavin Shan 95411685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 95511685becSGavin Shan phb = hose->private_data; 95611685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 95711685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 95811685becSGavin Shan } 95911685becSGavin Shan } 96011685becSGavin Shan } 96111685becSGavin Shan 962cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 96313395c48SGavin Shan { 96413395c48SGavin Shan struct pci_controller *hose, *tmp; 965db1266c8SGavin Shan struct pnv_phb *phb; 96613395c48SGavin Shan 96713395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 96813395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 969db1266c8SGavin Shan 970db1266c8SGavin Shan /* Mark the PHB initialization done */ 971db1266c8SGavin Shan phb = hose->private_data; 972db1266c8SGavin Shan phb->initialized = 1; 97313395c48SGavin Shan } 97413395c48SGavin Shan } 97513395c48SGavin Shan 976cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 977fb446ad0SGavin Shan { 978fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 97911685becSGavin Shan pnv_pci_ioda_setup_seg(); 98013395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 981fb446ad0SGavin Shan } 982fb446ad0SGavin Shan 983271fd03aSGavin Shan /* 984271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 985271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 986271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 987271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 988271fd03aSGavin Shan * 1MiB for memory) will be returned. 989271fd03aSGavin Shan * 990271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 991271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 992271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 993271fd03aSGavin Shan * resources. 994271fd03aSGavin Shan */ 995271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 996271fd03aSGavin Shan unsigned long type) 997271fd03aSGavin Shan { 998271fd03aSGavin Shan struct pci_dev *bridge; 999271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1000271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1001271fd03aSGavin Shan int num_pci_bridges = 0; 1002271fd03aSGavin Shan 1003271fd03aSGavin Shan bridge = bus->self; 1004271fd03aSGavin Shan while (bridge) { 1005271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1006271fd03aSGavin Shan num_pci_bridges++; 1007271fd03aSGavin Shan if (num_pci_bridges >= 2) 1008271fd03aSGavin Shan return 1; 1009271fd03aSGavin Shan } 1010271fd03aSGavin Shan 1011271fd03aSGavin Shan bridge = bridge->bus->self; 1012271fd03aSGavin Shan } 1013271fd03aSGavin Shan 1014271fd03aSGavin Shan /* We need support prefetchable memory window later */ 1015271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1016271fd03aSGavin Shan return phb->ioda.m32_segsize; 1017271fd03aSGavin Shan 1018271fd03aSGavin Shan return phb->ioda.io_segsize; 1019271fd03aSGavin Shan } 1020271fd03aSGavin Shan 1021184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1022184cd4a3SBenjamin Herrenschmidt * assign a PE 1023184cd4a3SBenjamin Herrenschmidt */ 1024cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1025184cd4a3SBenjamin Herrenschmidt { 1026db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1027db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1028db1266c8SGavin Shan struct pci_dn *pdn; 1029184cd4a3SBenjamin Herrenschmidt 1030db1266c8SGavin Shan /* The function is probably called while the PEs have 1031db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1032db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1033db1266c8SGavin Shan * PEs isn't ready. 1034db1266c8SGavin Shan */ 1035db1266c8SGavin Shan if (!phb->initialized) 1036db1266c8SGavin Shan return 0; 1037db1266c8SGavin Shan 1038db1266c8SGavin Shan pdn = pnv_ioda_get_pdn(dev); 1039184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1040184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1041db1266c8SGavin Shan 1042184cd4a3SBenjamin Herrenschmidt return 0; 1043184cd4a3SBenjamin Herrenschmidt } 1044184cd4a3SBenjamin Herrenschmidt 1045184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1046184cd4a3SBenjamin Herrenschmidt u32 devfn) 1047184cd4a3SBenjamin Herrenschmidt { 1048184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1049184cd4a3SBenjamin Herrenschmidt } 1050184cd4a3SBenjamin Herrenschmidt 1051aa0c033fSGavin Shan void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type) 1052184cd4a3SBenjamin Herrenschmidt { 1053184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1054184cd4a3SBenjamin Herrenschmidt static int primary = 1; 1055184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 1056184cd4a3SBenjamin Herrenschmidt unsigned long size, m32map_off, iomap_off, pemap_off; 1057184cd4a3SBenjamin Herrenschmidt const u64 *prop64; 1058aa0c033fSGavin Shan const u32 *prop32; 1059184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1060184cd4a3SBenjamin Herrenschmidt void *aux; 1061184cd4a3SBenjamin Herrenschmidt long rc; 1062184cd4a3SBenjamin Herrenschmidt 1063aa0c033fSGavin Shan pr_info(" Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1064184cd4a3SBenjamin Herrenschmidt 1065184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1066184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1067184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1068184cd4a3SBenjamin Herrenschmidt return; 1069184cd4a3SBenjamin Herrenschmidt } 1070184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1071184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1072184cd4a3SBenjamin Herrenschmidt 1073184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 1074184cd4a3SBenjamin Herrenschmidt if (phb) { 1075184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 1076184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 1077184cd4a3SBenjamin Herrenschmidt } 1078184cd4a3SBenjamin Herrenschmidt if (!phb || !phb->hose) { 1079184cd4a3SBenjamin Herrenschmidt pr_err("PCI: Failed to allocate PCI controller for %s\n", 1080184cd4a3SBenjamin Herrenschmidt np->full_name); 1081184cd4a3SBenjamin Herrenschmidt return; 1082184cd4a3SBenjamin Herrenschmidt } 1083184cd4a3SBenjamin Herrenschmidt 1084184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1085184cd4a3SBenjamin Herrenschmidt /* XXX Use device-tree */ 1086184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1087184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1088184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1089184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1090aa0c033fSGavin Shan phb->type = ioda_type; 1091184cd4a3SBenjamin Herrenschmidt 1092cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1093cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1094cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1095f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1096aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1097cee72d5bSBenjamin Herrenschmidt else 1098cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1099cee72d5bSBenjamin Herrenschmidt 1100aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 1101184cd4a3SBenjamin Herrenschmidt pci_process_bridge_OF_ranges(phb->hose, np, primary); 1102184cd4a3SBenjamin Herrenschmidt primary = 0; 1103184cd4a3SBenjamin Herrenschmidt 1104aa0c033fSGavin Shan /* Get registers */ 1105184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1106184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1107184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1108184cd4a3SBenjamin Herrenschmidt 1109184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1110aa0c033fSGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 1111aa0c033fSGavin Shan if (!prop32) 1112aa0c033fSGavin Shan phb->ioda.total_pe = 1; 1113aa0c033fSGavin Shan else 1114aa0c033fSGavin Shan phb->ioda.total_pe = *prop32; 1115184cd4a3SBenjamin Herrenschmidt 1116184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1117aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 1118184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 1119184cd4a3SBenjamin Herrenschmidt 1120184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 11213fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 1122184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 1123184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1124184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1125184cd4a3SBenjamin Herrenschmidt 1126aa0c033fSGavin Shan /* Allocate aux data & arrays 1127aa0c033fSGavin Shan * 1128aa0c033fSGavin Shan * XXX TODO: Don't allocate io segmap on PHB3 1129aa0c033fSGavin Shan */ 1130184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1131184cd4a3SBenjamin Herrenschmidt m32map_off = size; 1132e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 1133184cd4a3SBenjamin Herrenschmidt iomap_off = size; 1134e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 1135184cd4a3SBenjamin Herrenschmidt pemap_off = size; 1136184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1137184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 1138184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 1139184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 1140184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 1141184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 1142184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 1143184cd4a3SBenjamin Herrenschmidt set_bit(0, phb->ioda.pe_alloc); 1144184cd4a3SBenjamin Herrenschmidt 11457ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1146184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 1147184cd4a3SBenjamin Herrenschmidt 1148184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 1149184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1150184cd4a3SBenjamin Herrenschmidt 1151184cd4a3SBenjamin Herrenschmidt /* Clear unusable m64 */ 1152184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].flags = 0; 1153184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].start = 0; 1154184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].end = 0; 1155184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].flags = 0; 1156184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].start = 0; 1157184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].end = 0; 1158184cd4a3SBenjamin Herrenschmidt 1159aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 1160184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1161184cd4a3SBenjamin Herrenschmidt window_type, 1162184cd4a3SBenjamin Herrenschmidt window_num, 1163184cd4a3SBenjamin Herrenschmidt starting_real_address, 1164184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1165184cd4a3SBenjamin Herrenschmidt segment_size); 1166184cd4a3SBenjamin Herrenschmidt #endif 1167184cd4a3SBenjamin Herrenschmidt 1168184cd4a3SBenjamin Herrenschmidt pr_info(" %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n", 1169184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 1170184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size, phb->ioda.m32_segsize, 1171184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1172184cd4a3SBenjamin Herrenschmidt 1173184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 1174184cd4a3SBenjamin Herrenschmidt 1175184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1176184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1177184cd4a3SBenjamin Herrenschmidt 1178184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1179184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1180184cd4a3SBenjamin Herrenschmidt 1181184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1182184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1183184cd4a3SBenjamin Herrenschmidt 1184c40a4210SGavin Shan /* 1185c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1186c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1187c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1188c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1189c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1190184cd4a3SBenjamin Herrenschmidt */ 1191fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1192184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1193271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1194c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1195184cd4a3SBenjamin Herrenschmidt 1196184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1197f11fe552SBenjamin Herrenschmidt rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); 1198184cd4a3SBenjamin Herrenschmidt if (rc) 1199f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1200aa0c033fSGavin Shan 1201aa0c033fSGavin Shan /* 1202aa0c033fSGavin Shan * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset 1203aa0c033fSGavin Shan * has cleared the RTT which has the same effect 1204aa0c033fSGavin Shan */ 1205aa0c033fSGavin Shan if (ioda_type == PNV_PHB_IODA1) 1206184cd4a3SBenjamin Herrenschmidt opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE); 1207184cd4a3SBenjamin Herrenschmidt } 1208184cd4a3SBenjamin Herrenschmidt 1209aa0c033fSGavin Shan void pnv_pci_init_ioda2_phb(struct device_node *np) 1210aa0c033fSGavin Shan { 1211aa0c033fSGavin Shan pnv_pci_init_ioda_phb(np, PNV_PHB_IODA2); 1212aa0c033fSGavin Shan } 1213aa0c033fSGavin Shan 1214184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 1215184cd4a3SBenjamin Herrenschmidt { 1216184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 1217184cd4a3SBenjamin Herrenschmidt const u64 *prop64; 1218184cd4a3SBenjamin Herrenschmidt u64 hub_id; 1219184cd4a3SBenjamin Herrenschmidt 1220184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1221184cd4a3SBenjamin Herrenschmidt 1222184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1223184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1224184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1225184cd4a3SBenjamin Herrenschmidt return; 1226184cd4a3SBenjamin Herrenschmidt } 1227184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 1228184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1229184cd4a3SBenjamin Herrenschmidt 1230184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 1231184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 1232184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 1233184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1234aa0c033fSGavin Shan pnv_pci_init_ioda_phb(phbn, PNV_PHB_IODA1); 1235184cd4a3SBenjamin Herrenschmidt } 1236184cd4a3SBenjamin Herrenschmidt } 1237