1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 1637c367f2SGavin Shan #include <linux/debugfs.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 25184cd4a3SBenjamin Herrenschmidt 26184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 31fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 36137436c9SGavin Shan #include <asm/xics.h> 3737c367f2SGavin Shan #include <asm/debug.h> 38184cd4a3SBenjamin Herrenschmidt 39184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 40184cd4a3SBenjamin Herrenschmidt #include "pci.h" 41184cd4a3SBenjamin Herrenschmidt 42184cd4a3SBenjamin Herrenschmidt #define define_pe_printk_level(func, kern_level) \ 43184cd4a3SBenjamin Herrenschmidt static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ 44184cd4a3SBenjamin Herrenschmidt { \ 45184cd4a3SBenjamin Herrenschmidt struct va_format vaf; \ 46184cd4a3SBenjamin Herrenschmidt va_list args; \ 47490e078dSGavin Shan char pfix[32]; \ 48184cd4a3SBenjamin Herrenschmidt int r; \ 49184cd4a3SBenjamin Herrenschmidt \ 50184cd4a3SBenjamin Herrenschmidt va_start(args, fmt); \ 51184cd4a3SBenjamin Herrenschmidt \ 52184cd4a3SBenjamin Herrenschmidt vaf.fmt = fmt; \ 53184cd4a3SBenjamin Herrenschmidt vaf.va = &args; \ 54184cd4a3SBenjamin Herrenschmidt \ 55490e078dSGavin Shan if (pe->pdev) \ 56490e078dSGavin Shan strlcpy(pfix, dev_name(&pe->pdev->dev), \ 57490e078dSGavin Shan sizeof(pfix)); \ 58490e078dSGavin Shan else \ 59490e078dSGavin Shan sprintf(pfix, "%04x:%02x ", \ 60490e078dSGavin Shan pci_domain_nr(pe->pbus), \ 61490e078dSGavin Shan pe->pbus->number); \ 62490e078dSGavin Shan r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ 63490e078dSGavin Shan pfix, pe->pe_number, &vaf); \ 64490e078dSGavin Shan \ 65184cd4a3SBenjamin Herrenschmidt va_end(args); \ 66184cd4a3SBenjamin Herrenschmidt \ 67184cd4a3SBenjamin Herrenschmidt return r; \ 68184cd4a3SBenjamin Herrenschmidt } \ 69184cd4a3SBenjamin Herrenschmidt 70184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_err, KERN_ERR); 71184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_warn, KERN_WARNING); 72184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_info, KERN_INFO); 73184cd4a3SBenjamin Herrenschmidt 748e0a1611SAlexey Kardashevskiy /* 758e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 768e0a1611SAlexey Kardashevskiy * the architecture spec 778e0a1611SAlexey Kardashevskiy */ 788e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 798e0a1611SAlexey Kardashevskiy { 808e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 818e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 828e0a1611SAlexey Kardashevskiy } 838e0a1611SAlexey Kardashevskiy 84cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 85184cd4a3SBenjamin Herrenschmidt { 86184cd4a3SBenjamin Herrenschmidt unsigned long pe; 87184cd4a3SBenjamin Herrenschmidt 88184cd4a3SBenjamin Herrenschmidt do { 89184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 90184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 91184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 92184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 93184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 94184cd4a3SBenjamin Herrenschmidt 954cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 96184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 97184cd4a3SBenjamin Herrenschmidt return pe; 98184cd4a3SBenjamin Herrenschmidt } 99184cd4a3SBenjamin Herrenschmidt 100cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 101184cd4a3SBenjamin Herrenschmidt { 102184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 103184cd4a3SBenjamin Herrenschmidt 104184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 105184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 106184cd4a3SBenjamin Herrenschmidt } 107184cd4a3SBenjamin Herrenschmidt 108184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 109184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 110184cd4a3SBenjamin Herrenschmidt */ 111184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 112cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 113184cd4a3SBenjamin Herrenschmidt { 114184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 115184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 116b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 117184cd4a3SBenjamin Herrenschmidt 118184cd4a3SBenjamin Herrenschmidt if (!pdn) 119184cd4a3SBenjamin Herrenschmidt return NULL; 120184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 121184cd4a3SBenjamin Herrenschmidt return NULL; 122184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 123184cd4a3SBenjamin Herrenschmidt } 124184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 125184cd4a3SBenjamin Herrenschmidt 126cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 127184cd4a3SBenjamin Herrenschmidt { 128184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 129184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 130184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 131184cd4a3SBenjamin Herrenschmidt 132184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 133184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 134184cd4a3SBenjamin Herrenschmidt int count; 135184cd4a3SBenjamin Herrenschmidt 136184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 137184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 138184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 139fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 140b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 141fb446ad0SGavin Shan else 142fb446ad0SGavin Shan count = 1; 143fb446ad0SGavin Shan 144184cd4a3SBenjamin Herrenschmidt switch(count) { 145184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 146184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 147184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 148184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 149184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 150184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 151184cd4a3SBenjamin Herrenschmidt default: 152184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 153184cd4a3SBenjamin Herrenschmidt " unsupported\n", 154184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 155184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 156184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 157184cd4a3SBenjamin Herrenschmidt } 158184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 159184cd4a3SBenjamin Herrenschmidt } else { 160184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 161184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 162184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 163184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 164184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 165184cd4a3SBenjamin Herrenschmidt } 166184cd4a3SBenjamin Herrenschmidt 167631ad691SGavin Shan /* 168631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 169631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 170631ad691SGavin Shan * originated from the PE might contribute to other 171631ad691SGavin Shan * PEs. 172631ad691SGavin Shan */ 173184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 174184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 175184cd4a3SBenjamin Herrenschmidt if (rc) { 176184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 177184cd4a3SBenjamin Herrenschmidt return -ENXIO; 178184cd4a3SBenjamin Herrenschmidt } 179631ad691SGavin Shan 180631ad691SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 181631ad691SGavin Shan pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 182631ad691SGavin Shan if (rc) 183631ad691SGavin Shan pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc); 184184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 185184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 186184cd4a3SBenjamin Herrenschmidt 187184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 188184cd4a3SBenjamin Herrenschmidt while (parent) { 189b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(parent); 190184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 191184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 192cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 193184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 194184cd4a3SBenjamin Herrenschmidt } 195184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 196184cd4a3SBenjamin Herrenschmidt } 197184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 198184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 199184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 200184cd4a3SBenjamin Herrenschmidt 201184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 202184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 203184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 204184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 205184cd4a3SBenjamin Herrenschmidt pe->pe_number); 206184cd4a3SBenjamin Herrenschmidt if (rc) { 207184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 208184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 209184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 210184cd4a3SBenjamin Herrenschmidt } else { 211184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 212cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 213184cd4a3SBenjamin Herrenschmidt if (rc) { 214184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 215184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 216184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 217184cd4a3SBenjamin Herrenschmidt } 218184cd4a3SBenjamin Herrenschmidt } 219184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 220184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 221184cd4a3SBenjamin Herrenschmidt 222184cd4a3SBenjamin Herrenschmidt return 0; 223184cd4a3SBenjamin Herrenschmidt } 224184cd4a3SBenjamin Herrenschmidt 225cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 226184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 227184cd4a3SBenjamin Herrenschmidt { 228184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 229184cd4a3SBenjamin Herrenschmidt 2307ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 231184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 2327ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 233184cd4a3SBenjamin Herrenschmidt return; 234184cd4a3SBenjamin Herrenschmidt } 235184cd4a3SBenjamin Herrenschmidt } 2367ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 237184cd4a3SBenjamin Herrenschmidt } 238184cd4a3SBenjamin Herrenschmidt 239184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 240184cd4a3SBenjamin Herrenschmidt { 241184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 242184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 243184cd4a3SBenjamin Herrenschmidt */ 244184cd4a3SBenjamin Herrenschmidt 245184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 246184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 247184cd4a3SBenjamin Herrenschmidt return 0; 248184cd4a3SBenjamin Herrenschmidt 249184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 250184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 251184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 252184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 253184cd4a3SBenjamin Herrenschmidt return 3; 254184cd4a3SBenjamin Herrenschmidt 255184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 256184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 257184cd4a3SBenjamin Herrenschmidt return 15; 258184cd4a3SBenjamin Herrenschmidt 259184cd4a3SBenjamin Herrenschmidt /* Default */ 260184cd4a3SBenjamin Herrenschmidt return 10; 261184cd4a3SBenjamin Herrenschmidt } 262184cd4a3SBenjamin Herrenschmidt 263fb446ad0SGavin Shan #if 0 264cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 265184cd4a3SBenjamin Herrenschmidt { 266184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 267184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 268b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 269184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 270184cd4a3SBenjamin Herrenschmidt int pe_num; 271184cd4a3SBenjamin Herrenschmidt 272184cd4a3SBenjamin Herrenschmidt if (!pdn) { 273184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 274184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 275184cd4a3SBenjamin Herrenschmidt return NULL; 276184cd4a3SBenjamin Herrenschmidt } 277184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 278184cd4a3SBenjamin Herrenschmidt return NULL; 279184cd4a3SBenjamin Herrenschmidt 280184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 281184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 282184cd4a3SBenjamin Herrenschmidt pe_num = 0; 283184cd4a3SBenjamin Herrenschmidt else 284184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 285184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 286184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 287184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 288184cd4a3SBenjamin Herrenschmidt return NULL; 289184cd4a3SBenjamin Herrenschmidt } 290184cd4a3SBenjamin Herrenschmidt 291184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 292184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 293184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 294184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 295184cd4a3SBenjamin Herrenschmidt * 296184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 297184cd4a3SBenjamin Herrenschmidt */ 298184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 299184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 300184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 301184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 302184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 303184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 304184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 305184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 306184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 307184cd4a3SBenjamin Herrenschmidt 308184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 309184cd4a3SBenjamin Herrenschmidt 310184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 311184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 312184cd4a3SBenjamin Herrenschmidt if (pe_num) 313184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 314184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 315184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 316184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 317184cd4a3SBenjamin Herrenschmidt return NULL; 318184cd4a3SBenjamin Herrenschmidt } 319184cd4a3SBenjamin Herrenschmidt 320184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 321184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 322184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 323184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 324184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 325184cd4a3SBenjamin Herrenschmidt } 326184cd4a3SBenjamin Herrenschmidt 327184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 328184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 329184cd4a3SBenjamin Herrenschmidt 330184cd4a3SBenjamin Herrenschmidt return pe; 331184cd4a3SBenjamin Herrenschmidt } 332fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 333184cd4a3SBenjamin Herrenschmidt 334184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 335184cd4a3SBenjamin Herrenschmidt { 336184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 337184cd4a3SBenjamin Herrenschmidt 338184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 339b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 340184cd4a3SBenjamin Herrenschmidt 341184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 342184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 343184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 344184cd4a3SBenjamin Herrenschmidt continue; 345184cd4a3SBenjamin Herrenschmidt } 346184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 347184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 348184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 349184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 350fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 351184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 352184cd4a3SBenjamin Herrenschmidt } 353184cd4a3SBenjamin Herrenschmidt } 354184cd4a3SBenjamin Herrenschmidt 355fb446ad0SGavin Shan /* 356fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 357fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 358fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 359fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 360fb446ad0SGavin Shan */ 361cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 362184cd4a3SBenjamin Herrenschmidt { 363fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 364184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 365184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 366184cd4a3SBenjamin Herrenschmidt int pe_num; 367184cd4a3SBenjamin Herrenschmidt 368184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 369184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 370fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 371fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 372184cd4a3SBenjamin Herrenschmidt return; 373184cd4a3SBenjamin Herrenschmidt } 374184cd4a3SBenjamin Herrenschmidt 375184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 376fb446ad0SGavin Shan pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 377184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 378184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 379184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 380184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 381b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 382184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 383184cd4a3SBenjamin Herrenschmidt 384fb446ad0SGavin Shan if (all) 385fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 386fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 387fb446ad0SGavin Shan else 388fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 389fb446ad0SGavin Shan bus->busn_res.start, pe_num); 390184cd4a3SBenjamin Herrenschmidt 391184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 392184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 393184cd4a3SBenjamin Herrenschmidt if (pe_num) 394184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 395184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 396184cd4a3SBenjamin Herrenschmidt return; 397184cd4a3SBenjamin Herrenschmidt } 398184cd4a3SBenjamin Herrenschmidt 399184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 400184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 401184cd4a3SBenjamin Herrenschmidt 4027ebdf956SGavin Shan /* Put PE to the list */ 4037ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 4047ebdf956SGavin Shan 405184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 406184cd4a3SBenjamin Herrenschmidt * below the bridge 407184cd4a3SBenjamin Herrenschmidt */ 408184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 409184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 410184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 411184cd4a3SBenjamin Herrenschmidt } 412184cd4a3SBenjamin Herrenschmidt 413184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 414184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 415184cd4a3SBenjamin Herrenschmidt } 416184cd4a3SBenjamin Herrenschmidt 417cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 418184cd4a3SBenjamin Herrenschmidt { 419184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 420fb446ad0SGavin Shan 421fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 422184cd4a3SBenjamin Herrenschmidt 423184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 424fb446ad0SGavin Shan if (dev->subordinate) { 42562f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 426fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 427fb446ad0SGavin Shan else 428184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 429184cd4a3SBenjamin Herrenschmidt } 430184cd4a3SBenjamin Herrenschmidt } 431fb446ad0SGavin Shan } 432fb446ad0SGavin Shan 433fb446ad0SGavin Shan /* 434fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 435fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 436fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 437fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 438fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 439fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 440fb446ad0SGavin Shan */ 441cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 442fb446ad0SGavin Shan { 443fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 444fb446ad0SGavin Shan 445fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 446fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 447fb446ad0SGavin Shan } 448fb446ad0SGavin Shan } 449184cd4a3SBenjamin Herrenschmidt 450959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 451184cd4a3SBenjamin Herrenschmidt { 452b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 453959c9bddSGavin Shan struct pnv_ioda_pe *pe; 454184cd4a3SBenjamin Herrenschmidt 455959c9bddSGavin Shan /* 456959c9bddSGavin Shan * The function can be called while the PE# 457959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 458959c9bddSGavin Shan * case. 459959c9bddSGavin Shan */ 460959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 461959c9bddSGavin Shan return; 462184cd4a3SBenjamin Herrenschmidt 463959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 464cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 4653f28c5afSWei Yang set_iommu_table_base(&pdev->dev, &pe->tce32_table); 466184cd4a3SBenjamin Herrenschmidt } 467184cd4a3SBenjamin Herrenschmidt 468cd15b048SBenjamin Herrenschmidt static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, 469cd15b048SBenjamin Herrenschmidt struct pci_dev *pdev, u64 dma_mask) 470cd15b048SBenjamin Herrenschmidt { 471cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 472cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 473cd15b048SBenjamin Herrenschmidt uint64_t top; 474cd15b048SBenjamin Herrenschmidt bool bypass = false; 475cd15b048SBenjamin Herrenschmidt 476cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 477cd15b048SBenjamin Herrenschmidt return -ENODEV;; 478cd15b048SBenjamin Herrenschmidt 479cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 480cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 481cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 482cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 483cd15b048SBenjamin Herrenschmidt } 484cd15b048SBenjamin Herrenschmidt 485cd15b048SBenjamin Herrenschmidt if (bypass) { 486cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 487cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 488cd15b048SBenjamin Herrenschmidt set_dma_offset(&pdev->dev, pe->tce_bypass_base); 489cd15b048SBenjamin Herrenschmidt } else { 490cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 491cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 492cd15b048SBenjamin Herrenschmidt set_iommu_table_base(&pdev->dev, &pe->tce32_table); 493cd15b048SBenjamin Herrenschmidt } 494cd15b048SBenjamin Herrenschmidt return 0; 495cd15b048SBenjamin Herrenschmidt } 496cd15b048SBenjamin Herrenschmidt 49774251fe2SBenjamin Herrenschmidt static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 49874251fe2SBenjamin Herrenschmidt { 49974251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 50074251fe2SBenjamin Herrenschmidt 50174251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 502d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&dev->dev, &pe->tce32_table); 50374251fe2SBenjamin Herrenschmidt if (dev->subordinate) 50474251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, dev->subordinate); 50574251fe2SBenjamin Herrenschmidt } 50674251fe2SBenjamin Herrenschmidt } 50774251fe2SBenjamin Herrenschmidt 5088e0a1611SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, 5098e0a1611SAlexey Kardashevskiy struct iommu_table *tbl, 5103ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 5114cce9550SGavin Shan { 5123ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 5133ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 5143ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 5154cce9550SGavin Shan unsigned long start, end, inc; 5164cce9550SGavin Shan 5174cce9550SGavin Shan start = __pa(startp); 5184cce9550SGavin Shan end = __pa(endp); 5194cce9550SGavin Shan 5204cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 5214cce9550SGavin Shan if (tbl->it_busno) { 5224cce9550SGavin Shan start <<= 12; 5234cce9550SGavin Shan end <<= 12; 5244cce9550SGavin Shan inc = 128 << 12; 5254cce9550SGavin Shan start |= tbl->it_busno; 5264cce9550SGavin Shan end |= tbl->it_busno; 5274cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 5284cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 5294cce9550SGavin Shan start |= (1ull << 63); 5304cce9550SGavin Shan end |= (1ull << 63); 5314cce9550SGavin Shan inc = 16; 5324cce9550SGavin Shan } else { 5334cce9550SGavin Shan /* Default (older HW) */ 5344cce9550SGavin Shan inc = 128; 5354cce9550SGavin Shan } 5364cce9550SGavin Shan 5374cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 5384cce9550SGavin Shan 5394cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 5404cce9550SGavin Shan while (start <= end) { 5418e0a1611SAlexey Kardashevskiy if (rm) 5423ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 5438e0a1611SAlexey Kardashevskiy else 5443a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 5454cce9550SGavin Shan start += inc; 5464cce9550SGavin Shan } 5474cce9550SGavin Shan 5484cce9550SGavin Shan /* 5494cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 5504cce9550SGavin Shan * and we don't care on free() 5514cce9550SGavin Shan */ 5524cce9550SGavin Shan } 5534cce9550SGavin Shan 5544cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 5554cce9550SGavin Shan struct iommu_table *tbl, 5563ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 5574cce9550SGavin Shan { 5584cce9550SGavin Shan unsigned long start, end, inc; 5593ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 5603ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 5613ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 5624cce9550SGavin Shan 5634cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 5644cce9550SGavin Shan start = 0x2ul << 60; 5654cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 5664cce9550SGavin Shan end = start; 5674cce9550SGavin Shan 5684cce9550SGavin Shan /* Figure out the start, end and step */ 5694cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 5704cce9550SGavin Shan start |= (inc << 12); 5714cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 5724cce9550SGavin Shan end |= (inc << 12); 5734cce9550SGavin Shan inc = (0x1ul << 12); 5744cce9550SGavin Shan mb(); 5754cce9550SGavin Shan 5764cce9550SGavin Shan while (start <= end) { 5778e0a1611SAlexey Kardashevskiy if (rm) 5783ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 5798e0a1611SAlexey Kardashevskiy else 5803a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 5814cce9550SGavin Shan start += inc; 5824cce9550SGavin Shan } 5834cce9550SGavin Shan } 5844cce9550SGavin Shan 5854cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 5863ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 5874cce9550SGavin Shan { 5884cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 5894cce9550SGavin Shan tce32_table); 5904cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 5914cce9550SGavin Shan 5924cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 5938e0a1611SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); 5944cce9550SGavin Shan else 5958e0a1611SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); 5964cce9550SGavin Shan } 5974cce9550SGavin Shan 598cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 599cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 600184cd4a3SBenjamin Herrenschmidt unsigned int segs) 601184cd4a3SBenjamin Herrenschmidt { 602184cd4a3SBenjamin Herrenschmidt 603184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 604184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 605184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 606184cd4a3SBenjamin Herrenschmidt unsigned int i; 607184cd4a3SBenjamin Herrenschmidt int64_t rc; 608184cd4a3SBenjamin Herrenschmidt void *addr; 609184cd4a3SBenjamin Herrenschmidt 610184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 611184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 612184cd4a3SBenjamin Herrenschmidt 613184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 614184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 615184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 616184cd4a3SBenjamin Herrenschmidt 617184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 618184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 619184cd4a3SBenjamin Herrenschmidt return; 620184cd4a3SBenjamin Herrenschmidt 621184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 622184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 623184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 624184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 625184cd4a3SBenjamin Herrenschmidt 626184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 627184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 628184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 629184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 630184cd4a3SBenjamin Herrenschmidt */ 631184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 632184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 633184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 634184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 635184cd4a3SBenjamin Herrenschmidt goto fail; 636184cd4a3SBenjamin Herrenschmidt } 637184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 638184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 639184cd4a3SBenjamin Herrenschmidt 640184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 641184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 642184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 643184cd4a3SBenjamin Herrenschmidt pe->pe_number, 644184cd4a3SBenjamin Herrenschmidt base + i, 1, 645184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 646184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 647184cd4a3SBenjamin Herrenschmidt if (rc) { 648184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 649184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 650184cd4a3SBenjamin Herrenschmidt goto fail; 651184cd4a3SBenjamin Herrenschmidt } 652184cd4a3SBenjamin Herrenschmidt } 653184cd4a3SBenjamin Herrenschmidt 654184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 655184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 656184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 657184cd4a3SBenjamin Herrenschmidt base << 28); 658184cd4a3SBenjamin Herrenschmidt 659184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 660184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 661184cd4a3SBenjamin Herrenschmidt if (swinvp) { 662184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 663184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 664184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 665184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 666184cd4a3SBenjamin Herrenschmidt */ 667184cd4a3SBenjamin Herrenschmidt tbl->it_busno = 0; 6688e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 6698e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 6708e0a1611SAlexey Kardashevskiy 8); 671373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE | 672373f5657SGavin Shan TCE_PCI_SWINV_PAIR; 673184cd4a3SBenjamin Herrenschmidt } 674184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 6754e13c1acSAlexey Kardashevskiy iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number); 676184cd4a3SBenjamin Herrenschmidt 67774251fe2SBenjamin Herrenschmidt if (pe->pdev) 678d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 67974251fe2SBenjamin Herrenschmidt else 68074251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, pe->pbus); 68174251fe2SBenjamin Herrenschmidt 682184cd4a3SBenjamin Herrenschmidt return; 683184cd4a3SBenjamin Herrenschmidt fail: 684184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 685184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 686184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 687184cd4a3SBenjamin Herrenschmidt if (tce_mem) 688184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 689184cd4a3SBenjamin Herrenschmidt } 690184cd4a3SBenjamin Herrenschmidt 691cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) 692cd15b048SBenjamin Herrenschmidt { 693cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 694cd15b048SBenjamin Herrenschmidt tce32_table); 695cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 696cd15b048SBenjamin Herrenschmidt int64_t rc; 697cd15b048SBenjamin Herrenschmidt 698cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 699cd15b048SBenjamin Herrenschmidt if (enable) { 700cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 701cd15b048SBenjamin Herrenschmidt 702cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 703cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 704cd15b048SBenjamin Herrenschmidt pe->pe_number, 705cd15b048SBenjamin Herrenschmidt window_id, 706cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 707cd15b048SBenjamin Herrenschmidt top); 708cd15b048SBenjamin Herrenschmidt } else { 709cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 710cd15b048SBenjamin Herrenschmidt pe->pe_number, 711cd15b048SBenjamin Herrenschmidt window_id, 712cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 713cd15b048SBenjamin Herrenschmidt 0); 714cd15b048SBenjamin Herrenschmidt 715cd15b048SBenjamin Herrenschmidt /* 716cd15b048SBenjamin Herrenschmidt * We might want to reset the DMA ops of all devices on 717cd15b048SBenjamin Herrenschmidt * this PE. However in theory, that shouldn't be necessary 718cd15b048SBenjamin Herrenschmidt * as this is used for VFIO/KVM pass-through and the device 719cd15b048SBenjamin Herrenschmidt * hasn't yet been returned to its kernel driver 720cd15b048SBenjamin Herrenschmidt */ 721cd15b048SBenjamin Herrenschmidt } 722cd15b048SBenjamin Herrenschmidt if (rc) 723cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 724cd15b048SBenjamin Herrenschmidt else 725cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 726cd15b048SBenjamin Herrenschmidt } 727cd15b048SBenjamin Herrenschmidt 728cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, 729cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 730cd15b048SBenjamin Herrenschmidt { 731cd15b048SBenjamin Herrenschmidt /* TVE #1 is selected by PCI address bit 59 */ 732cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base = 1ull << 59; 733cd15b048SBenjamin Herrenschmidt 734cd15b048SBenjamin Herrenschmidt /* Install set_bypass callback for VFIO */ 735cd15b048SBenjamin Herrenschmidt pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; 736cd15b048SBenjamin Herrenschmidt 737cd15b048SBenjamin Herrenschmidt /* Enable bypass by default */ 738cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); 739cd15b048SBenjamin Herrenschmidt } 740cd15b048SBenjamin Herrenschmidt 741373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 742373f5657SGavin Shan struct pnv_ioda_pe *pe) 743373f5657SGavin Shan { 744373f5657SGavin Shan struct page *tce_mem = NULL; 745373f5657SGavin Shan void *addr; 746373f5657SGavin Shan const __be64 *swinvp; 747373f5657SGavin Shan struct iommu_table *tbl; 748373f5657SGavin Shan unsigned int tce_table_size, end; 749373f5657SGavin Shan int64_t rc; 750373f5657SGavin Shan 751373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 752373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 753373f5657SGavin Shan return; 754373f5657SGavin Shan 755373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 756373f5657SGavin Shan pe->tce32_seg = 0; 757373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 758373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 759373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 760373f5657SGavin Shan end); 761373f5657SGavin Shan 762373f5657SGavin Shan /* Allocate TCE table */ 763373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 764373f5657SGavin Shan get_order(tce_table_size)); 765373f5657SGavin Shan if (!tce_mem) { 766373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 767373f5657SGavin Shan goto fail; 768373f5657SGavin Shan } 769373f5657SGavin Shan addr = page_address(tce_mem); 770373f5657SGavin Shan memset(addr, 0, tce_table_size); 771373f5657SGavin Shan 772373f5657SGavin Shan /* 773373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 774373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 775373f5657SGavin Shan */ 776373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 777373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 778373f5657SGavin Shan tce_table_size, 0x1000); 779373f5657SGavin Shan if (rc) { 780373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 781373f5657SGavin Shan " err %ld\n", rc); 782373f5657SGavin Shan goto fail; 783373f5657SGavin Shan } 784373f5657SGavin Shan 785373f5657SGavin Shan /* Setup linux iommu table */ 786373f5657SGavin Shan tbl = &pe->tce32_table; 787373f5657SGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0); 788373f5657SGavin Shan 789373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 790373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 791373f5657SGavin Shan if (swinvp) { 792373f5657SGavin Shan /* We need a couple more fields -- an address and a data 793373f5657SGavin Shan * to or. Since the bus is only printed out on table free 794373f5657SGavin Shan * errors, and on the first pass the data will be a relative 795373f5657SGavin Shan * bus number, print that out instead. 796373f5657SGavin Shan */ 797373f5657SGavin Shan tbl->it_busno = 0; 7988e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 7998e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 8008e0a1611SAlexey Kardashevskiy 8); 801373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; 802373f5657SGavin Shan } 803373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 80408607afbSThadeu Lima de Souza Cascardo iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number); 805373f5657SGavin Shan 80674251fe2SBenjamin Herrenschmidt if (pe->pdev) 807d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 80874251fe2SBenjamin Herrenschmidt else 80974251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, pe->pbus); 81074251fe2SBenjamin Herrenschmidt 811cd15b048SBenjamin Herrenschmidt /* Also create a bypass window */ 812cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_setup_bypass_pe(phb, pe); 813373f5657SGavin Shan return; 814373f5657SGavin Shan fail: 815373f5657SGavin Shan if (pe->tce32_seg >= 0) 816373f5657SGavin Shan pe->tce32_seg = -1; 817373f5657SGavin Shan if (tce_mem) 818373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 819373f5657SGavin Shan } 820373f5657SGavin Shan 821cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 822184cd4a3SBenjamin Herrenschmidt { 823184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 824184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 825184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 826184cd4a3SBenjamin Herrenschmidt 827184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 828184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 829184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 830184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 831184cd4a3SBenjamin Herrenschmidt */ 832184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 833184cd4a3SBenjamin Herrenschmidt residual = 0; 834184cd4a3SBenjamin Herrenschmidt else 835184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 836184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 837184cd4a3SBenjamin Herrenschmidt 838184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 839184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 840184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 841184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 842184cd4a3SBenjamin Herrenschmidt 843184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 844184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 845184cd4a3SBenjamin Herrenschmidt * weight 846184cd4a3SBenjamin Herrenschmidt */ 847184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 848184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 849184cd4a3SBenjamin Herrenschmidt base = 0; 8507ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 851184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 852184cd4a3SBenjamin Herrenschmidt continue; 853184cd4a3SBenjamin Herrenschmidt if (!remaining) { 854184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 855184cd4a3SBenjamin Herrenschmidt continue; 856184cd4a3SBenjamin Herrenschmidt } 857184cd4a3SBenjamin Herrenschmidt segs = 1; 858184cd4a3SBenjamin Herrenschmidt if (residual) { 859184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 860184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 861184cd4a3SBenjamin Herrenschmidt segs = remaining; 862184cd4a3SBenjamin Herrenschmidt } 863373f5657SGavin Shan 864373f5657SGavin Shan /* 865373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 866373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 867373f5657SGavin Shan * the specific PE. 868373f5657SGavin Shan */ 869373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 870184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 871184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 872184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 873373f5657SGavin Shan } else { 874373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 875373f5657SGavin Shan segs = 0; 876373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 877373f5657SGavin Shan } 878373f5657SGavin Shan 879184cd4a3SBenjamin Herrenschmidt remaining -= segs; 880184cd4a3SBenjamin Herrenschmidt base += segs; 881184cd4a3SBenjamin Herrenschmidt } 882184cd4a3SBenjamin Herrenschmidt } 883184cd4a3SBenjamin Herrenschmidt 884184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 885137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 886137436c9SGavin Shan { 887137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 888137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 889137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 890137436c9SGavin Shan ioda.irq_chip); 891137436c9SGavin Shan int64_t rc; 892137436c9SGavin Shan 893137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 894137436c9SGavin Shan WARN_ON_ONCE(rc); 895137436c9SGavin Shan 896137436c9SGavin Shan icp_native_eoi(d); 897137436c9SGavin Shan } 898137436c9SGavin Shan 899184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 900137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 901137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 902184cd4a3SBenjamin Herrenschmidt { 903184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 904b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 905137436c9SGavin Shan struct irq_data *idata; 906137436c9SGavin Shan struct irq_chip *ichip; 907184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 9083a1a4661SBenjamin Herrenschmidt __be32 data; 909184cd4a3SBenjamin Herrenschmidt int rc; 910184cd4a3SBenjamin Herrenschmidt 911184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 912184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 913184cd4a3SBenjamin Herrenschmidt return -ENXIO; 914184cd4a3SBenjamin Herrenschmidt 915184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 916184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 917184cd4a3SBenjamin Herrenschmidt return -ENXIO; 918184cd4a3SBenjamin Herrenschmidt 919b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 920b72c1f65SBenjamin Herrenschmidt if (pdn && pdn->force_32bit_msi) 921b72c1f65SBenjamin Herrenschmidt is_64 = 0; 922b72c1f65SBenjamin Herrenschmidt 923184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 924184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 925184cd4a3SBenjamin Herrenschmidt if (rc) { 926184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 927184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 928184cd4a3SBenjamin Herrenschmidt return -EIO; 929184cd4a3SBenjamin Herrenschmidt } 930184cd4a3SBenjamin Herrenschmidt 931184cd4a3SBenjamin Herrenschmidt if (is_64) { 9323a1a4661SBenjamin Herrenschmidt __be64 addr64; 9333a1a4661SBenjamin Herrenschmidt 934184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 935184cd4a3SBenjamin Herrenschmidt &addr64, &data); 936184cd4a3SBenjamin Herrenschmidt if (rc) { 937184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 938184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 939184cd4a3SBenjamin Herrenschmidt return -EIO; 940184cd4a3SBenjamin Herrenschmidt } 9413a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 9423a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 943184cd4a3SBenjamin Herrenschmidt } else { 9443a1a4661SBenjamin Herrenschmidt __be32 addr32; 9453a1a4661SBenjamin Herrenschmidt 946184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 947184cd4a3SBenjamin Herrenschmidt &addr32, &data); 948184cd4a3SBenjamin Herrenschmidt if (rc) { 949184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 950184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 951184cd4a3SBenjamin Herrenschmidt return -EIO; 952184cd4a3SBenjamin Herrenschmidt } 953184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 9543a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 955184cd4a3SBenjamin Herrenschmidt } 9563a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 957184cd4a3SBenjamin Herrenschmidt 958137436c9SGavin Shan /* 959137436c9SGavin Shan * Change the IRQ chip for the MSI interrupts on PHB3. 960137436c9SGavin Shan * The corresponding IRQ chip should be populated for 961137436c9SGavin Shan * the first time. 962137436c9SGavin Shan */ 963137436c9SGavin Shan if (phb->type == PNV_PHB_IODA2) { 964137436c9SGavin Shan if (!phb->ioda.irq_chip_init) { 965137436c9SGavin Shan idata = irq_get_irq_data(virq); 966137436c9SGavin Shan ichip = irq_data_get_irq_chip(idata); 967137436c9SGavin Shan phb->ioda.irq_chip_init = 1; 968137436c9SGavin Shan phb->ioda.irq_chip = *ichip; 969137436c9SGavin Shan phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 970137436c9SGavin Shan } 971137436c9SGavin Shan 972137436c9SGavin Shan irq_set_chip(virq, &phb->ioda.irq_chip); 973137436c9SGavin Shan } 974137436c9SGavin Shan 975184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 976184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 977184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 978184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 979184cd4a3SBenjamin Herrenschmidt 980184cd4a3SBenjamin Herrenschmidt return 0; 981184cd4a3SBenjamin Herrenschmidt } 982184cd4a3SBenjamin Herrenschmidt 983184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 984184cd4a3SBenjamin Herrenschmidt { 985fb1b55d6SGavin Shan unsigned int count; 986184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 987184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 988184cd4a3SBenjamin Herrenschmidt if (!prop) { 989184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 990184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 991184cd4a3SBenjamin Herrenschmidt } 992184cd4a3SBenjamin Herrenschmidt if (!prop) 993184cd4a3SBenjamin Herrenschmidt return; 994184cd4a3SBenjamin Herrenschmidt 995184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 996fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 997fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 998184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 999184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 1000184cd4a3SBenjamin Herrenschmidt return; 1001184cd4a3SBenjamin Herrenschmidt } 1002fb1b55d6SGavin Shan 1003184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 1004184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 1005184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 1006fb1b55d6SGavin Shan count, phb->msi_base); 1007184cd4a3SBenjamin Herrenschmidt } 1008184cd4a3SBenjamin Herrenschmidt #else 1009184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 1010184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 1011184cd4a3SBenjamin Herrenschmidt 101211685becSGavin Shan /* 101311685becSGavin Shan * This function is supposed to be called on basis of PE from top 101411685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 101511685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 101611685becSGavin Shan */ 1017cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 101811685becSGavin Shan struct pnv_ioda_pe *pe) 101911685becSGavin Shan { 102011685becSGavin Shan struct pnv_phb *phb = hose->private_data; 102111685becSGavin Shan struct pci_bus_region region; 102211685becSGavin Shan struct resource *res; 102311685becSGavin Shan int i, index; 102411685becSGavin Shan int rc; 102511685becSGavin Shan 102611685becSGavin Shan /* 102711685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 102811685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 102911685becSGavin Shan * be figured out later. 103011685becSGavin Shan */ 103111685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 103211685becSGavin Shan 103311685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 103411685becSGavin Shan if (!res || !res->flags || 103511685becSGavin Shan res->start > res->end) 103611685becSGavin Shan continue; 103711685becSGavin Shan 103811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 103911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 104011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 104111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 104211685becSGavin Shan 104311685becSGavin Shan while (index < phb->ioda.total_pe && 104411685becSGavin Shan region.start <= region.end) { 104511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 104611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 104711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 104811685becSGavin Shan if (rc != OPAL_SUCCESS) { 104911685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 105011685becSGavin Shan "segment #%d to PE#%d\n", 105111685becSGavin Shan __func__, rc, index, pe->pe_number); 105211685becSGavin Shan break; 105311685becSGavin Shan } 105411685becSGavin Shan 105511685becSGavin Shan region.start += phb->ioda.io_segsize; 105611685becSGavin Shan index++; 105711685becSGavin Shan } 105811685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 10593fd47f06SBenjamin Herrenschmidt /* WARNING: Assumes M32 is mem region 0 in PHB. We need to 10603fd47f06SBenjamin Herrenschmidt * harden that algorithm when we start supporting M64 10613fd47f06SBenjamin Herrenschmidt */ 106211685becSGavin Shan region.start = res->start - 10633fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 106411685becSGavin Shan phb->ioda.m32_pci_base; 106511685becSGavin Shan region.end = res->end - 10663fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 106711685becSGavin Shan phb->ioda.m32_pci_base; 106811685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 106911685becSGavin Shan 107011685becSGavin Shan while (index < phb->ioda.total_pe && 107111685becSGavin Shan region.start <= region.end) { 107211685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 107311685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 107411685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 107511685becSGavin Shan if (rc != OPAL_SUCCESS) { 107611685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 107711685becSGavin Shan "segment#%d to PE#%d", 107811685becSGavin Shan __func__, rc, index, pe->pe_number); 107911685becSGavin Shan break; 108011685becSGavin Shan } 108111685becSGavin Shan 108211685becSGavin Shan region.start += phb->ioda.m32_segsize; 108311685becSGavin Shan index++; 108411685becSGavin Shan } 108511685becSGavin Shan } 108611685becSGavin Shan } 108711685becSGavin Shan } 108811685becSGavin Shan 1089cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 109011685becSGavin Shan { 109111685becSGavin Shan struct pci_controller *tmp, *hose; 109211685becSGavin Shan struct pnv_phb *phb; 109311685becSGavin Shan struct pnv_ioda_pe *pe; 109411685becSGavin Shan 109511685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 109611685becSGavin Shan phb = hose->private_data; 109711685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 109811685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 109911685becSGavin Shan } 110011685becSGavin Shan } 110111685becSGavin Shan } 110211685becSGavin Shan 1103cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 110413395c48SGavin Shan { 110513395c48SGavin Shan struct pci_controller *hose, *tmp; 1106db1266c8SGavin Shan struct pnv_phb *phb; 110713395c48SGavin Shan 110813395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 110913395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 1110db1266c8SGavin Shan 1111db1266c8SGavin Shan /* Mark the PHB initialization done */ 1112db1266c8SGavin Shan phb = hose->private_data; 1113db1266c8SGavin Shan phb->initialized = 1; 111413395c48SGavin Shan } 111513395c48SGavin Shan } 111613395c48SGavin Shan 111737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 111837c367f2SGavin Shan { 111937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 112037c367f2SGavin Shan struct pci_controller *hose, *tmp; 112137c367f2SGavin Shan struct pnv_phb *phb; 112237c367f2SGavin Shan char name[16]; 112337c367f2SGavin Shan 112437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 112537c367f2SGavin Shan phb = hose->private_data; 112637c367f2SGavin Shan 112737c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 112837c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 112937c367f2SGavin Shan if (!phb->dbgfs) 113037c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 113137c367f2SGavin Shan __func__, hose->global_number); 113237c367f2SGavin Shan } 113337c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 113437c367f2SGavin Shan } 113537c367f2SGavin Shan 1136cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 1137fb446ad0SGavin Shan { 1138fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 113911685becSGavin Shan pnv_pci_ioda_setup_seg(); 114013395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 1141e9cc17d4SGavin Shan 114237c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 114337c367f2SGavin Shan 1144e9cc17d4SGavin Shan #ifdef CONFIG_EEH 114588b6d14bSGavin Shan eeh_probe_mode_set(EEH_PROBE_MODE_DEV); 1146e9cc17d4SGavin Shan eeh_addr_cache_build(); 1147e9cc17d4SGavin Shan eeh_init(); 1148e9cc17d4SGavin Shan #endif 1149fb446ad0SGavin Shan } 1150fb446ad0SGavin Shan 1151271fd03aSGavin Shan /* 1152271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 1153271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 1154271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 1155271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 1156271fd03aSGavin Shan * 1MiB for memory) will be returned. 1157271fd03aSGavin Shan * 1158271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 1159271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 1160271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 1161271fd03aSGavin Shan * resources. 1162271fd03aSGavin Shan */ 1163271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1164271fd03aSGavin Shan unsigned long type) 1165271fd03aSGavin Shan { 1166271fd03aSGavin Shan struct pci_dev *bridge; 1167271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1168271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1169271fd03aSGavin Shan int num_pci_bridges = 0; 1170271fd03aSGavin Shan 1171271fd03aSGavin Shan bridge = bus->self; 1172271fd03aSGavin Shan while (bridge) { 1173271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1174271fd03aSGavin Shan num_pci_bridges++; 1175271fd03aSGavin Shan if (num_pci_bridges >= 2) 1176271fd03aSGavin Shan return 1; 1177271fd03aSGavin Shan } 1178271fd03aSGavin Shan 1179271fd03aSGavin Shan bridge = bridge->bus->self; 1180271fd03aSGavin Shan } 1181271fd03aSGavin Shan 1182271fd03aSGavin Shan /* We need support prefetchable memory window later */ 1183271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1184271fd03aSGavin Shan return phb->ioda.m32_segsize; 1185271fd03aSGavin Shan 1186271fd03aSGavin Shan return phb->ioda.io_segsize; 1187271fd03aSGavin Shan } 1188271fd03aSGavin Shan 1189184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1190184cd4a3SBenjamin Herrenschmidt * assign a PE 1191184cd4a3SBenjamin Herrenschmidt */ 1192cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1193184cd4a3SBenjamin Herrenschmidt { 1194db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1195db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1196db1266c8SGavin Shan struct pci_dn *pdn; 1197184cd4a3SBenjamin Herrenschmidt 1198db1266c8SGavin Shan /* The function is probably called while the PEs have 1199db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1200db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1201db1266c8SGavin Shan * PEs isn't ready. 1202db1266c8SGavin Shan */ 1203db1266c8SGavin Shan if (!phb->initialized) 1204db1266c8SGavin Shan return 0; 1205db1266c8SGavin Shan 1206b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1207184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1208184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1209db1266c8SGavin Shan 1210184cd4a3SBenjamin Herrenschmidt return 0; 1211184cd4a3SBenjamin Herrenschmidt } 1212184cd4a3SBenjamin Herrenschmidt 1213184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1214184cd4a3SBenjamin Herrenschmidt u32 devfn) 1215184cd4a3SBenjamin Herrenschmidt { 1216184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1217184cd4a3SBenjamin Herrenschmidt } 1218184cd4a3SBenjamin Herrenschmidt 121973ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 122073ed148aSBenjamin Herrenschmidt { 122173ed148aSBenjamin Herrenschmidt opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET, 122273ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 122373ed148aSBenjamin Herrenschmidt } 122473ed148aSBenjamin Herrenschmidt 1225e9cc17d4SGavin Shan void __init pnv_pci_init_ioda_phb(struct device_node *np, 1226e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 1227184cd4a3SBenjamin Herrenschmidt { 1228184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1229184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 12308184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 1231c681b93cSAlistair Popple const __be64 *prop64; 12323a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 1233f1b7cc3eSGavin Shan int len; 1234184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1235184cd4a3SBenjamin Herrenschmidt void *aux; 1236184cd4a3SBenjamin Herrenschmidt long rc; 1237184cd4a3SBenjamin Herrenschmidt 1238aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1239184cd4a3SBenjamin Herrenschmidt 1240184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1241184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1242184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1243184cd4a3SBenjamin Herrenschmidt return; 1244184cd4a3SBenjamin Herrenschmidt } 1245184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1246184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1247184cd4a3SBenjamin Herrenschmidt 1248184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 124958d714ecSGavin Shan if (!phb) { 125058d714ecSGavin Shan pr_err(" Out of memory !\n"); 125158d714ecSGavin Shan return; 125258d714ecSGavin Shan } 125358d714ecSGavin Shan 125458d714ecSGavin Shan /* Allocate PCI controller */ 1255184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 1256184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 125758d714ecSGavin Shan if (!phb->hose) { 125858d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 1259184cd4a3SBenjamin Herrenschmidt np->full_name); 126058d714ecSGavin Shan free_bootmem((unsigned long)phb, sizeof(struct pnv_phb)); 1261184cd4a3SBenjamin Herrenschmidt return; 1262184cd4a3SBenjamin Herrenschmidt } 1263184cd4a3SBenjamin Herrenschmidt 1264184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1265f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 1266f1b7cc3eSGavin Shan if (prop32 && len == 8) { 12673a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 12683a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 1269f1b7cc3eSGavin Shan } else { 1270f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 1271184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1272184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1273f1b7cc3eSGavin Shan } 1274184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1275e9cc17d4SGavin Shan phb->hub_id = hub_id; 1276184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1277aa0c033fSGavin Shan phb->type = ioda_type; 1278184cd4a3SBenjamin Herrenschmidt 1279cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1280cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1281cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1282f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1283aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1284cee72d5bSBenjamin Herrenschmidt else 1285cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1286cee72d5bSBenjamin Herrenschmidt 1287aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 12882f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 1289184cd4a3SBenjamin Herrenschmidt 1290aa0c033fSGavin Shan /* Get registers */ 1291184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1292184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1293184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1294184cd4a3SBenjamin Herrenschmidt 1295184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1296aa0c033fSGavin Shan phb->ioda.total_pe = 1; 129736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 129836954dc7SGavin Shan if (prop32) 12993a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 130036954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 130136954dc7SGavin Shan if (prop32) 130236954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 1303184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1304aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 1305184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 1306184cd4a3SBenjamin Herrenschmidt 1307184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 13083fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 1309184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 1310184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1311184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1312184cd4a3SBenjamin Herrenschmidt 1313c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 1314184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1315184cd4a3SBenjamin Herrenschmidt m32map_off = size; 1316e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 1317c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 1318c35d2a8cSGavin Shan iomap_off = size; 1319e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 1320c35d2a8cSGavin Shan } 1321184cd4a3SBenjamin Herrenschmidt pemap_off = size; 1322184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1323184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 1324184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 1325184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 1326184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 1327c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 1328184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 1329184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 133036954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 1331184cd4a3SBenjamin Herrenschmidt 13327ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1333184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 1334184cd4a3SBenjamin Herrenschmidt 1335184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 1336184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1337184cd4a3SBenjamin Herrenschmidt 1338184cd4a3SBenjamin Herrenschmidt /* Clear unusable m64 */ 1339184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].flags = 0; 1340184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].start = 0; 1341184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].end = 0; 1342184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].flags = 0; 1343184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].start = 0; 1344184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].end = 0; 1345184cd4a3SBenjamin Herrenschmidt 1346aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 1347184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1348184cd4a3SBenjamin Herrenschmidt window_type, 1349184cd4a3SBenjamin Herrenschmidt window_num, 1350184cd4a3SBenjamin Herrenschmidt starting_real_address, 1351184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1352184cd4a3SBenjamin Herrenschmidt segment_size); 1353184cd4a3SBenjamin Herrenschmidt #endif 1354184cd4a3SBenjamin Herrenschmidt 135536954dc7SGavin Shan pr_info(" %d (%d) PE's M32: 0x%x [segment=0x%x]" 135636954dc7SGavin Shan " IO: 0x%x [segment=0x%x]\n", 1357184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 135836954dc7SGavin Shan phb->ioda.reserved_pe, 1359184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size, phb->ioda.m32_segsize, 1360184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1361184cd4a3SBenjamin Herrenschmidt 1362184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 1363e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1364e9cc17d4SGavin Shan phb->eeh_ops = &ioda_eeh_ops; 1365e9cc17d4SGavin Shan #endif 1366184cd4a3SBenjamin Herrenschmidt 1367184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1368184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1369184cd4a3SBenjamin Herrenschmidt 1370184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1371184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1372cd15b048SBenjamin Herrenschmidt phb->dma_set_mask = pnv_pci_ioda_dma_set_mask; 1373184cd4a3SBenjamin Herrenschmidt 137473ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 137573ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 137673ed148aSBenjamin Herrenschmidt 1377184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1378184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1379184cd4a3SBenjamin Herrenschmidt 1380c40a4210SGavin Shan /* 1381c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1382c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1383c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1384c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1385c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1386184cd4a3SBenjamin Herrenschmidt */ 1387fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1388184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1389271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1390c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1391184cd4a3SBenjamin Herrenschmidt 1392184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1393f11fe552SBenjamin Herrenschmidt rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); 1394184cd4a3SBenjamin Herrenschmidt if (rc) 1395f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1396184cd4a3SBenjamin Herrenschmidt } 1397184cd4a3SBenjamin Herrenschmidt 139867975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 1399aa0c033fSGavin Shan { 1400e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 1401aa0c033fSGavin Shan } 1402aa0c033fSGavin Shan 1403184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 1404184cd4a3SBenjamin Herrenschmidt { 1405184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 1406c681b93cSAlistair Popple const __be64 *prop64; 1407184cd4a3SBenjamin Herrenschmidt u64 hub_id; 1408184cd4a3SBenjamin Herrenschmidt 1409184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1410184cd4a3SBenjamin Herrenschmidt 1411184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1412184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1413184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1414184cd4a3SBenjamin Herrenschmidt return; 1415184cd4a3SBenjamin Herrenschmidt } 1416184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 1417184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1418184cd4a3SBenjamin Herrenschmidt 1419184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 1420184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 1421184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 1422184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1423e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 1424184cd4a3SBenjamin Herrenschmidt } 1425184cd4a3SBenjamin Herrenschmidt } 1426