1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 1637c367f2SGavin Shan #include <linux/debugfs.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24184cd4a3SBenjamin Herrenschmidt 25184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 30fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 35137436c9SGavin Shan #include <asm/xics.h> 3637c367f2SGavin Shan #include <asm/debug.h> 37184cd4a3SBenjamin Herrenschmidt 38184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 39184cd4a3SBenjamin Herrenschmidt #include "pci.h" 40184cd4a3SBenjamin Herrenschmidt 41184cd4a3SBenjamin Herrenschmidt #define define_pe_printk_level(func, kern_level) \ 42184cd4a3SBenjamin Herrenschmidt static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ 43184cd4a3SBenjamin Herrenschmidt { \ 44184cd4a3SBenjamin Herrenschmidt struct va_format vaf; \ 45184cd4a3SBenjamin Herrenschmidt va_list args; \ 46490e078dSGavin Shan char pfix[32]; \ 47184cd4a3SBenjamin Herrenschmidt int r; \ 48184cd4a3SBenjamin Herrenschmidt \ 49184cd4a3SBenjamin Herrenschmidt va_start(args, fmt); \ 50184cd4a3SBenjamin Herrenschmidt \ 51184cd4a3SBenjamin Herrenschmidt vaf.fmt = fmt; \ 52184cd4a3SBenjamin Herrenschmidt vaf.va = &args; \ 53184cd4a3SBenjamin Herrenschmidt \ 54490e078dSGavin Shan if (pe->pdev) \ 55490e078dSGavin Shan strlcpy(pfix, dev_name(&pe->pdev->dev), \ 56490e078dSGavin Shan sizeof(pfix)); \ 57490e078dSGavin Shan else \ 58490e078dSGavin Shan sprintf(pfix, "%04x:%02x ", \ 59490e078dSGavin Shan pci_domain_nr(pe->pbus), \ 60490e078dSGavin Shan pe->pbus->number); \ 61490e078dSGavin Shan r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ 62490e078dSGavin Shan pfix, pe->pe_number, &vaf); \ 63490e078dSGavin Shan \ 64184cd4a3SBenjamin Herrenschmidt va_end(args); \ 65184cd4a3SBenjamin Herrenschmidt \ 66184cd4a3SBenjamin Herrenschmidt return r; \ 67184cd4a3SBenjamin Herrenschmidt } \ 68184cd4a3SBenjamin Herrenschmidt 69184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_err, KERN_ERR); 70184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_warn, KERN_WARNING); 71184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_info, KERN_INFO); 72184cd4a3SBenjamin Herrenschmidt 738e0a1611SAlexey Kardashevskiy /* 748e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 758e0a1611SAlexey Kardashevskiy * the architecture spec 768e0a1611SAlexey Kardashevskiy */ 778e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 788e0a1611SAlexey Kardashevskiy { 798e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 808e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 818e0a1611SAlexey Kardashevskiy } 828e0a1611SAlexey Kardashevskiy 83cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 84184cd4a3SBenjamin Herrenschmidt { 85184cd4a3SBenjamin Herrenschmidt unsigned long pe; 86184cd4a3SBenjamin Herrenschmidt 87184cd4a3SBenjamin Herrenschmidt do { 88184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 89184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 90184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 91184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 92184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 93184cd4a3SBenjamin Herrenschmidt 944cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 95184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 96184cd4a3SBenjamin Herrenschmidt return pe; 97184cd4a3SBenjamin Herrenschmidt } 98184cd4a3SBenjamin Herrenschmidt 99cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 100184cd4a3SBenjamin Herrenschmidt { 101184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 102184cd4a3SBenjamin Herrenschmidt 103184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 104184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 105184cd4a3SBenjamin Herrenschmidt } 106184cd4a3SBenjamin Herrenschmidt 107184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 108184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 109184cd4a3SBenjamin Herrenschmidt */ 110184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 111cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 112184cd4a3SBenjamin Herrenschmidt { 113184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 114184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 115b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 116184cd4a3SBenjamin Herrenschmidt 117184cd4a3SBenjamin Herrenschmidt if (!pdn) 118184cd4a3SBenjamin Herrenschmidt return NULL; 119184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 120184cd4a3SBenjamin Herrenschmidt return NULL; 121184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 122184cd4a3SBenjamin Herrenschmidt } 123184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 124184cd4a3SBenjamin Herrenschmidt 125cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 126184cd4a3SBenjamin Herrenschmidt { 127184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 128184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 129184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 130184cd4a3SBenjamin Herrenschmidt 131184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 132184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 133184cd4a3SBenjamin Herrenschmidt int count; 134184cd4a3SBenjamin Herrenschmidt 135184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 136184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 137184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 138fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 139b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 140fb446ad0SGavin Shan else 141fb446ad0SGavin Shan count = 1; 142fb446ad0SGavin Shan 143184cd4a3SBenjamin Herrenschmidt switch(count) { 144184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 145184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 146184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 147184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 148184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 149184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 150184cd4a3SBenjamin Herrenschmidt default: 151184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 152184cd4a3SBenjamin Herrenschmidt " unsupported\n", 153184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 154184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 155184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 156184cd4a3SBenjamin Herrenschmidt } 157184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 158184cd4a3SBenjamin Herrenschmidt } else { 159184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 160184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 161184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 162184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 163184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 164184cd4a3SBenjamin Herrenschmidt } 165184cd4a3SBenjamin Herrenschmidt 166631ad691SGavin Shan /* 167631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 168631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 169631ad691SGavin Shan * originated from the PE might contribute to other 170631ad691SGavin Shan * PEs. 171631ad691SGavin Shan */ 172184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 173184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 174184cd4a3SBenjamin Herrenschmidt if (rc) { 175184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 176184cd4a3SBenjamin Herrenschmidt return -ENXIO; 177184cd4a3SBenjamin Herrenschmidt } 178631ad691SGavin Shan 179631ad691SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 180631ad691SGavin Shan pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 181631ad691SGavin Shan if (rc) 182631ad691SGavin Shan pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc); 183184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 184184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 185184cd4a3SBenjamin Herrenschmidt 186184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 187184cd4a3SBenjamin Herrenschmidt while (parent) { 188b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(parent); 189184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 190184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 191cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 192184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 193184cd4a3SBenjamin Herrenschmidt } 194184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 195184cd4a3SBenjamin Herrenschmidt } 196184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 197184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 198184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 199184cd4a3SBenjamin Herrenschmidt 200184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 201184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 202184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 203184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 204184cd4a3SBenjamin Herrenschmidt pe->pe_number); 205184cd4a3SBenjamin Herrenschmidt if (rc) { 206184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 207184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 208184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 209184cd4a3SBenjamin Herrenschmidt } else { 210184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 211cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 212184cd4a3SBenjamin Herrenschmidt if (rc) { 213184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 214184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 215184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 216184cd4a3SBenjamin Herrenschmidt } 217184cd4a3SBenjamin Herrenschmidt } 218184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 219184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 220184cd4a3SBenjamin Herrenschmidt 221184cd4a3SBenjamin Herrenschmidt return 0; 222184cd4a3SBenjamin Herrenschmidt } 223184cd4a3SBenjamin Herrenschmidt 224cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 225184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 226184cd4a3SBenjamin Herrenschmidt { 227184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 228184cd4a3SBenjamin Herrenschmidt 2297ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 230184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 2317ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 232184cd4a3SBenjamin Herrenschmidt return; 233184cd4a3SBenjamin Herrenschmidt } 234184cd4a3SBenjamin Herrenschmidt } 2357ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 236184cd4a3SBenjamin Herrenschmidt } 237184cd4a3SBenjamin Herrenschmidt 238184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 239184cd4a3SBenjamin Herrenschmidt { 240184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 241184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 242184cd4a3SBenjamin Herrenschmidt */ 243184cd4a3SBenjamin Herrenschmidt 244184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 245184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 246184cd4a3SBenjamin Herrenschmidt return 0; 247184cd4a3SBenjamin Herrenschmidt 248184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 249184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 250184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 251184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 252184cd4a3SBenjamin Herrenschmidt return 3; 253184cd4a3SBenjamin Herrenschmidt 254184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 255184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 256184cd4a3SBenjamin Herrenschmidt return 15; 257184cd4a3SBenjamin Herrenschmidt 258184cd4a3SBenjamin Herrenschmidt /* Default */ 259184cd4a3SBenjamin Herrenschmidt return 10; 260184cd4a3SBenjamin Herrenschmidt } 261184cd4a3SBenjamin Herrenschmidt 262fb446ad0SGavin Shan #if 0 263cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 264184cd4a3SBenjamin Herrenschmidt { 265184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 266184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 267b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 268184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 269184cd4a3SBenjamin Herrenschmidt int pe_num; 270184cd4a3SBenjamin Herrenschmidt 271184cd4a3SBenjamin Herrenschmidt if (!pdn) { 272184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 273184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 274184cd4a3SBenjamin Herrenschmidt return NULL; 275184cd4a3SBenjamin Herrenschmidt } 276184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 277184cd4a3SBenjamin Herrenschmidt return NULL; 278184cd4a3SBenjamin Herrenschmidt 279184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 280184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 281184cd4a3SBenjamin Herrenschmidt pe_num = 0; 282184cd4a3SBenjamin Herrenschmidt else 283184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 284184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 285184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 286184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 287184cd4a3SBenjamin Herrenschmidt return NULL; 288184cd4a3SBenjamin Herrenschmidt } 289184cd4a3SBenjamin Herrenschmidt 290184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 291184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 292184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 293184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 294184cd4a3SBenjamin Herrenschmidt * 295184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 296184cd4a3SBenjamin Herrenschmidt */ 297184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 298184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 299184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 300184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 301184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 302184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 303184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 304184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 305184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 306184cd4a3SBenjamin Herrenschmidt 307184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 308184cd4a3SBenjamin Herrenschmidt 309184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 310184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 311184cd4a3SBenjamin Herrenschmidt if (pe_num) 312184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 313184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 314184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 315184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 316184cd4a3SBenjamin Herrenschmidt return NULL; 317184cd4a3SBenjamin Herrenschmidt } 318184cd4a3SBenjamin Herrenschmidt 319184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 320184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 321184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 322184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 323184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 324184cd4a3SBenjamin Herrenschmidt } 325184cd4a3SBenjamin Herrenschmidt 326184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 327184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 328184cd4a3SBenjamin Herrenschmidt 329184cd4a3SBenjamin Herrenschmidt return pe; 330184cd4a3SBenjamin Herrenschmidt } 331fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 332184cd4a3SBenjamin Herrenschmidt 333184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 334184cd4a3SBenjamin Herrenschmidt { 335184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 336184cd4a3SBenjamin Herrenschmidt 337184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 338b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 339184cd4a3SBenjamin Herrenschmidt 340184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 341184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 342184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 343184cd4a3SBenjamin Herrenschmidt continue; 344184cd4a3SBenjamin Herrenschmidt } 345184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 346184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 347184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 348184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 349fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 350184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 351184cd4a3SBenjamin Herrenschmidt } 352184cd4a3SBenjamin Herrenschmidt } 353184cd4a3SBenjamin Herrenschmidt 354fb446ad0SGavin Shan /* 355fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 356fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 357fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 358fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 359fb446ad0SGavin Shan */ 360cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 361184cd4a3SBenjamin Herrenschmidt { 362fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 363184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 364184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 365184cd4a3SBenjamin Herrenschmidt int pe_num; 366184cd4a3SBenjamin Herrenschmidt 367184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 368184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 369fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 370fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 371184cd4a3SBenjamin Herrenschmidt return; 372184cd4a3SBenjamin Herrenschmidt } 373184cd4a3SBenjamin Herrenschmidt 374184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 375fb446ad0SGavin Shan pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 376184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 377184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 378184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 379184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 380b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 381184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 382184cd4a3SBenjamin Herrenschmidt 383fb446ad0SGavin Shan if (all) 384fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 385fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 386fb446ad0SGavin Shan else 387fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 388fb446ad0SGavin Shan bus->busn_res.start, pe_num); 389184cd4a3SBenjamin Herrenschmidt 390184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 391184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 392184cd4a3SBenjamin Herrenschmidt if (pe_num) 393184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 394184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 395184cd4a3SBenjamin Herrenschmidt return; 396184cd4a3SBenjamin Herrenschmidt } 397184cd4a3SBenjamin Herrenschmidt 398184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 399184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 400184cd4a3SBenjamin Herrenschmidt 4017ebdf956SGavin Shan /* Put PE to the list */ 4027ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 4037ebdf956SGavin Shan 404184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 405184cd4a3SBenjamin Herrenschmidt * below the bridge 406184cd4a3SBenjamin Herrenschmidt */ 407184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 408184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 409184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 410184cd4a3SBenjamin Herrenschmidt } 411184cd4a3SBenjamin Herrenschmidt 412184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 413184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 414184cd4a3SBenjamin Herrenschmidt } 415184cd4a3SBenjamin Herrenschmidt 416cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 417184cd4a3SBenjamin Herrenschmidt { 418184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 419fb446ad0SGavin Shan 420fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 421184cd4a3SBenjamin Herrenschmidt 422184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 423fb446ad0SGavin Shan if (dev->subordinate) { 42462f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 425fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 426fb446ad0SGavin Shan else 427184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 428184cd4a3SBenjamin Herrenschmidt } 429184cd4a3SBenjamin Herrenschmidt } 430fb446ad0SGavin Shan } 431fb446ad0SGavin Shan 432fb446ad0SGavin Shan /* 433fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 434fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 435fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 436fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 437fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 438fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 439fb446ad0SGavin Shan */ 440cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 441fb446ad0SGavin Shan { 442fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 443fb446ad0SGavin Shan 444fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 445fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 446fb446ad0SGavin Shan } 447fb446ad0SGavin Shan } 448184cd4a3SBenjamin Herrenschmidt 449959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 450184cd4a3SBenjamin Herrenschmidt { 451b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 452959c9bddSGavin Shan struct pnv_ioda_pe *pe; 453184cd4a3SBenjamin Herrenschmidt 454959c9bddSGavin Shan /* 455959c9bddSGavin Shan * The function can be called while the PE# 456959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 457959c9bddSGavin Shan * case. 458959c9bddSGavin Shan */ 459959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 460959c9bddSGavin Shan return; 461184cd4a3SBenjamin Herrenschmidt 462959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 463959c9bddSGavin Shan set_iommu_table_base(&pdev->dev, &pe->tce32_table); 464184cd4a3SBenjamin Herrenschmidt } 465184cd4a3SBenjamin Herrenschmidt 46674251fe2SBenjamin Herrenschmidt static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 46774251fe2SBenjamin Herrenschmidt { 46874251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 46974251fe2SBenjamin Herrenschmidt 47074251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 47174251fe2SBenjamin Herrenschmidt set_iommu_table_base(&dev->dev, &pe->tce32_table); 47274251fe2SBenjamin Herrenschmidt if (dev->subordinate) 47374251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, dev->subordinate); 47474251fe2SBenjamin Herrenschmidt } 47574251fe2SBenjamin Herrenschmidt } 47674251fe2SBenjamin Herrenschmidt 4778e0a1611SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, 4788e0a1611SAlexey Kardashevskiy struct iommu_table *tbl, 4793ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 4804cce9550SGavin Shan { 4813ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 4823ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 4833ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 4844cce9550SGavin Shan unsigned long start, end, inc; 4854cce9550SGavin Shan 4864cce9550SGavin Shan start = __pa(startp); 4874cce9550SGavin Shan end = __pa(endp); 4884cce9550SGavin Shan 4894cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 4904cce9550SGavin Shan if (tbl->it_busno) { 4914cce9550SGavin Shan start <<= 12; 4924cce9550SGavin Shan end <<= 12; 4934cce9550SGavin Shan inc = 128 << 12; 4944cce9550SGavin Shan start |= tbl->it_busno; 4954cce9550SGavin Shan end |= tbl->it_busno; 4964cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 4974cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 4984cce9550SGavin Shan start |= (1ull << 63); 4994cce9550SGavin Shan end |= (1ull << 63); 5004cce9550SGavin Shan inc = 16; 5014cce9550SGavin Shan } else { 5024cce9550SGavin Shan /* Default (older HW) */ 5034cce9550SGavin Shan inc = 128; 5044cce9550SGavin Shan } 5054cce9550SGavin Shan 5064cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 5074cce9550SGavin Shan 5084cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 5094cce9550SGavin Shan while (start <= end) { 5108e0a1611SAlexey Kardashevskiy if (rm) 5113ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 5128e0a1611SAlexey Kardashevskiy else 5133a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 5144cce9550SGavin Shan start += inc; 5154cce9550SGavin Shan } 5164cce9550SGavin Shan 5174cce9550SGavin Shan /* 5184cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 5194cce9550SGavin Shan * and we don't care on free() 5204cce9550SGavin Shan */ 5214cce9550SGavin Shan } 5224cce9550SGavin Shan 5234cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 5244cce9550SGavin Shan struct iommu_table *tbl, 5253ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 5264cce9550SGavin Shan { 5274cce9550SGavin Shan unsigned long start, end, inc; 5283ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 5293ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 5303ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 5314cce9550SGavin Shan 5324cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 5334cce9550SGavin Shan start = 0x2ul << 60; 5344cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 5354cce9550SGavin Shan end = start; 5364cce9550SGavin Shan 5374cce9550SGavin Shan /* Figure out the start, end and step */ 5384cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 5394cce9550SGavin Shan start |= (inc << 12); 5404cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 5414cce9550SGavin Shan end |= (inc << 12); 5424cce9550SGavin Shan inc = (0x1ul << 12); 5434cce9550SGavin Shan mb(); 5444cce9550SGavin Shan 5454cce9550SGavin Shan while (start <= end) { 5468e0a1611SAlexey Kardashevskiy if (rm) 5473ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 5488e0a1611SAlexey Kardashevskiy else 5493a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 5504cce9550SGavin Shan start += inc; 5514cce9550SGavin Shan } 5524cce9550SGavin Shan } 5534cce9550SGavin Shan 5544cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 5553ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 5564cce9550SGavin Shan { 5574cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 5584cce9550SGavin Shan tce32_table); 5594cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 5604cce9550SGavin Shan 5614cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 5628e0a1611SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); 5634cce9550SGavin Shan else 5648e0a1611SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); 5654cce9550SGavin Shan } 5664cce9550SGavin Shan 567cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 568cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 569184cd4a3SBenjamin Herrenschmidt unsigned int segs) 570184cd4a3SBenjamin Herrenschmidt { 571184cd4a3SBenjamin Herrenschmidt 572184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 573184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 574184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 575184cd4a3SBenjamin Herrenschmidt unsigned int i; 576184cd4a3SBenjamin Herrenschmidt int64_t rc; 577184cd4a3SBenjamin Herrenschmidt void *addr; 578184cd4a3SBenjamin Herrenschmidt 579184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 580184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 581184cd4a3SBenjamin Herrenschmidt 582184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 583184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 584184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 585184cd4a3SBenjamin Herrenschmidt 586184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 587184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 588184cd4a3SBenjamin Herrenschmidt return; 589184cd4a3SBenjamin Herrenschmidt 590184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 591184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 592184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 593184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 594184cd4a3SBenjamin Herrenschmidt 595184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 596184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 597184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 598184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 599184cd4a3SBenjamin Herrenschmidt */ 600184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 601184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 602184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 603184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 604184cd4a3SBenjamin Herrenschmidt goto fail; 605184cd4a3SBenjamin Herrenschmidt } 606184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 607184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 608184cd4a3SBenjamin Herrenschmidt 609184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 610184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 611184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 612184cd4a3SBenjamin Herrenschmidt pe->pe_number, 613184cd4a3SBenjamin Herrenschmidt base + i, 1, 614184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 615184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 616184cd4a3SBenjamin Herrenschmidt if (rc) { 617184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 618184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 619184cd4a3SBenjamin Herrenschmidt goto fail; 620184cd4a3SBenjamin Herrenschmidt } 621184cd4a3SBenjamin Herrenschmidt } 622184cd4a3SBenjamin Herrenschmidt 623184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 624184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 625184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 626184cd4a3SBenjamin Herrenschmidt base << 28); 627184cd4a3SBenjamin Herrenschmidt 628184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 629184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 630184cd4a3SBenjamin Herrenschmidt if (swinvp) { 631184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 632184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 633184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 634184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 635184cd4a3SBenjamin Herrenschmidt */ 636184cd4a3SBenjamin Herrenschmidt tbl->it_busno = 0; 6378e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 6388e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 6398e0a1611SAlexey Kardashevskiy 8); 640373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE | 641373f5657SGavin Shan TCE_PCI_SWINV_PAIR; 642184cd4a3SBenjamin Herrenschmidt } 643184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 6444e13c1acSAlexey Kardashevskiy iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number); 645184cd4a3SBenjamin Herrenschmidt 64674251fe2SBenjamin Herrenschmidt if (pe->pdev) 64774251fe2SBenjamin Herrenschmidt set_iommu_table_base(&pe->pdev->dev, tbl); 64874251fe2SBenjamin Herrenschmidt else 64974251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, pe->pbus); 65074251fe2SBenjamin Herrenschmidt 651184cd4a3SBenjamin Herrenschmidt return; 652184cd4a3SBenjamin Herrenschmidt fail: 653184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 654184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 655184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 656184cd4a3SBenjamin Herrenschmidt if (tce_mem) 657184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 658184cd4a3SBenjamin Herrenschmidt } 659184cd4a3SBenjamin Herrenschmidt 660373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 661373f5657SGavin Shan struct pnv_ioda_pe *pe) 662373f5657SGavin Shan { 663373f5657SGavin Shan struct page *tce_mem = NULL; 664373f5657SGavin Shan void *addr; 665373f5657SGavin Shan const __be64 *swinvp; 666373f5657SGavin Shan struct iommu_table *tbl; 667373f5657SGavin Shan unsigned int tce_table_size, end; 668373f5657SGavin Shan int64_t rc; 669373f5657SGavin Shan 670373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 671373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 672373f5657SGavin Shan return; 673373f5657SGavin Shan 674373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 675373f5657SGavin Shan pe->tce32_seg = 0; 676373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 677373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 678373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 679373f5657SGavin Shan end); 680373f5657SGavin Shan 681373f5657SGavin Shan /* Allocate TCE table */ 682373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 683373f5657SGavin Shan get_order(tce_table_size)); 684373f5657SGavin Shan if (!tce_mem) { 685373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 686373f5657SGavin Shan goto fail; 687373f5657SGavin Shan } 688373f5657SGavin Shan addr = page_address(tce_mem); 689373f5657SGavin Shan memset(addr, 0, tce_table_size); 690373f5657SGavin Shan 691373f5657SGavin Shan /* 692373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 693373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 694373f5657SGavin Shan */ 695373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 696373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 697373f5657SGavin Shan tce_table_size, 0x1000); 698373f5657SGavin Shan if (rc) { 699373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 700373f5657SGavin Shan " err %ld\n", rc); 701373f5657SGavin Shan goto fail; 702373f5657SGavin Shan } 703373f5657SGavin Shan 704373f5657SGavin Shan /* Setup linux iommu table */ 705373f5657SGavin Shan tbl = &pe->tce32_table; 706373f5657SGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0); 707373f5657SGavin Shan 708373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 709373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 710373f5657SGavin Shan if (swinvp) { 711373f5657SGavin Shan /* We need a couple more fields -- an address and a data 712373f5657SGavin Shan * to or. Since the bus is only printed out on table free 713373f5657SGavin Shan * errors, and on the first pass the data will be a relative 714373f5657SGavin Shan * bus number, print that out instead. 715373f5657SGavin Shan */ 716373f5657SGavin Shan tbl->it_busno = 0; 7178e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 7188e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 7198e0a1611SAlexey Kardashevskiy 8); 720373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; 721373f5657SGavin Shan } 722373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 723373f5657SGavin Shan 72474251fe2SBenjamin Herrenschmidt if (pe->pdev) 72574251fe2SBenjamin Herrenschmidt set_iommu_table_base(&pe->pdev->dev, tbl); 72674251fe2SBenjamin Herrenschmidt else 72774251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, pe->pbus); 72874251fe2SBenjamin Herrenschmidt 729373f5657SGavin Shan return; 730373f5657SGavin Shan fail: 731373f5657SGavin Shan if (pe->tce32_seg >= 0) 732373f5657SGavin Shan pe->tce32_seg = -1; 733373f5657SGavin Shan if (tce_mem) 734373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 735373f5657SGavin Shan } 736373f5657SGavin Shan 737cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 738184cd4a3SBenjamin Herrenschmidt { 739184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 740184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 741184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 742184cd4a3SBenjamin Herrenschmidt 743184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 744184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 745184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 746184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 747184cd4a3SBenjamin Herrenschmidt */ 748184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 749184cd4a3SBenjamin Herrenschmidt residual = 0; 750184cd4a3SBenjamin Herrenschmidt else 751184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 752184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 753184cd4a3SBenjamin Herrenschmidt 754184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 755184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 756184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 757184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 758184cd4a3SBenjamin Herrenschmidt 759184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 760184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 761184cd4a3SBenjamin Herrenschmidt * weight 762184cd4a3SBenjamin Herrenschmidt */ 763184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 764184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 765184cd4a3SBenjamin Herrenschmidt base = 0; 7667ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 767184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 768184cd4a3SBenjamin Herrenschmidt continue; 769184cd4a3SBenjamin Herrenschmidt if (!remaining) { 770184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 771184cd4a3SBenjamin Herrenschmidt continue; 772184cd4a3SBenjamin Herrenschmidt } 773184cd4a3SBenjamin Herrenschmidt segs = 1; 774184cd4a3SBenjamin Herrenschmidt if (residual) { 775184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 776184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 777184cd4a3SBenjamin Herrenschmidt segs = remaining; 778184cd4a3SBenjamin Herrenschmidt } 779373f5657SGavin Shan 780373f5657SGavin Shan /* 781373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 782373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 783373f5657SGavin Shan * the specific PE. 784373f5657SGavin Shan */ 785373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 786184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 787184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 788184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 789373f5657SGavin Shan } else { 790373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 791373f5657SGavin Shan segs = 0; 792373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 793373f5657SGavin Shan } 794373f5657SGavin Shan 795184cd4a3SBenjamin Herrenschmidt remaining -= segs; 796184cd4a3SBenjamin Herrenschmidt base += segs; 797184cd4a3SBenjamin Herrenschmidt } 798184cd4a3SBenjamin Herrenschmidt } 799184cd4a3SBenjamin Herrenschmidt 800184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 801137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 802137436c9SGavin Shan { 803137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 804137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 805137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 806137436c9SGavin Shan ioda.irq_chip); 807137436c9SGavin Shan int64_t rc; 808137436c9SGavin Shan 809137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 810137436c9SGavin Shan WARN_ON_ONCE(rc); 811137436c9SGavin Shan 812137436c9SGavin Shan icp_native_eoi(d); 813137436c9SGavin Shan } 814137436c9SGavin Shan 815184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 816137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 817137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 818184cd4a3SBenjamin Herrenschmidt { 819184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 820b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 821137436c9SGavin Shan struct irq_data *idata; 822137436c9SGavin Shan struct irq_chip *ichip; 823184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 8243a1a4661SBenjamin Herrenschmidt __be32 data; 825184cd4a3SBenjamin Herrenschmidt int rc; 826184cd4a3SBenjamin Herrenschmidt 827184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 828184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 829184cd4a3SBenjamin Herrenschmidt return -ENXIO; 830184cd4a3SBenjamin Herrenschmidt 831184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 832184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 833184cd4a3SBenjamin Herrenschmidt return -ENXIO; 834184cd4a3SBenjamin Herrenschmidt 835b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 836b72c1f65SBenjamin Herrenschmidt if (pdn && pdn->force_32bit_msi) 837b72c1f65SBenjamin Herrenschmidt is_64 = 0; 838b72c1f65SBenjamin Herrenschmidt 839184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 840184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 841184cd4a3SBenjamin Herrenschmidt if (rc) { 842184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 843184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 844184cd4a3SBenjamin Herrenschmidt return -EIO; 845184cd4a3SBenjamin Herrenschmidt } 846184cd4a3SBenjamin Herrenschmidt 847184cd4a3SBenjamin Herrenschmidt if (is_64) { 8483a1a4661SBenjamin Herrenschmidt __be64 addr64; 8493a1a4661SBenjamin Herrenschmidt 850184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 851184cd4a3SBenjamin Herrenschmidt &addr64, &data); 852184cd4a3SBenjamin Herrenschmidt if (rc) { 853184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 854184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 855184cd4a3SBenjamin Herrenschmidt return -EIO; 856184cd4a3SBenjamin Herrenschmidt } 8573a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 8583a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 859184cd4a3SBenjamin Herrenschmidt } else { 8603a1a4661SBenjamin Herrenschmidt __be32 addr32; 8613a1a4661SBenjamin Herrenschmidt 862184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 863184cd4a3SBenjamin Herrenschmidt &addr32, &data); 864184cd4a3SBenjamin Herrenschmidt if (rc) { 865184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 866184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 867184cd4a3SBenjamin Herrenschmidt return -EIO; 868184cd4a3SBenjamin Herrenschmidt } 869184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 8703a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 871184cd4a3SBenjamin Herrenschmidt } 8723a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 873184cd4a3SBenjamin Herrenschmidt 874137436c9SGavin Shan /* 875137436c9SGavin Shan * Change the IRQ chip for the MSI interrupts on PHB3. 876137436c9SGavin Shan * The corresponding IRQ chip should be populated for 877137436c9SGavin Shan * the first time. 878137436c9SGavin Shan */ 879137436c9SGavin Shan if (phb->type == PNV_PHB_IODA2) { 880137436c9SGavin Shan if (!phb->ioda.irq_chip_init) { 881137436c9SGavin Shan idata = irq_get_irq_data(virq); 882137436c9SGavin Shan ichip = irq_data_get_irq_chip(idata); 883137436c9SGavin Shan phb->ioda.irq_chip_init = 1; 884137436c9SGavin Shan phb->ioda.irq_chip = *ichip; 885137436c9SGavin Shan phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 886137436c9SGavin Shan } 887137436c9SGavin Shan 888137436c9SGavin Shan irq_set_chip(virq, &phb->ioda.irq_chip); 889137436c9SGavin Shan } 890137436c9SGavin Shan 891184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 892184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 893184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 894184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 895184cd4a3SBenjamin Herrenschmidt 896184cd4a3SBenjamin Herrenschmidt return 0; 897184cd4a3SBenjamin Herrenschmidt } 898184cd4a3SBenjamin Herrenschmidt 899184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 900184cd4a3SBenjamin Herrenschmidt { 901fb1b55d6SGavin Shan unsigned int count; 902184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 903184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 904184cd4a3SBenjamin Herrenschmidt if (!prop) { 905184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 906184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 907184cd4a3SBenjamin Herrenschmidt } 908184cd4a3SBenjamin Herrenschmidt if (!prop) 909184cd4a3SBenjamin Herrenschmidt return; 910184cd4a3SBenjamin Herrenschmidt 911184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 912fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 913fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 914184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 915184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 916184cd4a3SBenjamin Herrenschmidt return; 917184cd4a3SBenjamin Herrenschmidt } 918fb1b55d6SGavin Shan 919184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 920184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 921184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 922fb1b55d6SGavin Shan count, phb->msi_base); 923184cd4a3SBenjamin Herrenschmidt } 924184cd4a3SBenjamin Herrenschmidt #else 925184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 926184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 927184cd4a3SBenjamin Herrenschmidt 92811685becSGavin Shan /* 92911685becSGavin Shan * This function is supposed to be called on basis of PE from top 93011685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 93111685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 93211685becSGavin Shan */ 933cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 93411685becSGavin Shan struct pnv_ioda_pe *pe) 93511685becSGavin Shan { 93611685becSGavin Shan struct pnv_phb *phb = hose->private_data; 93711685becSGavin Shan struct pci_bus_region region; 93811685becSGavin Shan struct resource *res; 93911685becSGavin Shan int i, index; 94011685becSGavin Shan int rc; 94111685becSGavin Shan 94211685becSGavin Shan /* 94311685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 94411685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 94511685becSGavin Shan * be figured out later. 94611685becSGavin Shan */ 94711685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 94811685becSGavin Shan 94911685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 95011685becSGavin Shan if (!res || !res->flags || 95111685becSGavin Shan res->start > res->end) 95211685becSGavin Shan continue; 95311685becSGavin Shan 95411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 95511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 95611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 95711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 95811685becSGavin Shan 95911685becSGavin Shan while (index < phb->ioda.total_pe && 96011685becSGavin Shan region.start <= region.end) { 96111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 96211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 96311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 96411685becSGavin Shan if (rc != OPAL_SUCCESS) { 96511685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 96611685becSGavin Shan "segment #%d to PE#%d\n", 96711685becSGavin Shan __func__, rc, index, pe->pe_number); 96811685becSGavin Shan break; 96911685becSGavin Shan } 97011685becSGavin Shan 97111685becSGavin Shan region.start += phb->ioda.io_segsize; 97211685becSGavin Shan index++; 97311685becSGavin Shan } 97411685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 9753fd47f06SBenjamin Herrenschmidt /* WARNING: Assumes M32 is mem region 0 in PHB. We need to 9763fd47f06SBenjamin Herrenschmidt * harden that algorithm when we start supporting M64 9773fd47f06SBenjamin Herrenschmidt */ 97811685becSGavin Shan region.start = res->start - 9793fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 98011685becSGavin Shan phb->ioda.m32_pci_base; 98111685becSGavin Shan region.end = res->end - 9823fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 98311685becSGavin Shan phb->ioda.m32_pci_base; 98411685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 98511685becSGavin Shan 98611685becSGavin Shan while (index < phb->ioda.total_pe && 98711685becSGavin Shan region.start <= region.end) { 98811685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 98911685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 99011685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 99111685becSGavin Shan if (rc != OPAL_SUCCESS) { 99211685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 99311685becSGavin Shan "segment#%d to PE#%d", 99411685becSGavin Shan __func__, rc, index, pe->pe_number); 99511685becSGavin Shan break; 99611685becSGavin Shan } 99711685becSGavin Shan 99811685becSGavin Shan region.start += phb->ioda.m32_segsize; 99911685becSGavin Shan index++; 100011685becSGavin Shan } 100111685becSGavin Shan } 100211685becSGavin Shan } 100311685becSGavin Shan } 100411685becSGavin Shan 1005cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 100611685becSGavin Shan { 100711685becSGavin Shan struct pci_controller *tmp, *hose; 100811685becSGavin Shan struct pnv_phb *phb; 100911685becSGavin Shan struct pnv_ioda_pe *pe; 101011685becSGavin Shan 101111685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 101211685becSGavin Shan phb = hose->private_data; 101311685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 101411685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 101511685becSGavin Shan } 101611685becSGavin Shan } 101711685becSGavin Shan } 101811685becSGavin Shan 1019cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 102013395c48SGavin Shan { 102113395c48SGavin Shan struct pci_controller *hose, *tmp; 1022db1266c8SGavin Shan struct pnv_phb *phb; 102313395c48SGavin Shan 102413395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 102513395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 1026db1266c8SGavin Shan 1027db1266c8SGavin Shan /* Mark the PHB initialization done */ 1028db1266c8SGavin Shan phb = hose->private_data; 1029db1266c8SGavin Shan phb->initialized = 1; 103013395c48SGavin Shan } 103113395c48SGavin Shan } 103213395c48SGavin Shan 103337c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 103437c367f2SGavin Shan { 103537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 103637c367f2SGavin Shan struct pci_controller *hose, *tmp; 103737c367f2SGavin Shan struct pnv_phb *phb; 103837c367f2SGavin Shan char name[16]; 103937c367f2SGavin Shan 104037c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 104137c367f2SGavin Shan phb = hose->private_data; 104237c367f2SGavin Shan 104337c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 104437c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 104537c367f2SGavin Shan if (!phb->dbgfs) 104637c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 104737c367f2SGavin Shan __func__, hose->global_number); 104837c367f2SGavin Shan } 104937c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 105037c367f2SGavin Shan } 105137c367f2SGavin Shan 1052cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 1053fb446ad0SGavin Shan { 1054fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 105511685becSGavin Shan pnv_pci_ioda_setup_seg(); 105613395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 1057e9cc17d4SGavin Shan 105837c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 105937c367f2SGavin Shan 1060e9cc17d4SGavin Shan #ifdef CONFIG_EEH 106188b6d14bSGavin Shan eeh_probe_mode_set(EEH_PROBE_MODE_DEV); 1062e9cc17d4SGavin Shan eeh_addr_cache_build(); 1063e9cc17d4SGavin Shan eeh_init(); 1064e9cc17d4SGavin Shan #endif 1065fb446ad0SGavin Shan } 1066fb446ad0SGavin Shan 1067271fd03aSGavin Shan /* 1068271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 1069271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 1070271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 1071271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 1072271fd03aSGavin Shan * 1MiB for memory) will be returned. 1073271fd03aSGavin Shan * 1074271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 1075271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 1076271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 1077271fd03aSGavin Shan * resources. 1078271fd03aSGavin Shan */ 1079271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1080271fd03aSGavin Shan unsigned long type) 1081271fd03aSGavin Shan { 1082271fd03aSGavin Shan struct pci_dev *bridge; 1083271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1084271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1085271fd03aSGavin Shan int num_pci_bridges = 0; 1086271fd03aSGavin Shan 1087271fd03aSGavin Shan bridge = bus->self; 1088271fd03aSGavin Shan while (bridge) { 1089271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1090271fd03aSGavin Shan num_pci_bridges++; 1091271fd03aSGavin Shan if (num_pci_bridges >= 2) 1092271fd03aSGavin Shan return 1; 1093271fd03aSGavin Shan } 1094271fd03aSGavin Shan 1095271fd03aSGavin Shan bridge = bridge->bus->self; 1096271fd03aSGavin Shan } 1097271fd03aSGavin Shan 1098271fd03aSGavin Shan /* We need support prefetchable memory window later */ 1099271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1100271fd03aSGavin Shan return phb->ioda.m32_segsize; 1101271fd03aSGavin Shan 1102271fd03aSGavin Shan return phb->ioda.io_segsize; 1103271fd03aSGavin Shan } 1104271fd03aSGavin Shan 1105184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1106184cd4a3SBenjamin Herrenschmidt * assign a PE 1107184cd4a3SBenjamin Herrenschmidt */ 1108cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1109184cd4a3SBenjamin Herrenschmidt { 1110db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1111db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1112db1266c8SGavin Shan struct pci_dn *pdn; 1113184cd4a3SBenjamin Herrenschmidt 1114db1266c8SGavin Shan /* The function is probably called while the PEs have 1115db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1116db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1117db1266c8SGavin Shan * PEs isn't ready. 1118db1266c8SGavin Shan */ 1119db1266c8SGavin Shan if (!phb->initialized) 1120db1266c8SGavin Shan return 0; 1121db1266c8SGavin Shan 1122b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1123184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1124184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1125db1266c8SGavin Shan 1126184cd4a3SBenjamin Herrenschmidt return 0; 1127184cd4a3SBenjamin Herrenschmidt } 1128184cd4a3SBenjamin Herrenschmidt 1129184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1130184cd4a3SBenjamin Herrenschmidt u32 devfn) 1131184cd4a3SBenjamin Herrenschmidt { 1132184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1133184cd4a3SBenjamin Herrenschmidt } 1134184cd4a3SBenjamin Herrenschmidt 113573ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 113673ed148aSBenjamin Herrenschmidt { 113773ed148aSBenjamin Herrenschmidt opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET, 113873ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 113973ed148aSBenjamin Herrenschmidt } 114073ed148aSBenjamin Herrenschmidt 1141e9cc17d4SGavin Shan void __init pnv_pci_init_ioda_phb(struct device_node *np, 1142e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 1143184cd4a3SBenjamin Herrenschmidt { 1144184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1145184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 1146184cd4a3SBenjamin Herrenschmidt unsigned long size, m32map_off, iomap_off, pemap_off; 1147c681b93cSAlistair Popple const __be64 *prop64; 11483a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 1149f1b7cc3eSGavin Shan int len; 1150184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1151184cd4a3SBenjamin Herrenschmidt void *aux; 1152184cd4a3SBenjamin Herrenschmidt long rc; 1153184cd4a3SBenjamin Herrenschmidt 1154aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1155184cd4a3SBenjamin Herrenschmidt 1156184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1157184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1158184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1159184cd4a3SBenjamin Herrenschmidt return; 1160184cd4a3SBenjamin Herrenschmidt } 1161184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1162184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1163184cd4a3SBenjamin Herrenschmidt 1164184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 116558d714ecSGavin Shan if (!phb) { 116658d714ecSGavin Shan pr_err(" Out of memory !\n"); 116758d714ecSGavin Shan return; 116858d714ecSGavin Shan } 116958d714ecSGavin Shan 117058d714ecSGavin Shan /* Allocate PCI controller */ 1171184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 1172184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 117358d714ecSGavin Shan if (!phb->hose) { 117458d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 1175184cd4a3SBenjamin Herrenschmidt np->full_name); 117658d714ecSGavin Shan free_bootmem((unsigned long)phb, sizeof(struct pnv_phb)); 1177184cd4a3SBenjamin Herrenschmidt return; 1178184cd4a3SBenjamin Herrenschmidt } 1179184cd4a3SBenjamin Herrenschmidt 1180184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1181f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 1182f1b7cc3eSGavin Shan if (prop32 && len == 8) { 11833a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 11843a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 1185f1b7cc3eSGavin Shan } else { 1186f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 1187184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1188184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1189f1b7cc3eSGavin Shan } 1190184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1191e9cc17d4SGavin Shan phb->hub_id = hub_id; 1192184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1193aa0c033fSGavin Shan phb->type = ioda_type; 1194184cd4a3SBenjamin Herrenschmidt 1195cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1196cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1197cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1198f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1199aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1200cee72d5bSBenjamin Herrenschmidt else 1201cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1202cee72d5bSBenjamin Herrenschmidt 1203aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 12042f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 1205184cd4a3SBenjamin Herrenschmidt 1206aa0c033fSGavin Shan /* Get registers */ 1207184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1208184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1209184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1210184cd4a3SBenjamin Herrenschmidt 1211184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1212aa0c033fSGavin Shan phb->ioda.total_pe = 1; 121336954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 121436954dc7SGavin Shan if (prop32) 12153a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 121636954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 121736954dc7SGavin Shan if (prop32) 121836954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 1219184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1220aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 1221184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 1222184cd4a3SBenjamin Herrenschmidt 1223184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 12243fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 1225184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 1226184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1227184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1228184cd4a3SBenjamin Herrenschmidt 1229c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 1230184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1231184cd4a3SBenjamin Herrenschmidt m32map_off = size; 1232e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 1233184cd4a3SBenjamin Herrenschmidt iomap_off = size; 1234c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 1235c35d2a8cSGavin Shan iomap_off = size; 1236e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 1237c35d2a8cSGavin Shan } 1238184cd4a3SBenjamin Herrenschmidt pemap_off = size; 1239184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1240184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 1241184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 1242184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 1243184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 1244c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 1245184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 1246184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 124736954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 1248184cd4a3SBenjamin Herrenschmidt 12497ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1250184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 1251184cd4a3SBenjamin Herrenschmidt 1252184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 1253184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1254184cd4a3SBenjamin Herrenschmidt 1255184cd4a3SBenjamin Herrenschmidt /* Clear unusable m64 */ 1256184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].flags = 0; 1257184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].start = 0; 1258184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].end = 0; 1259184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].flags = 0; 1260184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].start = 0; 1261184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].end = 0; 1262184cd4a3SBenjamin Herrenschmidt 1263aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 1264184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1265184cd4a3SBenjamin Herrenschmidt window_type, 1266184cd4a3SBenjamin Herrenschmidt window_num, 1267184cd4a3SBenjamin Herrenschmidt starting_real_address, 1268184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1269184cd4a3SBenjamin Herrenschmidt segment_size); 1270184cd4a3SBenjamin Herrenschmidt #endif 1271184cd4a3SBenjamin Herrenschmidt 127236954dc7SGavin Shan pr_info(" %d (%d) PE's M32: 0x%x [segment=0x%x]" 127336954dc7SGavin Shan " IO: 0x%x [segment=0x%x]\n", 1274184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 127536954dc7SGavin Shan phb->ioda.reserved_pe, 1276184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size, phb->ioda.m32_segsize, 1277184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1278184cd4a3SBenjamin Herrenschmidt 1279184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 1280e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1281e9cc17d4SGavin Shan phb->eeh_ops = &ioda_eeh_ops; 1282e9cc17d4SGavin Shan #endif 1283184cd4a3SBenjamin Herrenschmidt 1284184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1285184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1286184cd4a3SBenjamin Herrenschmidt 1287184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1288184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1289184cd4a3SBenjamin Herrenschmidt 129073ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 129173ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 129273ed148aSBenjamin Herrenschmidt 1293184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1294184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1295184cd4a3SBenjamin Herrenschmidt 1296c40a4210SGavin Shan /* 1297c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1298c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1299c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1300c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1301c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1302184cd4a3SBenjamin Herrenschmidt */ 1303fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1304184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1305271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1306c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1307184cd4a3SBenjamin Herrenschmidt 1308184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1309f11fe552SBenjamin Herrenschmidt rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); 1310184cd4a3SBenjamin Herrenschmidt if (rc) 1311f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1312184cd4a3SBenjamin Herrenschmidt } 1313184cd4a3SBenjamin Herrenschmidt 131467975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 1315aa0c033fSGavin Shan { 1316e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 1317aa0c033fSGavin Shan } 1318aa0c033fSGavin Shan 1319184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 1320184cd4a3SBenjamin Herrenschmidt { 1321184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 1322c681b93cSAlistair Popple const __be64 *prop64; 1323184cd4a3SBenjamin Herrenschmidt u64 hub_id; 1324184cd4a3SBenjamin Herrenschmidt 1325184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1326184cd4a3SBenjamin Herrenschmidt 1327184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1328184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1329184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1330184cd4a3SBenjamin Herrenschmidt return; 1331184cd4a3SBenjamin Herrenschmidt } 1332184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 1333184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1334184cd4a3SBenjamin Herrenschmidt 1335184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 1336184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 1337184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 1338184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1339e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 1340184cd4a3SBenjamin Herrenschmidt } 1341184cd4a3SBenjamin Herrenschmidt } 1342