1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26184cd4a3SBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 32fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 37137436c9SGavin Shan #include <asm/xics.h> 3837c367f2SGavin Shan #include <asm/debug.h> 39262af557SGuo Chao #include <asm/firmware.h> 4080c49c7eSIan Munsie #include <asm/pnv-pci.h> 4180c49c7eSIan Munsie 4280c49c7eSIan Munsie #include <misc/cxl.h> 43184cd4a3SBenjamin Herrenschmidt 44184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 45184cd4a3SBenjamin Herrenschmidt #include "pci.h" 46184cd4a3SBenjamin Herrenschmidt 476d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 486d31c2faSJoe Perches const char *fmt, ...) 496d31c2faSJoe Perches { 506d31c2faSJoe Perches struct va_format vaf; 516d31c2faSJoe Perches va_list args; 526d31c2faSJoe Perches char pfix[32]; 53184cd4a3SBenjamin Herrenschmidt 546d31c2faSJoe Perches va_start(args, fmt); 556d31c2faSJoe Perches 566d31c2faSJoe Perches vaf.fmt = fmt; 576d31c2faSJoe Perches vaf.va = &args; 586d31c2faSJoe Perches 596d31c2faSJoe Perches if (pe->pdev) 606d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 616d31c2faSJoe Perches else 626d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 636d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 646d31c2faSJoe Perches 656d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 666d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 676d31c2faSJoe Perches 686d31c2faSJoe Perches va_end(args); 696d31c2faSJoe Perches } 706d31c2faSJoe Perches 716d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 726d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 736d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 746d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 756d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 766d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 77184cd4a3SBenjamin Herrenschmidt 788e0a1611SAlexey Kardashevskiy /* 798e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 808e0a1611SAlexey Kardashevskiy * the architecture spec 818e0a1611SAlexey Kardashevskiy */ 828e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 838e0a1611SAlexey Kardashevskiy { 848e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 858e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 868e0a1611SAlexey Kardashevskiy } 878e0a1611SAlexey Kardashevskiy 88262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 89262af557SGuo Chao { 90262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 91262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 92262af557SGuo Chao } 93262af557SGuo Chao 94cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 95184cd4a3SBenjamin Herrenschmidt { 96184cd4a3SBenjamin Herrenschmidt unsigned long pe; 97184cd4a3SBenjamin Herrenschmidt 98184cd4a3SBenjamin Herrenschmidt do { 99184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 100184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 101184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 102184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 103184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 104184cd4a3SBenjamin Herrenschmidt 1054cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 106184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 107184cd4a3SBenjamin Herrenschmidt return pe; 108184cd4a3SBenjamin Herrenschmidt } 109184cd4a3SBenjamin Herrenschmidt 110cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 111184cd4a3SBenjamin Herrenschmidt { 112184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 113184cd4a3SBenjamin Herrenschmidt 114184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 115184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 116184cd4a3SBenjamin Herrenschmidt } 117184cd4a3SBenjamin Herrenschmidt 118262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 119262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 120262af557SGuo Chao { 121262af557SGuo Chao const char *desc; 122262af557SGuo Chao struct resource *r; 123262af557SGuo Chao s64 rc; 124262af557SGuo Chao 125262af557SGuo Chao /* Configure the default M64 BAR */ 126262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 127262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 128262af557SGuo Chao phb->ioda.m64_bar_idx, 129262af557SGuo Chao phb->ioda.m64_base, 130262af557SGuo Chao 0, /* unused */ 131262af557SGuo Chao phb->ioda.m64_size); 132262af557SGuo Chao if (rc != OPAL_SUCCESS) { 133262af557SGuo Chao desc = "configuring"; 134262af557SGuo Chao goto fail; 135262af557SGuo Chao } 136262af557SGuo Chao 137262af557SGuo Chao /* Enable the default M64 BAR */ 138262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 139262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 140262af557SGuo Chao phb->ioda.m64_bar_idx, 141262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 142262af557SGuo Chao if (rc != OPAL_SUCCESS) { 143262af557SGuo Chao desc = "enabling"; 144262af557SGuo Chao goto fail; 145262af557SGuo Chao } 146262af557SGuo Chao 147262af557SGuo Chao /* Mark the M64 BAR assigned */ 148262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 149262af557SGuo Chao 150262af557SGuo Chao /* 151262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 152262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 153262af557SGuo Chao */ 154262af557SGuo Chao r = &phb->hose->mem_resources[1]; 155262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 156262af557SGuo Chao r->start += phb->ioda.m64_segsize; 157262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 158262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 159262af557SGuo Chao else 160262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 161262af557SGuo Chao phb->ioda.reserved_pe); 162262af557SGuo Chao 163262af557SGuo Chao return 0; 164262af557SGuo Chao 165262af557SGuo Chao fail: 166262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 167262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 168262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 169262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 170262af557SGuo Chao phb->ioda.m64_bar_idx, 171262af557SGuo Chao OPAL_DISABLE_M64); 172262af557SGuo Chao return -EIO; 173262af557SGuo Chao } 174262af557SGuo Chao 175262af557SGuo Chao static void pnv_ioda2_alloc_m64_pe(struct pnv_phb *phb) 176262af557SGuo Chao { 177262af557SGuo Chao resource_size_t sgsz = phb->ioda.m64_segsize; 178262af557SGuo Chao struct pci_dev *pdev; 179262af557SGuo Chao struct resource *r; 180262af557SGuo Chao int base, step, i; 181262af557SGuo Chao 182262af557SGuo Chao /* 183262af557SGuo Chao * Root bus always has full M64 range and root port has 184262af557SGuo Chao * M64 range used in reality. So we're checking root port 185262af557SGuo Chao * instead of root bus. 186262af557SGuo Chao */ 187262af557SGuo Chao list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { 188262af557SGuo Chao for (i = PCI_BRIDGE_RESOURCES; 189262af557SGuo Chao i <= PCI_BRIDGE_RESOURCE_END; i++) { 190262af557SGuo Chao r = &pdev->resource[i]; 191262af557SGuo Chao if (!r->parent || 192262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 193262af557SGuo Chao continue; 194262af557SGuo Chao 195262af557SGuo Chao base = (r->start - phb->ioda.m64_base) / sgsz; 196262af557SGuo Chao for (step = 0; step < resource_size(r) / sgsz; step++) 197262af557SGuo Chao set_bit(base + step, phb->ioda.pe_alloc); 198262af557SGuo Chao } 199262af557SGuo Chao } 200262af557SGuo Chao } 201262af557SGuo Chao 202262af557SGuo Chao static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 203262af557SGuo Chao struct pci_bus *bus, int all) 204262af557SGuo Chao { 205262af557SGuo Chao resource_size_t segsz = phb->ioda.m64_segsize; 206262af557SGuo Chao struct pci_dev *pdev; 207262af557SGuo Chao struct resource *r; 208262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 209262af557SGuo Chao unsigned long size, *pe_alloc; 210262af557SGuo Chao bool found; 211262af557SGuo Chao int start, i, j; 212262af557SGuo Chao 213262af557SGuo Chao /* Root bus shouldn't use M64 */ 214262af557SGuo Chao if (pci_is_root_bus(bus)) 215262af557SGuo Chao return IODA_INVALID_PE; 216262af557SGuo Chao 217262af557SGuo Chao /* We support only one M64 window on each bus */ 218262af557SGuo Chao found = false; 219262af557SGuo Chao pci_bus_for_each_resource(bus, r, i) { 220262af557SGuo Chao if (r && r->parent && 221262af557SGuo Chao pnv_pci_is_mem_pref_64(r->flags)) { 222262af557SGuo Chao found = true; 223262af557SGuo Chao break; 224262af557SGuo Chao } 225262af557SGuo Chao } 226262af557SGuo Chao 227262af557SGuo Chao /* No M64 window found ? */ 228262af557SGuo Chao if (!found) 229262af557SGuo Chao return IODA_INVALID_PE; 230262af557SGuo Chao 231262af557SGuo Chao /* Allocate bitmap */ 232262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 233262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 234262af557SGuo Chao if (!pe_alloc) { 235262af557SGuo Chao pr_warn("%s: Out of memory !\n", 236262af557SGuo Chao __func__); 237262af557SGuo Chao return IODA_INVALID_PE; 238262af557SGuo Chao } 239262af557SGuo Chao 240262af557SGuo Chao /* 241262af557SGuo Chao * Figure out reserved PE numbers by the PE 242262af557SGuo Chao * the its child PEs. 243262af557SGuo Chao */ 244262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 245262af557SGuo Chao for (i = 0; i < resource_size(r) / segsz; i++) 246262af557SGuo Chao set_bit(start + i, pe_alloc); 247262af557SGuo Chao 248262af557SGuo Chao if (all) 249262af557SGuo Chao goto done; 250262af557SGuo Chao 251262af557SGuo Chao /* 252262af557SGuo Chao * If the PE doesn't cover all subordinate buses, 253262af557SGuo Chao * we need subtract from reserved PEs for children. 254262af557SGuo Chao */ 255262af557SGuo Chao list_for_each_entry(pdev, &bus->devices, bus_list) { 256262af557SGuo Chao if (!pdev->subordinate) 257262af557SGuo Chao continue; 258262af557SGuo Chao 259262af557SGuo Chao pci_bus_for_each_resource(pdev->subordinate, r, i) { 260262af557SGuo Chao if (!r || !r->parent || 261262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 262262af557SGuo Chao continue; 263262af557SGuo Chao 264262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 265262af557SGuo Chao for (j = 0; j < resource_size(r) / segsz ; j++) 266262af557SGuo Chao clear_bit(start + j, pe_alloc); 267262af557SGuo Chao } 268262af557SGuo Chao } 269262af557SGuo Chao 270262af557SGuo Chao /* 271262af557SGuo Chao * the current bus might not own M64 window and that's all 272262af557SGuo Chao * contributed by its child buses. For the case, we needn't 273262af557SGuo Chao * pick M64 dependent PE#. 274262af557SGuo Chao */ 275262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 276262af557SGuo Chao kfree(pe_alloc); 277262af557SGuo Chao return IODA_INVALID_PE; 278262af557SGuo Chao } 279262af557SGuo Chao 280262af557SGuo Chao /* 281262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 282262af557SGuo Chao * PE's list to form compound PE. 283262af557SGuo Chao */ 284262af557SGuo Chao done: 285262af557SGuo Chao master_pe = NULL; 286262af557SGuo Chao i = -1; 287262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 288262af557SGuo Chao phb->ioda.total_pe) { 289262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 290262af557SGuo Chao pe->phb = phb; 291262af557SGuo Chao pe->pe_number = i; 292262af557SGuo Chao 293262af557SGuo Chao if (!master_pe) { 294262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 295262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 296262af557SGuo Chao master_pe = pe; 297262af557SGuo Chao } else { 298262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 299262af557SGuo Chao pe->master = master_pe; 300262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 301262af557SGuo Chao } 302262af557SGuo Chao } 303262af557SGuo Chao 304262af557SGuo Chao kfree(pe_alloc); 305262af557SGuo Chao return master_pe->pe_number; 306262af557SGuo Chao } 307262af557SGuo Chao 308262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 309262af557SGuo Chao { 310262af557SGuo Chao struct pci_controller *hose = phb->hose; 311262af557SGuo Chao struct device_node *dn = hose->dn; 312262af557SGuo Chao struct resource *res; 313262af557SGuo Chao const u32 *r; 314262af557SGuo Chao u64 pci_addr; 315262af557SGuo Chao 316262af557SGuo Chao if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 317262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 318262af557SGuo Chao return; 319262af557SGuo Chao } 320262af557SGuo Chao 321262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 322262af557SGuo Chao if (!r) { 323262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 324262af557SGuo Chao dn->full_name); 325262af557SGuo Chao return; 326262af557SGuo Chao } 327262af557SGuo Chao 328262af557SGuo Chao /* FIXME: Support M64 for P7IOC */ 329262af557SGuo Chao if (phb->type != PNV_PHB_IODA2) { 330262af557SGuo Chao pr_info(" Not support M64 window\n"); 331262af557SGuo Chao return; 332262af557SGuo Chao } 333262af557SGuo Chao 334262af557SGuo Chao res = &hose->mem_resources[1]; 335262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 336262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 337262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 338262af557SGuo Chao pci_addr = of_read_number(r, 2); 339262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 340262af557SGuo Chao 341262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 342262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 343262af557SGuo Chao phb->ioda.m64_base = pci_addr; 344262af557SGuo Chao 345262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 346262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 347262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 348262af557SGuo Chao phb->alloc_m64_pe = pnv_ioda2_alloc_m64_pe; 349262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 350262af557SGuo Chao } 351262af557SGuo Chao 35249dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 35349dec922SGavin Shan { 35449dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 35549dec922SGavin Shan struct pnv_ioda_pe *slave; 35649dec922SGavin Shan s64 rc; 35749dec922SGavin Shan 35849dec922SGavin Shan /* Fetch master PE */ 35949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 36049dec922SGavin Shan pe = pe->master; 36149dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 36249dec922SGavin Shan pe_no = pe->pe_number; 36349dec922SGavin Shan } 36449dec922SGavin Shan 36549dec922SGavin Shan /* Freeze master PE */ 36649dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 36749dec922SGavin Shan pe_no, 36849dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 36949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 37049dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 37149dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 37249dec922SGavin Shan return; 37349dec922SGavin Shan } 37449dec922SGavin Shan 37549dec922SGavin Shan /* Freeze slave PEs */ 37649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 37749dec922SGavin Shan return; 37849dec922SGavin Shan 37949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 38049dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 38149dec922SGavin Shan slave->pe_number, 38249dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 38349dec922SGavin Shan if (rc != OPAL_SUCCESS) 38449dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 38549dec922SGavin Shan __func__, rc, phb->hose->global_number, 38649dec922SGavin Shan slave->pe_number); 38749dec922SGavin Shan } 38849dec922SGavin Shan } 38949dec922SGavin Shan 390e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 39149dec922SGavin Shan { 39249dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 39349dec922SGavin Shan s64 rc; 39449dec922SGavin Shan 39549dec922SGavin Shan /* Find master PE */ 39649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 39749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 39849dec922SGavin Shan pe = pe->master; 39949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 40049dec922SGavin Shan pe_no = pe->pe_number; 40149dec922SGavin Shan } 40249dec922SGavin Shan 40349dec922SGavin Shan /* Clear frozen state for master PE */ 40449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 40549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 40649dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 40749dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 40849dec922SGavin Shan return -EIO; 40949dec922SGavin Shan } 41049dec922SGavin Shan 41149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 41249dec922SGavin Shan return 0; 41349dec922SGavin Shan 41449dec922SGavin Shan /* Clear frozen state for slave PEs */ 41549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 41649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 41749dec922SGavin Shan slave->pe_number, 41849dec922SGavin Shan opt); 41949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 42049dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 42149dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 42249dec922SGavin Shan slave->pe_number); 42349dec922SGavin Shan return -EIO; 42449dec922SGavin Shan } 42549dec922SGavin Shan } 42649dec922SGavin Shan 42749dec922SGavin Shan return 0; 42849dec922SGavin Shan } 42949dec922SGavin Shan 43049dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 43149dec922SGavin Shan { 43249dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 43349dec922SGavin Shan u8 fstate, state; 43449dec922SGavin Shan __be16 pcierr; 43549dec922SGavin Shan s64 rc; 43649dec922SGavin Shan 43749dec922SGavin Shan /* Sanity check on PE number */ 43849dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 43949dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 44049dec922SGavin Shan 44149dec922SGavin Shan /* 44249dec922SGavin Shan * Fetch the master PE and the PE instance might be 44349dec922SGavin Shan * not initialized yet. 44449dec922SGavin Shan */ 44549dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 44649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 44749dec922SGavin Shan pe = pe->master; 44849dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 44949dec922SGavin Shan pe_no = pe->pe_number; 45049dec922SGavin Shan } 45149dec922SGavin Shan 45249dec922SGavin Shan /* Check the master PE */ 45349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 45449dec922SGavin Shan &state, &pcierr, NULL); 45549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 45649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 45749dec922SGavin Shan "PHB#%x-PE#%x state\n", 45849dec922SGavin Shan __func__, rc, 45949dec922SGavin Shan phb->hose->global_number, pe_no); 46049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 46149dec922SGavin Shan } 46249dec922SGavin Shan 46349dec922SGavin Shan /* Check the slave PE */ 46449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 46549dec922SGavin Shan return state; 46649dec922SGavin Shan 46749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 46849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 46949dec922SGavin Shan slave->pe_number, 47049dec922SGavin Shan &fstate, 47149dec922SGavin Shan &pcierr, 47249dec922SGavin Shan NULL); 47349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 47549dec922SGavin Shan "PHB#%x-PE#%x state\n", 47649dec922SGavin Shan __func__, rc, 47749dec922SGavin Shan phb->hose->global_number, slave->pe_number); 47849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 47949dec922SGavin Shan } 48049dec922SGavin Shan 48149dec922SGavin Shan /* 48249dec922SGavin Shan * Override the result based on the ascending 48349dec922SGavin Shan * priority. 48449dec922SGavin Shan */ 48549dec922SGavin Shan if (fstate > state) 48649dec922SGavin Shan state = fstate; 48749dec922SGavin Shan } 48849dec922SGavin Shan 48949dec922SGavin Shan return state; 49049dec922SGavin Shan } 49149dec922SGavin Shan 492184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 493184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 494184cd4a3SBenjamin Herrenschmidt */ 495184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 496cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 497184cd4a3SBenjamin Herrenschmidt { 498184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 499184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 500b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 501184cd4a3SBenjamin Herrenschmidt 502184cd4a3SBenjamin Herrenschmidt if (!pdn) 503184cd4a3SBenjamin Herrenschmidt return NULL; 504184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 505184cd4a3SBenjamin Herrenschmidt return NULL; 506184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 507184cd4a3SBenjamin Herrenschmidt } 508184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 509184cd4a3SBenjamin Herrenschmidt 510cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 511184cd4a3SBenjamin Herrenschmidt { 512184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 513184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 514184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 515184cd4a3SBenjamin Herrenschmidt 516184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 517184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 518184cd4a3SBenjamin Herrenschmidt int count; 519184cd4a3SBenjamin Herrenschmidt 520184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 521184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 522184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 523fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 524b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 525fb446ad0SGavin Shan else 526fb446ad0SGavin Shan count = 1; 527fb446ad0SGavin Shan 528184cd4a3SBenjamin Herrenschmidt switch(count) { 529184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 530184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 531184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 532184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 533184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 534184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 535184cd4a3SBenjamin Herrenschmidt default: 536184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 537184cd4a3SBenjamin Herrenschmidt " unsupported\n", 538184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 539184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 540184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 541184cd4a3SBenjamin Herrenschmidt } 542184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 543184cd4a3SBenjamin Herrenschmidt } else { 544184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 545184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 546184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 547184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 548184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 549184cd4a3SBenjamin Herrenschmidt } 550184cd4a3SBenjamin Herrenschmidt 551631ad691SGavin Shan /* 552631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 553631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 554631ad691SGavin Shan * originated from the PE might contribute to other 555631ad691SGavin Shan * PEs. 556631ad691SGavin Shan */ 557184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 558184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 559184cd4a3SBenjamin Herrenschmidt if (rc) { 560184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 561184cd4a3SBenjamin Herrenschmidt return -ENXIO; 562184cd4a3SBenjamin Herrenschmidt } 563631ad691SGavin Shan 564631ad691SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 565631ad691SGavin Shan pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 566631ad691SGavin Shan if (rc) 567631ad691SGavin Shan pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc); 568184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 569184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 570184cd4a3SBenjamin Herrenschmidt 571184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 572184cd4a3SBenjamin Herrenschmidt while (parent) { 573b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(parent); 574184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 575184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 576cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 577184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 578184cd4a3SBenjamin Herrenschmidt } 579184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 580184cd4a3SBenjamin Herrenschmidt } 581184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 582184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 583184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 584184cd4a3SBenjamin Herrenschmidt 585184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 586184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 587184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 588184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 589184cd4a3SBenjamin Herrenschmidt pe->pe_number); 590184cd4a3SBenjamin Herrenschmidt if (rc) { 591184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 592184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 593184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 594184cd4a3SBenjamin Herrenschmidt } else { 595184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 596cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 597184cd4a3SBenjamin Herrenschmidt if (rc) { 598184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 599184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 600184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 601184cd4a3SBenjamin Herrenschmidt } 602184cd4a3SBenjamin Herrenschmidt } 603184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 604184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 605184cd4a3SBenjamin Herrenschmidt 606184cd4a3SBenjamin Herrenschmidt return 0; 607184cd4a3SBenjamin Herrenschmidt } 608184cd4a3SBenjamin Herrenschmidt 609cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 610184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 611184cd4a3SBenjamin Herrenschmidt { 612184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 613184cd4a3SBenjamin Herrenschmidt 6147ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 615184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 6167ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 617184cd4a3SBenjamin Herrenschmidt return; 618184cd4a3SBenjamin Herrenschmidt } 619184cd4a3SBenjamin Herrenschmidt } 6207ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 621184cd4a3SBenjamin Herrenschmidt } 622184cd4a3SBenjamin Herrenschmidt 623184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 624184cd4a3SBenjamin Herrenschmidt { 625184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 626184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 627184cd4a3SBenjamin Herrenschmidt */ 628184cd4a3SBenjamin Herrenschmidt 629184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 630184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 631184cd4a3SBenjamin Herrenschmidt return 0; 632184cd4a3SBenjamin Herrenschmidt 633184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 634184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 635184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 636184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 637184cd4a3SBenjamin Herrenschmidt return 3; 638184cd4a3SBenjamin Herrenschmidt 639184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 640184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 641184cd4a3SBenjamin Herrenschmidt return 15; 642184cd4a3SBenjamin Herrenschmidt 643184cd4a3SBenjamin Herrenschmidt /* Default */ 644184cd4a3SBenjamin Herrenschmidt return 10; 645184cd4a3SBenjamin Herrenschmidt } 646184cd4a3SBenjamin Herrenschmidt 647fb446ad0SGavin Shan #if 0 648cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 649184cd4a3SBenjamin Herrenschmidt { 650184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 651184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 652b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 653184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 654184cd4a3SBenjamin Herrenschmidt int pe_num; 655184cd4a3SBenjamin Herrenschmidt 656184cd4a3SBenjamin Herrenschmidt if (!pdn) { 657184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 658184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 659184cd4a3SBenjamin Herrenschmidt return NULL; 660184cd4a3SBenjamin Herrenschmidt } 661184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 662184cd4a3SBenjamin Herrenschmidt return NULL; 663184cd4a3SBenjamin Herrenschmidt 664184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 665184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 666184cd4a3SBenjamin Herrenschmidt pe_num = 0; 667184cd4a3SBenjamin Herrenschmidt else 668184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 669184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 670184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 671184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 672184cd4a3SBenjamin Herrenschmidt return NULL; 673184cd4a3SBenjamin Herrenschmidt } 674184cd4a3SBenjamin Herrenschmidt 675184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 676184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 677184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 678184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 679184cd4a3SBenjamin Herrenschmidt * 680184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 681184cd4a3SBenjamin Herrenschmidt */ 682184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 683184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 684184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 685184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 686184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 687184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 688184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 689184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 690184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 691184cd4a3SBenjamin Herrenschmidt 692184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 693184cd4a3SBenjamin Herrenschmidt 694184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 695184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 696184cd4a3SBenjamin Herrenschmidt if (pe_num) 697184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 698184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 699184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 700184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 701184cd4a3SBenjamin Herrenschmidt return NULL; 702184cd4a3SBenjamin Herrenschmidt } 703184cd4a3SBenjamin Herrenschmidt 704184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 705184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 706184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 707184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 708184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 709184cd4a3SBenjamin Herrenschmidt } 710184cd4a3SBenjamin Herrenschmidt 711184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 712184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 713184cd4a3SBenjamin Herrenschmidt 714184cd4a3SBenjamin Herrenschmidt return pe; 715184cd4a3SBenjamin Herrenschmidt } 716fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 717184cd4a3SBenjamin Herrenschmidt 718184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 719184cd4a3SBenjamin Herrenschmidt { 720184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 721184cd4a3SBenjamin Herrenschmidt 722184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 723b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 724184cd4a3SBenjamin Herrenschmidt 725184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 726184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 727184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 728184cd4a3SBenjamin Herrenschmidt continue; 729184cd4a3SBenjamin Herrenschmidt } 730184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 731184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 732184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 733fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 734184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 735184cd4a3SBenjamin Herrenschmidt } 736184cd4a3SBenjamin Herrenschmidt } 737184cd4a3SBenjamin Herrenschmidt 738fb446ad0SGavin Shan /* 739fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 740fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 741fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 742fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 743fb446ad0SGavin Shan */ 744cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 745184cd4a3SBenjamin Herrenschmidt { 746fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 747184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 748184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 749262af557SGuo Chao int pe_num = IODA_INVALID_PE; 750184cd4a3SBenjamin Herrenschmidt 751262af557SGuo Chao /* Check if PE is determined by M64 */ 752262af557SGuo Chao if (phb->pick_m64_pe) 753262af557SGuo Chao pe_num = phb->pick_m64_pe(phb, bus, all); 754262af557SGuo Chao 755262af557SGuo Chao /* The PE number isn't pinned by M64 */ 756262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 757184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 758262af557SGuo Chao 759184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 760fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 761fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 762184cd4a3SBenjamin Herrenschmidt return; 763184cd4a3SBenjamin Herrenschmidt } 764184cd4a3SBenjamin Herrenschmidt 765184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 766262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 767184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 768184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 769184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 770184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 771b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 772184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 773184cd4a3SBenjamin Herrenschmidt 774fb446ad0SGavin Shan if (all) 775fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 776fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 777fb446ad0SGavin Shan else 778fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 779fb446ad0SGavin Shan bus->busn_res.start, pe_num); 780184cd4a3SBenjamin Herrenschmidt 781184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 782184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 783184cd4a3SBenjamin Herrenschmidt if (pe_num) 784184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 785184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 786184cd4a3SBenjamin Herrenschmidt return; 787184cd4a3SBenjamin Herrenschmidt } 788184cd4a3SBenjamin Herrenschmidt 789184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 790184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 791184cd4a3SBenjamin Herrenschmidt 7927ebdf956SGavin Shan /* Put PE to the list */ 7937ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 7947ebdf956SGavin Shan 795184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 796184cd4a3SBenjamin Herrenschmidt * below the bridge 797184cd4a3SBenjamin Herrenschmidt */ 798184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 799184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 800184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 801184cd4a3SBenjamin Herrenschmidt } 802184cd4a3SBenjamin Herrenschmidt 803184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 804184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 805184cd4a3SBenjamin Herrenschmidt } 806184cd4a3SBenjamin Herrenschmidt 807cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 808184cd4a3SBenjamin Herrenschmidt { 809184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 810fb446ad0SGavin Shan 811fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 812184cd4a3SBenjamin Herrenschmidt 813184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 814fb446ad0SGavin Shan if (dev->subordinate) { 81562f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 816fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 817fb446ad0SGavin Shan else 818184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 819184cd4a3SBenjamin Herrenschmidt } 820184cd4a3SBenjamin Herrenschmidt } 821fb446ad0SGavin Shan } 822fb446ad0SGavin Shan 823fb446ad0SGavin Shan /* 824fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 825fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 826fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 827fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 828fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 829fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 830fb446ad0SGavin Shan */ 831cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 832fb446ad0SGavin Shan { 833fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 834262af557SGuo Chao struct pnv_phb *phb; 835fb446ad0SGavin Shan 836fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 837262af557SGuo Chao phb = hose->private_data; 838262af557SGuo Chao 839262af557SGuo Chao /* M64 layout might affect PE allocation */ 840262af557SGuo Chao if (phb->alloc_m64_pe) 841262af557SGuo Chao phb->alloc_m64_pe(phb); 842262af557SGuo Chao 843fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 844fb446ad0SGavin Shan } 845fb446ad0SGavin Shan } 846184cd4a3SBenjamin Herrenschmidt 847959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 848184cd4a3SBenjamin Herrenschmidt { 849b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 850959c9bddSGavin Shan struct pnv_ioda_pe *pe; 851184cd4a3SBenjamin Herrenschmidt 852959c9bddSGavin Shan /* 853959c9bddSGavin Shan * The function can be called while the PE# 854959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 855959c9bddSGavin Shan * case. 856959c9bddSGavin Shan */ 857959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 858959c9bddSGavin Shan return; 859184cd4a3SBenjamin Herrenschmidt 860959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 861cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 862763fe0adSGavin Shan set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); 863184cd4a3SBenjamin Herrenschmidt } 864184cd4a3SBenjamin Herrenschmidt 865cd15b048SBenjamin Herrenschmidt static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, 866cd15b048SBenjamin Herrenschmidt struct pci_dev *pdev, u64 dma_mask) 867cd15b048SBenjamin Herrenschmidt { 868cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 869cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 870cd15b048SBenjamin Herrenschmidt uint64_t top; 871cd15b048SBenjamin Herrenschmidt bool bypass = false; 872cd15b048SBenjamin Herrenschmidt 873cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 874cd15b048SBenjamin Herrenschmidt return -ENODEV;; 875cd15b048SBenjamin Herrenschmidt 876cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 877cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 878cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 879cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 880cd15b048SBenjamin Herrenschmidt } 881cd15b048SBenjamin Herrenschmidt 882cd15b048SBenjamin Herrenschmidt if (bypass) { 883cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 884cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 885cd15b048SBenjamin Herrenschmidt set_dma_offset(&pdev->dev, pe->tce_bypass_base); 886cd15b048SBenjamin Herrenschmidt } else { 887cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 888cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 889cd15b048SBenjamin Herrenschmidt set_iommu_table_base(&pdev->dev, &pe->tce32_table); 890cd15b048SBenjamin Herrenschmidt } 891a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 892cd15b048SBenjamin Herrenschmidt return 0; 893cd15b048SBenjamin Herrenschmidt } 894cd15b048SBenjamin Herrenschmidt 895fe7e85c6SGavin Shan static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, 896fe7e85c6SGavin Shan struct pci_dev *pdev) 897fe7e85c6SGavin Shan { 898fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 899fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 900fe7e85c6SGavin Shan u64 end, mask; 901fe7e85c6SGavin Shan 902fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 903fe7e85c6SGavin Shan return 0; 904fe7e85c6SGavin Shan 905fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 906fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 907fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 908fe7e85c6SGavin Shan 909fe7e85c6SGavin Shan 910fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 911fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 912fe7e85c6SGavin Shan mask += mask - 1; 913fe7e85c6SGavin Shan 914fe7e85c6SGavin Shan return mask; 915fe7e85c6SGavin Shan } 916fe7e85c6SGavin Shan 917dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 918dff4a39eSGavin Shan struct pci_bus *bus, 919dff4a39eSGavin Shan bool add_to_iommu_group) 92074251fe2SBenjamin Herrenschmidt { 92174251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 92274251fe2SBenjamin Herrenschmidt 92374251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 924dff4a39eSGavin Shan if (add_to_iommu_group) 925dff4a39eSGavin Shan set_iommu_table_base_and_group(&dev->dev, 926dff4a39eSGavin Shan &pe->tce32_table); 927dff4a39eSGavin Shan else 928dff4a39eSGavin Shan set_iommu_table_base(&dev->dev, &pe->tce32_table); 929dff4a39eSGavin Shan 93074251fe2SBenjamin Herrenschmidt if (dev->subordinate) 931dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, dev->subordinate, 932dff4a39eSGavin Shan add_to_iommu_group); 93374251fe2SBenjamin Herrenschmidt } 93474251fe2SBenjamin Herrenschmidt } 93574251fe2SBenjamin Herrenschmidt 9368e0a1611SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, 9378e0a1611SAlexey Kardashevskiy struct iommu_table *tbl, 9383ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 9394cce9550SGavin Shan { 9403ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 9413ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 9423ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 9434cce9550SGavin Shan unsigned long start, end, inc; 944b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 9454cce9550SGavin Shan 9464cce9550SGavin Shan start = __pa(startp); 9474cce9550SGavin Shan end = __pa(endp); 9484cce9550SGavin Shan 9494cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 9504cce9550SGavin Shan if (tbl->it_busno) { 951b0376c9bSAlexey Kardashevskiy start <<= shift; 952b0376c9bSAlexey Kardashevskiy end <<= shift; 953b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 9544cce9550SGavin Shan start |= tbl->it_busno; 9554cce9550SGavin Shan end |= tbl->it_busno; 9564cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 9574cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 9584cce9550SGavin Shan start |= (1ull << 63); 9594cce9550SGavin Shan end |= (1ull << 63); 9604cce9550SGavin Shan inc = 16; 9614cce9550SGavin Shan } else { 9624cce9550SGavin Shan /* Default (older HW) */ 9634cce9550SGavin Shan inc = 128; 9644cce9550SGavin Shan } 9654cce9550SGavin Shan 9664cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 9674cce9550SGavin Shan 9684cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 9694cce9550SGavin Shan while (start <= end) { 9708e0a1611SAlexey Kardashevskiy if (rm) 9713ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 9728e0a1611SAlexey Kardashevskiy else 9733a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 9744cce9550SGavin Shan start += inc; 9754cce9550SGavin Shan } 9764cce9550SGavin Shan 9774cce9550SGavin Shan /* 9784cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 9794cce9550SGavin Shan * and we don't care on free() 9804cce9550SGavin Shan */ 9814cce9550SGavin Shan } 9824cce9550SGavin Shan 9834cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 9844cce9550SGavin Shan struct iommu_table *tbl, 9853ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 9864cce9550SGavin Shan { 9874cce9550SGavin Shan unsigned long start, end, inc; 9883ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 9893ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 9903ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 991b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 9924cce9550SGavin Shan 9934cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 994b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 9954cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 9964cce9550SGavin Shan end = start; 9974cce9550SGavin Shan 9984cce9550SGavin Shan /* Figure out the start, end and step */ 9994cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 1000b0376c9bSAlexey Kardashevskiy start |= (inc << shift); 10014cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 1002b0376c9bSAlexey Kardashevskiy end |= (inc << shift); 1003b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 10044cce9550SGavin Shan mb(); 10054cce9550SGavin Shan 10064cce9550SGavin Shan while (start <= end) { 10078e0a1611SAlexey Kardashevskiy if (rm) 10083ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 10098e0a1611SAlexey Kardashevskiy else 10103a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 10114cce9550SGavin Shan start += inc; 10124cce9550SGavin Shan } 10134cce9550SGavin Shan } 10144cce9550SGavin Shan 10154cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 10163ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 10174cce9550SGavin Shan { 10184cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 10194cce9550SGavin Shan tce32_table); 10204cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 10214cce9550SGavin Shan 10224cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 10238e0a1611SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); 10244cce9550SGavin Shan else 10258e0a1611SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); 10264cce9550SGavin Shan } 10274cce9550SGavin Shan 1028cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1029cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1030184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1031184cd4a3SBenjamin Herrenschmidt { 1032184cd4a3SBenjamin Herrenschmidt 1033184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1034184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 1035184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1036184cd4a3SBenjamin Herrenschmidt unsigned int i; 1037184cd4a3SBenjamin Herrenschmidt int64_t rc; 1038184cd4a3SBenjamin Herrenschmidt void *addr; 1039184cd4a3SBenjamin Herrenschmidt 1040184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 1041184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 1042184cd4a3SBenjamin Herrenschmidt 1043184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1044184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1045184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1046184cd4a3SBenjamin Herrenschmidt 1047184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1048184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1049184cd4a3SBenjamin Herrenschmidt return; 1050184cd4a3SBenjamin Herrenschmidt 1051184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1052184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1053184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1054184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1055184cd4a3SBenjamin Herrenschmidt 1056184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1057184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1058184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1059184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1060184cd4a3SBenjamin Herrenschmidt */ 1061184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1062184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1063184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1064184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1065184cd4a3SBenjamin Herrenschmidt goto fail; 1066184cd4a3SBenjamin Herrenschmidt } 1067184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1068184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1069184cd4a3SBenjamin Herrenschmidt 1070184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1071184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1072184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1073184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1074184cd4a3SBenjamin Herrenschmidt base + i, 1, 1075184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1076184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1077184cd4a3SBenjamin Herrenschmidt if (rc) { 1078184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1079184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1080184cd4a3SBenjamin Herrenschmidt goto fail; 1081184cd4a3SBenjamin Herrenschmidt } 1082184cd4a3SBenjamin Herrenschmidt } 1083184cd4a3SBenjamin Herrenschmidt 1084184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1085184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 1086184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 10878fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1088184cd4a3SBenjamin Herrenschmidt 1089184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 1090184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1091184cd4a3SBenjamin Herrenschmidt if (swinvp) { 1092184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 1093184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 1094184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 1095184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 1096184cd4a3SBenjamin Herrenschmidt */ 10978e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 10988e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 10998e0a1611SAlexey Kardashevskiy 8); 110065fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 110165fd766bSGavin Shan TCE_PCI_SWINV_FREE | 110265fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 1103184cd4a3SBenjamin Herrenschmidt } 1104184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1105e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1106184cd4a3SBenjamin Herrenschmidt 110774251fe2SBenjamin Herrenschmidt if (pe->pdev) 1108d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 110974251fe2SBenjamin Herrenschmidt else 1110dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 111174251fe2SBenjamin Herrenschmidt 1112184cd4a3SBenjamin Herrenschmidt return; 1113184cd4a3SBenjamin Herrenschmidt fail: 1114184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1115184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1116184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1117184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1118184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 1119184cd4a3SBenjamin Herrenschmidt } 1120184cd4a3SBenjamin Herrenschmidt 1121cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) 1122cd15b048SBenjamin Herrenschmidt { 1123cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 1124cd15b048SBenjamin Herrenschmidt tce32_table); 1125cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1126cd15b048SBenjamin Herrenschmidt int64_t rc; 1127cd15b048SBenjamin Herrenschmidt 1128cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1129cd15b048SBenjamin Herrenschmidt if (enable) { 1130cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1131cd15b048SBenjamin Herrenschmidt 1132cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1133cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1134cd15b048SBenjamin Herrenschmidt pe->pe_number, 1135cd15b048SBenjamin Herrenschmidt window_id, 1136cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1137cd15b048SBenjamin Herrenschmidt top); 1138cd15b048SBenjamin Herrenschmidt } else { 1139cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1140cd15b048SBenjamin Herrenschmidt pe->pe_number, 1141cd15b048SBenjamin Herrenschmidt window_id, 1142cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1143cd15b048SBenjamin Herrenschmidt 0); 1144cd15b048SBenjamin Herrenschmidt 1145cd15b048SBenjamin Herrenschmidt /* 1146dff4a39eSGavin Shan * EEH needs the mapping between IOMMU table and group 1147dff4a39eSGavin Shan * of those VFIO/KVM pass-through devices. We can postpone 1148dff4a39eSGavin Shan * resetting DMA ops until the DMA mask is configured in 1149dff4a39eSGavin Shan * host side. 1150cd15b048SBenjamin Herrenschmidt */ 1151dff4a39eSGavin Shan if (pe->pdev) 1152dff4a39eSGavin Shan set_iommu_table_base(&pe->pdev->dev, tbl); 1153dff4a39eSGavin Shan else 1154dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 1155cd15b048SBenjamin Herrenschmidt } 1156cd15b048SBenjamin Herrenschmidt if (rc) 1157cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1158cd15b048SBenjamin Herrenschmidt else 1159cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1160cd15b048SBenjamin Herrenschmidt } 1161cd15b048SBenjamin Herrenschmidt 1162cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, 1163cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 1164cd15b048SBenjamin Herrenschmidt { 1165cd15b048SBenjamin Herrenschmidt /* TVE #1 is selected by PCI address bit 59 */ 1166cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base = 1ull << 59; 1167cd15b048SBenjamin Herrenschmidt 1168cd15b048SBenjamin Herrenschmidt /* Install set_bypass callback for VFIO */ 1169cd15b048SBenjamin Herrenschmidt pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; 1170cd15b048SBenjamin Herrenschmidt 1171cd15b048SBenjamin Herrenschmidt /* Enable bypass by default */ 1172cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); 1173cd15b048SBenjamin Herrenschmidt } 1174cd15b048SBenjamin Herrenschmidt 1175373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1176373f5657SGavin Shan struct pnv_ioda_pe *pe) 1177373f5657SGavin Shan { 1178373f5657SGavin Shan struct page *tce_mem = NULL; 1179373f5657SGavin Shan void *addr; 1180373f5657SGavin Shan const __be64 *swinvp; 1181373f5657SGavin Shan struct iommu_table *tbl; 1182373f5657SGavin Shan unsigned int tce_table_size, end; 1183373f5657SGavin Shan int64_t rc; 1184373f5657SGavin Shan 1185373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 1186373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 1187373f5657SGavin Shan return; 1188373f5657SGavin Shan 1189373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1190373f5657SGavin Shan pe->tce32_seg = 0; 1191373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 1192373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 1193373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1194373f5657SGavin Shan end); 1195373f5657SGavin Shan 1196373f5657SGavin Shan /* Allocate TCE table */ 1197373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1198373f5657SGavin Shan get_order(tce_table_size)); 1199373f5657SGavin Shan if (!tce_mem) { 1200373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 1201373f5657SGavin Shan goto fail; 1202373f5657SGavin Shan } 1203373f5657SGavin Shan addr = page_address(tce_mem); 1204373f5657SGavin Shan memset(addr, 0, tce_table_size); 1205373f5657SGavin Shan 1206373f5657SGavin Shan /* 1207373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 1208373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 1209373f5657SGavin Shan */ 1210373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1211373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 1212373f5657SGavin Shan tce_table_size, 0x1000); 1213373f5657SGavin Shan if (rc) { 1214373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 1215373f5657SGavin Shan " err %ld\n", rc); 1216373f5657SGavin Shan goto fail; 1217373f5657SGavin Shan } 1218373f5657SGavin Shan 1219373f5657SGavin Shan /* Setup linux iommu table */ 1220373f5657SGavin Shan tbl = &pe->tce32_table; 12218fa5d454SAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, 12228fa5d454SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K); 1223373f5657SGavin Shan 1224373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 1225373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1226373f5657SGavin Shan if (swinvp) { 1227373f5657SGavin Shan /* We need a couple more fields -- an address and a data 1228373f5657SGavin Shan * to or. Since the bus is only printed out on table free 1229373f5657SGavin Shan * errors, and on the first pass the data will be a relative 1230373f5657SGavin Shan * bus number, print that out instead. 1231373f5657SGavin Shan */ 12328e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 12338e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 12348e0a1611SAlexey Kardashevskiy 8); 123565fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 1236373f5657SGavin Shan } 1237373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 1238e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1239373f5657SGavin Shan 124074251fe2SBenjamin Herrenschmidt if (pe->pdev) 1241d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 124274251fe2SBenjamin Herrenschmidt else 1243dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 124474251fe2SBenjamin Herrenschmidt 1245cd15b048SBenjamin Herrenschmidt /* Also create a bypass window */ 1246cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_setup_bypass_pe(phb, pe); 1247373f5657SGavin Shan return; 1248373f5657SGavin Shan fail: 1249373f5657SGavin Shan if (pe->tce32_seg >= 0) 1250373f5657SGavin Shan pe->tce32_seg = -1; 1251373f5657SGavin Shan if (tce_mem) 1252373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 1253373f5657SGavin Shan } 1254373f5657SGavin Shan 1255cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 1256184cd4a3SBenjamin Herrenschmidt { 1257184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 1258184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 1259184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1260184cd4a3SBenjamin Herrenschmidt 1261184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 1262184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 1263184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 1264184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 1265184cd4a3SBenjamin Herrenschmidt */ 1266184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 1267184cd4a3SBenjamin Herrenschmidt residual = 0; 1268184cd4a3SBenjamin Herrenschmidt else 1269184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 1270184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 1271184cd4a3SBenjamin Herrenschmidt 1272184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 1273184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 1274184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 1275184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 1276184cd4a3SBenjamin Herrenschmidt 1277184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 1278184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 1279184cd4a3SBenjamin Herrenschmidt * weight 1280184cd4a3SBenjamin Herrenschmidt */ 1281184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 1282184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 1283184cd4a3SBenjamin Herrenschmidt base = 0; 12847ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 1285184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 1286184cd4a3SBenjamin Herrenschmidt continue; 1287184cd4a3SBenjamin Herrenschmidt if (!remaining) { 1288184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 1289184cd4a3SBenjamin Herrenschmidt continue; 1290184cd4a3SBenjamin Herrenschmidt } 1291184cd4a3SBenjamin Herrenschmidt segs = 1; 1292184cd4a3SBenjamin Herrenschmidt if (residual) { 1293184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 1294184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 1295184cd4a3SBenjamin Herrenschmidt segs = remaining; 1296184cd4a3SBenjamin Herrenschmidt } 1297373f5657SGavin Shan 1298373f5657SGavin Shan /* 1299373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 1300373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 1301373f5657SGavin Shan * the specific PE. 1302373f5657SGavin Shan */ 1303373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 1304184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 1305184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 1306184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 1307373f5657SGavin Shan } else { 1308373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 1309373f5657SGavin Shan segs = 0; 1310373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 1311373f5657SGavin Shan } 1312373f5657SGavin Shan 1313184cd4a3SBenjamin Herrenschmidt remaining -= segs; 1314184cd4a3SBenjamin Herrenschmidt base += segs; 1315184cd4a3SBenjamin Herrenschmidt } 1316184cd4a3SBenjamin Herrenschmidt } 1317184cd4a3SBenjamin Herrenschmidt 1318184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 1319137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 1320137436c9SGavin Shan { 1321137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1322137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 1323137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 1324137436c9SGavin Shan ioda.irq_chip); 1325137436c9SGavin Shan int64_t rc; 1326137436c9SGavin Shan 1327137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1328137436c9SGavin Shan WARN_ON_ONCE(rc); 1329137436c9SGavin Shan 1330137436c9SGavin Shan icp_native_eoi(d); 1331137436c9SGavin Shan } 1332137436c9SGavin Shan 1333fd9a1c26SIan Munsie 1334fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 1335fd9a1c26SIan Munsie { 1336fd9a1c26SIan Munsie struct irq_data *idata; 1337fd9a1c26SIan Munsie struct irq_chip *ichip; 1338fd9a1c26SIan Munsie 1339fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 1340fd9a1c26SIan Munsie return; 1341fd9a1c26SIan Munsie 1342fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 1343fd9a1c26SIan Munsie /* 1344fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 1345fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 1346fd9a1c26SIan Munsie */ 1347fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 1348fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 1349fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 1350fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 1351fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 1352fd9a1c26SIan Munsie } 1353fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 1354fd9a1c26SIan Munsie } 1355fd9a1c26SIan Munsie 135680c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 135780c49c7eSIan Munsie 135880c49c7eSIan Munsie struct device_node *pnv_pci_to_phb_node(struct pci_dev *dev) 135980c49c7eSIan Munsie { 136080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 136180c49c7eSIan Munsie 136280c49c7eSIan Munsie return hose->dn; 136380c49c7eSIan Munsie } 136480c49c7eSIan Munsie EXPORT_SYMBOL(pnv_pci_to_phb_node); 136580c49c7eSIan Munsie 136680c49c7eSIan Munsie int pnv_phb_to_cxl(struct pci_dev *dev) 136780c49c7eSIan Munsie { 136880c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 136980c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 137080c49c7eSIan Munsie struct pnv_ioda_pe *pe; 137180c49c7eSIan Munsie int rc; 137280c49c7eSIan Munsie 137380c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 137480c49c7eSIan Munsie if (!pe) 137580c49c7eSIan Munsie return -ENODEV; 137680c49c7eSIan Munsie 137780c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 137880c49c7eSIan Munsie 137980c49c7eSIan Munsie rc = opal_pci_set_phb_cxl_mode(phb->opal_id, 1, pe->pe_number); 138080c49c7eSIan Munsie if (rc) 138180c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 138280c49c7eSIan Munsie 138380c49c7eSIan Munsie return rc; 138480c49c7eSIan Munsie } 138580c49c7eSIan Munsie EXPORT_SYMBOL(pnv_phb_to_cxl); 138680c49c7eSIan Munsie 138780c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 138880c49c7eSIan Munsie * Returns the absolute hardware IRQ number 138980c49c7eSIan Munsie */ 139080c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 139180c49c7eSIan Munsie { 139280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 139380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 139480c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 139580c49c7eSIan Munsie 139680c49c7eSIan Munsie if (hwirq < 0) { 139780c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 139880c49c7eSIan Munsie return -ENOSPC; 139980c49c7eSIan Munsie } 140080c49c7eSIan Munsie 140180c49c7eSIan Munsie return phb->msi_base + hwirq; 140280c49c7eSIan Munsie } 140380c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 140480c49c7eSIan Munsie 140580c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 140680c49c7eSIan Munsie { 140780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 140880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 140980c49c7eSIan Munsie 141080c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 141180c49c7eSIan Munsie } 141280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 141380c49c7eSIan Munsie 141480c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 141580c49c7eSIan Munsie struct pci_dev *dev) 141680c49c7eSIan Munsie { 141780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 141880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 141980c49c7eSIan Munsie int i, hwirq; 142080c49c7eSIan Munsie 142180c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 142280c49c7eSIan Munsie if (!irqs->range[i]) 142380c49c7eSIan Munsie continue; 142480c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 142580c49c7eSIan Munsie i, irqs->offset[i], 142680c49c7eSIan Munsie irqs->range[i]); 142780c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 142880c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 142980c49c7eSIan Munsie irqs->range[i]); 143080c49c7eSIan Munsie } 143180c49c7eSIan Munsie } 143280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 143380c49c7eSIan Munsie 143480c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 143580c49c7eSIan Munsie struct pci_dev *dev, int num) 143680c49c7eSIan Munsie { 143780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 143880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 143980c49c7eSIan Munsie int i, hwirq, try; 144080c49c7eSIan Munsie 144180c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 144280c49c7eSIan Munsie 144380c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 144480c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 144580c49c7eSIan Munsie try = num; 144680c49c7eSIan Munsie while (try) { 144780c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 144880c49c7eSIan Munsie if (hwirq >= 0) 144980c49c7eSIan Munsie break; 145080c49c7eSIan Munsie try /= 2; 145180c49c7eSIan Munsie } 145280c49c7eSIan Munsie if (!try) 145380c49c7eSIan Munsie goto fail; 145480c49c7eSIan Munsie 145580c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 145680c49c7eSIan Munsie irqs->range[i] = try; 145780c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 145880c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 145980c49c7eSIan Munsie num -= try; 146080c49c7eSIan Munsie } 146180c49c7eSIan Munsie if (num) 146280c49c7eSIan Munsie goto fail; 146380c49c7eSIan Munsie 146480c49c7eSIan Munsie return 0; 146580c49c7eSIan Munsie fail: 146680c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 146780c49c7eSIan Munsie return -ENOSPC; 146880c49c7eSIan Munsie } 146980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 147080c49c7eSIan Munsie 147180c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 147280c49c7eSIan Munsie { 147380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 147480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 147580c49c7eSIan Munsie 147680c49c7eSIan Munsie return phb->msi_bmp.irq_count; 147780c49c7eSIan Munsie } 147880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 147980c49c7eSIan Munsie 148080c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 148180c49c7eSIan Munsie unsigned int virq) 148280c49c7eSIan Munsie { 148380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 148480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 148580c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 148680c49c7eSIan Munsie struct pnv_ioda_pe *pe; 148780c49c7eSIan Munsie int rc; 148880c49c7eSIan Munsie 148980c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 149080c49c7eSIan Munsie return -ENODEV; 149180c49c7eSIan Munsie 149280c49c7eSIan Munsie /* Assign XIVE to PE */ 149380c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 149480c49c7eSIan Munsie if (rc) { 149580c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 149680c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 149780c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 149880c49c7eSIan Munsie return -EIO; 149980c49c7eSIan Munsie } 150080c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 150180c49c7eSIan Munsie 150280c49c7eSIan Munsie return 0; 150380c49c7eSIan Munsie } 150480c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 150580c49c7eSIan Munsie #endif 150680c49c7eSIan Munsie 1507184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 1508137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 1509137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 1510184cd4a3SBenjamin Herrenschmidt { 1511184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 1512184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 15133a1a4661SBenjamin Herrenschmidt __be32 data; 1514184cd4a3SBenjamin Herrenschmidt int rc; 1515184cd4a3SBenjamin Herrenschmidt 1516184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 1517184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 1518184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1519184cd4a3SBenjamin Herrenschmidt 1520184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 1521184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 1522184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1523184cd4a3SBenjamin Herrenschmidt 1524b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 152536074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 1526b72c1f65SBenjamin Herrenschmidt is_64 = 0; 1527b72c1f65SBenjamin Herrenschmidt 1528184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 1529184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 1530184cd4a3SBenjamin Herrenschmidt if (rc) { 1531184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 1532184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 1533184cd4a3SBenjamin Herrenschmidt return -EIO; 1534184cd4a3SBenjamin Herrenschmidt } 1535184cd4a3SBenjamin Herrenschmidt 1536184cd4a3SBenjamin Herrenschmidt if (is_64) { 15373a1a4661SBenjamin Herrenschmidt __be64 addr64; 15383a1a4661SBenjamin Herrenschmidt 1539184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 1540184cd4a3SBenjamin Herrenschmidt &addr64, &data); 1541184cd4a3SBenjamin Herrenschmidt if (rc) { 1542184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 1543184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1544184cd4a3SBenjamin Herrenschmidt return -EIO; 1545184cd4a3SBenjamin Herrenschmidt } 15463a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 15473a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 1548184cd4a3SBenjamin Herrenschmidt } else { 15493a1a4661SBenjamin Herrenschmidt __be32 addr32; 15503a1a4661SBenjamin Herrenschmidt 1551184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 1552184cd4a3SBenjamin Herrenschmidt &addr32, &data); 1553184cd4a3SBenjamin Herrenschmidt if (rc) { 1554184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 1555184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1556184cd4a3SBenjamin Herrenschmidt return -EIO; 1557184cd4a3SBenjamin Herrenschmidt } 1558184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 15593a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 1560184cd4a3SBenjamin Herrenschmidt } 15613a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 1562184cd4a3SBenjamin Herrenschmidt 1563fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 1564137436c9SGavin Shan 1565184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 1566184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 1567184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 1568184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 1569184cd4a3SBenjamin Herrenschmidt 1570184cd4a3SBenjamin Herrenschmidt return 0; 1571184cd4a3SBenjamin Herrenschmidt } 1572184cd4a3SBenjamin Herrenschmidt 1573184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 1574184cd4a3SBenjamin Herrenschmidt { 1575fb1b55d6SGavin Shan unsigned int count; 1576184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 1577184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 1578184cd4a3SBenjamin Herrenschmidt if (!prop) { 1579184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 1580184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 1581184cd4a3SBenjamin Herrenschmidt } 1582184cd4a3SBenjamin Herrenschmidt if (!prop) 1583184cd4a3SBenjamin Herrenschmidt return; 1584184cd4a3SBenjamin Herrenschmidt 1585184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 1586fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 1587fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 1588184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 1589184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 1590184cd4a3SBenjamin Herrenschmidt return; 1591184cd4a3SBenjamin Herrenschmidt } 1592fb1b55d6SGavin Shan 1593184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 1594184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 1595184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 1596fb1b55d6SGavin Shan count, phb->msi_base); 1597184cd4a3SBenjamin Herrenschmidt } 1598184cd4a3SBenjamin Herrenschmidt #else 1599184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 1600184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 1601184cd4a3SBenjamin Herrenschmidt 160211685becSGavin Shan /* 160311685becSGavin Shan * This function is supposed to be called on basis of PE from top 160411685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 160511685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 160611685becSGavin Shan */ 1607cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 160811685becSGavin Shan struct pnv_ioda_pe *pe) 160911685becSGavin Shan { 161011685becSGavin Shan struct pnv_phb *phb = hose->private_data; 161111685becSGavin Shan struct pci_bus_region region; 161211685becSGavin Shan struct resource *res; 161311685becSGavin Shan int i, index; 161411685becSGavin Shan int rc; 161511685becSGavin Shan 161611685becSGavin Shan /* 161711685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 161811685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 161911685becSGavin Shan * be figured out later. 162011685becSGavin Shan */ 162111685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 162211685becSGavin Shan 162311685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 162411685becSGavin Shan if (!res || !res->flags || 162511685becSGavin Shan res->start > res->end) 162611685becSGavin Shan continue; 162711685becSGavin Shan 162811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 162911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 163011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 163111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 163211685becSGavin Shan 163311685becSGavin Shan while (index < phb->ioda.total_pe && 163411685becSGavin Shan region.start <= region.end) { 163511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 163611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 163711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 163811685becSGavin Shan if (rc != OPAL_SUCCESS) { 163911685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 164011685becSGavin Shan "segment #%d to PE#%d\n", 164111685becSGavin Shan __func__, rc, index, pe->pe_number); 164211685becSGavin Shan break; 164311685becSGavin Shan } 164411685becSGavin Shan 164511685becSGavin Shan region.start += phb->ioda.io_segsize; 164611685becSGavin Shan index++; 164711685becSGavin Shan } 164811685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 164911685becSGavin Shan region.start = res->start - 16503fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 165111685becSGavin Shan phb->ioda.m32_pci_base; 165211685becSGavin Shan region.end = res->end - 16533fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 165411685becSGavin Shan phb->ioda.m32_pci_base; 165511685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 165611685becSGavin Shan 165711685becSGavin Shan while (index < phb->ioda.total_pe && 165811685becSGavin Shan region.start <= region.end) { 165911685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 166011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 166111685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 166211685becSGavin Shan if (rc != OPAL_SUCCESS) { 166311685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 166411685becSGavin Shan "segment#%d to PE#%d", 166511685becSGavin Shan __func__, rc, index, pe->pe_number); 166611685becSGavin Shan break; 166711685becSGavin Shan } 166811685becSGavin Shan 166911685becSGavin Shan region.start += phb->ioda.m32_segsize; 167011685becSGavin Shan index++; 167111685becSGavin Shan } 167211685becSGavin Shan } 167311685becSGavin Shan } 167411685becSGavin Shan } 167511685becSGavin Shan 1676cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 167711685becSGavin Shan { 167811685becSGavin Shan struct pci_controller *tmp, *hose; 167911685becSGavin Shan struct pnv_phb *phb; 168011685becSGavin Shan struct pnv_ioda_pe *pe; 168111685becSGavin Shan 168211685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 168311685becSGavin Shan phb = hose->private_data; 168411685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 168511685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 168611685becSGavin Shan } 168711685becSGavin Shan } 168811685becSGavin Shan } 168911685becSGavin Shan 1690cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 169113395c48SGavin Shan { 169213395c48SGavin Shan struct pci_controller *hose, *tmp; 1693db1266c8SGavin Shan struct pnv_phb *phb; 169413395c48SGavin Shan 169513395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 169613395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 1697db1266c8SGavin Shan 1698db1266c8SGavin Shan /* Mark the PHB initialization done */ 1699db1266c8SGavin Shan phb = hose->private_data; 1700db1266c8SGavin Shan phb->initialized = 1; 170113395c48SGavin Shan } 170213395c48SGavin Shan } 170313395c48SGavin Shan 170437c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 170537c367f2SGavin Shan { 170637c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 170737c367f2SGavin Shan struct pci_controller *hose, *tmp; 170837c367f2SGavin Shan struct pnv_phb *phb; 170937c367f2SGavin Shan char name[16]; 171037c367f2SGavin Shan 171137c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 171237c367f2SGavin Shan phb = hose->private_data; 171337c367f2SGavin Shan 171437c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 171537c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 171637c367f2SGavin Shan if (!phb->dbgfs) 171737c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 171837c367f2SGavin Shan __func__, hose->global_number); 171937c367f2SGavin Shan } 172037c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 172137c367f2SGavin Shan } 172237c367f2SGavin Shan 1723cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 1724fb446ad0SGavin Shan { 1725fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 172611685becSGavin Shan pnv_pci_ioda_setup_seg(); 172713395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 1728e9cc17d4SGavin Shan 172937c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 173037c367f2SGavin Shan 1731e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1732e9cc17d4SGavin Shan eeh_init(); 1733dadcd6d6SMike Qiu eeh_addr_cache_build(); 1734e9cc17d4SGavin Shan #endif 1735fb446ad0SGavin Shan } 1736fb446ad0SGavin Shan 1737271fd03aSGavin Shan /* 1738271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 1739271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 1740271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 1741271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 1742271fd03aSGavin Shan * 1MiB for memory) will be returned. 1743271fd03aSGavin Shan * 1744271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 1745271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 1746271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 1747271fd03aSGavin Shan * resources. 1748271fd03aSGavin Shan */ 1749271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1750271fd03aSGavin Shan unsigned long type) 1751271fd03aSGavin Shan { 1752271fd03aSGavin Shan struct pci_dev *bridge; 1753271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1754271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1755271fd03aSGavin Shan int num_pci_bridges = 0; 1756271fd03aSGavin Shan 1757271fd03aSGavin Shan bridge = bus->self; 1758271fd03aSGavin Shan while (bridge) { 1759271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1760271fd03aSGavin Shan num_pci_bridges++; 1761271fd03aSGavin Shan if (num_pci_bridges >= 2) 1762271fd03aSGavin Shan return 1; 1763271fd03aSGavin Shan } 1764271fd03aSGavin Shan 1765271fd03aSGavin Shan bridge = bridge->bus->self; 1766271fd03aSGavin Shan } 1767271fd03aSGavin Shan 1768262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 1769262af557SGuo Chao if (phb->ioda.m64_segsize && 1770262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 1771262af557SGuo Chao return phb->ioda.m64_segsize; 1772271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1773271fd03aSGavin Shan return phb->ioda.m32_segsize; 1774271fd03aSGavin Shan 1775271fd03aSGavin Shan return phb->ioda.io_segsize; 1776271fd03aSGavin Shan } 1777271fd03aSGavin Shan 1778184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1779184cd4a3SBenjamin Herrenschmidt * assign a PE 1780184cd4a3SBenjamin Herrenschmidt */ 1781cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1782184cd4a3SBenjamin Herrenschmidt { 1783db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1784db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1785db1266c8SGavin Shan struct pci_dn *pdn; 1786184cd4a3SBenjamin Herrenschmidt 1787db1266c8SGavin Shan /* The function is probably called while the PEs have 1788db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1789db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1790db1266c8SGavin Shan * PEs isn't ready. 1791db1266c8SGavin Shan */ 1792db1266c8SGavin Shan if (!phb->initialized) 1793db1266c8SGavin Shan return 0; 1794db1266c8SGavin Shan 1795b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1796184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1797184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1798db1266c8SGavin Shan 1799184cd4a3SBenjamin Herrenschmidt return 0; 1800184cd4a3SBenjamin Herrenschmidt } 1801184cd4a3SBenjamin Herrenschmidt 1802184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1803184cd4a3SBenjamin Herrenschmidt u32 devfn) 1804184cd4a3SBenjamin Herrenschmidt { 1805184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1806184cd4a3SBenjamin Herrenschmidt } 1807184cd4a3SBenjamin Herrenschmidt 180873ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 180973ed148aSBenjamin Herrenschmidt { 1810d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 181173ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 181273ed148aSBenjamin Herrenschmidt } 181373ed148aSBenjamin Herrenschmidt 1814e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 1815e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 1816184cd4a3SBenjamin Herrenschmidt { 1817184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1818184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 18198184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 1820c681b93cSAlistair Popple const __be64 *prop64; 18213a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 1822f1b7cc3eSGavin Shan int len; 1823184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1824184cd4a3SBenjamin Herrenschmidt void *aux; 1825184cd4a3SBenjamin Herrenschmidt long rc; 1826184cd4a3SBenjamin Herrenschmidt 1827aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1828184cd4a3SBenjamin Herrenschmidt 1829184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1830184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1831184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1832184cd4a3SBenjamin Herrenschmidt return; 1833184cd4a3SBenjamin Herrenschmidt } 1834184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1835184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1836184cd4a3SBenjamin Herrenschmidt 1837184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 183858d714ecSGavin Shan if (!phb) { 183958d714ecSGavin Shan pr_err(" Out of memory !\n"); 184058d714ecSGavin Shan return; 184158d714ecSGavin Shan } 184258d714ecSGavin Shan 184358d714ecSGavin Shan /* Allocate PCI controller */ 1844184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 1845184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 184658d714ecSGavin Shan if (!phb->hose) { 184758d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 1848184cd4a3SBenjamin Herrenschmidt np->full_name); 184958d714ecSGavin Shan free_bootmem((unsigned long)phb, sizeof(struct pnv_phb)); 1850184cd4a3SBenjamin Herrenschmidt return; 1851184cd4a3SBenjamin Herrenschmidt } 1852184cd4a3SBenjamin Herrenschmidt 1853184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1854f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 1855f1b7cc3eSGavin Shan if (prop32 && len == 8) { 18563a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 18573a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 1858f1b7cc3eSGavin Shan } else { 1859f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 1860184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1861184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1862f1b7cc3eSGavin Shan } 1863184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1864e9cc17d4SGavin Shan phb->hub_id = hub_id; 1865184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1866aa0c033fSGavin Shan phb->type = ioda_type; 1867184cd4a3SBenjamin Herrenschmidt 1868cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1869cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1870cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1871f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1872aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1873cee72d5bSBenjamin Herrenschmidt else 1874cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1875cee72d5bSBenjamin Herrenschmidt 1876aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 18772f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 1878184cd4a3SBenjamin Herrenschmidt 1879aa0c033fSGavin Shan /* Get registers */ 1880184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1881184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1882184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1883184cd4a3SBenjamin Herrenschmidt 1884184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1885aa0c033fSGavin Shan phb->ioda.total_pe = 1; 188636954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 188736954dc7SGavin Shan if (prop32) 18883a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 188936954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 189036954dc7SGavin Shan if (prop32) 189136954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 1892262af557SGuo Chao 1893262af557SGuo Chao /* Parse 64-bit MMIO range */ 1894262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 1895262af557SGuo Chao 1896184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1897aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 1898184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 1899184cd4a3SBenjamin Herrenschmidt 1900184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 19013fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 1902184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 1903184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1904184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1905184cd4a3SBenjamin Herrenschmidt 1906c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 1907184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1908184cd4a3SBenjamin Herrenschmidt m32map_off = size; 1909e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 1910c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 1911c35d2a8cSGavin Shan iomap_off = size; 1912e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 1913c35d2a8cSGavin Shan } 1914184cd4a3SBenjamin Herrenschmidt pemap_off = size; 1915184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1916184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 1917184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 1918184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 1919184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 1920c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 1921184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 1922184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 192336954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 1924184cd4a3SBenjamin Herrenschmidt 19257ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1926184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 1927184cd4a3SBenjamin Herrenschmidt 1928184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 1929184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1930184cd4a3SBenjamin Herrenschmidt 1931aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 1932184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1933184cd4a3SBenjamin Herrenschmidt window_type, 1934184cd4a3SBenjamin Herrenschmidt window_num, 1935184cd4a3SBenjamin Herrenschmidt starting_real_address, 1936184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1937184cd4a3SBenjamin Herrenschmidt segment_size); 1938184cd4a3SBenjamin Herrenschmidt #endif 1939184cd4a3SBenjamin Herrenschmidt 1940262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 1941262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 1942262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 1943262af557SGuo Chao if (phb->ioda.m64_size) 1944262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 1945262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 1946262af557SGuo Chao if (phb->ioda.io_size) 1947262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 1948184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1949184cd4a3SBenjamin Herrenschmidt 1950262af557SGuo Chao 1951184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 195249dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 195349dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 195449dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 1955e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1956e9cc17d4SGavin Shan phb->eeh_ops = &ioda_eeh_ops; 1957e9cc17d4SGavin Shan #endif 1958184cd4a3SBenjamin Herrenschmidt 1959184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1960184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1961184cd4a3SBenjamin Herrenschmidt 1962184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1963184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1964cd15b048SBenjamin Herrenschmidt phb->dma_set_mask = pnv_pci_ioda_dma_set_mask; 1965fe7e85c6SGavin Shan phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; 1966184cd4a3SBenjamin Herrenschmidt 196773ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 196873ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 196973ed148aSBenjamin Herrenschmidt 1970184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1971184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1972184cd4a3SBenjamin Herrenschmidt 1973c40a4210SGavin Shan /* 1974c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1975c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1976c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1977c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1978c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1979184cd4a3SBenjamin Herrenschmidt */ 1980fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1981184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1982271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1983d92a208dSGavin Shan ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus; 1984c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1985184cd4a3SBenjamin Herrenschmidt 1986184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1987d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 1988184cd4a3SBenjamin Herrenschmidt if (rc) 1989f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1990361f2a2aSGavin Shan 1991361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 1992361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 1993361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 1994361f2a2aSGavin Shan * transactions from previous kerenl. 1995361f2a2aSGavin Shan */ 1996361f2a2aSGavin Shan if (is_kdump_kernel()) { 1997361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 1998361f2a2aSGavin Shan ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 1999361f2a2aSGavin Shan ioda_eeh_phb_reset(hose, OPAL_DEASSERT_RESET); 2000361f2a2aSGavin Shan } 2001262af557SGuo Chao 2002262af557SGuo Chao /* Configure M64 window */ 2003262af557SGuo Chao if (phb->init_m64 && phb->init_m64(phb)) 2004262af557SGuo Chao hose->mem_resources[1].flags = 0; 2005184cd4a3SBenjamin Herrenschmidt } 2006184cd4a3SBenjamin Herrenschmidt 200767975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 2008aa0c033fSGavin Shan { 2009e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 2010aa0c033fSGavin Shan } 2011aa0c033fSGavin Shan 2012184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 2013184cd4a3SBenjamin Herrenschmidt { 2014184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 2015c681b93cSAlistair Popple const __be64 *prop64; 2016184cd4a3SBenjamin Herrenschmidt u64 hub_id; 2017184cd4a3SBenjamin Herrenschmidt 2018184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 2019184cd4a3SBenjamin Herrenschmidt 2020184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 2021184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2022184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 2023184cd4a3SBenjamin Herrenschmidt return; 2024184cd4a3SBenjamin Herrenschmidt } 2025184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 2026184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 2027184cd4a3SBenjamin Herrenschmidt 2028184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 2029184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 2030184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 2031184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 2032e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 2033184cd4a3SBenjamin Herrenschmidt } 2034184cd4a3SBenjamin Herrenschmidt } 2035