12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 357644d581SMichael Ellerman #include <asm/debugfs.h> 36262af557SGuo Chao #include <asm/firmware.h> 3780c49c7eSIan Munsie #include <asm/pnv-pci.h> 38aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 3980c49c7eSIan Munsie 40ec249dd8SMichael Neuling #include <misc/cxl-base.h> 41184cd4a3SBenjamin Herrenschmidt 42184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 43184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4444bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 45184cd4a3SBenjamin Herrenschmidt 4699451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4799451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 48acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 49781a868fSWei Yang 50562d1e20SChristoph Hellwig static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_OCAPI" }; 51aca6913fSAlexey Kardashevskiy 52c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 53dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus); 54c498a4f9SChristoph Hellwig 557d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 566d31c2faSJoe Perches const char *fmt, ...) 576d31c2faSJoe Perches { 586d31c2faSJoe Perches struct va_format vaf; 596d31c2faSJoe Perches va_list args; 606d31c2faSJoe Perches char pfix[32]; 61184cd4a3SBenjamin Herrenschmidt 626d31c2faSJoe Perches va_start(args, fmt); 636d31c2faSJoe Perches 646d31c2faSJoe Perches vaf.fmt = fmt; 656d31c2faSJoe Perches vaf.va = &args; 666d31c2faSJoe Perches 67781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 686d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 69781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 706d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 716d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 72781a868fSWei Yang #ifdef CONFIG_PCI_IOV 73781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 74781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 75781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 76781a868fSWei Yang (pe->rid & 0xff00) >> 8, 77781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 78781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 796d31c2faSJoe Perches 801f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 816d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 826d31c2faSJoe Perches 836d31c2faSJoe Perches va_end(args); 846d31c2faSJoe Perches } 856d31c2faSJoe Perches 864e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8745baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 884e287840SThadeu Lima de Souza Cascardo 894e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 904e287840SThadeu Lima de Souza Cascardo { 914e287840SThadeu Lima de Souza Cascardo if (!str) 924e287840SThadeu Lima de Souza Cascardo return -EINVAL; 934e287840SThadeu Lima de Souza Cascardo 944e287840SThadeu Lima de Souza Cascardo while (*str) { 954e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 964e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 974e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 984e287840SThadeu Lima de Souza Cascardo break; 994e287840SThadeu Lima de Souza Cascardo } 1004e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1014e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1024e287840SThadeu Lima de Souza Cascardo str++; 1034e287840SThadeu Lima de Souza Cascardo } 1044e287840SThadeu Lima de Souza Cascardo 1054e287840SThadeu Lima de Souza Cascardo return 0; 1064e287840SThadeu Lima de Souza Cascardo } 1074e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1084e287840SThadeu Lima de Souza Cascardo 10945baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11045baee14SGuilherme G. Piccoli { 11145baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11245baee14SGuilherme G. Piccoli return 0; 11345baee14SGuilherme G. Piccoli } 11445baee14SGuilherme G. Piccoli 11545baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11645baee14SGuilherme G. Piccoli 1171e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1181e916772SGavin Shan { 119313483ddSGavin Shan s64 rc; 120313483ddSGavin Shan 1211e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1221e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 12301e12629SOliver O'Halloran phb->ioda.pe_array[pe_no].dma_setup_done = false; 1241e916772SGavin Shan 125313483ddSGavin Shan /* 126313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 127313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 128313483ddSGavin Shan * PE is already in unfrozen state. 129313483ddSGavin Shan */ 130313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 131313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 132d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1331f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 134313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 135313483ddSGavin Shan 1361e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1371e916772SGavin Shan } 1381e916772SGavin Shan 1394b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1404b82ab18SGavin Shan { 14192b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1421f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1434b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1444b82ab18SGavin Shan return; 1454b82ab18SGavin Shan } 1464b82ab18SGavin Shan 147a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 148e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1491f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1504b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 151a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 1524b82ab18SGavin Shan 1531e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1544b82ab18SGavin Shan } 1554b82ab18SGavin Shan 156a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count) 157184cd4a3SBenjamin Herrenschmidt { 158a4bc676eSOliver O'Halloran struct pnv_ioda_pe *ret = NULL; 159a4bc676eSOliver O'Halloran int run = 0, pe, i; 160184cd4a3SBenjamin Herrenschmidt 161a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 162a4bc676eSOliver O'Halloran 163a4bc676eSOliver O'Halloran /* scan backwards for a run of @count cleared bits */ 1649fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 165a4bc676eSOliver O'Halloran if (test_bit(pe, phb->ioda.pe_alloc)) { 166a4bc676eSOliver O'Halloran run = 0; 167a4bc676eSOliver O'Halloran continue; 168184cd4a3SBenjamin Herrenschmidt } 169184cd4a3SBenjamin Herrenschmidt 170a4bc676eSOliver O'Halloran run++; 171a4bc676eSOliver O'Halloran if (run == count) 172a4bc676eSOliver O'Halloran break; 173a4bc676eSOliver O'Halloran } 174a4bc676eSOliver O'Halloran if (run != count) 175a4bc676eSOliver O'Halloran goto out; 176a4bc676eSOliver O'Halloran 177a4bc676eSOliver O'Halloran for (i = pe; i < pe + count; i++) { 178a4bc676eSOliver O'Halloran set_bit(i, phb->ioda.pe_alloc); 179a4bc676eSOliver O'Halloran pnv_ioda_init_pe(phb, i); 180a4bc676eSOliver O'Halloran } 181a4bc676eSOliver O'Halloran ret = &phb->ioda.pe_array[pe]; 182a4bc676eSOliver O'Halloran 183a4bc676eSOliver O'Halloran out: 184a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 185a4bc676eSOliver O'Halloran return ret; 1869fcd6f4aSGavin Shan } 1879fcd6f4aSGavin Shan 18837b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 189184cd4a3SBenjamin Herrenschmidt { 1901e916772SGavin Shan struct pnv_phb *phb = pe->phb; 191caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 192184cd4a3SBenjamin Herrenschmidt 1931e916772SGavin Shan WARN_ON(pe->pdev); 1941e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 195a4bc676eSOliver O'Halloran 196a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 197caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 198a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 199184cd4a3SBenjamin Herrenschmidt } 200184cd4a3SBenjamin Herrenschmidt 201262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 202262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 203262af557SGuo Chao { 204262af557SGuo Chao const char *desc; 205262af557SGuo Chao struct resource *r; 206262af557SGuo Chao s64 rc; 207262af557SGuo Chao 208262af557SGuo Chao /* Configure the default M64 BAR */ 209262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 210262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 211262af557SGuo Chao phb->ioda.m64_bar_idx, 212262af557SGuo Chao phb->ioda.m64_base, 213262af557SGuo Chao 0, /* unused */ 214262af557SGuo Chao phb->ioda.m64_size); 215262af557SGuo Chao if (rc != OPAL_SUCCESS) { 216262af557SGuo Chao desc = "configuring"; 217262af557SGuo Chao goto fail; 218262af557SGuo Chao } 219262af557SGuo Chao 220262af557SGuo Chao /* Enable the default M64 BAR */ 221262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 222262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 223262af557SGuo Chao phb->ioda.m64_bar_idx, 224262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 225262af557SGuo Chao if (rc != OPAL_SUCCESS) { 226262af557SGuo Chao desc = "enabling"; 227262af557SGuo Chao goto fail; 228262af557SGuo Chao } 229262af557SGuo Chao 230262af557SGuo Chao /* 23163803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23263803c39SGavin Shan * are first or last two PEs. 233262af557SGuo Chao */ 234262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23592b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23663803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23792b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23863803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 239262af557SGuo Chao else 2401f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 24192b8f137SGavin Shan phb->ioda.reserved_pe_idx); 242262af557SGuo Chao 243262af557SGuo Chao return 0; 244262af557SGuo Chao 245262af557SGuo Chao fail: 246262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 247262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 248262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 249262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 250262af557SGuo Chao phb->ioda.m64_bar_idx, 251262af557SGuo Chao OPAL_DISABLE_M64); 252262af557SGuo Chao return -EIO; 253262af557SGuo Chao } 254262af557SGuo Chao 255c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25696a2f92bSGavin Shan unsigned long *pe_bitmap) 257262af557SGuo Chao { 2585609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 259262af557SGuo Chao struct resource *r; 26096a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26196a2f92bSGavin Shan int segno, i; 262262af557SGuo Chao 26396a2f92bSGavin Shan base = phb->ioda.m64_base; 26496a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26596a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26696a2f92bSGavin Shan r = &pdev->resource[i]; 2675958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 268262af557SGuo Chao continue; 269262af557SGuo Chao 270e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 271b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 27296a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27396a2f92bSGavin Shan if (pe_bitmap) 27496a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27596a2f92bSGavin Shan else 27696a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 277262af557SGuo Chao } 278262af557SGuo Chao } 279262af557SGuo Chao } 280262af557SGuo Chao 28199451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28299451551SGavin Shan { 28399451551SGavin Shan struct resource *r; 28499451551SGavin Shan int index; 28599451551SGavin Shan 28699451551SGavin Shan /* 28799451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28899451551SGavin Shan * there are as many M64 segments as the maximum number of 28999451551SGavin Shan * PEs, which is 128. 29099451551SGavin Shan */ 29199451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29299451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29399451551SGavin Shan int64_t rc; 29499451551SGavin Shan 29599451551SGavin Shan base = phb->ioda.m64_base + 29699451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29799451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29899451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29999451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 30099451551SGavin Shan if (rc != OPAL_SUCCESS) { 3011f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30299451551SGavin Shan rc, phb->hose->global_number, index); 30399451551SGavin Shan goto fail; 30499451551SGavin Shan } 30599451551SGavin Shan 30699451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30799451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30899451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30999451551SGavin Shan if (rc != OPAL_SUCCESS) { 3101f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31199451551SGavin Shan rc, phb->hose->global_number, index); 31299451551SGavin Shan goto fail; 31399451551SGavin Shan } 31499451551SGavin Shan } 31599451551SGavin Shan 31636963365SOliver O'Halloran for (index = 0; index < phb->ioda.total_pe_num; index++) { 31736963365SOliver O'Halloran int64_t rc; 31836963365SOliver O'Halloran 31936963365SOliver O'Halloran /* 32036963365SOliver O'Halloran * P7IOC supports M64DT, which helps mapping M64 segment 32136963365SOliver O'Halloran * to one particular PE#. However, PHB3 has fixed mapping 32236963365SOliver O'Halloran * between M64 segment and PE#. In order to have same logic 32336963365SOliver O'Halloran * for P7IOC and PHB3, we enforce fixed mapping between M64 32436963365SOliver O'Halloran * segment and PE# on P7IOC. 32536963365SOliver O'Halloran */ 32636963365SOliver O'Halloran rc = opal_pci_map_pe_mmio_window(phb->opal_id, 32736963365SOliver O'Halloran index, OPAL_M64_WINDOW_TYPE, 32836963365SOliver O'Halloran index / PNV_IODA1_M64_SEGS, 32936963365SOliver O'Halloran index % PNV_IODA1_M64_SEGS); 33036963365SOliver O'Halloran if (rc != OPAL_SUCCESS) { 33136963365SOliver O'Halloran pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 33236963365SOliver O'Halloran __func__, rc, phb->hose->global_number, 33336963365SOliver O'Halloran index); 33436963365SOliver O'Halloran goto fail; 33536963365SOliver O'Halloran } 33636963365SOliver O'Halloran } 33736963365SOliver O'Halloran 33899451551SGavin Shan /* 33963803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 34063803c39SGavin Shan * are first or last two PEs. 34199451551SGavin Shan */ 34299451551SGavin Shan r = &phb->hose->mem_resources[1]; 34399451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 34463803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 34599451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 34663803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 34799451551SGavin Shan else 3481f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 34999451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 35099451551SGavin Shan 35199451551SGavin Shan return 0; 35299451551SGavin Shan 35399451551SGavin Shan fail: 35499451551SGavin Shan for ( ; index >= 0; index--) 35599451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 35699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 35799451551SGavin Shan 35899451551SGavin Shan return -EIO; 35999451551SGavin Shan } 36099451551SGavin Shan 361c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 36296a2f92bSGavin Shan unsigned long *pe_bitmap, 36396a2f92bSGavin Shan bool all) 364262af557SGuo Chao { 365262af557SGuo Chao struct pci_dev *pdev; 36696a2f92bSGavin Shan 36796a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 368c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 36996a2f92bSGavin Shan 37096a2f92bSGavin Shan if (all && pdev->subordinate) 371c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 37296a2f92bSGavin Shan pe_bitmap, all); 37396a2f92bSGavin Shan } 37496a2f92bSGavin Shan } 37596a2f92bSGavin Shan 3761e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 377262af557SGuo Chao { 3785609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 379262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 380262af557SGuo Chao unsigned long size, *pe_alloc; 38126ba248dSGavin Shan int i; 382262af557SGuo Chao 383262af557SGuo Chao /* Root bus shouldn't use M64 */ 384262af557SGuo Chao if (pci_is_root_bus(bus)) 3851e916772SGavin Shan return NULL; 386262af557SGuo Chao 387262af557SGuo Chao /* Allocate bitmap */ 388b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 389262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 390262af557SGuo Chao if (!pe_alloc) { 391262af557SGuo Chao pr_warn("%s: Out of memory !\n", 392262af557SGuo Chao __func__); 3931e916772SGavin Shan return NULL; 394262af557SGuo Chao } 395262af557SGuo Chao 39626ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 397c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 398262af557SGuo Chao 399262af557SGuo Chao /* 400262af557SGuo Chao * the current bus might not own M64 window and that's all 401262af557SGuo Chao * contributed by its child buses. For the case, we needn't 402262af557SGuo Chao * pick M64 dependent PE#. 403262af557SGuo Chao */ 40492b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 405262af557SGuo Chao kfree(pe_alloc); 4061e916772SGavin Shan return NULL; 407262af557SGuo Chao } 408262af557SGuo Chao 409262af557SGuo Chao /* 410262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 411262af557SGuo Chao * PE's list to form compound PE. 412262af557SGuo Chao */ 413262af557SGuo Chao master_pe = NULL; 414262af557SGuo Chao i = -1; 41592b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 41692b8f137SGavin Shan phb->ioda.total_pe_num) { 417262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 418262af557SGuo Chao 41993289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 420262af557SGuo Chao if (!master_pe) { 421262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 422262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 423262af557SGuo Chao master_pe = pe; 424262af557SGuo Chao } else { 425262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 426262af557SGuo Chao pe->master = master_pe; 427262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 428262af557SGuo Chao } 429262af557SGuo Chao } 430262af557SGuo Chao 431262af557SGuo Chao kfree(pe_alloc); 4321e916772SGavin Shan return master_pe; 433262af557SGuo Chao } 434262af557SGuo Chao 435262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 436262af557SGuo Chao { 437262af557SGuo Chao struct pci_controller *hose = phb->hose; 438262af557SGuo Chao struct device_node *dn = hose->dn; 439262af557SGuo Chao struct resource *res; 440a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4410e7736c6SGavin Shan const __be32 *r; 442262af557SGuo Chao u64 pci_addr; 443262af557SGuo Chao 44499451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4451665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4461665c4a8SGavin Shan return; 4471665c4a8SGavin Shan } 4481665c4a8SGavin Shan 449e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 450262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 451262af557SGuo Chao return; 452262af557SGuo Chao } 453262af557SGuo Chao 454262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 455262af557SGuo Chao if (!r) { 456b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 457b7c670d6SRob Herring dn); 458262af557SGuo Chao return; 459262af557SGuo Chao } 460262af557SGuo Chao 461a1339fafSBenjamin Herrenschmidt /* 462a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 463a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 464a1339fafSBenjamin Herrenschmidt */ 465a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 466a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 467a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 468a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 469a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 470a1339fafSBenjamin Herrenschmidt } 471a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 472a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 473a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 474a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 475a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 476a1339fafSBenjamin Herrenschmidt } 477a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 478a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 479a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 480a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 481a1339fafSBenjamin Herrenschmidt return; 482a1339fafSBenjamin Herrenschmidt } 483a1339fafSBenjamin Herrenschmidt 484a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 485262af557SGuo Chao res = &hose->mem_resources[1]; 486e80c4e7cSGavin Shan res->name = dn->full_name; 487262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 488262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 489262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 490262af557SGuo Chao pci_addr = of_read_number(r, 2); 491262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 492262af557SGuo Chao 493262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49492b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 495262af557SGuo Chao phb->ioda.m64_base = pci_addr; 496262af557SGuo Chao 497a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 498a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 499a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 500a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 501a1339fafSBenjamin Herrenschmidt 502a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 503a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 504e9863e68SWei Yang 505262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 506a1339fafSBenjamin Herrenschmidt m64_range[1]--; 507a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 508a1339fafSBenjamin Herrenschmidt 509a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 510a1339fafSBenjamin Herrenschmidt 511a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 512a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 513a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 514a1339fafSBenjamin Herrenschmidt 515a1339fafSBenjamin Herrenschmidt /* 516a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 517a1339fafSBenjamin Herrenschmidt * the IODA2 code. 518a1339fafSBenjamin Herrenschmidt */ 51999451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 52099451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 52199451551SGavin Shan else 522262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 523262af557SGuo Chao } 524262af557SGuo Chao 52549dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52649dec922SGavin Shan { 52749dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52849dec922SGavin Shan struct pnv_ioda_pe *slave; 52949dec922SGavin Shan s64 rc; 53049dec922SGavin Shan 53149dec922SGavin Shan /* Fetch master PE */ 53249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53349dec922SGavin Shan pe = pe->master; 534ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 535ec8e4e9dSGavin Shan return; 536ec8e4e9dSGavin Shan 53749dec922SGavin Shan pe_no = pe->pe_number; 53849dec922SGavin Shan } 53949dec922SGavin Shan 54049dec922SGavin Shan /* Freeze master PE */ 54149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54249dec922SGavin Shan pe_no, 54349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54649dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54749dec922SGavin Shan return; 54849dec922SGavin Shan } 54949dec922SGavin Shan 55049dec922SGavin Shan /* Freeze slave PEs */ 55149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55249dec922SGavin Shan return; 55349dec922SGavin Shan 55449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55549dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55649dec922SGavin Shan slave->pe_number, 55749dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55849dec922SGavin Shan if (rc != OPAL_SUCCESS) 55949dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 56049dec922SGavin Shan __func__, rc, phb->hose->global_number, 56149dec922SGavin Shan slave->pe_number); 56249dec922SGavin Shan } 56349dec922SGavin Shan } 56449dec922SGavin Shan 565e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56649dec922SGavin Shan { 56749dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56849dec922SGavin Shan s64 rc; 56949dec922SGavin Shan 57049dec922SGavin Shan /* Find master PE */ 57149dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57349dec922SGavin Shan pe = pe->master; 57449dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57549dec922SGavin Shan pe_no = pe->pe_number; 57649dec922SGavin Shan } 57749dec922SGavin Shan 57849dec922SGavin Shan /* Clear frozen state for master PE */ 57949dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 58049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58349dec922SGavin Shan return -EIO; 58449dec922SGavin Shan } 58549dec922SGavin Shan 58649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58749dec922SGavin Shan return 0; 58849dec922SGavin Shan 58949dec922SGavin Shan /* Clear frozen state for slave PEs */ 59049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59149dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59249dec922SGavin Shan slave->pe_number, 59349dec922SGavin Shan opt); 59449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59549dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59649dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59749dec922SGavin Shan slave->pe_number); 59849dec922SGavin Shan return -EIO; 59949dec922SGavin Shan } 60049dec922SGavin Shan } 60149dec922SGavin Shan 60249dec922SGavin Shan return 0; 60349dec922SGavin Shan } 60449dec922SGavin Shan 60549dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60649dec922SGavin Shan { 60749dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 608c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 609c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 61049dec922SGavin Shan s64 rc; 61149dec922SGavin Shan 61249dec922SGavin Shan /* Sanity check on PE number */ 61392b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61449dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61549dec922SGavin Shan 61649dec922SGavin Shan /* 61749dec922SGavin Shan * Fetch the master PE and the PE instance might be 61849dec922SGavin Shan * not initialized yet. 61949dec922SGavin Shan */ 62049dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62249dec922SGavin Shan pe = pe->master; 62349dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62449dec922SGavin Shan pe_no = pe->pe_number; 62549dec922SGavin Shan } 62649dec922SGavin Shan 62749dec922SGavin Shan /* Check the master PE */ 62849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62949dec922SGavin Shan &state, &pcierr, NULL); 63049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63149dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63249dec922SGavin Shan "PHB#%x-PE#%x state\n", 63349dec922SGavin Shan __func__, rc, 63449dec922SGavin Shan phb->hose->global_number, pe_no); 63549dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63649dec922SGavin Shan } 63749dec922SGavin Shan 63849dec922SGavin Shan /* Check the slave PE */ 63949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 64049dec922SGavin Shan return state; 64149dec922SGavin Shan 64249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64449dec922SGavin Shan slave->pe_number, 64549dec922SGavin Shan &fstate, 64649dec922SGavin Shan &pcierr, 64749dec922SGavin Shan NULL); 64849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64949dec922SGavin Shan pr_warn("%s: Failure %lld getting " 65049dec922SGavin Shan "PHB#%x-PE#%x state\n", 65149dec922SGavin Shan __func__, rc, 65249dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65349dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65449dec922SGavin Shan } 65549dec922SGavin Shan 65649dec922SGavin Shan /* 65749dec922SGavin Shan * Override the result based on the ascending 65849dec922SGavin Shan * priority. 65949dec922SGavin Shan */ 66049dec922SGavin Shan if (fstate > state) 66149dec922SGavin Shan state = fstate; 66249dec922SGavin Shan } 66349dec922SGavin Shan 66449dec922SGavin Shan return state; 66549dec922SGavin Shan } 66649dec922SGavin Shan 667a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 668a8d7d5fcSOliver O'Halloran { 669a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn]; 670a8d7d5fcSOliver O'Halloran 671a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE) 672a8d7d5fcSOliver O'Halloran return NULL; 673a8d7d5fcSOliver O'Halloran 674a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number]; 675a8d7d5fcSOliver O'Halloran } 676a8d7d5fcSOliver O'Halloran 677f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 678184cd4a3SBenjamin Herrenschmidt { 6795609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 680b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 681184cd4a3SBenjamin Herrenschmidt 682184cd4a3SBenjamin Herrenschmidt if (!pdn) 683184cd4a3SBenjamin Herrenschmidt return NULL; 684184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 685184cd4a3SBenjamin Herrenschmidt return NULL; 686184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 687184cd4a3SBenjamin Herrenschmidt } 688184cd4a3SBenjamin Herrenschmidt 689b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 690b131a842SGavin Shan struct pnv_ioda_pe *parent, 691b131a842SGavin Shan struct pnv_ioda_pe *child, 692b131a842SGavin Shan bool is_add) 693b131a842SGavin Shan { 694b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 695b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 696b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 697b131a842SGavin Shan struct pnv_ioda_pe *slave; 698b131a842SGavin Shan long rc; 699b131a842SGavin Shan 700b131a842SGavin Shan /* Parent PE affects child PE */ 701b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 702b131a842SGavin Shan child->pe_number, op); 703b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 704b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 705b131a842SGavin Shan rc, desc); 706b131a842SGavin Shan return -ENXIO; 707b131a842SGavin Shan } 708b131a842SGavin Shan 709b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 710b131a842SGavin Shan return 0; 711b131a842SGavin Shan 712b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 713b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 714b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 715b131a842SGavin Shan slave->pe_number, op); 716b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 717b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 718b131a842SGavin Shan rc, desc); 719b131a842SGavin Shan return -ENXIO; 720b131a842SGavin Shan } 721b131a842SGavin Shan } 722b131a842SGavin Shan 723b131a842SGavin Shan return 0; 724b131a842SGavin Shan } 725b131a842SGavin Shan 726b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 727b131a842SGavin Shan struct pnv_ioda_pe *pe, 728b131a842SGavin Shan bool is_add) 729b131a842SGavin Shan { 730b131a842SGavin Shan struct pnv_ioda_pe *slave; 731781a868fSWei Yang struct pci_dev *pdev = NULL; 732b131a842SGavin Shan int ret; 733b131a842SGavin Shan 734b131a842SGavin Shan /* 735b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 736b131a842SGavin Shan * clear slave PE frozen state as well. 737b131a842SGavin Shan */ 738b131a842SGavin Shan if (is_add) { 739b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 740b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 741b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 742b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 743b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 744b131a842SGavin Shan slave->pe_number, 745b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 746b131a842SGavin Shan } 747b131a842SGavin Shan } 748b131a842SGavin Shan 749b131a842SGavin Shan /* 750b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 751b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 752b131a842SGavin Shan * originated from the PE might contribute to other 753b131a842SGavin Shan * PEs. 754b131a842SGavin Shan */ 755b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 756b131a842SGavin Shan if (ret) 757b131a842SGavin Shan return ret; 758b131a842SGavin Shan 759b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 760b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 761b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 762b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 763b131a842SGavin Shan if (ret) 764b131a842SGavin Shan return ret; 765b131a842SGavin Shan } 766b131a842SGavin Shan } 767b131a842SGavin Shan 768b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 769b131a842SGavin Shan pdev = pe->pbus->self; 770781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 771b131a842SGavin Shan pdev = pe->pdev->bus->self; 772781a868fSWei Yang #ifdef CONFIG_PCI_IOV 773781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 774283e2d8aSGavin Shan pdev = pe->parent_dev; 775781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 776b131a842SGavin Shan while (pdev) { 777b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 778b131a842SGavin Shan struct pnv_ioda_pe *parent; 779b131a842SGavin Shan 780b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 781b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 782b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 783b131a842SGavin Shan if (ret) 784b131a842SGavin Shan return ret; 785b131a842SGavin Shan } 786b131a842SGavin Shan 787b131a842SGavin Shan pdev = pdev->bus->self; 788b131a842SGavin Shan } 789b131a842SGavin Shan 790b131a842SGavin Shan return 0; 791b131a842SGavin Shan } 792b131a842SGavin Shan 793f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 794f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 795f724385fSFrederic Barrat struct pci_dev *parent) 796f724385fSFrederic Barrat { 797f724385fSFrederic Barrat int64_t rc; 798f724385fSFrederic Barrat 799f724385fSFrederic Barrat while (parent) { 800f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 801f724385fSFrederic Barrat 802f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 803f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 804f724385fSFrederic Barrat pe->pe_number, 805f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 806f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 807f724385fSFrederic Barrat } 808f724385fSFrederic Barrat parent = parent->bus->self; 809f724385fSFrederic Barrat } 810f724385fSFrederic Barrat 811f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 812f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 813f724385fSFrederic Barrat 814f724385fSFrederic Barrat /* Disassociate PE in PELT */ 815f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 816f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 817f724385fSFrederic Barrat if (rc) 818f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 819f724385fSFrederic Barrat } 820f724385fSFrederic Barrat 82137b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 822781a868fSWei Yang { 823781a868fSWei Yang struct pci_dev *parent; 824781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 825781a868fSWei Yang int64_t rc; 826781a868fSWei Yang long rid_end, rid; 827781a868fSWei Yang 828781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 829781a868fSWei Yang if (pe->pbus) { 830781a868fSWei Yang int count; 831781a868fSWei Yang 832781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 833781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 834781a868fSWei Yang parent = pe->pbus->self; 835781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 836552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 837781a868fSWei Yang else 838781a868fSWei Yang count = 1; 839781a868fSWei Yang 840781a868fSWei Yang switch(count) { 841781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 842781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 843781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 844781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 845781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 846781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 847781a868fSWei Yang default: 848781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 849781a868fSWei Yang count); 850781a868fSWei Yang /* Do an exact match only */ 851781a868fSWei Yang bcomp = OpalPciBusAll; 852781a868fSWei Yang } 853781a868fSWei Yang rid_end = pe->rid + (count << 8); 854781a868fSWei Yang } else { 85593e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 856781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 857781a868fSWei Yang parent = pe->parent_dev; 858781a868fSWei Yang else 85993e01a50SGavin Shan #endif 860781a868fSWei Yang parent = pe->pdev->bus->self; 861781a868fSWei Yang bcomp = OpalPciBusAll; 862781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 863781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 864781a868fSWei Yang rid_end = pe->rid + 1; 865781a868fSWei Yang } 866781a868fSWei Yang 867781a868fSWei Yang /* Clear the reverse map */ 868781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 869c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 870781a868fSWei Yang 871f724385fSFrederic Barrat /* 872f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 873f724385fSFrederic Barrat * table 874f724385fSFrederic Barrat */ 875562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI) 876f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 877781a868fSWei Yang 878781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 879781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 880781a868fSWei Yang if (rc) 8811e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 882781a868fSWei Yang 883781a868fSWei Yang pe->pbus = NULL; 884781a868fSWei Yang pe->pdev = NULL; 88593e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 886781a868fSWei Yang pe->parent_dev = NULL; 88793e01a50SGavin Shan #endif 888781a868fSWei Yang 889781a868fSWei Yang return 0; 890781a868fSWei Yang } 891781a868fSWei Yang 89237b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 893184cd4a3SBenjamin Herrenschmidt { 894184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 895184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 896184cd4a3SBenjamin Herrenschmidt 897184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 898184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 899184cd4a3SBenjamin Herrenschmidt int count; 900184cd4a3SBenjamin Herrenschmidt 901184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 902184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 903fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 904552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 905fb446ad0SGavin Shan else 906fb446ad0SGavin Shan count = 1; 907fb446ad0SGavin Shan 908184cd4a3SBenjamin Herrenschmidt switch(count) { 909184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 910184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 911184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 912184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 913184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 914184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 915184cd4a3SBenjamin Herrenschmidt default: 916781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 917781a868fSWei Yang count); 918184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 919184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 920184cd4a3SBenjamin Herrenschmidt } 921184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 922184cd4a3SBenjamin Herrenschmidt } else { 923184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 924184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 925184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 926184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 927184cd4a3SBenjamin Herrenschmidt } 928184cd4a3SBenjamin Herrenschmidt 929631ad691SGavin Shan /* 930631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 931631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 932631ad691SGavin Shan * originated from the PE might contribute to other 933631ad691SGavin Shan * PEs. 934631ad691SGavin Shan */ 935184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 936184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 937184cd4a3SBenjamin Herrenschmidt if (rc) { 938184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 939184cd4a3SBenjamin Herrenschmidt return -ENXIO; 940184cd4a3SBenjamin Herrenschmidt } 941631ad691SGavin Shan 9425d2aa710SAlistair Popple /* 9435d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9445d2aa710SAlistair Popple * configuration on them. 9455d2aa710SAlistair Popple */ 946562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI) 947b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 948184cd4a3SBenjamin Herrenschmidt 949184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 950184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 951184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 952184cd4a3SBenjamin Herrenschmidt 953184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9544773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9554773f76bSGavin Shan pe->mve_number = 0; 9564773f76bSGavin Shan goto out; 9574773f76bSGavin Shan } 9584773f76bSGavin Shan 959184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9604773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9614773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9621f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 963184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 964184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 965184cd4a3SBenjamin Herrenschmidt } else { 966184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 967cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 968184cd4a3SBenjamin Herrenschmidt if (rc) { 9691f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 970184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 971184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 972184cd4a3SBenjamin Herrenschmidt } 973184cd4a3SBenjamin Herrenschmidt } 974184cd4a3SBenjamin Herrenschmidt 9754773f76bSGavin Shan out: 976184cd4a3SBenjamin Herrenschmidt return 0; 977184cd4a3SBenjamin Herrenschmidt } 978184cd4a3SBenjamin Herrenschmidt 979cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 980184cd4a3SBenjamin Herrenschmidt { 9815609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 982b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 983184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 984184cd4a3SBenjamin Herrenschmidt 985184cd4a3SBenjamin Herrenschmidt if (!pdn) { 986184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 987184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 988184cd4a3SBenjamin Herrenschmidt return NULL; 989184cd4a3SBenjamin Herrenschmidt } 990184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 991184cd4a3SBenjamin Herrenschmidt return NULL; 992184cd4a3SBenjamin Herrenschmidt 993a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 9941e916772SGavin Shan if (!pe) { 995f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 996184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 997184cd4a3SBenjamin Herrenschmidt return NULL; 998184cd4a3SBenjamin Herrenschmidt } 999184cd4a3SBenjamin Herrenschmidt 100005dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 100105dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 1002562d1e20SChristoph Hellwig * destroyed at the same time. 1003184cd4a3SBenjamin Herrenschmidt * 1004184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1005184cd4a3SBenjamin Herrenschmidt */ 10061e916772SGavin Shan pdn->pe_number = pe->pe_number; 10075d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1008184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1009184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1010184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1011184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1012f724385fSFrederic Barrat pe->device_count++; 1013184cd4a3SBenjamin Herrenschmidt 1014184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1015184cd4a3SBenjamin Herrenschmidt 1016184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1017184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10181e916772SGavin Shan pnv_ioda_free_pe(pe); 1019184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1020184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1021184cd4a3SBenjamin Herrenschmidt return NULL; 1022184cd4a3SBenjamin Herrenschmidt } 1023184cd4a3SBenjamin Herrenschmidt 10241d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 102580f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 10261d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 102780f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 1028184cd4a3SBenjamin Herrenschmidt return pe; 1029184cd4a3SBenjamin Herrenschmidt } 1030184cd4a3SBenjamin Herrenschmidt 1031fb446ad0SGavin Shan /* 1032fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1033fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1034fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1035fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1036fb446ad0SGavin Shan */ 10371e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1038184cd4a3SBenjamin Herrenschmidt { 10395609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 10401e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1041ccd1c191SGavin Shan unsigned int pe_num; 1042ccd1c191SGavin Shan 1043ccd1c191SGavin Shan /* 1044ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1045ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1046ccd1c191SGavin Shan */ 1047ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 10486ae8aedfSOliver O'Halloran if (WARN_ON(pe_num != IODA_INVALID_PE)) { 1049ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1050ccd1c191SGavin Shan return NULL; 1051ccd1c191SGavin Shan } 1052184cd4a3SBenjamin Herrenschmidt 105363803c39SGavin Shan /* PE number for root bus should have been reserved */ 1054718d249aSOliver O'Halloran if (pci_is_root_bus(bus)) 105563803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 105663803c39SGavin Shan 1057262af557SGuo Chao /* Check if PE is determined by M64 */ 1058a25de7afSAlexey Kardashevskiy if (!pe) 1059a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1060262af557SGuo Chao 1061262af557SGuo Chao /* The PE number isn't pinned by M64 */ 10621e916772SGavin Shan if (!pe) 1063a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 1064262af557SGuo Chao 10651e916772SGavin Shan if (!pe) { 1066f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1067fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 10681e916772SGavin Shan return NULL; 1069184cd4a3SBenjamin Herrenschmidt } 1070184cd4a3SBenjamin Herrenschmidt 1071262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1072184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1073184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1074184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1075b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1076184cd4a3SBenjamin Herrenschmidt 1077fb446ad0SGavin Shan if (all) 10781e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 10791e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 10801e496391SJoe Perches pe->pe_number); 1081fb446ad0SGavin Shan else 10821e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 10831e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1084184cd4a3SBenjamin Herrenschmidt 1085184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1086184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10871e916772SGavin Shan pnv_ioda_free_pe(pe); 1088184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 10891e916772SGavin Shan return NULL; 1090184cd4a3SBenjamin Herrenschmidt } 1091184cd4a3SBenjamin Herrenschmidt 10927ebdf956SGavin Shan /* Put PE to the list */ 10937ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10941e916772SGavin Shan 10951e916772SGavin Shan return pe; 1096184cd4a3SBenjamin Herrenschmidt } 1097184cd4a3SBenjamin Herrenschmidt 109801e12629SOliver O'Halloran static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 109901e12629SOliver O'Halloran struct pnv_ioda_pe *pe); 110001e12629SOliver O'Halloran 11010a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1102184cd4a3SBenjamin Herrenschmidt { 11035609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1104b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1105959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1106184cd4a3SBenjamin Herrenschmidt 1107dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */ 1108dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1109dc3d8f85SOliver O'Halloran if (!pe) { 1110dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1111dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn)) 1112959c9bddSGavin Shan return; 1113184cd4a3SBenjamin Herrenschmidt 1114dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus); 1115dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1116dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1117dc3d8f85SOliver O'Halloran 1118dc3d8f85SOliver O'Halloran 1119dc3d8f85SOliver O'Halloran /* 1120dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly 1121dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device. 1122dc3d8f85SOliver O'Halloran */ 1123dc3d8f85SOliver O'Halloran if (WARN_ON(!pe)) 1124dc3d8f85SOliver O'Halloran return; 1125dc3d8f85SOliver O'Halloran } else { 1126dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1127dc3d8f85SOliver O'Halloran } 1128dc3d8f85SOliver O'Halloran 112901e12629SOliver O'Halloran /* 113001e12629SOliver O'Halloran * We assume that bridges *probably* don't need to do any DMA so we can 113101e12629SOliver O'Halloran * skip allocating a TCE table, etc unless we get a non-bridge device. 113201e12629SOliver O'Halloran */ 113301e12629SOliver O'Halloran if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { 113401e12629SOliver O'Halloran switch (phb->type) { 113501e12629SOliver O'Halloran case PNV_PHB_IODA1: 113601e12629SOliver O'Halloran pnv_pci_ioda1_setup_dma_pe(phb, pe); 113701e12629SOliver O'Halloran break; 113801e12629SOliver O'Halloran case PNV_PHB_IODA2: 113901e12629SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe); 114001e12629SOliver O'Halloran break; 114101e12629SOliver O'Halloran default: 114201e12629SOliver O'Halloran pr_warn("%s: No DMA for PHB#%x (type %d)\n", 114301e12629SOliver O'Halloran __func__, phb->hose->global_number, phb->type); 114401e12629SOliver O'Halloran } 114501e12629SOliver O'Halloran } 114601e12629SOliver O'Halloran 1147dc3d8f85SOliver O'Halloran if (pdn) 1148dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number; 1149dc3d8f85SOliver O'Halloran pe->device_count++; 1150dc3d8f85SOliver O'Halloran 1151cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 11520617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1153b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 115484d8cc07SOliver O'Halloran 115584d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */ 115684d8cc07SOliver O'Halloran if (pe->table_group.group) 115784d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev); 1158184cd4a3SBenjamin Herrenschmidt } 1159184cd4a3SBenjamin Herrenschmidt 11608e3f1b1dSRussell Currey /* 11618e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 11628e3f1b1dSRussell Currey * 11638e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 11648e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 11658e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 11668e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 11678e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 11688e3f1b1dSRussell Currey * devices in TVE#0. 11698e3f1b1dSRussell Currey * 11708e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 11718e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 11728e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 11738e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 11748e3f1b1dSRussell Currey * 11758e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 11768e3f1b1dSRussell Currey */ 11778e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 11788e3f1b1dSRussell Currey { 11798e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 11808e3f1b1dSRussell Currey struct page *table_pages; 11818e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 11828e3f1b1dSRussell Currey __be64 *tces; 11838e3f1b1dSRussell Currey s64 rc; 11848e3f1b1dSRussell Currey 11858e3f1b1dSRussell Currey /* 11868e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 11878e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 11888e3f1b1dSRussell Currey */ 11898e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 11908e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 11918e3f1b1dSRussell Currey table_size = tce_count << 3; 11928e3f1b1dSRussell Currey 11938e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 11948e3f1b1dSRussell Currey table_size = PAGE_SIZE; 11958e3f1b1dSRussell Currey 11968e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 11978e3f1b1dSRussell Currey get_order(table_size)); 11988e3f1b1dSRussell Currey if (!table_pages) 11998e3f1b1dSRussell Currey goto err; 12008e3f1b1dSRussell Currey 12018e3f1b1dSRussell Currey tces = page_address(table_pages); 12028e3f1b1dSRussell Currey if (!tces) 12038e3f1b1dSRussell Currey goto err; 12048e3f1b1dSRussell Currey 12058e3f1b1dSRussell Currey memset(tces, 0, table_size); 12068e3f1b1dSRussell Currey 12078e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 12088e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 12098e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 12108e3f1b1dSRussell Currey } 12118e3f1b1dSRussell Currey 12128e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 12138e3f1b1dSRussell Currey pe->pe_number, 12148e3f1b1dSRussell Currey /* reconfigure window 0 */ 12158e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 12168e3f1b1dSRussell Currey 1, 12178e3f1b1dSRussell Currey __pa(tces), 12188e3f1b1dSRussell Currey table_size, 12198e3f1b1dSRussell Currey 1 << tce_order); 12208e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 12218e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 12228e3f1b1dSRussell Currey return 0; 12238e3f1b1dSRussell Currey } 12248e3f1b1dSRussell Currey err: 12258e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 12268e3f1b1dSRussell Currey return -EIO; 12278e3f1b1dSRussell Currey } 12288e3f1b1dSRussell Currey 12292d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 12302d6ad41bSChristoph Hellwig u64 dma_mask) 1231cd15b048SBenjamin Herrenschmidt { 12325609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1233cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1234cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1235cd15b048SBenjamin Herrenschmidt 1236cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1237b511cdd1SAlexey Kardashevskiy return false; 1238cd15b048SBenjamin Herrenschmidt 1239cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1240cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 12412d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 12422d6ad41bSChristoph Hellwig if (dma_mask >= top) 12432d6ad41bSChristoph Hellwig return true; 1244cd15b048SBenjamin Herrenschmidt } 1245cd15b048SBenjamin Herrenschmidt 12468e3f1b1dSRussell Currey /* 12478e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 12488e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 12498e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 12508e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 12518e3f1b1dSRussell Currey */ 12528e3f1b1dSRussell Currey if (dma_mask >> 32 && 12538e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1254661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1255661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 12568e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 12578e3f1b1dSRussell Currey /* Configure the bypass mode */ 12582d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 12598e3f1b1dSRussell Currey if (rc) 1260b511cdd1SAlexey Kardashevskiy return false; 12618e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 12620617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 12632d6ad41bSChristoph Hellwig return true; 1264cd15b048SBenjamin Herrenschmidt } 1265cd15b048SBenjamin Herrenschmidt 12662d6ad41bSChristoph Hellwig return false; 1267fe7e85c6SGavin Shan } 1268fe7e85c6SGavin Shan 1269fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1270fd141d1aSBenjamin Herrenschmidt bool real_mode) 1271fd141d1aSBenjamin Herrenschmidt { 1272fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1273fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1274fd141d1aSBenjamin Herrenschmidt } 1275fd141d1aSBenjamin Herrenschmidt 1276a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1277decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 12784cce9550SGavin Shan { 12790eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 12800eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 12810eaf4defSAlexey Kardashevskiy next); 12820eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1283b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1284fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 12854cce9550SGavin Shan unsigned long start, end, inc; 12864cce9550SGavin Shan 1287decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1288decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1289decbda25SAlexey Kardashevskiy npages - 1); 12904cce9550SGavin Shan 12914cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 12924cce9550SGavin Shan start |= (1ull << 63); 12934cce9550SGavin Shan end |= (1ull << 63); 12944cce9550SGavin Shan inc = 16; 12954cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 12964cce9550SGavin Shan 12974cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 12984cce9550SGavin Shan while (start <= end) { 12998e0a1611SAlexey Kardashevskiy if (rm) 1300001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 13018e0a1611SAlexey Kardashevskiy else 1302001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1303001ff2eeSMichael Ellerman 13044cce9550SGavin Shan start += inc; 13054cce9550SGavin Shan } 13064cce9550SGavin Shan 13074cce9550SGavin Shan /* 13084cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 13094cce9550SGavin Shan * and we don't care on free() 13104cce9550SGavin Shan */ 13114cce9550SGavin Shan } 13124cce9550SGavin Shan 1313decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1314decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1315decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 131600085f1eSKrzysztof Kozlowski unsigned long attrs) 1317decbda25SAlexey Kardashevskiy { 1318decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1319decbda25SAlexey Kardashevskiy attrs); 1320decbda25SAlexey Kardashevskiy 132108acce1cSBenjamin Herrenschmidt if (!ret) 1322a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1323decbda25SAlexey Kardashevskiy 1324decbda25SAlexey Kardashevskiy return ret; 1325decbda25SAlexey Kardashevskiy } 1326decbda25SAlexey Kardashevskiy 132705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 132835872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 132935872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 133035872480SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 133135872480SAlexey Kardashevskiy bool realmode) 133205c6cfb9SAlexey Kardashevskiy { 133335872480SAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1334a540aa56SAlexey Kardashevskiy } 133505c6cfb9SAlexey Kardashevskiy #endif 133605c6cfb9SAlexey Kardashevskiy 1337decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1338decbda25SAlexey Kardashevskiy long npages) 1339decbda25SAlexey Kardashevskiy { 1340decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1341decbda25SAlexey Kardashevskiy 1342a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1343decbda25SAlexey Kardashevskiy } 1344decbda25SAlexey Kardashevskiy 1345da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1346decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 134705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 134835872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 134935872480SAlexey Kardashevskiy .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1350090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 135105c6cfb9SAlexey Kardashevskiy #endif 1352decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1353da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1354da004c36SAlexey Kardashevskiy }; 1355da004c36SAlexey Kardashevskiy 1356a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1357a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1358a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1359bef9253fSAlexey Kardashevskiy 1360a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 13615780fb04SAlexey Kardashevskiy { 13625780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1363fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1364a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 13655780fb04SAlexey Kardashevskiy 13665780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1367001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 13685780fb04SAlexey Kardashevskiy } 13695780fb04SAlexey Kardashevskiy 1370fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1371fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1372fd141d1aSBenjamin Herrenschmidt unsigned long npages) 13734cce9550SGavin Shan { 13744d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 13754cce9550SGavin Shan unsigned long start, end, inc; 13764cce9550SGavin Shan 13774cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1378a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1379fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 13804cce9550SGavin Shan end = start; 13814cce9550SGavin Shan 13824cce9550SGavin Shan /* Figure out the start, end and step */ 1383decbda25SAlexey Kardashevskiy start |= (index << shift); 1384decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1385b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 13864cce9550SGavin Shan mb(); 13874cce9550SGavin Shan 13884cce9550SGavin Shan while (start <= end) { 13898e0a1611SAlexey Kardashevskiy if (rm) 1390001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 13918e0a1611SAlexey Kardashevskiy else 1392001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 13934cce9550SGavin Shan start += inc; 13944cce9550SGavin Shan } 13954cce9550SGavin Shan } 13964cce9550SGavin Shan 1397f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1398f0228c41SBenjamin Herrenschmidt { 1399f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1400f0228c41SBenjamin Herrenschmidt 1401f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1402f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1403f0228c41SBenjamin Herrenschmidt else 1404f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1405f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1406f0228c41SBenjamin Herrenschmidt } 1407f0228c41SBenjamin Herrenschmidt 1408e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1409e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1410e57080f1SAlexey Kardashevskiy { 1411e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1412e57080f1SAlexey Kardashevskiy 1413a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1414e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1415e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1416f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1417f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1418f0228c41SBenjamin Herrenschmidt 1419f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1420f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 142185674868SAlexey Kardashevskiy index, npages); 1422f0228c41SBenjamin Herrenschmidt else 1423f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 1424f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1425f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1426f0228c41SBenjamin Herrenschmidt index << shift, npages); 1427e57080f1SAlexey Kardashevskiy } 1428e57080f1SAlexey Kardashevskiy } 1429e57080f1SAlexey Kardashevskiy 1430decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1431decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1432decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 143300085f1eSKrzysztof Kozlowski unsigned long attrs) 14344cce9550SGavin Shan { 1435decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1436decbda25SAlexey Kardashevskiy attrs); 14374cce9550SGavin Shan 143808acce1cSBenjamin Herrenschmidt if (!ret) 1439decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1440decbda25SAlexey Kardashevskiy 1441decbda25SAlexey Kardashevskiy return ret; 1442decbda25SAlexey Kardashevskiy } 1443decbda25SAlexey Kardashevskiy 1444decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1445decbda25SAlexey Kardashevskiy long npages) 1446decbda25SAlexey Kardashevskiy { 1447decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1448decbda25SAlexey Kardashevskiy 1449decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 14504cce9550SGavin Shan } 14514cce9550SGavin Shan 1452da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1453decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 145405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 145535872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 145635872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 1457090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 145805c6cfb9SAlexey Kardashevskiy #endif 1459decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1460da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1461da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 1462da004c36SAlexey Kardashevskiy }; 1463da004c36SAlexey Kardashevskiy 1464801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1465801846d1SGavin Shan { 1466801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1467801846d1SGavin Shan 1468801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1469801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1470801846d1SGavin Shan */ 1471801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1472801846d1SGavin Shan return 0; 1473801846d1SGavin Shan 1474801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1475801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1476801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1477801846d1SGavin Shan *weight += 3; 1478801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1479801846d1SGavin Shan *weight += 15; 1480801846d1SGavin Shan else 1481801846d1SGavin Shan *weight += 10; 1482801846d1SGavin Shan 1483801846d1SGavin Shan return 0; 1484801846d1SGavin Shan } 1485801846d1SGavin Shan 1486801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1487801846d1SGavin Shan { 1488801846d1SGavin Shan unsigned int weight = 0; 1489801846d1SGavin Shan 1490801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 1491801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 1492801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1493801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1494801846d1SGavin Shan return weight; 1495801846d1SGavin Shan } 1496801846d1SGavin Shan #endif 1497801846d1SGavin Shan 1498801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1499801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1500801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1501801846d1SGavin Shan struct pci_dev *pdev; 1502801846d1SGavin Shan 1503801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1504801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1505801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1506801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1507801846d1SGavin Shan } 1508801846d1SGavin Shan 1509801846d1SGavin Shan return weight; 1510801846d1SGavin Shan } 1511801846d1SGavin Shan 1512b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 15132b923ed1SGavin Shan struct pnv_ioda_pe *pe) 1514184cd4a3SBenjamin Herrenschmidt { 1515184cd4a3SBenjamin Herrenschmidt 1516184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1517184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 15182b923ed1SGavin Shan unsigned int weight, total_weight = 0; 15192b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 1520184cd4a3SBenjamin Herrenschmidt int64_t rc; 1521184cd4a3SBenjamin Herrenschmidt void *addr; 1522184cd4a3SBenjamin Herrenschmidt 1523184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1524184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1525184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 15262b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 15272b923ed1SGavin Shan if (!weight) 15282b923ed1SGavin Shan return; 1529184cd4a3SBenjamin Herrenschmidt 15302b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 15312b923ed1SGavin Shan &total_weight); 15322b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 15332b923ed1SGavin Shan if (!segs) 15342b923ed1SGavin Shan segs = 1; 15352b923ed1SGavin Shan 15362b923ed1SGavin Shan /* 15372b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 15382b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 15392b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 15402b923ed1SGavin Shan * is allocated successfully. 15412b923ed1SGavin Shan */ 15422b923ed1SGavin Shan do { 15432b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 15442b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 15452b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 15462b923ed1SGavin Shan IODA_INVALID_PE) 15472b923ed1SGavin Shan avail++; 15482b923ed1SGavin Shan } 15492b923ed1SGavin Shan 15502b923ed1SGavin Shan if (avail == segs) 15512b923ed1SGavin Shan goto found; 15522b923ed1SGavin Shan } 15532b923ed1SGavin Shan } while (--segs); 15542b923ed1SGavin Shan 15552b923ed1SGavin Shan if (!segs) { 15562b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 15572b923ed1SGavin Shan return; 15582b923ed1SGavin Shan } 15592b923ed1SGavin Shan 15602b923ed1SGavin Shan found: 15610eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 156282eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 156382eae1afSAlexey Kardashevskiy return; 156482eae1afSAlexey Kardashevskiy 1565b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1566b348aa65SAlexey Kardashevskiy pe->pe_number); 15670eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1568c5773822SAlexey Kardashevskiy 1569184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 15702b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 15712b923ed1SGavin Shan weight, total_weight, base, segs); 1572184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1573acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1574acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 1575184cd4a3SBenjamin Herrenschmidt 1576184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1577184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1578184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1579184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1580acce971cSGavin Shan * 1581acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 1582acce971cSGavin Shan * bytes 1583184cd4a3SBenjamin Herrenschmidt */ 1584acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 1585184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1586acce971cSGavin Shan get_order(tce32_segsz * segs)); 1587184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1588184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1589184cd4a3SBenjamin Herrenschmidt goto fail; 1590184cd4a3SBenjamin Herrenschmidt } 1591184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1592acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 1593184cd4a3SBenjamin Herrenschmidt 1594184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1595184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1596184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1597184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1598184cd4a3SBenjamin Herrenschmidt base + i, 1, 1599acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 1600acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 1601184cd4a3SBenjamin Herrenschmidt if (rc) { 16021e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 16031e496391SJoe Perches rc); 1604184cd4a3SBenjamin Herrenschmidt goto fail; 1605184cd4a3SBenjamin Herrenschmidt } 1606184cd4a3SBenjamin Herrenschmidt } 1607184cd4a3SBenjamin Herrenschmidt 16082b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 16092b923ed1SGavin Shan for (i = base; i < base + segs; i++) 16102b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 16112b923ed1SGavin Shan 1612184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1613acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 1614acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1615acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 1616184cd4a3SBenjamin Herrenschmidt 1617da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 16184793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 16194793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 16204be518d8SAlexey Kardashevskiy if (!iommu_init_table(tbl, phb->hose->node, 0, 0)) 16214be518d8SAlexey Kardashevskiy panic("Failed to initialize iommu table"); 1622184cd4a3SBenjamin Herrenschmidt 162301e12629SOliver O'Halloran pe->dma_setup_done = true; 1624184cd4a3SBenjamin Herrenschmidt return; 1625184cd4a3SBenjamin Herrenschmidt fail: 1626184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1627184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1628acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 16290eaf4defSAlexey Kardashevskiy if (tbl) { 16300eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 1631e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 16320eaf4defSAlexey Kardashevskiy } 1633184cd4a3SBenjamin Herrenschmidt } 1634184cd4a3SBenjamin Herrenschmidt 163543cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 163643cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 163743cb60abSAlexey Kardashevskiy { 163843cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 163943cb60abSAlexey Kardashevskiy table_group); 164043cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 164143cb60abSAlexey Kardashevskiy int64_t rc; 1642bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1643bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 164443cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 164543cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 164643cb60abSAlexey Kardashevskiy 16471e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 16481e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 164943cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 165043cb60abSAlexey Kardashevskiy 165143cb60abSAlexey Kardashevskiy /* 165243cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 165343cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 165443cb60abSAlexey Kardashevskiy */ 165543cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 165643cb60abSAlexey Kardashevskiy pe->pe_number, 16574793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 1658bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 165943cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 1660bbb845c4SAlexey Kardashevskiy size << 3, 166143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 166243cb60abSAlexey Kardashevskiy if (rc) { 16631e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 166443cb60abSAlexey Kardashevskiy return rc; 166543cb60abSAlexey Kardashevskiy } 166643cb60abSAlexey Kardashevskiy 166743cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 166843cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 1669ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 167043cb60abSAlexey Kardashevskiy 167143cb60abSAlexey Kardashevskiy return 0; 167243cb60abSAlexey Kardashevskiy } 167343cb60abSAlexey Kardashevskiy 1674c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1675cd15b048SBenjamin Herrenschmidt { 1676cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1677cd15b048SBenjamin Herrenschmidt int64_t rc; 1678cd15b048SBenjamin Herrenschmidt 1679cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1680cd15b048SBenjamin Herrenschmidt if (enable) { 1681cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1682cd15b048SBenjamin Herrenschmidt 1683cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1684cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1685cd15b048SBenjamin Herrenschmidt pe->pe_number, 1686cd15b048SBenjamin Herrenschmidt window_id, 1687cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1688cd15b048SBenjamin Herrenschmidt top); 1689cd15b048SBenjamin Herrenschmidt } else { 1690cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1691cd15b048SBenjamin Herrenschmidt pe->pe_number, 1692cd15b048SBenjamin Herrenschmidt window_id, 1693cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1694cd15b048SBenjamin Herrenschmidt 0); 1695cd15b048SBenjamin Herrenschmidt } 1696cd15b048SBenjamin Herrenschmidt if (rc) 1697cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1698cd15b048SBenjamin Herrenschmidt else 1699cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1700cd15b048SBenjamin Herrenschmidt } 1701cd15b048SBenjamin Herrenschmidt 17024793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 17034793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1704090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 17054793d65dSAlexey Kardashevskiy { 17064793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 17074793d65dSAlexey Kardashevskiy table_group); 17084793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 17094793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 17104793d65dSAlexey Kardashevskiy long ret; 17114793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 17124793d65dSAlexey Kardashevskiy 17134793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 17144793d65dSAlexey Kardashevskiy if (!tbl) 17154793d65dSAlexey Kardashevskiy return -ENOMEM; 17164793d65dSAlexey Kardashevskiy 171711edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 171811edf116SAlexey Kardashevskiy 17194793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 17204793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 1721090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 17224793d65dSAlexey Kardashevskiy if (ret) { 1723e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 17244793d65dSAlexey Kardashevskiy return ret; 17254793d65dSAlexey Kardashevskiy } 17264793d65dSAlexey Kardashevskiy 17274793d65dSAlexey Kardashevskiy *ptbl = tbl; 17284793d65dSAlexey Kardashevskiy 17294793d65dSAlexey Kardashevskiy return 0; 17304793d65dSAlexey Kardashevskiy } 17314793d65dSAlexey Kardashevskiy 173246d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 173346d3e1e1SAlexey Kardashevskiy { 173446d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 173546d3e1e1SAlexey Kardashevskiy long rc; 1736201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 173746d3e1e1SAlexey Kardashevskiy 1738bb005455SNishanth Aravamudan /* 1739fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 1740fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 1741fa144869SNishanth Aravamudan * of 2, which will cause errors later. 1742fa144869SNishanth Aravamudan */ 1743fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 1744fa144869SNishanth Aravamudan 1745fa144869SNishanth Aravamudan /* 1746bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 1747bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 1748bb005455SNishanth Aravamudan * cause errors later. 1749bb005455SNishanth Aravamudan */ 1750201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 1751bb005455SNishanth Aravamudan 1752201ed7f3SAlexey Kardashevskiy /* 1753201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 1754201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 1755201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 1756201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 1757201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 1758201ed7f3SAlexey Kardashevskiy */ 1759201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 1760201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 1761201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 1762201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 1763201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 1764201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 1765201ed7f3SAlexey Kardashevskiy 1766201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 1767201ed7f3SAlexey Kardashevskiy levels += 1; 1768201ed7f3SAlexey Kardashevskiy /* 1769201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 1770201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 1771201ed7f3SAlexey Kardashevskiy */ 1772201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 1773201ed7f3SAlexey Kardashevskiy 1774201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 1775201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 177646d3e1e1SAlexey Kardashevskiy if (rc) { 177746d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 177846d3e1e1SAlexey Kardashevskiy rc); 177946d3e1e1SAlexey Kardashevskiy return rc; 178046d3e1e1SAlexey Kardashevskiy } 178146d3e1e1SAlexey Kardashevskiy 1782201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 1783201ed7f3SAlexey Kardashevskiy res_start = 0; 1784201ed7f3SAlexey Kardashevskiy res_end = 0; 1785201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 1786201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 1787201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 1788201ed7f3SAlexey Kardashevskiy } 178946d3e1e1SAlexey Kardashevskiy 17904be518d8SAlexey Kardashevskiy if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) 179146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 17924be518d8SAlexey Kardashevskiy else 17934be518d8SAlexey Kardashevskiy rc = -ENOMEM; 179446d3e1e1SAlexey Kardashevskiy if (rc) { 17954be518d8SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); 1796e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 17974be518d8SAlexey Kardashevskiy tbl = NULL; /* This clears iommu_table_base below */ 179846d3e1e1SAlexey Kardashevskiy } 179946d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 180046d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 180146d3e1e1SAlexey Kardashevskiy 18025636427dSAlexey Kardashevskiy /* 18035636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 18045636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 18055636427dSAlexey Kardashevskiy * from VFIO so do it here. 18065636427dSAlexey Kardashevskiy */ 18075636427dSAlexey Kardashevskiy if (pe->pdev) 18085636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 18095636427dSAlexey Kardashevskiy 181046d3e1e1SAlexey Kardashevskiy return 0; 181146d3e1e1SAlexey Kardashevskiy } 181246d3e1e1SAlexey Kardashevskiy 1813b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1814b5926430SAlexey Kardashevskiy int num) 1815b5926430SAlexey Kardashevskiy { 1816b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1817b5926430SAlexey Kardashevskiy table_group); 1818b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 1819b5926430SAlexey Kardashevskiy long ret; 1820b5926430SAlexey Kardashevskiy 1821b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 1822b5926430SAlexey Kardashevskiy 1823b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1824b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 1825b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 1826b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 1827b5926430SAlexey Kardashevskiy if (ret) 1828b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 1829b5926430SAlexey Kardashevskiy else 1830ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 1831b5926430SAlexey Kardashevskiy 1832b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 1833b5926430SAlexey Kardashevskiy 1834b5926430SAlexey Kardashevskiy return ret; 1835b5926430SAlexey Kardashevskiy } 1836b5926430SAlexey Kardashevskiy 1837f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 18380bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 183900547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 184000547193SAlexey Kardashevskiy { 184100547193SAlexey Kardashevskiy unsigned long bytes = 0; 184200547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 184300547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 184400547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 184500547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 184600547193SAlexey Kardashevskiy unsigned long direct_table_size; 184700547193SAlexey Kardashevskiy 184800547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 184900547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 185000547193SAlexey Kardashevskiy return 0; 185100547193SAlexey Kardashevskiy 185200547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 185300547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 185400547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 185500547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 185600547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 185700547193SAlexey Kardashevskiy 185800547193SAlexey Kardashevskiy for ( ; levels; --levels) { 1859b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 186000547193SAlexey Kardashevskiy 186100547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 186200547193SAlexey Kardashevskiy tce_table_size <<= 3; 1863e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 1864e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 186500547193SAlexey Kardashevskiy } 186600547193SAlexey Kardashevskiy 1867090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 1868090bad39SAlexey Kardashevskiy } 1869090bad39SAlexey Kardashevskiy 1870090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 1871090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 1872090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1873090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 1874090bad39SAlexey Kardashevskiy { 187511f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 1876090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 187711f5acceSAlexey Kardashevskiy 187811f5acceSAlexey Kardashevskiy if (!ret) 187911f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 188011f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 188111f5acceSAlexey Kardashevskiy return ret; 188200547193SAlexey Kardashevskiy } 188300547193SAlexey Kardashevskiy 1884e3417faeSOliver O'Halloran static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 1885e3417faeSOliver O'Halloran { 1886e3417faeSOliver O'Halloran struct pci_dev *dev; 1887e3417faeSOliver O'Halloran 1888e3417faeSOliver O'Halloran list_for_each_entry(dev, &bus->devices, bus_list) { 1889e3417faeSOliver O'Halloran set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1890e3417faeSOliver O'Halloran dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1891e3417faeSOliver O'Halloran 1892e3417faeSOliver O'Halloran if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1893e3417faeSOliver O'Halloran pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1894e3417faeSOliver O'Halloran } 1895e3417faeSOliver O'Halloran } 1896e3417faeSOliver O'Halloran 1897f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 1898cd15b048SBenjamin Herrenschmidt { 1899f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1900f87a8864SAlexey Kardashevskiy table_group); 190146d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 190246d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 1903cd15b048SBenjamin Herrenschmidt 1904f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 190546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1906db08e1d5SAlexey Kardashevskiy if (pe->pbus) 19075eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 19085636427dSAlexey Kardashevskiy else if (pe->pdev) 19095636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 1910e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1911cd15b048SBenjamin Herrenschmidt } 1912cd15b048SBenjamin Herrenschmidt 1913f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 1914f87a8864SAlexey Kardashevskiy { 1915f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1916f87a8864SAlexey Kardashevskiy table_group); 1917f87a8864SAlexey Kardashevskiy 191846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 1919db08e1d5SAlexey Kardashevskiy if (pe->pbus) 19205eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 1921f87a8864SAlexey Kardashevskiy } 1922f87a8864SAlexey Kardashevskiy 1923f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 192400547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 1925090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 19264793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 19274793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 1928f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 1929f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 1930f87a8864SAlexey Kardashevskiy }; 1931f87a8864SAlexey Kardashevskiy #endif 1932f87a8864SAlexey Kardashevskiy 193337b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1934373f5657SGavin Shan struct pnv_ioda_pe *pe) 1935373f5657SGavin Shan { 1936373f5657SGavin Shan int64_t rc; 1937373f5657SGavin Shan 1938f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 1939f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 1940f87a8864SAlexey Kardashevskiy 1941373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1942373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1943aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 1944373f5657SGavin Shan 1945e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 19464793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 19474793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 19484793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 19494793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 19504793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 19517ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 1952e5aad1e6SAlexey Kardashevskiy 195346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 1954801846d1SGavin Shan if (rc) 195546d3e1e1SAlexey Kardashevskiy return; 195646d3e1e1SAlexey Kardashevskiy 19579b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 19589b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 19599b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 19609b9408c5SOliver O'Halloran pe->pe_number); 19619b9408c5SOliver O'Halloran #endif 196201e12629SOliver O'Halloran pe->dma_setup_done = true; 1963373f5657SGavin Shan } 1964373f5657SGavin Shan 19654ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 1966137436c9SGavin Shan { 1967137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 1968137436c9SGavin Shan ioda.irq_chip); 1969137436c9SGavin Shan 19704ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 19714ee11c1aSSuresh Warrier } 19724ee11c1aSSuresh Warrier 19734ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 19744ee11c1aSSuresh Warrier { 19754ee11c1aSSuresh Warrier int64_t rc; 19764ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 19774ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 19784ee11c1aSSuresh Warrier 19794ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 1980137436c9SGavin Shan WARN_ON_ONCE(rc); 1981137436c9SGavin Shan 1982137436c9SGavin Shan icp_native_eoi(d); 1983137436c9SGavin Shan } 1984137436c9SGavin Shan 1985fd9a1c26SIan Munsie 1986f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 1987fd9a1c26SIan Munsie { 1988fd9a1c26SIan Munsie struct irq_data *idata; 1989fd9a1c26SIan Munsie struct irq_chip *ichip; 1990fd9a1c26SIan Munsie 1991fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 1992fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 1993fd9a1c26SIan Munsie return; 1994fd9a1c26SIan Munsie 1995fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 1996fd9a1c26SIan Munsie /* 1997fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 1998fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 1999fd9a1c26SIan Munsie */ 2000fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2001fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2002fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2003fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2004fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2005fd9a1c26SIan Munsie } 2006fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2007fd9a1c26SIan Munsie } 2008fd9a1c26SIan Munsie 20094ee11c1aSSuresh Warrier /* 20104ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 20114ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 20124ee11c1aSSuresh Warrier */ 20134ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 20144ee11c1aSSuresh Warrier { 20154ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 20164ee11c1aSSuresh Warrier } 20174ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 20184ee11c1aSSuresh Warrier 2019*2c50d7e9SCédric Le Goater static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2020*2c50d7e9SCédric Le Goater unsigned int xive_num, 2021137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2022184cd4a3SBenjamin Herrenschmidt { 2023184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 20243a1a4661SBenjamin Herrenschmidt __be32 data; 2025184cd4a3SBenjamin Herrenschmidt int rc; 2026184cd4a3SBenjamin Herrenschmidt 2027*2c50d7e9SCédric Le Goater dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__, 2028*2c50d7e9SCédric Le Goater is_64 ? "64" : "32", xive_num); 2029*2c50d7e9SCédric Le Goater 2030184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2031184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2032184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2033184cd4a3SBenjamin Herrenschmidt 2034184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2035184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2036184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2037184cd4a3SBenjamin Herrenschmidt 2038b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 203936074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2040b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2041b72c1f65SBenjamin Herrenschmidt 2042184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2043184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2044184cd4a3SBenjamin Herrenschmidt if (rc) { 2045184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2046184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2047184cd4a3SBenjamin Herrenschmidt return -EIO; 2048184cd4a3SBenjamin Herrenschmidt } 2049184cd4a3SBenjamin Herrenschmidt 2050184cd4a3SBenjamin Herrenschmidt if (is_64) { 20513a1a4661SBenjamin Herrenschmidt __be64 addr64; 20523a1a4661SBenjamin Herrenschmidt 2053184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2054184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2055184cd4a3SBenjamin Herrenschmidt if (rc) { 2056184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2057184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2058184cd4a3SBenjamin Herrenschmidt return -EIO; 2059184cd4a3SBenjamin Herrenschmidt } 20603a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 20613a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2062184cd4a3SBenjamin Herrenschmidt } else { 20633a1a4661SBenjamin Herrenschmidt __be32 addr32; 20643a1a4661SBenjamin Herrenschmidt 2065184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2066184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2067184cd4a3SBenjamin Herrenschmidt if (rc) { 2068184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2069184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2070184cd4a3SBenjamin Herrenschmidt return -EIO; 2071184cd4a3SBenjamin Herrenschmidt } 2072184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 20733a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2074184cd4a3SBenjamin Herrenschmidt } 20753a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2076184cd4a3SBenjamin Herrenschmidt 2077*2c50d7e9SCédric Le Goater return 0; 2078*2c50d7e9SCédric Le Goater } 2079*2c50d7e9SCédric Le Goater 2080*2c50d7e9SCédric Le Goater static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2081*2c50d7e9SCédric Le Goater unsigned int hwirq, unsigned int virq, 2082*2c50d7e9SCédric Le Goater unsigned int is_64, struct msi_msg *msg) 2083*2c50d7e9SCédric Le Goater { 2084*2c50d7e9SCédric Le Goater struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2085*2c50d7e9SCédric Le Goater unsigned int xive_num = hwirq - phb->msi_base; 2086*2c50d7e9SCédric Le Goater int rc; 2087*2c50d7e9SCédric Le Goater 2088*2c50d7e9SCédric Le Goater rc = __pnv_pci_ioda_msi_setup(phb, dev, xive_num, is_64, msg); 2089*2c50d7e9SCédric Le Goater if (rc) 2090*2c50d7e9SCédric Le Goater return rc; 2091*2c50d7e9SCédric Le Goater 2092*2c50d7e9SCédric Le Goater /* P8 only */ 2093f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2094137436c9SGavin Shan 2095184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 20961f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2097184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2098*2c50d7e9SCédric Le Goater msg->address_hi, msg->address_lo, msg->data, pe->pe_number); 2099184cd4a3SBenjamin Herrenschmidt 2100184cd4a3SBenjamin Herrenschmidt return 0; 2101184cd4a3SBenjamin Herrenschmidt } 2102184cd4a3SBenjamin Herrenschmidt 2103184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2104184cd4a3SBenjamin Herrenschmidt { 2105fb1b55d6SGavin Shan unsigned int count; 2106184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2107184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2108184cd4a3SBenjamin Herrenschmidt if (!prop) { 2109184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2110184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2111184cd4a3SBenjamin Herrenschmidt } 2112184cd4a3SBenjamin Herrenschmidt if (!prop) 2113184cd4a3SBenjamin Herrenschmidt return; 2114184cd4a3SBenjamin Herrenschmidt 2115184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2116fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2117fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2118184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2119184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2120184cd4a3SBenjamin Herrenschmidt return; 2121184cd4a3SBenjamin Herrenschmidt } 2122fb1b55d6SGavin Shan 2123184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2124184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2125184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2126fb1b55d6SGavin Shan count, phb->msi_base); 2127184cd4a3SBenjamin Herrenschmidt } 2128184cd4a3SBenjamin Herrenschmidt 212923e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 213023e79425SGavin Shan struct resource *res) 213111685becSGavin Shan { 213223e79425SGavin Shan struct pnv_phb *phb = pe->phb; 213311685becSGavin Shan struct pci_bus_region region; 213423e79425SGavin Shan int index; 213523e79425SGavin Shan int64_t rc; 213611685becSGavin Shan 213723e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 213823e79425SGavin Shan return; 213911685becSGavin Shan 214011685becSGavin Shan if (res->flags & IORESOURCE_IO) { 214111685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 214211685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 214311685becSGavin Shan index = region.start / phb->ioda.io_segsize; 214411685becSGavin Shan 214592b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 214611685becSGavin Shan region.start <= region.end) { 214711685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 214811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 214911685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 215011685becSGavin Shan if (rc != OPAL_SUCCESS) { 21511f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 215211685becSGavin Shan __func__, rc, index, pe->pe_number); 215311685becSGavin Shan break; 215411685becSGavin Shan } 215511685becSGavin Shan 215611685becSGavin Shan region.start += phb->ioda.io_segsize; 215711685becSGavin Shan index++; 215811685becSGavin Shan } 2159027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 21605958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 216111685becSGavin Shan region.start = res->start - 216223e79425SGavin Shan phb->hose->mem_offset[0] - 216311685becSGavin Shan phb->ioda.m32_pci_base; 216411685becSGavin Shan region.end = res->end - 216523e79425SGavin Shan phb->hose->mem_offset[0] - 216611685becSGavin Shan phb->ioda.m32_pci_base; 216711685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 216811685becSGavin Shan 216992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 217011685becSGavin Shan region.start <= region.end) { 217111685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 217211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 217311685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 217411685becSGavin Shan if (rc != OPAL_SUCCESS) { 21751f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 217611685becSGavin Shan __func__, rc, index, pe->pe_number); 217711685becSGavin Shan break; 217811685becSGavin Shan } 217911685becSGavin Shan 218011685becSGavin Shan region.start += phb->ioda.m32_segsize; 218111685becSGavin Shan index++; 218211685becSGavin Shan } 218311685becSGavin Shan } 218411685becSGavin Shan } 218523e79425SGavin Shan 218623e79425SGavin Shan /* 218723e79425SGavin Shan * This function is supposed to be called on basis of PE from top 218823e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 218903671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 219023e79425SGavin Shan */ 219123e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 219223e79425SGavin Shan { 219369d733e7SGavin Shan struct pci_dev *pdev; 219423e79425SGavin Shan int i; 219523e79425SGavin Shan 219623e79425SGavin Shan /* 219723e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 219823e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 219923e79425SGavin Shan * be figured out later. 220023e79425SGavin Shan */ 220123e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 220223e79425SGavin Shan 220369d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 220469d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 220569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 220669d733e7SGavin Shan 220769d733e7SGavin Shan /* 220869d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 220969d733e7SGavin Shan * windows of the child bridges should be mapped to 221069d733e7SGavin Shan * the PE as well. 221169d733e7SGavin Shan */ 221269d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 221369d733e7SGavin Shan continue; 221469d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 221569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 221669d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 221769d733e7SGavin Shan } 221811685becSGavin Shan } 221911685becSGavin Shan 222098b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 222198b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 222298b665daSRussell Currey { 222322ba7289SOliver O'Halloran struct pnv_phb *phb = data; 222498b665daSRussell Currey s64 ret; 222598b665daSRussell Currey 222698b665daSRussell Currey /* Retrieve the diag data from firmware */ 22275cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 22285cb1f8fdSRussell Currey phb->diag_data_size); 222998b665daSRussell Currey if (ret != OPAL_SUCCESS) 223098b665daSRussell Currey return -EIO; 223198b665daSRussell Currey 223298b665daSRussell Currey /* Print the diag data to the kernel log */ 22335cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 223498b665daSRussell Currey return 0; 223598b665daSRussell Currey } 223698b665daSRussell Currey 2237bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2238bfa2325eSYueHaibing "%llu\n"); 223998b665daSRussell Currey 224018697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 224118697d2bSOliver O'Halloran { 224218697d2bSOliver O'Halloran struct pnv_phb *phb = data; 224318697d2bSOliver O'Halloran int pe_num; 224418697d2bSOliver O'Halloran 224518697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 224618697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 224718697d2bSOliver O'Halloran 224818697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 224918697d2bSOliver O'Halloran continue; 225018697d2bSOliver O'Halloran 225118697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 225218697d2bSOliver O'Halloran pe->rid, pe->device_count, 225318697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 225418697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 225518697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 225618697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 225718697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 225818697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 225918697d2bSOliver O'Halloran } 226018697d2bSOliver O'Halloran 226118697d2bSOliver O'Halloran return 0; 226218697d2bSOliver O'Halloran } 226318697d2bSOliver O'Halloran 226418697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 226518697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 226618697d2bSOliver O'Halloran 226798b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 226898b665daSRussell Currey 226937c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 227037c367f2SGavin Shan { 227137c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 227237c367f2SGavin Shan struct pci_controller *hose, *tmp; 227337c367f2SGavin Shan struct pnv_phb *phb; 227437c367f2SGavin Shan char name[16]; 227537c367f2SGavin Shan 227637c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 227737c367f2SGavin Shan phb = hose->private_data; 227837c367f2SGavin Shan 227937c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 228037c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 228198b665daSRussell Currey 2282bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 228322ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 228418697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 228518697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 228637c367f2SGavin Shan } 228737c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 228837c367f2SGavin Shan } 228937c367f2SGavin Shan 2290db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 2291db217319SBenjamin Herrenschmidt { 2292db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 2293db217319SBenjamin Herrenschmidt struct pci_bus *child; 2294db217319SBenjamin Herrenschmidt 2295db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 2296db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 2297db217319SBenjamin Herrenschmidt return; 2298db217319SBenjamin Herrenschmidt 2299db217319SBenjamin Herrenschmidt /* 2300db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 2301db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 2302db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 2303db217319SBenjamin Herrenschmidt * fixed. 2304db217319SBenjamin Herrenschmidt */ 2305db217319SBenjamin Herrenschmidt if (dev) { 2306db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 2307db217319SBenjamin Herrenschmidt if (rc) 2308db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 2309db217319SBenjamin Herrenschmidt pci_set_master(dev); 2310db217319SBenjamin Herrenschmidt } 2311db217319SBenjamin Herrenschmidt 2312db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 2313db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 2314db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 2315db217319SBenjamin Herrenschmidt } 2316db217319SBenjamin Herrenschmidt 2317db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 2318db217319SBenjamin Herrenschmidt { 2319db217319SBenjamin Herrenschmidt struct pci_controller *hose; 2320db217319SBenjamin Herrenschmidt 2321db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 2322db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 2323db217319SBenjamin Herrenschmidt } 2324db217319SBenjamin Herrenschmidt 2325cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2326fb446ad0SGavin Shan { 232737c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 232837c367f2SGavin Shan 2329db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 2330db217319SBenjamin Herrenschmidt 2331e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2332b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 2333e9cc17d4SGavin Shan #endif 2334fb446ad0SGavin Shan } 2335fb446ad0SGavin Shan 2336271fd03aSGavin Shan /* 2337271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2338271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2339271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2340271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2341271fd03aSGavin Shan * 1MiB for memory) will be returned. 2342271fd03aSGavin Shan * 2343271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2344271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2345271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2346271fd03aSGavin Shan * resources. 2347271fd03aSGavin Shan */ 2348271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2349271fd03aSGavin Shan unsigned long type) 2350271fd03aSGavin Shan { 23515609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2352271fd03aSGavin Shan int num_pci_bridges = 0; 23535609ffddSOliver O'Halloran struct pci_dev *bridge; 2354271fd03aSGavin Shan 2355271fd03aSGavin Shan bridge = bus->self; 2356271fd03aSGavin Shan while (bridge) { 2357271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2358271fd03aSGavin Shan num_pci_bridges++; 2359271fd03aSGavin Shan if (num_pci_bridges >= 2) 2360271fd03aSGavin Shan return 1; 2361271fd03aSGavin Shan } 2362271fd03aSGavin Shan 2363271fd03aSGavin Shan bridge = bridge->bus->self; 2364271fd03aSGavin Shan } 2365271fd03aSGavin Shan 23665958d19aSBenjamin Herrenschmidt /* 23675958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 23685958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 23695958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 23705958d19aSBenjamin Herrenschmidt */ 2371b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 2372262af557SGuo Chao return phb->ioda.m64_segsize; 2373271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2374271fd03aSGavin Shan return phb->ioda.m32_segsize; 2375271fd03aSGavin Shan 2376271fd03aSGavin Shan return phb->ioda.io_segsize; 2377271fd03aSGavin Shan } 2378271fd03aSGavin Shan 237940e2a47eSGavin Shan /* 238040e2a47eSGavin Shan * We are updating root port or the upstream port of the 238140e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 238240e2a47eSGavin Shan * to accommodate the changes on required resources during 238340e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 238440e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 238540e2a47eSGavin Shan * root port. 238640e2a47eSGavin Shan */ 238740e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 238840e2a47eSGavin Shan unsigned long type) 238940e2a47eSGavin Shan { 239040e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 239140e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 239240e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 239340e2a47eSGavin Shan struct resource *r, *w; 239440e2a47eSGavin Shan bool msi_region = false; 239540e2a47eSGavin Shan int i; 239640e2a47eSGavin Shan 239740e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 239840e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 239940e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 240040e2a47eSGavin Shan return; 240140e2a47eSGavin Shan 240240e2a47eSGavin Shan /* Fixup the resources */ 240340e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 240440e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 240540e2a47eSGavin Shan if (!r->flags || !r->parent) 240640e2a47eSGavin Shan continue; 240740e2a47eSGavin Shan 240840e2a47eSGavin Shan w = NULL; 240940e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 241040e2a47eSGavin Shan w = &hose->io_resource; 24115958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 241240e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 241340e2a47eSGavin Shan phb->ioda.m64_segsize) 241440e2a47eSGavin Shan w = &hose->mem_resources[1]; 241540e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 241640e2a47eSGavin Shan w = &hose->mem_resources[0]; 241740e2a47eSGavin Shan msi_region = true; 241840e2a47eSGavin Shan } 241940e2a47eSGavin Shan 242040e2a47eSGavin Shan r->start = w->start; 242140e2a47eSGavin Shan r->end = w->end; 242240e2a47eSGavin Shan 242340e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 242440e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 242540e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 242640e2a47eSGavin Shan * 242740e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 242840e2a47eSGavin Shan * 32-bits bridge window. 242940e2a47eSGavin Shan */ 243040e2a47eSGavin Shan if (msi_region) { 243140e2a47eSGavin Shan r->end += 0x10000; 243240e2a47eSGavin Shan r->end -= 0x100000; 243340e2a47eSGavin Shan } 243440e2a47eSGavin Shan } 243540e2a47eSGavin Shan } 243640e2a47eSGavin Shan 2437dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus) 2438ccd1c191SGavin Shan { 2439ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 2440ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 2441dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 2442ccd1c191SGavin Shan 2443dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n"); 244440e2a47eSGavin Shan 2445ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 24466ae8aedfSOliver O'Halloran if (WARN_ON(list_empty(&bus->devices))) 2447ccd1c191SGavin Shan return; 2448ccd1c191SGavin Shan 2449ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 2450a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 2451ccd1c191SGavin Shan 2452ccd1c191SGavin Shan /* 2453ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 2454ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 2455ccd1c191SGavin Shan * not allocate resources again. 2456ccd1c191SGavin Shan */ 2457ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 2458ccd1c191SGavin Shan if (!pe) 2459ccd1c191SGavin Shan return; 2460ccd1c191SGavin Shan 2461ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 2462ccd1c191SGavin Shan } 2463ccd1c191SGavin Shan 246438274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 246538274637SYongji Xie { 246638274637SYongji Xie return PAGE_SIZE; 246738274637SYongji Xie } 246838274637SYongji Xie 2469184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 2470184cd4a3SBenjamin Herrenschmidt * assign a PE 2471184cd4a3SBenjamin Herrenschmidt */ 24728bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2473184cd4a3SBenjamin Herrenschmidt { 2474db1266c8SGavin Shan struct pci_dn *pdn; 2475184cd4a3SBenjamin Herrenschmidt 2476b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 24776c58b1b4SOliver O'Halloran if (!pdn || pdn->pe_number == IODA_INVALID_PE) { 24786c58b1b4SOliver O'Halloran pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); 2479c88c2a18SDaniel Axtens return false; 24806c58b1b4SOliver O'Halloran } 2481db1266c8SGavin Shan 2482c88c2a18SDaniel Axtens return true; 2483184cd4a3SBenjamin Herrenschmidt } 2484184cd4a3SBenjamin Herrenschmidt 2485c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 2486c1a2feadSFrederic Barrat { 2487c1a2feadSFrederic Barrat struct pci_dn *pdn; 2488c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 2489c1a2feadSFrederic Barrat 2490c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 2491c1a2feadSFrederic Barrat if (!pdn) 2492c1a2feadSFrederic Barrat return false; 2493c1a2feadSFrederic Barrat 2494c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 2495c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 2496c1a2feadSFrederic Barrat if (!pe) 2497c1a2feadSFrederic Barrat return false; 2498c1a2feadSFrederic Barrat } 2499c1a2feadSFrederic Barrat return true; 2500c1a2feadSFrederic Barrat } 2501c1a2feadSFrederic Barrat 2502c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 2503c5f7700bSGavin Shan int num) 2504c5f7700bSGavin Shan { 2505c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 2506c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 2507c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2508c5f7700bSGavin Shan unsigned int idx; 2509c5f7700bSGavin Shan long rc; 2510c5f7700bSGavin Shan 2511c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 2512c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 2513c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 2514c5f7700bSGavin Shan continue; 2515c5f7700bSGavin Shan 2516c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2517c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 2518c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 2519c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 2520c5f7700bSGavin Shan rc, idx); 2521c5f7700bSGavin Shan return rc; 2522c5f7700bSGavin Shan } 2523c5f7700bSGavin Shan 2524c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 2525c5f7700bSGavin Shan } 2526c5f7700bSGavin Shan 2527c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2528c5f7700bSGavin Shan return OPAL_SUCCESS; 2529c5f7700bSGavin Shan } 2530c5f7700bSGavin Shan 2531c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 2532c5f7700bSGavin Shan { 2533c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2534c5f7700bSGavin Shan int64_t rc; 2535c5f7700bSGavin Shan 253601e12629SOliver O'Halloran if (!pe->dma_setup_done) 2537c5f7700bSGavin Shan return; 2538c5f7700bSGavin Shan 2539c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 2540c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 2541c5f7700bSGavin Shan return; 2542c5f7700bSGavin Shan 2543a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 2544c5f7700bSGavin Shan if (pe->table_group.group) { 2545c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2546c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2547c5f7700bSGavin Shan } 2548c5f7700bSGavin Shan 2549c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 2550e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2551c5f7700bSGavin Shan } 2552c5f7700bSGavin Shan 255337b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 2554c5f7700bSGavin Shan { 2555c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2556c5f7700bSGavin Shan int64_t rc; 2557c5f7700bSGavin Shan 2558e17a7c0eSFrederic Barrat if (!pe->dma_setup_done) 2559c5f7700bSGavin Shan return; 2560c5f7700bSGavin Shan 2561c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2562c5f7700bSGavin Shan if (rc) 25631e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 2564c5f7700bSGavin Shan 2565c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 2566c5f7700bSGavin Shan if (pe->table_group.group) { 2567c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2568c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2569c5f7700bSGavin Shan } 2570c5f7700bSGavin Shan 2571e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2572c5f7700bSGavin Shan } 2573c5f7700bSGavin Shan 2574c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 2575c5f7700bSGavin Shan unsigned short win, 2576c5f7700bSGavin Shan unsigned int *map) 2577c5f7700bSGavin Shan { 2578c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2579c5f7700bSGavin Shan int idx; 2580c5f7700bSGavin Shan int64_t rc; 2581c5f7700bSGavin Shan 2582c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 2583c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 2584c5f7700bSGavin Shan continue; 2585c5f7700bSGavin Shan 2586c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2587c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 2588c5f7700bSGavin Shan 2589c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 25901e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 2591c5f7700bSGavin Shan rc, win, idx); 2592c5f7700bSGavin Shan 2593c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 2594c5f7700bSGavin Shan } 2595c5f7700bSGavin Shan } 2596c5f7700bSGavin Shan 2597c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 2598c5f7700bSGavin Shan { 2599c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2600c5f7700bSGavin Shan 2601c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2602c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 2603c5f7700bSGavin Shan phb->ioda.io_segmap); 2604c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2605c5f7700bSGavin Shan phb->ioda.m32_segmap); 260636963365SOliver O'Halloran /* M64 is pre-configured by pnv_ioda1_init_m64() */ 2607c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 2608c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2609c5f7700bSGavin Shan phb->ioda.m32_segmap); 2610c5f7700bSGavin Shan } 2611c5f7700bSGavin Shan } 2612c5f7700bSGavin Shan 2613c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 2614c5f7700bSGavin Shan { 2615c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2616c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 2617c5f7700bSGavin Shan 2618e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n"); 2619e5500ab6SOliver O'Halloran 262080f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 2621c5f7700bSGavin Shan list_del(&pe->list); 262280f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 262380f1ff83SFrederic Barrat 2624c5f7700bSGavin Shan switch (phb->type) { 2625c5f7700bSGavin Shan case PNV_PHB_IODA1: 2626c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 2627c5f7700bSGavin Shan break; 2628c5f7700bSGavin Shan case PNV_PHB_IODA2: 2629c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 2630c5f7700bSGavin Shan break; 2631f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 2632f724385fSFrederic Barrat break; 2633c5f7700bSGavin Shan default: 2634c5f7700bSGavin Shan WARN_ON(1); 2635c5f7700bSGavin Shan } 2636c5f7700bSGavin Shan 2637c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 2638c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 2639b314427aSGavin Shan 2640b314427aSGavin Shan /* Release slave PEs in the compound PE */ 2641b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 2642b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 2643b314427aSGavin Shan list_del(&slave->list); 2644b314427aSGavin Shan pnv_ioda_free_pe(slave); 2645b314427aSGavin Shan } 2646b314427aSGavin Shan } 2647b314427aSGavin Shan 26486eaed166SGavin Shan /* 26496eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 26506eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 26516eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 26526eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 26536eaed166SGavin Shan */ 2654718d249aSOliver O'Halloran if (phb->ioda.root_pe_idx == pe->pe_number) 2655718d249aSOliver O'Halloran return; 2656718d249aSOliver O'Halloran 2657c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 2658c5f7700bSGavin Shan } 2659c5f7700bSGavin Shan 2660c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 2661c5f7700bSGavin Shan { 26625609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2663c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 2664c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 2665c5f7700bSGavin Shan 266637b59ef0SOliver O'Halloran /* The VF PE state is torn down when sriov_disable() is called */ 2667c5f7700bSGavin Shan if (pdev->is_virtfn) 2668c5f7700bSGavin Shan return; 2669c5f7700bSGavin Shan 2670c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2671c5f7700bSGavin Shan return; 2672c5f7700bSGavin Shan 267337b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV 267437b59ef0SOliver O'Halloran /* 267537b59ef0SOliver O'Halloran * FIXME: Try move this to sriov_disable(). It's here since we allocate 267637b59ef0SOliver O'Halloran * the iov state at probe time since we need to fiddle with the IOV 267737b59ef0SOliver O'Halloran * resources. 267837b59ef0SOliver O'Halloran */ 267937b59ef0SOliver O'Halloran if (pdev->is_physfn) 268037b59ef0SOliver O'Halloran kfree(pdev->dev.archdata.iov_data); 268137b59ef0SOliver O'Halloran #endif 268237b59ef0SOliver O'Halloran 268329bf282dSGavin Shan /* 268429bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 268529bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 268629bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 268729bf282dSGavin Shan * device count is decreased on removing devices while failing to 268829bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 268929bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 269029bf282dSGavin Shan */ 2691c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 269229bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 269329bf282dSGavin Shan 2694c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 2695c5f7700bSGavin Shan if (pe->device_count == 0) 2696c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 2697c5f7700bSGavin Shan } 2698c5f7700bSGavin Shan 26997a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 270073ed148aSBenjamin Herrenschmidt { 27017a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 27027a8e6bbfSMichael Neuling 2703d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 270473ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 270573ed148aSBenjamin Herrenschmidt } 270673ed148aSBenjamin Herrenschmidt 2707946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 2708946743d0SOliver O'Halloran { 27095609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2710946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 2711946743d0SOliver O'Halloran 2712946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2713946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 2714946743d0SOliver O'Halloran continue; 2715946743d0SOliver O'Halloran 2716946743d0SOliver O'Halloran if (!pe->pbus) 2717946743d0SOliver O'Halloran continue; 2718946743d0SOliver O'Halloran 2719946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 2720946743d0SOliver O'Halloran pe->pbus = bus; 2721946743d0SOliver O'Halloran break; 2722946743d0SOliver O'Halloran } 2723946743d0SOliver O'Halloran } 2724946743d0SOliver O'Halloran } 2725946743d0SOliver O'Halloran 272692ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 27270a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 2728946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 27292d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 273092ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 273192ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 273292ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 2733c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 273492ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 2735dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources, 273692ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 27377a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 273892ae0353SDaniel Axtens }; 273992ae0353SDaniel Axtens 27407f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 2741c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 2742f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 27437f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 27447f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 27457f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 27467f2c39e9SFrederic Barrat }; 27477f2c39e9SFrederic Barrat 2748e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2749e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 2750184cd4a3SBenjamin Herrenschmidt { 2751184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 2752184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 27532b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 27542b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 2755718d249aSOliver O'Halloran struct pnv_ioda_pe *root_pe; 2756fd141d1aSBenjamin Herrenschmidt struct resource r; 2757c681b93cSAlistair Popple const __be64 *prop64; 27583a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 2759f1b7cc3eSGavin Shan int len; 27603fa23ff8SGavin Shan unsigned int segno; 2761184cd4a3SBenjamin Herrenschmidt u64 phb_id; 2762184cd4a3SBenjamin Herrenschmidt void *aux; 2763184cd4a3SBenjamin Herrenschmidt long rc; 2764184cd4a3SBenjamin Herrenschmidt 276508a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 276608a45b32SBenjamin Herrenschmidt return; 276708a45b32SBenjamin Herrenschmidt 2768b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 2769184cd4a3SBenjamin Herrenschmidt 2770184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2771184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2772184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2773184cd4a3SBenjamin Herrenschmidt return; 2774184cd4a3SBenjamin Herrenschmidt } 2775184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 2776184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2777184cd4a3SBenjamin Herrenschmidt 2778dea6f4c6SMichael Ellerman phb = kzalloc(sizeof(*phb), GFP_KERNEL); 27798a7f97b9SMike Rapoport if (!phb) 27808a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 27818a7f97b9SMike Rapoport sizeof(*phb)); 278258d714ecSGavin Shan 278358d714ecSGavin Shan /* Allocate PCI controller */ 2784184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 278558d714ecSGavin Shan if (!phb->hose) { 2786b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 2787b7c670d6SRob Herring np); 2788e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 2789184cd4a3SBenjamin Herrenschmidt return; 2790184cd4a3SBenjamin Herrenschmidt } 2791184cd4a3SBenjamin Herrenschmidt 2792184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 2793f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 2794f1b7cc3eSGavin Shan if (prop32 && len == 8) { 27953a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 27963a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 2797f1b7cc3eSGavin Shan } else { 2798b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 2799184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 2800184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 2801f1b7cc3eSGavin Shan } 2802184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 2803e9cc17d4SGavin Shan phb->hub_id = hub_id; 2804184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 2805aa0c033fSGavin Shan phb->type = ioda_type; 2806781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 2807184cd4a3SBenjamin Herrenschmidt 2808cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 2809cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 2810cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 2811f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 2812aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 2813cee72d5bSBenjamin Herrenschmidt else 2814cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 2815cee72d5bSBenjamin Herrenschmidt 28165cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 28175cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 28185cb1f8fdSRussell Currey if (prop32) 28195cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 28205cb1f8fdSRussell Currey else 28215cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 28225cb1f8fdSRussell Currey 2823dea6f4c6SMichael Ellerman phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL); 28248a7f97b9SMike Rapoport if (!phb->diag_data) 28258a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 28268a7f97b9SMike Rapoport phb->diag_data_size); 28275cb1f8fdSRussell Currey 2828aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 28292f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 2830184cd4a3SBenjamin Herrenschmidt 2831aa0c033fSGavin Shan /* Get registers */ 2832fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 2833fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 2834fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 2835184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 2836184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 2837fd141d1aSBenjamin Herrenschmidt } 2838577c8c88SGavin Shan 2839184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 284092b8f137SGavin Shan phb->ioda.total_pe_num = 1; 284136954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 284236954dc7SGavin Shan if (prop32) 284392b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 284436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 284536954dc7SGavin Shan if (prop32) 284692b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 2847262af557SGuo Chao 2848c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 2849c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 2850c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 2851c127562aSGavin Shan 2852262af557SGuo Chao /* Parse 64-bit MMIO range */ 2853262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 2854262af557SGuo Chao 2855184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 2856aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 2857184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 2858184cd4a3SBenjamin Herrenschmidt 285992b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 28603fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 2861184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 286292b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 2863184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 2864184cd4a3SBenjamin Herrenschmidt 28652b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 28662b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 28672b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 28682b923ed1SGavin Shan 2869c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 2870b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 287192a86756SAlexey Kardashevskiy sizeof(unsigned long)); 287293289d8cSGavin Shan m64map_off = size; 287393289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 2874184cd4a3SBenjamin Herrenschmidt m32map_off = size; 287592b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 2876c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2877c35d2a8cSGavin Shan iomap_off = size; 287892b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 28792b923ed1SGavin Shan dma32map_off = size; 28802b923ed1SGavin Shan size += phb->ioda.dma32_count * 28812b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 2882c35d2a8cSGavin Shan } 2883184cd4a3SBenjamin Herrenschmidt pemap_off = size; 288492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 2885dea6f4c6SMichael Ellerman aux = kzalloc(size, GFP_KERNEL); 28868a7f97b9SMike Rapoport if (!aux) 28878a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 2888fbbefb32SOliver O'Halloran 2889184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 289093289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 2891184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 289293289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 289393289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 28943fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 289593289d8cSGavin Shan } 28963fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 2897184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 28983fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 28993fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 29002b923ed1SGavin Shan 29012b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 29022b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 29032b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 29043fa23ff8SGavin Shan } 2905184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 290663803c39SGavin Shan 290763803c39SGavin Shan /* 290863803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 290963803c39SGavin Shan * M64 resources consumed by its child devices. To pick 291063803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 291163803c39SGavin Shan */ 291263803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 291363803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 291463803c39SGavin Shan phb->ioda.root_pe_idx = 1; 291563803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 291663803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 291763803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 291863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 291963803c39SGavin Shan } else { 2920718d249aSOliver O'Halloran /* otherwise just allocate one */ 2921a4bc676eSOliver O'Halloran root_pe = pnv_ioda_alloc_pe(phb, 1); 2922718d249aSOliver O'Halloran phb->ioda.root_pe_idx = root_pe->pe_number; 292363803c39SGavin Shan } 2924184cd4a3SBenjamin Herrenschmidt 2925184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 2926781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 2927184cd4a3SBenjamin Herrenschmidt 2928184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 29292b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 2930acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 2931184cd4a3SBenjamin Herrenschmidt 2932aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 2933184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 2934184cd4a3SBenjamin Herrenschmidt window_type, 2935184cd4a3SBenjamin Herrenschmidt window_num, 2936184cd4a3SBenjamin Herrenschmidt starting_real_address, 2937184cd4a3SBenjamin Herrenschmidt starting_pci_address, 2938184cd4a3SBenjamin Herrenschmidt segment_size); 2939184cd4a3SBenjamin Herrenschmidt #endif 2940184cd4a3SBenjamin Herrenschmidt 2941262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 294292b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 2943262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 2944262af557SGuo Chao if (phb->ioda.m64_size) 2945262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 2946262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 2947262af557SGuo Chao if (phb->ioda.io_size) 2948262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 2949184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 2950184cd4a3SBenjamin Herrenschmidt 2951262af557SGuo Chao 2952184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 295349dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 295449dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 295549dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 2956184cd4a3SBenjamin Herrenschmidt 2957184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 2958184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 2959184cd4a3SBenjamin Herrenschmidt 2960c40a4210SGavin Shan /* 2961c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 2962c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 2963c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 2964c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 2965c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 2966184cd4a3SBenjamin Herrenschmidt */ 2967fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 29685d2aa710SAlistair Popple 29697f2c39e9SFrederic Barrat switch (phb->type) { 29707f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 29717f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 29727f2c39e9SFrederic Barrat break; 29737f2c39e9SFrederic Barrat default: 297492ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 2975f9f83456SAlexey Kardashevskiy } 2976ad30cb99SMichael Ellerman 297738274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 297838274637SYongji Xie 29796e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 2980965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 29815350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 2982988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 2983988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 2984ad30cb99SMichael Ellerman #endif 2985ad30cb99SMichael Ellerman 2986c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 2987184cd4a3SBenjamin Herrenschmidt 2988184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 2989d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 2990184cd4a3SBenjamin Herrenschmidt if (rc) 2991f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 2992361f2a2aSGavin Shan 29936060e9eaSAndrew Donnellan /* 29946060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 2995361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 2996361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 299745baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 2998b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 2999b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3000b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3001b174b4fbSOliver O'Halloran * boot. 3002361f2a2aSGavin Shan */ 3003b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3004361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3005cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3006cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3007361f2a2aSGavin Shan } 3008262af557SGuo Chao 30099e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 30109e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3011262af557SGuo Chao hose->mem_resources[1].flags = 0; 3012fbbefb32SOliver O'Halloran 3013fbbefb32SOliver O'Halloran /* create pci_dn's for DT nodes under this PHB */ 3014fbbefb32SOliver O'Halloran pci_devs_phb_init_dynamic(hose); 3015184cd4a3SBenjamin Herrenschmidt } 3016184cd4a3SBenjamin Herrenschmidt 301767975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3018aa0c033fSGavin Shan { 3019e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3020aa0c033fSGavin Shan } 3021aa0c033fSGavin Shan 30227f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 30237f2c39e9SFrederic Barrat { 30247f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 30255d2aa710SAlistair Popple } 30265d2aa710SAlistair Popple 3027228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3028228c2f41SAndrew Donnellan { 30295609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3030228c2f41SAndrew Donnellan 3031228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3032228c2f41SAndrew Donnellan return; 3033228c2f41SAndrew Donnellan 3034228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3035228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3036228c2f41SAndrew Donnellan } 3037228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3038228c2f41SAndrew Donnellan 3039184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3040184cd4a3SBenjamin Herrenschmidt { 3041184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3042c681b93cSAlistair Popple const __be64 *prop64; 3043184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3044184cd4a3SBenjamin Herrenschmidt 3045b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3046184cd4a3SBenjamin Herrenschmidt 3047184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3048184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3049184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3050184cd4a3SBenjamin Herrenschmidt return; 3051184cd4a3SBenjamin Herrenschmidt } 3052184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3053184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3054184cd4a3SBenjamin Herrenschmidt 3055184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3056184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3057184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3058184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3059e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3060184cd4a3SBenjamin Herrenschmidt } 3061184cd4a3SBenjamin Herrenschmidt } 3062