1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 5199451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5299451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54781a868fSWei Yang 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 57bbb845c4SAlexey Kardashevskiy 58aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59aca6913fSAlexey Kardashevskiy 606d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 616d31c2faSJoe Perches const char *fmt, ...) 626d31c2faSJoe Perches { 636d31c2faSJoe Perches struct va_format vaf; 646d31c2faSJoe Perches va_list args; 656d31c2faSJoe Perches char pfix[32]; 66184cd4a3SBenjamin Herrenschmidt 676d31c2faSJoe Perches va_start(args, fmt); 686d31c2faSJoe Perches 696d31c2faSJoe Perches vaf.fmt = fmt; 706d31c2faSJoe Perches vaf.va = &args; 716d31c2faSJoe Perches 72781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 736d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 756d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 766d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 77781a868fSWei Yang #ifdef CONFIG_PCI_IOV 78781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 79781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 80781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 81781a868fSWei Yang (pe->rid & 0xff00) >> 8, 82781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 846d31c2faSJoe Perches 856d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 866d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 876d31c2faSJoe Perches 886d31c2faSJoe Perches va_end(args); 896d31c2faSJoe Perches } 906d31c2faSJoe Perches 916d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 926d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 936d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 946d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 956d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 966d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 97184cd4a3SBenjamin Herrenschmidt 984e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 994e287840SThadeu Lima de Souza Cascardo 1004e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 1014e287840SThadeu Lima de Souza Cascardo { 1024e287840SThadeu Lima de Souza Cascardo if (!str) 1034e287840SThadeu Lima de Souza Cascardo return -EINVAL; 1044e287840SThadeu Lima de Souza Cascardo 1054e287840SThadeu Lima de Souza Cascardo while (*str) { 1064e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1074e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1084e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1094e287840SThadeu Lima de Souza Cascardo break; 1104e287840SThadeu Lima de Souza Cascardo } 1114e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1124e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1134e287840SThadeu Lima de Souza Cascardo str++; 1144e287840SThadeu Lima de Souza Cascardo } 1154e287840SThadeu Lima de Souza Cascardo 1164e287840SThadeu Lima de Souza Cascardo return 0; 1174e287840SThadeu Lima de Souza Cascardo } 1184e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1194e287840SThadeu Lima de Souza Cascardo 120262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 121262af557SGuo Chao { 122262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 123262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 124262af557SGuo Chao } 125262af557SGuo Chao 1264b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1274b82ab18SGavin Shan { 12892b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1294b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1304b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1314b82ab18SGavin Shan return; 1324b82ab18SGavin Shan } 1334b82ab18SGavin Shan 134e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 135e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1364b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1374b82ab18SGavin Shan 1384b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1394b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1404b82ab18SGavin Shan } 1414b82ab18SGavin Shan 142689ee8c9SGavin Shan static unsigned int pnv_ioda_alloc_pe(struct pnv_phb *phb) 143184cd4a3SBenjamin Herrenschmidt { 144184cd4a3SBenjamin Herrenschmidt unsigned long pe; 145184cd4a3SBenjamin Herrenschmidt 146184cd4a3SBenjamin Herrenschmidt do { 147184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 14892b8f137SGavin Shan phb->ioda.total_pe_num, 0); 14992b8f137SGavin Shan if (pe >= phb->ioda.total_pe_num) 150184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 151184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 152184cd4a3SBenjamin Herrenschmidt 1534cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 154184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 155184cd4a3SBenjamin Herrenschmidt return pe; 156184cd4a3SBenjamin Herrenschmidt } 157184cd4a3SBenjamin Herrenschmidt 158cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 159184cd4a3SBenjamin Herrenschmidt { 160184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 161184cd4a3SBenjamin Herrenschmidt 162184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 163184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 164184cd4a3SBenjamin Herrenschmidt } 165184cd4a3SBenjamin Herrenschmidt 166262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 167262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 168262af557SGuo Chao { 169262af557SGuo Chao const char *desc; 170262af557SGuo Chao struct resource *r; 171262af557SGuo Chao s64 rc; 172262af557SGuo Chao 173262af557SGuo Chao /* Configure the default M64 BAR */ 174262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 175262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 176262af557SGuo Chao phb->ioda.m64_bar_idx, 177262af557SGuo Chao phb->ioda.m64_base, 178262af557SGuo Chao 0, /* unused */ 179262af557SGuo Chao phb->ioda.m64_size); 180262af557SGuo Chao if (rc != OPAL_SUCCESS) { 181262af557SGuo Chao desc = "configuring"; 182262af557SGuo Chao goto fail; 183262af557SGuo Chao } 184262af557SGuo Chao 185262af557SGuo Chao /* Enable the default M64 BAR */ 186262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 187262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 188262af557SGuo Chao phb->ioda.m64_bar_idx, 189262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 190262af557SGuo Chao if (rc != OPAL_SUCCESS) { 191262af557SGuo Chao desc = "enabling"; 192262af557SGuo Chao goto fail; 193262af557SGuo Chao } 194262af557SGuo Chao 195262af557SGuo Chao /* Mark the M64 BAR assigned */ 196262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 197262af557SGuo Chao 198262af557SGuo Chao /* 199262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 200262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 201262af557SGuo Chao */ 202262af557SGuo Chao r = &phb->hose->mem_resources[1]; 20392b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 204262af557SGuo Chao r->start += phb->ioda.m64_segsize; 20592b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 206262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 207262af557SGuo Chao else 208262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 20992b8f137SGavin Shan phb->ioda.reserved_pe_idx); 210262af557SGuo Chao 211262af557SGuo Chao return 0; 212262af557SGuo Chao 213262af557SGuo Chao fail: 214262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 215262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 216262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 217262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 218262af557SGuo Chao phb->ioda.m64_bar_idx, 219262af557SGuo Chao OPAL_DISABLE_M64); 220262af557SGuo Chao return -EIO; 221262af557SGuo Chao } 222262af557SGuo Chao 223c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 22496a2f92bSGavin Shan unsigned long *pe_bitmap) 225262af557SGuo Chao { 22696a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 22796a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 228262af557SGuo Chao struct resource *r; 22996a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 23096a2f92bSGavin Shan int segno, i; 231262af557SGuo Chao 23296a2f92bSGavin Shan base = phb->ioda.m64_base; 23396a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 23496a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 23596a2f92bSGavin Shan r = &pdev->resource[i]; 23696a2f92bSGavin Shan if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 237262af557SGuo Chao continue; 238262af557SGuo Chao 23996a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 24096a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 24196a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 24296a2f92bSGavin Shan if (pe_bitmap) 24396a2f92bSGavin Shan set_bit(segno, pe_bitmap); 24496a2f92bSGavin Shan else 24596a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 246262af557SGuo Chao } 247262af557SGuo Chao } 248262af557SGuo Chao } 249262af557SGuo Chao 25099451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 25199451551SGavin Shan { 25299451551SGavin Shan struct resource *r; 25399451551SGavin Shan int index; 25499451551SGavin Shan 25599451551SGavin Shan /* 25699451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 25799451551SGavin Shan * there are as many M64 segments as the maximum number of 25899451551SGavin Shan * PEs, which is 128. 25999451551SGavin Shan */ 26099451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 26199451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 26299451551SGavin Shan int64_t rc; 26399451551SGavin Shan 26499451551SGavin Shan base = phb->ioda.m64_base + 26599451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 26699451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 26799451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 26899451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 26999451551SGavin Shan if (rc != OPAL_SUCCESS) { 27099451551SGavin Shan pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 27199451551SGavin Shan rc, phb->hose->global_number, index); 27299451551SGavin Shan goto fail; 27399451551SGavin Shan } 27499451551SGavin Shan 27599451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 27699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 27799451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 27899451551SGavin Shan if (rc != OPAL_SUCCESS) { 27999451551SGavin Shan pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 28099451551SGavin Shan rc, phb->hose->global_number, index); 28199451551SGavin Shan goto fail; 28299451551SGavin Shan } 28399451551SGavin Shan } 28499451551SGavin Shan 28599451551SGavin Shan /* 28699451551SGavin Shan * Exclude the segment used by the reserved PE, which 28799451551SGavin Shan * is expected to be 0 or last supported PE#. 28899451551SGavin Shan */ 28999451551SGavin Shan r = &phb->hose->mem_resources[1]; 29099451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 29199451551SGavin Shan r->start += phb->ioda.m64_segsize; 29299451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 29399451551SGavin Shan r->end -= phb->ioda.m64_segsize; 29499451551SGavin Shan else 29599451551SGavin Shan WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 29699451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 29799451551SGavin Shan 29899451551SGavin Shan return 0; 29999451551SGavin Shan 30099451551SGavin Shan fail: 30199451551SGavin Shan for ( ; index >= 0; index--) 30299451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 30399451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 30499451551SGavin Shan 30599451551SGavin Shan return -EIO; 30699451551SGavin Shan } 30799451551SGavin Shan 308c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 30996a2f92bSGavin Shan unsigned long *pe_bitmap, 31096a2f92bSGavin Shan bool all) 311262af557SGuo Chao { 312262af557SGuo Chao struct pci_dev *pdev; 31396a2f92bSGavin Shan 31496a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 315c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 31696a2f92bSGavin Shan 31796a2f92bSGavin Shan if (all && pdev->subordinate) 318c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 31996a2f92bSGavin Shan pe_bitmap, all); 32096a2f92bSGavin Shan } 32196a2f92bSGavin Shan } 32296a2f92bSGavin Shan 323c430670aSGavin Shan static unsigned int pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 324262af557SGuo Chao { 32526ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 32626ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 327262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 328262af557SGuo Chao unsigned long size, *pe_alloc; 32926ba248dSGavin Shan int i; 330262af557SGuo Chao 331262af557SGuo Chao /* Root bus shouldn't use M64 */ 332262af557SGuo Chao if (pci_is_root_bus(bus)) 333262af557SGuo Chao return IODA_INVALID_PE; 334262af557SGuo Chao 335262af557SGuo Chao /* Allocate bitmap */ 33692b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 337262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 338262af557SGuo Chao if (!pe_alloc) { 339262af557SGuo Chao pr_warn("%s: Out of memory !\n", 340262af557SGuo Chao __func__); 341262af557SGuo Chao return IODA_INVALID_PE; 342262af557SGuo Chao } 343262af557SGuo Chao 34426ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 345c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 346262af557SGuo Chao 347262af557SGuo Chao /* 348262af557SGuo Chao * the current bus might not own M64 window and that's all 349262af557SGuo Chao * contributed by its child buses. For the case, we needn't 350262af557SGuo Chao * pick M64 dependent PE#. 351262af557SGuo Chao */ 35292b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 353262af557SGuo Chao kfree(pe_alloc); 354262af557SGuo Chao return IODA_INVALID_PE; 355262af557SGuo Chao } 356262af557SGuo Chao 357262af557SGuo Chao /* 358262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 359262af557SGuo Chao * PE's list to form compound PE. 360262af557SGuo Chao */ 361262af557SGuo Chao master_pe = NULL; 362262af557SGuo Chao i = -1; 36392b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 36492b8f137SGavin Shan phb->ioda.total_pe_num) { 365262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 366262af557SGuo Chao 36793289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 368262af557SGuo Chao if (!master_pe) { 369262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 370262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 371262af557SGuo Chao master_pe = pe; 372262af557SGuo Chao } else { 373262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 374262af557SGuo Chao pe->master = master_pe; 375262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 376262af557SGuo Chao } 37799451551SGavin Shan 37899451551SGavin Shan /* 37999451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 38099451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 38199451551SGavin Shan * between M64 segment and PE#. In order to have same logic 38299451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 38399451551SGavin Shan * segment and PE# on P7IOC. 38499451551SGavin Shan */ 38599451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 38699451551SGavin Shan int64_t rc; 38799451551SGavin Shan 38899451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 38999451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 39099451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 39199451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 39299451551SGavin Shan if (rc != OPAL_SUCCESS) 39399451551SGavin Shan pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 39499451551SGavin Shan __func__, rc, phb->hose->global_number, 39599451551SGavin Shan pe->pe_number); 39699451551SGavin Shan } 397262af557SGuo Chao } 398262af557SGuo Chao 399262af557SGuo Chao kfree(pe_alloc); 400262af557SGuo Chao return master_pe->pe_number; 401262af557SGuo Chao } 402262af557SGuo Chao 403262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 404262af557SGuo Chao { 405262af557SGuo Chao struct pci_controller *hose = phb->hose; 406262af557SGuo Chao struct device_node *dn = hose->dn; 407262af557SGuo Chao struct resource *res; 408262af557SGuo Chao const u32 *r; 409262af557SGuo Chao u64 pci_addr; 410262af557SGuo Chao 41199451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4121665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4131665c4a8SGavin Shan return; 4141665c4a8SGavin Shan } 4151665c4a8SGavin Shan 416e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 417262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 418262af557SGuo Chao return; 419262af557SGuo Chao } 420262af557SGuo Chao 421262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 422262af557SGuo Chao if (!r) { 423262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 424262af557SGuo Chao dn->full_name); 425262af557SGuo Chao return; 426262af557SGuo Chao } 427262af557SGuo Chao 428262af557SGuo Chao res = &hose->mem_resources[1]; 429e80c4e7cSGavin Shan res->name = dn->full_name; 430262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 431262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 432262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 433262af557SGuo Chao pci_addr = of_read_number(r, 2); 434262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 435262af557SGuo Chao 436262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 43792b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 438262af557SGuo Chao phb->ioda.m64_base = pci_addr; 439262af557SGuo Chao 440e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 441e9863e68SWei Yang res->start, res->end, pci_addr); 442e9863e68SWei Yang 443262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 444262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 44599451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 44699451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 44799451551SGavin Shan else 448262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 449c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 450c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 451262af557SGuo Chao } 452262af557SGuo Chao 45349dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 45449dec922SGavin Shan { 45549dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 45649dec922SGavin Shan struct pnv_ioda_pe *slave; 45749dec922SGavin Shan s64 rc; 45849dec922SGavin Shan 45949dec922SGavin Shan /* Fetch master PE */ 46049dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 46149dec922SGavin Shan pe = pe->master; 462ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 463ec8e4e9dSGavin Shan return; 464ec8e4e9dSGavin Shan 46549dec922SGavin Shan pe_no = pe->pe_number; 46649dec922SGavin Shan } 46749dec922SGavin Shan 46849dec922SGavin Shan /* Freeze master PE */ 46949dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 47049dec922SGavin Shan pe_no, 47149dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 47249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47349dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 47449dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 47549dec922SGavin Shan return; 47649dec922SGavin Shan } 47749dec922SGavin Shan 47849dec922SGavin Shan /* Freeze slave PEs */ 47949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 48049dec922SGavin Shan return; 48149dec922SGavin Shan 48249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 48349dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 48449dec922SGavin Shan slave->pe_number, 48549dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 48649dec922SGavin Shan if (rc != OPAL_SUCCESS) 48749dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 48849dec922SGavin Shan __func__, rc, phb->hose->global_number, 48949dec922SGavin Shan slave->pe_number); 49049dec922SGavin Shan } 49149dec922SGavin Shan } 49249dec922SGavin Shan 493e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 49449dec922SGavin Shan { 49549dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 49649dec922SGavin Shan s64 rc; 49749dec922SGavin Shan 49849dec922SGavin Shan /* Find master PE */ 49949dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 50049dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 50149dec922SGavin Shan pe = pe->master; 50249dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 50349dec922SGavin Shan pe_no = pe->pe_number; 50449dec922SGavin Shan } 50549dec922SGavin Shan 50649dec922SGavin Shan /* Clear frozen state for master PE */ 50749dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 50849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 50949dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 51049dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 51149dec922SGavin Shan return -EIO; 51249dec922SGavin Shan } 51349dec922SGavin Shan 51449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 51549dec922SGavin Shan return 0; 51649dec922SGavin Shan 51749dec922SGavin Shan /* Clear frozen state for slave PEs */ 51849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 51949dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 52049dec922SGavin Shan slave->pe_number, 52149dec922SGavin Shan opt); 52249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 52349dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 52449dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 52549dec922SGavin Shan slave->pe_number); 52649dec922SGavin Shan return -EIO; 52749dec922SGavin Shan } 52849dec922SGavin Shan } 52949dec922SGavin Shan 53049dec922SGavin Shan return 0; 53149dec922SGavin Shan } 53249dec922SGavin Shan 53349dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 53449dec922SGavin Shan { 53549dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 53649dec922SGavin Shan u8 fstate, state; 53749dec922SGavin Shan __be16 pcierr; 53849dec922SGavin Shan s64 rc; 53949dec922SGavin Shan 54049dec922SGavin Shan /* Sanity check on PE number */ 54192b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 54249dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 54349dec922SGavin Shan 54449dec922SGavin Shan /* 54549dec922SGavin Shan * Fetch the master PE and the PE instance might be 54649dec922SGavin Shan * not initialized yet. 54749dec922SGavin Shan */ 54849dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 54949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 55049dec922SGavin Shan pe = pe->master; 55149dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 55249dec922SGavin Shan pe_no = pe->pe_number; 55349dec922SGavin Shan } 55449dec922SGavin Shan 55549dec922SGavin Shan /* Check the master PE */ 55649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 55749dec922SGavin Shan &state, &pcierr, NULL); 55849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 55949dec922SGavin Shan pr_warn("%s: Failure %lld getting " 56049dec922SGavin Shan "PHB#%x-PE#%x state\n", 56149dec922SGavin Shan __func__, rc, 56249dec922SGavin Shan phb->hose->global_number, pe_no); 56349dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 56449dec922SGavin Shan } 56549dec922SGavin Shan 56649dec922SGavin Shan /* Check the slave PE */ 56749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 56849dec922SGavin Shan return state; 56949dec922SGavin Shan 57049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 57149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 57249dec922SGavin Shan slave->pe_number, 57349dec922SGavin Shan &fstate, 57449dec922SGavin Shan &pcierr, 57549dec922SGavin Shan NULL); 57649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57749dec922SGavin Shan pr_warn("%s: Failure %lld getting " 57849dec922SGavin Shan "PHB#%x-PE#%x state\n", 57949dec922SGavin Shan __func__, rc, 58049dec922SGavin Shan phb->hose->global_number, slave->pe_number); 58149dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 58249dec922SGavin Shan } 58349dec922SGavin Shan 58449dec922SGavin Shan /* 58549dec922SGavin Shan * Override the result based on the ascending 58649dec922SGavin Shan * priority. 58749dec922SGavin Shan */ 58849dec922SGavin Shan if (fstate > state) 58949dec922SGavin Shan state = fstate; 59049dec922SGavin Shan } 59149dec922SGavin Shan 59249dec922SGavin Shan return state; 59349dec922SGavin Shan } 59449dec922SGavin Shan 595184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 596184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 597184cd4a3SBenjamin Herrenschmidt */ 598184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 599cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 600184cd4a3SBenjamin Herrenschmidt { 601184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 602184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 603b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 604184cd4a3SBenjamin Herrenschmidt 605184cd4a3SBenjamin Herrenschmidt if (!pdn) 606184cd4a3SBenjamin Herrenschmidt return NULL; 607184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 608184cd4a3SBenjamin Herrenschmidt return NULL; 609184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 610184cd4a3SBenjamin Herrenschmidt } 611184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 612184cd4a3SBenjamin Herrenschmidt 613b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 614b131a842SGavin Shan struct pnv_ioda_pe *parent, 615b131a842SGavin Shan struct pnv_ioda_pe *child, 616b131a842SGavin Shan bool is_add) 617b131a842SGavin Shan { 618b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 619b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 620b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 621b131a842SGavin Shan struct pnv_ioda_pe *slave; 622b131a842SGavin Shan long rc; 623b131a842SGavin Shan 624b131a842SGavin Shan /* Parent PE affects child PE */ 625b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 626b131a842SGavin Shan child->pe_number, op); 627b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 628b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 629b131a842SGavin Shan rc, desc); 630b131a842SGavin Shan return -ENXIO; 631b131a842SGavin Shan } 632b131a842SGavin Shan 633b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 634b131a842SGavin Shan return 0; 635b131a842SGavin Shan 636b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 637b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 638b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 639b131a842SGavin Shan slave->pe_number, op); 640b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 641b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 642b131a842SGavin Shan rc, desc); 643b131a842SGavin Shan return -ENXIO; 644b131a842SGavin Shan } 645b131a842SGavin Shan } 646b131a842SGavin Shan 647b131a842SGavin Shan return 0; 648b131a842SGavin Shan } 649b131a842SGavin Shan 650b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 651b131a842SGavin Shan struct pnv_ioda_pe *pe, 652b131a842SGavin Shan bool is_add) 653b131a842SGavin Shan { 654b131a842SGavin Shan struct pnv_ioda_pe *slave; 655781a868fSWei Yang struct pci_dev *pdev = NULL; 656b131a842SGavin Shan int ret; 657b131a842SGavin Shan 658b131a842SGavin Shan /* 659b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 660b131a842SGavin Shan * clear slave PE frozen state as well. 661b131a842SGavin Shan */ 662b131a842SGavin Shan if (is_add) { 663b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 664b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 665b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 666b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 667b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 668b131a842SGavin Shan slave->pe_number, 669b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 670b131a842SGavin Shan } 671b131a842SGavin Shan } 672b131a842SGavin Shan 673b131a842SGavin Shan /* 674b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 675b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 676b131a842SGavin Shan * originated from the PE might contribute to other 677b131a842SGavin Shan * PEs. 678b131a842SGavin Shan */ 679b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 680b131a842SGavin Shan if (ret) 681b131a842SGavin Shan return ret; 682b131a842SGavin Shan 683b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 684b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 685b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 686b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 687b131a842SGavin Shan if (ret) 688b131a842SGavin Shan return ret; 689b131a842SGavin Shan } 690b131a842SGavin Shan } 691b131a842SGavin Shan 692b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 693b131a842SGavin Shan pdev = pe->pbus->self; 694781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 695b131a842SGavin Shan pdev = pe->pdev->bus->self; 696781a868fSWei Yang #ifdef CONFIG_PCI_IOV 697781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 698283e2d8aSGavin Shan pdev = pe->parent_dev; 699781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 700b131a842SGavin Shan while (pdev) { 701b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 702b131a842SGavin Shan struct pnv_ioda_pe *parent; 703b131a842SGavin Shan 704b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 705b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 706b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 707b131a842SGavin Shan if (ret) 708b131a842SGavin Shan return ret; 709b131a842SGavin Shan } 710b131a842SGavin Shan 711b131a842SGavin Shan pdev = pdev->bus->self; 712b131a842SGavin Shan } 713b131a842SGavin Shan 714b131a842SGavin Shan return 0; 715b131a842SGavin Shan } 716b131a842SGavin Shan 717781a868fSWei Yang #ifdef CONFIG_PCI_IOV 718781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 719781a868fSWei Yang { 720781a868fSWei Yang struct pci_dev *parent; 721781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 722781a868fSWei Yang int64_t rc; 723781a868fSWei Yang long rid_end, rid; 724781a868fSWei Yang 725781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 726781a868fSWei Yang if (pe->pbus) { 727781a868fSWei Yang int count; 728781a868fSWei Yang 729781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 730781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 731781a868fSWei Yang parent = pe->pbus->self; 732781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 733781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 734781a868fSWei Yang else 735781a868fSWei Yang count = 1; 736781a868fSWei Yang 737781a868fSWei Yang switch(count) { 738781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 739781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 740781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 741781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 742781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 743781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 744781a868fSWei Yang default: 745781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 746781a868fSWei Yang count); 747781a868fSWei Yang /* Do an exact match only */ 748781a868fSWei Yang bcomp = OpalPciBusAll; 749781a868fSWei Yang } 750781a868fSWei Yang rid_end = pe->rid + (count << 8); 751781a868fSWei Yang } else { 752781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 753781a868fSWei Yang parent = pe->parent_dev; 754781a868fSWei Yang else 755781a868fSWei Yang parent = pe->pdev->bus->self; 756781a868fSWei Yang bcomp = OpalPciBusAll; 757781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 758781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 759781a868fSWei Yang rid_end = pe->rid + 1; 760781a868fSWei Yang } 761781a868fSWei Yang 762781a868fSWei Yang /* Clear the reverse map */ 763781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 764781a868fSWei Yang phb->ioda.pe_rmap[rid] = 0; 765781a868fSWei Yang 766781a868fSWei Yang /* Release from all parents PELT-V */ 767781a868fSWei Yang while (parent) { 768781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 769781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 771781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 772781a868fSWei Yang /* XXX What to do in case of error ? */ 773781a868fSWei Yang } 774781a868fSWei Yang parent = parent->bus->self; 775781a868fSWei Yang } 776781a868fSWei Yang 777f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 778781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 779781a868fSWei Yang 780781a868fSWei Yang /* Disassociate PE in PELT */ 781781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 782781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 783781a868fSWei Yang if (rc) 784781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 785781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 786781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 787781a868fSWei Yang if (rc) 788781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 789781a868fSWei Yang 790781a868fSWei Yang pe->pbus = NULL; 791781a868fSWei Yang pe->pdev = NULL; 792781a868fSWei Yang pe->parent_dev = NULL; 793781a868fSWei Yang 794781a868fSWei Yang return 0; 795781a868fSWei Yang } 796781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 797781a868fSWei Yang 798cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 799184cd4a3SBenjamin Herrenschmidt { 800184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 801184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 802184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 803184cd4a3SBenjamin Herrenschmidt 804184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 805184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 806184cd4a3SBenjamin Herrenschmidt int count; 807184cd4a3SBenjamin Herrenschmidt 808184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 809184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 810184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 811fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 812b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 813fb446ad0SGavin Shan else 814fb446ad0SGavin Shan count = 1; 815fb446ad0SGavin Shan 816184cd4a3SBenjamin Herrenschmidt switch(count) { 817184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 818184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 819184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 820184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 821184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 822184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 823184cd4a3SBenjamin Herrenschmidt default: 824781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 825781a868fSWei Yang count); 826184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 827184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 828184cd4a3SBenjamin Herrenschmidt } 829184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 830184cd4a3SBenjamin Herrenschmidt } else { 831781a868fSWei Yang #ifdef CONFIG_PCI_IOV 832781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 833781a868fSWei Yang parent = pe->parent_dev; 834781a868fSWei Yang else 835781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 836184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 837184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 838184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 839184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 840184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 841184cd4a3SBenjamin Herrenschmidt } 842184cd4a3SBenjamin Herrenschmidt 843631ad691SGavin Shan /* 844631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 845631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 846631ad691SGavin Shan * originated from the PE might contribute to other 847631ad691SGavin Shan * PEs. 848631ad691SGavin Shan */ 849184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 850184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 851184cd4a3SBenjamin Herrenschmidt if (rc) { 852184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 853184cd4a3SBenjamin Herrenschmidt return -ENXIO; 854184cd4a3SBenjamin Herrenschmidt } 855631ad691SGavin Shan 8565d2aa710SAlistair Popple /* 8575d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 8585d2aa710SAlistair Popple * configuration on them. 8595d2aa710SAlistair Popple */ 8605d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 861b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 862184cd4a3SBenjamin Herrenschmidt 863184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 864184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 865184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 866184cd4a3SBenjamin Herrenschmidt 867184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8684773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8694773f76bSGavin Shan pe->mve_number = 0; 8704773f76bSGavin Shan goto out; 8714773f76bSGavin Shan } 8724773f76bSGavin Shan 873184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8744773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8754773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 876184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 877184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 878184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 879184cd4a3SBenjamin Herrenschmidt } else { 880184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 881cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 882184cd4a3SBenjamin Herrenschmidt if (rc) { 883184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 884184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 885184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 886184cd4a3SBenjamin Herrenschmidt } 887184cd4a3SBenjamin Herrenschmidt } 888184cd4a3SBenjamin Herrenschmidt 8894773f76bSGavin Shan out: 890184cd4a3SBenjamin Herrenschmidt return 0; 891184cd4a3SBenjamin Herrenschmidt } 892184cd4a3SBenjamin Herrenschmidt 893781a868fSWei Yang #ifdef CONFIG_PCI_IOV 894781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 895781a868fSWei Yang { 896781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 897781a868fSWei Yang int i; 898781a868fSWei Yang struct resource *res, res2; 899781a868fSWei Yang resource_size_t size; 900781a868fSWei Yang u16 num_vfs; 901781a868fSWei Yang 902781a868fSWei Yang if (!dev->is_physfn) 903781a868fSWei Yang return -EINVAL; 904781a868fSWei Yang 905781a868fSWei Yang /* 906781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 907781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 908781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 909781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 910781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 911781a868fSWei Yang * range of PEs the VFs are in. 912781a868fSWei Yang */ 913781a868fSWei Yang num_vfs = pdn->num_vfs; 914781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 915781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 916781a868fSWei Yang if (!res->flags || !res->parent) 917781a868fSWei Yang continue; 918781a868fSWei Yang 919781a868fSWei Yang /* 920781a868fSWei Yang * The actual IOV BAR range is determined by the start address 921781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 922781a868fSWei Yang * make sure that after shifting, the range will not overlap 923781a868fSWei Yang * with another device. 924781a868fSWei Yang */ 925781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 926781a868fSWei Yang res2.flags = res->flags; 927781a868fSWei Yang res2.start = res->start + (size * offset); 928781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 929781a868fSWei Yang 930781a868fSWei Yang if (res2.end > res->end) { 931781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 932781a868fSWei Yang i, &res2, res, num_vfs, offset); 933781a868fSWei Yang return -EBUSY; 934781a868fSWei Yang } 935781a868fSWei Yang } 936781a868fSWei Yang 937781a868fSWei Yang /* 938781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 939781a868fSWei Yang * offset is a positive value. It looks like the device return some 940781a868fSWei Yang * mmio back to the system, which actually no one could use it. 941781a868fSWei Yang */ 942781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 943781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 944781a868fSWei Yang if (!res->flags || !res->parent) 945781a868fSWei Yang continue; 946781a868fSWei Yang 947781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 948781a868fSWei Yang res2 = *res; 949781a868fSWei Yang res->start += size * offset; 950781a868fSWei Yang 95174703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 95274703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 95374703cc4SWei Yang num_vfs, offset); 954781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 955781a868fSWei Yang } 956781a868fSWei Yang return 0; 957781a868fSWei Yang } 958781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 959781a868fSWei Yang 960cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 961184cd4a3SBenjamin Herrenschmidt { 962184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 963184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 964b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 965184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 966689ee8c9SGavin Shan unsigned int pe_num; 967184cd4a3SBenjamin Herrenschmidt 968184cd4a3SBenjamin Herrenschmidt if (!pdn) { 969184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 970184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 971184cd4a3SBenjamin Herrenschmidt return NULL; 972184cd4a3SBenjamin Herrenschmidt } 973184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 974184cd4a3SBenjamin Herrenschmidt return NULL; 975184cd4a3SBenjamin Herrenschmidt 976184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 977184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 978184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 979184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 980184cd4a3SBenjamin Herrenschmidt return NULL; 981184cd4a3SBenjamin Herrenschmidt } 982184cd4a3SBenjamin Herrenschmidt 983184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 984184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 985184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 986184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 987184cd4a3SBenjamin Herrenschmidt * 988184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 989184cd4a3SBenjamin Herrenschmidt */ 990184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 991184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 992184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 993184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 9945d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 995184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 996184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 997184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 998184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 999184cd4a3SBenjamin Herrenschmidt 1000184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1001184cd4a3SBenjamin Herrenschmidt 1002184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1003184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1004184cd4a3SBenjamin Herrenschmidt if (pe_num) 1005184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1006184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1007184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1008184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1009184cd4a3SBenjamin Herrenschmidt return NULL; 1010184cd4a3SBenjamin Herrenschmidt } 1011184cd4a3SBenjamin Herrenschmidt 1012184cd4a3SBenjamin Herrenschmidt return pe; 1013184cd4a3SBenjamin Herrenschmidt } 1014184cd4a3SBenjamin Herrenschmidt 1015184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1016184cd4a3SBenjamin Herrenschmidt { 1017184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1018184cd4a3SBenjamin Herrenschmidt 1019184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1020b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1021184cd4a3SBenjamin Herrenschmidt 1022184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1023184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1024184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1025184cd4a3SBenjamin Herrenschmidt continue; 1026184cd4a3SBenjamin Herrenschmidt } 102794973b24SAlistair Popple pdn->pcidev = dev; 1028184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1029fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1030184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1031184cd4a3SBenjamin Herrenschmidt } 1032184cd4a3SBenjamin Herrenschmidt } 1033184cd4a3SBenjamin Herrenschmidt 1034fb446ad0SGavin Shan /* 1035fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1036fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1037fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1038fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1039fb446ad0SGavin Shan */ 1040d1203852SGavin Shan static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1041184cd4a3SBenjamin Herrenschmidt { 1042fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1043184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1044184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1045689ee8c9SGavin Shan unsigned int pe_num = IODA_INVALID_PE; 1046184cd4a3SBenjamin Herrenschmidt 1047262af557SGuo Chao /* Check if PE is determined by M64 */ 1048262af557SGuo Chao if (phb->pick_m64_pe) 104926ba248dSGavin Shan pe_num = phb->pick_m64_pe(bus, all); 1050262af557SGuo Chao 1051262af557SGuo Chao /* The PE number isn't pinned by M64 */ 1052262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 1053184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 1054262af557SGuo Chao 1055184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 1056fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1057fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 1058184cd4a3SBenjamin Herrenschmidt return; 1059184cd4a3SBenjamin Herrenschmidt } 1060184cd4a3SBenjamin Herrenschmidt 1061184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1062262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1063184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1064184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1065184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1066b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1067184cd4a3SBenjamin Herrenschmidt 1068fb446ad0SGavin Shan if (all) 1069fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1070fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 1071fb446ad0SGavin Shan else 1072fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1073fb446ad0SGavin Shan bus->busn_res.start, pe_num); 1074184cd4a3SBenjamin Herrenschmidt 1075184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1076184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1077184cd4a3SBenjamin Herrenschmidt if (pe_num) 1078184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1079184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1080184cd4a3SBenjamin Herrenschmidt return; 1081184cd4a3SBenjamin Herrenschmidt } 1082184cd4a3SBenjamin Herrenschmidt 1083184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1084184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1085184cd4a3SBenjamin Herrenschmidt 10867ebdf956SGavin Shan /* Put PE to the list */ 10877ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 1088184cd4a3SBenjamin Herrenschmidt } 1089184cd4a3SBenjamin Herrenschmidt 1090b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 10915d2aa710SAlistair Popple { 1092b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1093b521549aSAlistair Popple long rid; 1094b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1095b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1096b521549aSAlistair Popple struct pci_dn *npu_pdn; 1097b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1098b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1099b521549aSAlistair Popple 1100b521549aSAlistair Popple /* 1101b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1102b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1103b521549aSAlistair Popple * which need to be assigned to four links, implying some 1104b521549aSAlistair Popple * links must share PEs. 1105b521549aSAlistair Popple * 1106b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1107b521549aSAlistair Popple * same GPU get assigned the same PE. 1108b521549aSAlistair Popple */ 1109b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 111092b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1111b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1112b521549aSAlistair Popple if (!pe->pdev) 1113b521549aSAlistair Popple continue; 1114b521549aSAlistair Popple 1115b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1116b521549aSAlistair Popple /* 1117b521549aSAlistair Popple * This device has the same peer GPU so should 1118b521549aSAlistair Popple * be assigned the same PE as the existing 1119b521549aSAlistair Popple * peer NPU. 1120b521549aSAlistair Popple */ 1121b521549aSAlistair Popple dev_info(&npu_pdev->dev, 1122b521549aSAlistair Popple "Associating to existing PE %d\n", pe_num); 1123b521549aSAlistair Popple pci_dev_get(npu_pdev); 1124b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1125b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1126b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1127b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1128b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1129b521549aSAlistair Popple 1130b521549aSAlistair Popple /* Map the PE to this link */ 1131b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1132b521549aSAlistair Popple OpalPciBusAll, 1133b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1134b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1135b521549aSAlistair Popple OPAL_MAP_PE); 1136b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1137b521549aSAlistair Popple found_pe = true; 1138b521549aSAlistair Popple break; 1139b521549aSAlistair Popple } 1140b521549aSAlistair Popple } 1141b521549aSAlistair Popple 1142b521549aSAlistair Popple if (!found_pe) 1143b521549aSAlistair Popple /* 1144b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1145b521549aSAlistair Popple * one. 1146b521549aSAlistair Popple */ 1147b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1148b521549aSAlistair Popple else 1149b521549aSAlistair Popple return pe; 1150b521549aSAlistair Popple } 1151b521549aSAlistair Popple 1152b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1153b521549aSAlistair Popple { 11545d2aa710SAlistair Popple struct pci_dev *pdev; 11555d2aa710SAlistair Popple 11565d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1157b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 11585d2aa710SAlistair Popple } 11595d2aa710SAlistair Popple 1160cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1161184cd4a3SBenjamin Herrenschmidt { 1162184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1163fb446ad0SGavin Shan 1164d1203852SGavin Shan pnv_ioda_setup_bus_PE(bus, false); 1165184cd4a3SBenjamin Herrenschmidt 1166184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1167fb446ad0SGavin Shan if (dev->subordinate) { 116862f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1169d1203852SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, true); 1170fb446ad0SGavin Shan else 1171184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 1172184cd4a3SBenjamin Herrenschmidt } 1173184cd4a3SBenjamin Herrenschmidt } 1174fb446ad0SGavin Shan } 1175fb446ad0SGavin Shan 1176fb446ad0SGavin Shan /* 1177fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 1178fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 1179fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 1180fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 1181fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 1182fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 1183fb446ad0SGavin Shan */ 1184cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1185fb446ad0SGavin Shan { 1186fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1187262af557SGuo Chao struct pnv_phb *phb; 1188fb446ad0SGavin Shan 1189fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1190262af557SGuo Chao phb = hose->private_data; 1191262af557SGuo Chao 1192262af557SGuo Chao /* M64 layout might affect PE allocation */ 11935ef73567SGavin Shan if (phb->reserve_m64_pe) 119496a2f92bSGavin Shan phb->reserve_m64_pe(hose->bus, NULL, true); 1195262af557SGuo Chao 11965d2aa710SAlistair Popple /* 11975d2aa710SAlistair Popple * On NPU PHB, we expect separate PEs for individual PCI 11985d2aa710SAlistair Popple * functions. PCI bus dependent PEs are required for the 11995d2aa710SAlistair Popple * remaining types of PHBs. 12005d2aa710SAlistair Popple */ 120108f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 120208f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 120308f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1204b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 120508f48f32SAlistair Popple } else 1206fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 1207fb446ad0SGavin Shan } 1208fb446ad0SGavin Shan } 1209184cd4a3SBenjamin Herrenschmidt 1210a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1211ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1212781a868fSWei Yang { 1213781a868fSWei Yang struct pci_bus *bus; 1214781a868fSWei Yang struct pci_controller *hose; 1215781a868fSWei Yang struct pnv_phb *phb; 1216781a868fSWei Yang struct pci_dn *pdn; 121702639b0eSWei Yang int i, j; 1218ee8222feSWei Yang int m64_bars; 1219781a868fSWei Yang 1220781a868fSWei Yang bus = pdev->bus; 1221781a868fSWei Yang hose = pci_bus_to_host(bus); 1222781a868fSWei Yang phb = hose->private_data; 1223781a868fSWei Yang pdn = pci_get_pdn(pdev); 1224781a868fSWei Yang 1225ee8222feSWei Yang if (pdn->m64_single_mode) 1226ee8222feSWei Yang m64_bars = num_vfs; 1227ee8222feSWei Yang else 1228ee8222feSWei Yang m64_bars = 1; 1229ee8222feSWei Yang 123002639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1231ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1232ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1233781a868fSWei Yang continue; 1234781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1235ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1236ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1237ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1238781a868fSWei Yang } 1239781a868fSWei Yang 1240ee8222feSWei Yang kfree(pdn->m64_map); 1241781a868fSWei Yang return 0; 1242781a868fSWei Yang } 1243781a868fSWei Yang 124402639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1245781a868fSWei Yang { 1246781a868fSWei Yang struct pci_bus *bus; 1247781a868fSWei Yang struct pci_controller *hose; 1248781a868fSWei Yang struct pnv_phb *phb; 1249781a868fSWei Yang struct pci_dn *pdn; 1250781a868fSWei Yang unsigned int win; 1251781a868fSWei Yang struct resource *res; 125202639b0eSWei Yang int i, j; 1253781a868fSWei Yang int64_t rc; 125402639b0eSWei Yang int total_vfs; 125502639b0eSWei Yang resource_size_t size, start; 125602639b0eSWei Yang int pe_num; 1257ee8222feSWei Yang int m64_bars; 1258781a868fSWei Yang 1259781a868fSWei Yang bus = pdev->bus; 1260781a868fSWei Yang hose = pci_bus_to_host(bus); 1261781a868fSWei Yang phb = hose->private_data; 1262781a868fSWei Yang pdn = pci_get_pdn(pdev); 126302639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1264781a868fSWei Yang 1265ee8222feSWei Yang if (pdn->m64_single_mode) 1266ee8222feSWei Yang m64_bars = num_vfs; 1267ee8222feSWei Yang else 1268ee8222feSWei Yang m64_bars = 1; 126902639b0eSWei Yang 1270ee8222feSWei Yang pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1271ee8222feSWei Yang if (!pdn->m64_map) 1272ee8222feSWei Yang return -ENOMEM; 1273ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1274ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1275ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1276ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1277ee8222feSWei Yang 1278781a868fSWei Yang 1279781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1280781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1281781a868fSWei Yang if (!res->flags || !res->parent) 1282781a868fSWei Yang continue; 1283781a868fSWei Yang 1284ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1285781a868fSWei Yang do { 1286781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1287781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1288781a868fSWei Yang 1289781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1290781a868fSWei Yang goto m64_failed; 1291781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1292781a868fSWei Yang 1293ee8222feSWei Yang pdn->m64_map[j][i] = win; 129402639b0eSWei Yang 1295ee8222feSWei Yang if (pdn->m64_single_mode) { 129602639b0eSWei Yang size = pci_iov_resource_size(pdev, 129702639b0eSWei Yang PCI_IOV_RESOURCES + i); 129802639b0eSWei Yang start = res->start + size * j; 129902639b0eSWei Yang } else { 130002639b0eSWei Yang size = resource_size(res); 130102639b0eSWei Yang start = res->start; 130202639b0eSWei Yang } 1303781a868fSWei Yang 1304781a868fSWei Yang /* Map the M64 here */ 1305ee8222feSWei Yang if (pdn->m64_single_mode) { 1306be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 130702639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 130802639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1309ee8222feSWei Yang pdn->m64_map[j][i], 0); 131002639b0eSWei Yang } 131102639b0eSWei Yang 1312781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1313781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1314ee8222feSWei Yang pdn->m64_map[j][i], 131502639b0eSWei Yang start, 1316781a868fSWei Yang 0, /* unused */ 131702639b0eSWei Yang size); 131802639b0eSWei Yang 131902639b0eSWei Yang 1320781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1321781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1322781a868fSWei Yang win, rc); 1323781a868fSWei Yang goto m64_failed; 1324781a868fSWei Yang } 1325781a868fSWei Yang 1326ee8222feSWei Yang if (pdn->m64_single_mode) 1327781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1328ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 132902639b0eSWei Yang else 133002639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1331ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 133202639b0eSWei Yang 1333781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1334781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1335781a868fSWei Yang win, rc); 1336781a868fSWei Yang goto m64_failed; 1337781a868fSWei Yang } 1338781a868fSWei Yang } 133902639b0eSWei Yang } 1340781a868fSWei Yang return 0; 1341781a868fSWei Yang 1342781a868fSWei Yang m64_failed: 1343ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1344781a868fSWei Yang return -EBUSY; 1345781a868fSWei Yang } 1346781a868fSWei Yang 1347c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1348c035e37bSAlexey Kardashevskiy int num); 1349c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1350c035e37bSAlexey Kardashevskiy 1351781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1352781a868fSWei Yang { 1353781a868fSWei Yang struct iommu_table *tbl; 1354781a868fSWei Yang int64_t rc; 1355781a868fSWei Yang 1356b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1357c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1358781a868fSWei Yang if (rc) 1359781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1360781a868fSWei Yang 1361c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 13620eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 13630eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 13640eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1365ac9a5889SAlexey Kardashevskiy } 1366aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1367781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1368781a868fSWei Yang } 1369781a868fSWei Yang 1370ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1371781a868fSWei Yang { 1372781a868fSWei Yang struct pci_bus *bus; 1373781a868fSWei Yang struct pci_controller *hose; 1374781a868fSWei Yang struct pnv_phb *phb; 1375781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1376781a868fSWei Yang struct pci_dn *pdn; 1377781a868fSWei Yang 1378781a868fSWei Yang bus = pdev->bus; 1379781a868fSWei Yang hose = pci_bus_to_host(bus); 1380781a868fSWei Yang phb = hose->private_data; 138102639b0eSWei Yang pdn = pci_get_pdn(pdev); 1382781a868fSWei Yang 1383781a868fSWei Yang if (!pdev->is_physfn) 1384781a868fSWei Yang return; 1385781a868fSWei Yang 1386781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1387781a868fSWei Yang if (pe->parent_dev != pdev) 1388781a868fSWei Yang continue; 1389781a868fSWei Yang 1390781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1391781a868fSWei Yang 1392781a868fSWei Yang /* Remove from list */ 1393781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1394781a868fSWei Yang list_del(&pe->list); 1395781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1396781a868fSWei Yang 1397781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1398781a868fSWei Yang 1399781a868fSWei Yang pnv_ioda_free_pe(phb, pe->pe_number); 1400781a868fSWei Yang } 1401781a868fSWei Yang } 1402781a868fSWei Yang 1403781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1404781a868fSWei Yang { 1405781a868fSWei Yang struct pci_bus *bus; 1406781a868fSWei Yang struct pci_controller *hose; 1407781a868fSWei Yang struct pnv_phb *phb; 1408781a868fSWei Yang struct pci_dn *pdn; 1409781a868fSWei Yang struct pci_sriov *iov; 1410be283eebSWei Yang u16 num_vfs, i; 1411781a868fSWei Yang 1412781a868fSWei Yang bus = pdev->bus; 1413781a868fSWei Yang hose = pci_bus_to_host(bus); 1414781a868fSWei Yang phb = hose->private_data; 1415781a868fSWei Yang pdn = pci_get_pdn(pdev); 1416781a868fSWei Yang iov = pdev->sriov; 1417781a868fSWei Yang num_vfs = pdn->num_vfs; 1418781a868fSWei Yang 1419781a868fSWei Yang /* Release VF PEs */ 1420ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1421781a868fSWei Yang 1422781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1423ee8222feSWei Yang if (!pdn->m64_single_mode) 1424be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1425781a868fSWei Yang 1426781a868fSWei Yang /* Release M64 windows */ 1427ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1428781a868fSWei Yang 1429781a868fSWei Yang /* Release PE numbers */ 1430be283eebSWei Yang if (pdn->m64_single_mode) { 1431be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1432be283eebSWei Yang if (pdn->pe_num_map[i] != IODA_INVALID_PE) 1433be283eebSWei Yang pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); 1434be283eebSWei Yang } 1435be283eebSWei Yang } else 1436be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1437be283eebSWei Yang /* Releasing pe_num_map */ 1438be283eebSWei Yang kfree(pdn->pe_num_map); 1439781a868fSWei Yang } 1440781a868fSWei Yang } 1441781a868fSWei Yang 1442781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1443781a868fSWei Yang struct pnv_ioda_pe *pe); 1444781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1445781a868fSWei Yang { 1446781a868fSWei Yang struct pci_bus *bus; 1447781a868fSWei Yang struct pci_controller *hose; 1448781a868fSWei Yang struct pnv_phb *phb; 1449781a868fSWei Yang struct pnv_ioda_pe *pe; 1450781a868fSWei Yang int pe_num; 1451781a868fSWei Yang u16 vf_index; 1452781a868fSWei Yang struct pci_dn *pdn; 1453781a868fSWei Yang 1454781a868fSWei Yang bus = pdev->bus; 1455781a868fSWei Yang hose = pci_bus_to_host(bus); 1456781a868fSWei Yang phb = hose->private_data; 1457781a868fSWei Yang pdn = pci_get_pdn(pdev); 1458781a868fSWei Yang 1459781a868fSWei Yang if (!pdev->is_physfn) 1460781a868fSWei Yang return; 1461781a868fSWei Yang 1462781a868fSWei Yang /* Reserve PE for each VF */ 1463781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1464be283eebSWei Yang if (pdn->m64_single_mode) 1465be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1466be283eebSWei Yang else 1467be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1468781a868fSWei Yang 1469781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1470781a868fSWei Yang pe->pe_number = pe_num; 1471781a868fSWei Yang pe->phb = phb; 1472781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1473781a868fSWei Yang pe->pbus = NULL; 1474781a868fSWei Yang pe->parent_dev = pdev; 1475781a868fSWei Yang pe->mve_number = -1; 1476781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1477781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1478781a868fSWei Yang 1479781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1480781a868fSWei Yang hose->global_number, pdev->bus->number, 1481781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1482781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1483781a868fSWei Yang 1484781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1485781a868fSWei Yang /* XXX What do we do here ? */ 1486781a868fSWei Yang if (pe_num) 1487781a868fSWei Yang pnv_ioda_free_pe(phb, pe_num); 1488781a868fSWei Yang pe->pdev = NULL; 1489781a868fSWei Yang continue; 1490781a868fSWei Yang } 1491781a868fSWei Yang 1492781a868fSWei Yang /* Put PE to the list */ 1493781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1494781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1495781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1496781a868fSWei Yang 1497781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1498781a868fSWei Yang } 1499781a868fSWei Yang } 1500781a868fSWei Yang 1501781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1502781a868fSWei Yang { 1503781a868fSWei Yang struct pci_bus *bus; 1504781a868fSWei Yang struct pci_controller *hose; 1505781a868fSWei Yang struct pnv_phb *phb; 1506781a868fSWei Yang struct pci_dn *pdn; 1507781a868fSWei Yang int ret; 1508be283eebSWei Yang u16 i; 1509781a868fSWei Yang 1510781a868fSWei Yang bus = pdev->bus; 1511781a868fSWei Yang hose = pci_bus_to_host(bus); 1512781a868fSWei Yang phb = hose->private_data; 1513781a868fSWei Yang pdn = pci_get_pdn(pdev); 1514781a868fSWei Yang 1515781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1516b0331854SWei Yang if (!pdn->vfs_expanded) { 1517b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1518b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1519b0331854SWei Yang return -ENOSPC; 1520b0331854SWei Yang } 1521b0331854SWei Yang 1522ee8222feSWei Yang /* 1523ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1524ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1525ee8222feSWei Yang */ 1526ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1527ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1528ee8222feSWei Yang return -EBUSY; 1529ee8222feSWei Yang } 1530ee8222feSWei Yang 1531be283eebSWei Yang /* Allocating pe_num_map */ 1532be283eebSWei Yang if (pdn->m64_single_mode) 1533be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1534be283eebSWei Yang GFP_KERNEL); 1535be283eebSWei Yang else 1536be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1537be283eebSWei Yang 1538be283eebSWei Yang if (!pdn->pe_num_map) 1539be283eebSWei Yang return -ENOMEM; 1540be283eebSWei Yang 1541be283eebSWei Yang if (pdn->m64_single_mode) 1542be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1543be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1544be283eebSWei Yang 1545781a868fSWei Yang /* Calculate available PE for required VFs */ 1546be283eebSWei Yang if (pdn->m64_single_mode) { 1547be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1548be283eebSWei Yang pdn->pe_num_map[i] = pnv_ioda_alloc_pe(phb); 1549be283eebSWei Yang if (pdn->pe_num_map[i] == IODA_INVALID_PE) { 1550be283eebSWei Yang ret = -EBUSY; 1551be283eebSWei Yang goto m64_failed; 1552be283eebSWei Yang } 1553be283eebSWei Yang } 1554be283eebSWei Yang } else { 1555781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1556be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 155792b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1558781a868fSWei Yang 0, num_vfs, 0); 155992b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1560781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1561781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1562be283eebSWei Yang kfree(pdn->pe_num_map); 1563781a868fSWei Yang return -EBUSY; 1564781a868fSWei Yang } 1565be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1566781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1567be283eebSWei Yang } 1568be283eebSWei Yang pdn->num_vfs = num_vfs; 1569781a868fSWei Yang 1570781a868fSWei Yang /* Assign M64 window accordingly */ 157102639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1572781a868fSWei Yang if (ret) { 1573781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1574781a868fSWei Yang goto m64_failed; 1575781a868fSWei Yang } 1576781a868fSWei Yang 1577781a868fSWei Yang /* 1578781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1579781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1580781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1581781a868fSWei Yang */ 1582ee8222feSWei Yang if (!pdn->m64_single_mode) { 1583be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1584781a868fSWei Yang if (ret) 1585781a868fSWei Yang goto m64_failed; 1586781a868fSWei Yang } 158702639b0eSWei Yang } 1588781a868fSWei Yang 1589781a868fSWei Yang /* Setup VF PEs */ 1590781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1591781a868fSWei Yang 1592781a868fSWei Yang return 0; 1593781a868fSWei Yang 1594781a868fSWei Yang m64_failed: 1595be283eebSWei Yang if (pdn->m64_single_mode) { 1596be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1597be283eebSWei Yang if (pdn->pe_num_map[i] != IODA_INVALID_PE) 1598be283eebSWei Yang pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); 1599be283eebSWei Yang } 1600be283eebSWei Yang } else 1601be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1602be283eebSWei Yang 1603be283eebSWei Yang /* Releasing pe_num_map */ 1604be283eebSWei Yang kfree(pdn->pe_num_map); 1605781a868fSWei Yang 1606781a868fSWei Yang return ret; 1607781a868fSWei Yang } 1608781a868fSWei Yang 1609a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1610a8b2f828SGavin Shan { 1611781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1612781a868fSWei Yang 1613a8b2f828SGavin Shan /* Release PCI data */ 1614a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1615a8b2f828SGavin Shan return 0; 1616a8b2f828SGavin Shan } 1617a8b2f828SGavin Shan 1618a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1619a8b2f828SGavin Shan { 1620a8b2f828SGavin Shan /* Allocate PCI data */ 1621a8b2f828SGavin Shan add_dev_pci_data(pdev); 1622781a868fSWei Yang 1623ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1624a8b2f828SGavin Shan } 1625a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1626a8b2f828SGavin Shan 1627959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1628184cd4a3SBenjamin Herrenschmidt { 1629b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1630959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1631184cd4a3SBenjamin Herrenschmidt 1632959c9bddSGavin Shan /* 1633959c9bddSGavin Shan * The function can be called while the PE# 1634959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1635959c9bddSGavin Shan * case. 1636959c9bddSGavin Shan */ 1637959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1638959c9bddSGavin Shan return; 1639184cd4a3SBenjamin Herrenschmidt 1640959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1641cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 16420e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1643b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 16444617082eSAlexey Kardashevskiy /* 16454617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 16464617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 16474617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 16484617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 16494617082eSAlexey Kardashevskiy */ 1650184cd4a3SBenjamin Herrenschmidt } 1651184cd4a3SBenjamin Herrenschmidt 1652763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1653cd15b048SBenjamin Herrenschmidt { 1654763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1655763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1656cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1657cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1658cd15b048SBenjamin Herrenschmidt uint64_t top; 1659cd15b048SBenjamin Herrenschmidt bool bypass = false; 16605d2aa710SAlistair Popple struct pci_dev *linked_npu_dev; 16615d2aa710SAlistair Popple int i; 1662cd15b048SBenjamin Herrenschmidt 1663cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1664cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1665cd15b048SBenjamin Herrenschmidt 1666cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1667cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1668cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1669cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1670cd15b048SBenjamin Herrenschmidt } 1671cd15b048SBenjamin Herrenschmidt 1672cd15b048SBenjamin Herrenschmidt if (bypass) { 1673cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1674cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1675cd15b048SBenjamin Herrenschmidt } else { 1676cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1677cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1678cd15b048SBenjamin Herrenschmidt } 1679a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 16805d2aa710SAlistair Popple 16815d2aa710SAlistair Popple /* Update peer npu devices */ 16825d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 1683419dbd5eSAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 1684419dbd5eSAlistair Popple if (!pe->peers[i]) 1685419dbd5eSAlistair Popple continue; 1686419dbd5eSAlistair Popple 16875d2aa710SAlistair Popple linked_npu_dev = pe->peers[i]->pdev; 16885d2aa710SAlistair Popple if (dma_get_mask(&linked_npu_dev->dev) != dma_mask) 16895d2aa710SAlistair Popple dma_set_mask(&linked_npu_dev->dev, dma_mask); 16905d2aa710SAlistair Popple } 16915d2aa710SAlistair Popple 1692cd15b048SBenjamin Herrenschmidt return 0; 1693cd15b048SBenjamin Herrenschmidt } 1694cd15b048SBenjamin Herrenschmidt 169553522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1696fe7e85c6SGavin Shan { 169753522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 169853522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1699fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1700fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1701fe7e85c6SGavin Shan u64 end, mask; 1702fe7e85c6SGavin Shan 1703fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1704fe7e85c6SGavin Shan return 0; 1705fe7e85c6SGavin Shan 1706fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1707fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1708fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1709fe7e85c6SGavin Shan 1710fe7e85c6SGavin Shan 1711fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1712fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1713fe7e85c6SGavin Shan mask += mask - 1; 1714fe7e85c6SGavin Shan 1715fe7e85c6SGavin Shan return mask; 1716fe7e85c6SGavin Shan } 1717fe7e85c6SGavin Shan 1718dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1719ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 172074251fe2SBenjamin Herrenschmidt { 172174251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 172274251fe2SBenjamin Herrenschmidt 172374251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1724b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1725e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 17264617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1727dff4a39eSGavin Shan 17285c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1729ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 173074251fe2SBenjamin Herrenschmidt } 173174251fe2SBenjamin Herrenschmidt } 173274251fe2SBenjamin Herrenschmidt 1733decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1734decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 17354cce9550SGavin Shan { 17360eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 17370eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 17380eaf4defSAlexey Kardashevskiy next); 17390eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1740b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 17413ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 17425780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 17435780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 17444cce9550SGavin Shan unsigned long start, end, inc; 1745b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 17464cce9550SGavin Shan 1747decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1748decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1749decbda25SAlexey Kardashevskiy npages - 1); 17504cce9550SGavin Shan 17514cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 17524cce9550SGavin Shan if (tbl->it_busno) { 1753b0376c9bSAlexey Kardashevskiy start <<= shift; 1754b0376c9bSAlexey Kardashevskiy end <<= shift; 1755b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 17564cce9550SGavin Shan start |= tbl->it_busno; 17574cce9550SGavin Shan end |= tbl->it_busno; 17584cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 17594cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 17604cce9550SGavin Shan start |= (1ull << 63); 17614cce9550SGavin Shan end |= (1ull << 63); 17624cce9550SGavin Shan inc = 16; 17634cce9550SGavin Shan } else { 17644cce9550SGavin Shan /* Default (older HW) */ 17654cce9550SGavin Shan inc = 128; 17664cce9550SGavin Shan } 17674cce9550SGavin Shan 17684cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17694cce9550SGavin Shan 17704cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17714cce9550SGavin Shan while (start <= end) { 17728e0a1611SAlexey Kardashevskiy if (rm) 17733ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17748e0a1611SAlexey Kardashevskiy else 17753a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17764cce9550SGavin Shan start += inc; 17774cce9550SGavin Shan } 17784cce9550SGavin Shan 17794cce9550SGavin Shan /* 17804cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 17814cce9550SGavin Shan * and we don't care on free() 17824cce9550SGavin Shan */ 17834cce9550SGavin Shan } 17844cce9550SGavin Shan 1785decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1786decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1787decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1788decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1789decbda25SAlexey Kardashevskiy { 1790decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1791decbda25SAlexey Kardashevskiy attrs); 1792decbda25SAlexey Kardashevskiy 1793decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1794decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1795decbda25SAlexey Kardashevskiy 1796decbda25SAlexey Kardashevskiy return ret; 1797decbda25SAlexey Kardashevskiy } 1798decbda25SAlexey Kardashevskiy 179905c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 180005c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 180105c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 180205c6cfb9SAlexey Kardashevskiy { 180305c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 180405c6cfb9SAlexey Kardashevskiy 180505c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 180605c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 180705c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 180805c6cfb9SAlexey Kardashevskiy 180905c6cfb9SAlexey Kardashevskiy return ret; 181005c6cfb9SAlexey Kardashevskiy } 181105c6cfb9SAlexey Kardashevskiy #endif 181205c6cfb9SAlexey Kardashevskiy 1813decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1814decbda25SAlexey Kardashevskiy long npages) 1815decbda25SAlexey Kardashevskiy { 1816decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1817decbda25SAlexey Kardashevskiy 1818decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1819decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1820decbda25SAlexey Kardashevskiy } 1821decbda25SAlexey Kardashevskiy 1822da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1823decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 182405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 182505c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 182605c6cfb9SAlexey Kardashevskiy #endif 1827decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1828da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1829da004c36SAlexey Kardashevskiy }; 1830da004c36SAlexey Kardashevskiy 18315780fb04SAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 18325780fb04SAlexey Kardashevskiy { 18335780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 18345780fb04SAlexey Kardashevskiy unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 18355780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 18365d2aa710SAlistair Popple struct pnv_ioda_pe *npe; 18375d2aa710SAlistair Popple int i; 18385780fb04SAlexey Kardashevskiy 18395780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 18405780fb04SAlexey Kardashevskiy return; 18415780fb04SAlexey Kardashevskiy 18425780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 18435780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 18445d2aa710SAlistair Popple 18455d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 18465d2aa710SAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 18475d2aa710SAlistair Popple npe = pe->peers[i]; 18485d2aa710SAlistair Popple if (!npe || npe->phb->type != PNV_PHB_NPU) 18495d2aa710SAlistair Popple continue; 18505d2aa710SAlistair Popple 18515d2aa710SAlistair Popple pnv_npu_tce_invalidate_entire(npe); 18525d2aa710SAlistair Popple } 18535780fb04SAlexey Kardashevskiy } 18545780fb04SAlexey Kardashevskiy 1855e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1856e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1857e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 18584cce9550SGavin Shan { 18594cce9550SGavin Shan unsigned long start, end, inc; 18604cce9550SGavin Shan 18614cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1862b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 1863e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 18644cce9550SGavin Shan end = start; 18654cce9550SGavin Shan 18664cce9550SGavin Shan /* Figure out the start, end and step */ 1867decbda25SAlexey Kardashevskiy start |= (index << shift); 1868decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1869b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 18704cce9550SGavin Shan mb(); 18714cce9550SGavin Shan 18724cce9550SGavin Shan while (start <= end) { 18738e0a1611SAlexey Kardashevskiy if (rm) 18743ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18758e0a1611SAlexey Kardashevskiy else 18763a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18774cce9550SGavin Shan start += inc; 18784cce9550SGavin Shan } 18794cce9550SGavin Shan } 18804cce9550SGavin Shan 1881e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1882e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1883e57080f1SAlexey Kardashevskiy { 1884e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1885e57080f1SAlexey Kardashevskiy 1886e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 18875d2aa710SAlistair Popple struct pnv_ioda_pe *npe; 1888e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1889e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1890e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1891e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1892e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 18935d2aa710SAlistair Popple int i; 1894e57080f1SAlexey Kardashevskiy 1895e57080f1SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1896e57080f1SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 1897e57080f1SAlexey Kardashevskiy index, npages); 18985d2aa710SAlistair Popple 18995d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 19005d2aa710SAlistair Popple /* Invalidate PEs using the same TCE table */ 19015d2aa710SAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 19025d2aa710SAlistair Popple npe = pe->peers[i]; 19035d2aa710SAlistair Popple if (!npe || npe->phb->type != PNV_PHB_NPU) 19045d2aa710SAlistair Popple continue; 19055d2aa710SAlistair Popple 19065d2aa710SAlistair Popple pnv_npu_tce_invalidate(npe, tbl, index, 19075d2aa710SAlistair Popple npages, rm); 19085d2aa710SAlistair Popple } 1909e57080f1SAlexey Kardashevskiy } 1910e57080f1SAlexey Kardashevskiy } 1911e57080f1SAlexey Kardashevskiy 1912decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1913decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1914decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1915decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 19164cce9550SGavin Shan { 1917decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1918decbda25SAlexey Kardashevskiy attrs); 19194cce9550SGavin Shan 1920decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1921decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1922decbda25SAlexey Kardashevskiy 1923decbda25SAlexey Kardashevskiy return ret; 1924decbda25SAlexey Kardashevskiy } 1925decbda25SAlexey Kardashevskiy 192605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 192705c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 192805c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 192905c6cfb9SAlexey Kardashevskiy { 193005c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 193105c6cfb9SAlexey Kardashevskiy 193205c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 193305c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 193405c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 193505c6cfb9SAlexey Kardashevskiy 193605c6cfb9SAlexey Kardashevskiy return ret; 193705c6cfb9SAlexey Kardashevskiy } 193805c6cfb9SAlexey Kardashevskiy #endif 193905c6cfb9SAlexey Kardashevskiy 1940decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1941decbda25SAlexey Kardashevskiy long npages) 1942decbda25SAlexey Kardashevskiy { 1943decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1944decbda25SAlexey Kardashevskiy 1945decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1946decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 19474cce9550SGavin Shan } 19484cce9550SGavin Shan 19494793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 19504793d65dSAlexey Kardashevskiy { 19514793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 19524793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19534793d65dSAlexey Kardashevskiy } 19544793d65dSAlexey Kardashevskiy 1955da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1956decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 195705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 195805c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 195905c6cfb9SAlexey Kardashevskiy #endif 1960decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1961da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 19624793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 1963da004c36SAlexey Kardashevskiy }; 1964da004c36SAlexey Kardashevskiy 1965801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1966801846d1SGavin Shan { 1967801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1968801846d1SGavin Shan 1969801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1970801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1971801846d1SGavin Shan */ 1972801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1973801846d1SGavin Shan return 0; 1974801846d1SGavin Shan 1975801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1976801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1977801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1978801846d1SGavin Shan *weight += 3; 1979801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1980801846d1SGavin Shan *weight += 15; 1981801846d1SGavin Shan else 1982801846d1SGavin Shan *weight += 10; 1983801846d1SGavin Shan 1984801846d1SGavin Shan return 0; 1985801846d1SGavin Shan } 1986801846d1SGavin Shan 1987801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1988801846d1SGavin Shan { 1989801846d1SGavin Shan unsigned int weight = 0; 1990801846d1SGavin Shan 1991801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 1992801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 1993801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1994801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1995801846d1SGavin Shan return weight; 1996801846d1SGavin Shan } 1997801846d1SGavin Shan #endif 1998801846d1SGavin Shan 1999801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2000801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2001801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2002801846d1SGavin Shan struct pci_dev *pdev; 2003801846d1SGavin Shan 2004801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2005801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2006801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2007801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2008801846d1SGavin Shan } 2009801846d1SGavin Shan 2010801846d1SGavin Shan return weight; 2011801846d1SGavin Shan } 2012801846d1SGavin Shan 2013b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 20142b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2015184cd4a3SBenjamin Herrenschmidt { 2016184cd4a3SBenjamin Herrenschmidt 2017184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2018184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 20192b923ed1SGavin Shan unsigned int weight, total_weight = 0; 20202b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2021184cd4a3SBenjamin Herrenschmidt int64_t rc; 2022184cd4a3SBenjamin Herrenschmidt void *addr; 2023184cd4a3SBenjamin Herrenschmidt 2024184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2025184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2026184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 20272b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 20282b923ed1SGavin Shan if (!weight) 20292b923ed1SGavin Shan return; 2030184cd4a3SBenjamin Herrenschmidt 20312b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 20322b923ed1SGavin Shan &total_weight); 20332b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 20342b923ed1SGavin Shan if (!segs) 20352b923ed1SGavin Shan segs = 1; 20362b923ed1SGavin Shan 20372b923ed1SGavin Shan /* 20382b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 20392b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 20402b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 20412b923ed1SGavin Shan * is allocated successfully. 20422b923ed1SGavin Shan */ 20432b923ed1SGavin Shan do { 20442b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 20452b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 20462b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 20472b923ed1SGavin Shan IODA_INVALID_PE) 20482b923ed1SGavin Shan avail++; 20492b923ed1SGavin Shan } 20502b923ed1SGavin Shan 20512b923ed1SGavin Shan if (avail == segs) 20522b923ed1SGavin Shan goto found; 20532b923ed1SGavin Shan } 20542b923ed1SGavin Shan } while (--segs); 20552b923ed1SGavin Shan 20562b923ed1SGavin Shan if (!segs) { 20572b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 20582b923ed1SGavin Shan return; 20592b923ed1SGavin Shan } 20602b923ed1SGavin Shan 20612b923ed1SGavin Shan found: 20620eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 2063b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2064b348aa65SAlexey Kardashevskiy pe->pe_number); 20650eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2066c5773822SAlexey Kardashevskiy 2067184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 20682b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 20692b923ed1SGavin Shan weight, total_weight, base, segs); 2070184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2071acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2072acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2073184cd4a3SBenjamin Herrenschmidt 2074184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2075184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2076184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2077184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2078acce971cSGavin Shan * 2079acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2080acce971cSGavin Shan * bytes 2081184cd4a3SBenjamin Herrenschmidt */ 2082acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2083184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2084acce971cSGavin Shan get_order(tce32_segsz * segs)); 2085184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2086184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2087184cd4a3SBenjamin Herrenschmidt goto fail; 2088184cd4a3SBenjamin Herrenschmidt } 2089184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2090acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2091184cd4a3SBenjamin Herrenschmidt 2092184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2093184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2094184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2095184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2096184cd4a3SBenjamin Herrenschmidt base + i, 1, 2097acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2098acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2099184cd4a3SBenjamin Herrenschmidt if (rc) { 2100184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2101184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2102184cd4a3SBenjamin Herrenschmidt goto fail; 2103184cd4a3SBenjamin Herrenschmidt } 2104184cd4a3SBenjamin Herrenschmidt } 2105184cd4a3SBenjamin Herrenschmidt 21062b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 21072b923ed1SGavin Shan for (i = base; i < base + segs; i++) 21082b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 21092b923ed1SGavin Shan 2110184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2111acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2112acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2113acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2114184cd4a3SBenjamin Herrenschmidt 2115184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 21165780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 211765fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 211865fd766bSGavin Shan TCE_PCI_SWINV_FREE | 211965fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 21205780fb04SAlexey Kardashevskiy 2121da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 21224793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 21234793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2124184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2125184cd4a3SBenjamin Herrenschmidt 2126781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 21274617082eSAlexey Kardashevskiy /* 21284617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 21294617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 21304617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 21314617082eSAlexey Kardashevskiy */ 21324617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 21334617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2134c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2135ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 213674251fe2SBenjamin Herrenschmidt 2137184cd4a3SBenjamin Herrenschmidt return; 2138184cd4a3SBenjamin Herrenschmidt fail: 2139184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2140184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2141acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 21420eaf4defSAlexey Kardashevskiy if (tbl) { 21430eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 21440eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 21450eaf4defSAlexey Kardashevskiy } 2146184cd4a3SBenjamin Herrenschmidt } 2147184cd4a3SBenjamin Herrenschmidt 214843cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 214943cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 215043cb60abSAlexey Kardashevskiy { 215143cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 215243cb60abSAlexey Kardashevskiy table_group); 215343cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 215443cb60abSAlexey Kardashevskiy int64_t rc; 2155bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2156bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 215743cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 215843cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 215943cb60abSAlexey Kardashevskiy 21604793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 216143cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 216243cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 216343cb60abSAlexey Kardashevskiy 216443cb60abSAlexey Kardashevskiy /* 216543cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 216643cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 216743cb60abSAlexey Kardashevskiy */ 216843cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 216943cb60abSAlexey Kardashevskiy pe->pe_number, 21704793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2171bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 217243cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2173bbb845c4SAlexey Kardashevskiy size << 3, 217443cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 217543cb60abSAlexey Kardashevskiy if (rc) { 217643cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 217743cb60abSAlexey Kardashevskiy return rc; 217843cb60abSAlexey Kardashevskiy } 217943cb60abSAlexey Kardashevskiy 218043cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 218143cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 218243cb60abSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 218343cb60abSAlexey Kardashevskiy 218443cb60abSAlexey Kardashevskiy return 0; 218543cb60abSAlexey Kardashevskiy } 218643cb60abSAlexey Kardashevskiy 2187f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2188cd15b048SBenjamin Herrenschmidt { 2189cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2190cd15b048SBenjamin Herrenschmidt int64_t rc; 2191cd15b048SBenjamin Herrenschmidt 2192cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2193cd15b048SBenjamin Herrenschmidt if (enable) { 2194cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2195cd15b048SBenjamin Herrenschmidt 2196cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2197cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2198cd15b048SBenjamin Herrenschmidt pe->pe_number, 2199cd15b048SBenjamin Herrenschmidt window_id, 2200cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2201cd15b048SBenjamin Herrenschmidt top); 2202cd15b048SBenjamin Herrenschmidt } else { 2203cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2204cd15b048SBenjamin Herrenschmidt pe->pe_number, 2205cd15b048SBenjamin Herrenschmidt window_id, 2206cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2207cd15b048SBenjamin Herrenschmidt 0); 2208cd15b048SBenjamin Herrenschmidt } 2209cd15b048SBenjamin Herrenschmidt if (rc) 2210cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2211cd15b048SBenjamin Herrenschmidt else 2212cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2213cd15b048SBenjamin Herrenschmidt } 2214cd15b048SBenjamin Herrenschmidt 22154793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 22164793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 22174793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 22184793d65dSAlexey Kardashevskiy 22194793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 22204793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 22214793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 22224793d65dSAlexey Kardashevskiy { 22234793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 22244793d65dSAlexey Kardashevskiy table_group); 22254793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 22264793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 22274793d65dSAlexey Kardashevskiy long ret; 22284793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 22294793d65dSAlexey Kardashevskiy 22304793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 22314793d65dSAlexey Kardashevskiy if (!tbl) 22324793d65dSAlexey Kardashevskiy return -ENOMEM; 22334793d65dSAlexey Kardashevskiy 22344793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 22354793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 22364793d65dSAlexey Kardashevskiy levels, tbl); 22374793d65dSAlexey Kardashevskiy if (ret) { 22384793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 22394793d65dSAlexey Kardashevskiy return ret; 22404793d65dSAlexey Kardashevskiy } 22414793d65dSAlexey Kardashevskiy 22424793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 22434793d65dSAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 22444793d65dSAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 22454793d65dSAlexey Kardashevskiy 22464793d65dSAlexey Kardashevskiy *ptbl = tbl; 22474793d65dSAlexey Kardashevskiy 22484793d65dSAlexey Kardashevskiy return 0; 22494793d65dSAlexey Kardashevskiy } 22504793d65dSAlexey Kardashevskiy 225146d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 225246d3e1e1SAlexey Kardashevskiy { 225346d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 225446d3e1e1SAlexey Kardashevskiy long rc; 225546d3e1e1SAlexey Kardashevskiy 2256bb005455SNishanth Aravamudan /* 2257fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2258fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2259fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2260fa144869SNishanth Aravamudan */ 2261fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2262fa144869SNishanth Aravamudan 2263fa144869SNishanth Aravamudan /* 2264bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2265bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2266bb005455SNishanth Aravamudan * cause errors later. 2267bb005455SNishanth Aravamudan */ 2268fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2269bb005455SNishanth Aravamudan 227046d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 227146d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2272bb005455SNishanth Aravamudan window_size, 227346d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 227446d3e1e1SAlexey Kardashevskiy if (rc) { 227546d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 227646d3e1e1SAlexey Kardashevskiy rc); 227746d3e1e1SAlexey Kardashevskiy return rc; 227846d3e1e1SAlexey Kardashevskiy } 227946d3e1e1SAlexey Kardashevskiy 228046d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 228146d3e1e1SAlexey Kardashevskiy 228246d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 228346d3e1e1SAlexey Kardashevskiy if (rc) { 228446d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 228546d3e1e1SAlexey Kardashevskiy rc); 228646d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 228746d3e1e1SAlexey Kardashevskiy return rc; 228846d3e1e1SAlexey Kardashevskiy } 228946d3e1e1SAlexey Kardashevskiy 229046d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 229146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 229246d3e1e1SAlexey Kardashevskiy 229346d3e1e1SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 229446d3e1e1SAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 229546d3e1e1SAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 229646d3e1e1SAlexey Kardashevskiy 229746d3e1e1SAlexey Kardashevskiy /* 229846d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 229946d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 230046d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 230146d3e1e1SAlexey Kardashevskiy */ 230246d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 230346d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 230446d3e1e1SAlexey Kardashevskiy 230546d3e1e1SAlexey Kardashevskiy return 0; 230646d3e1e1SAlexey Kardashevskiy } 230746d3e1e1SAlexey Kardashevskiy 2308b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2309b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2310b5926430SAlexey Kardashevskiy int num) 2311b5926430SAlexey Kardashevskiy { 2312b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2313b5926430SAlexey Kardashevskiy table_group); 2314b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2315b5926430SAlexey Kardashevskiy long ret; 2316b5926430SAlexey Kardashevskiy 2317b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2318b5926430SAlexey Kardashevskiy 2319b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2320b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2321b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2322b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2323b5926430SAlexey Kardashevskiy if (ret) 2324b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2325b5926430SAlexey Kardashevskiy else 2326b5926430SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 2327b5926430SAlexey Kardashevskiy 2328b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2329b5926430SAlexey Kardashevskiy 2330b5926430SAlexey Kardashevskiy return ret; 2331b5926430SAlexey Kardashevskiy } 2332b5926430SAlexey Kardashevskiy #endif 2333b5926430SAlexey Kardashevskiy 2334f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 233500547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 233600547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 233700547193SAlexey Kardashevskiy { 233800547193SAlexey Kardashevskiy unsigned long bytes = 0; 233900547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 234000547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 234100547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 234200547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 234300547193SAlexey Kardashevskiy unsigned long direct_table_size; 234400547193SAlexey Kardashevskiy 234500547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 234600547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 234700547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 234800547193SAlexey Kardashevskiy return 0; 234900547193SAlexey Kardashevskiy 235000547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 235100547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 235200547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 235300547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 235400547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 235500547193SAlexey Kardashevskiy 235600547193SAlexey Kardashevskiy for ( ; levels; --levels) { 235700547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 235800547193SAlexey Kardashevskiy 235900547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 236000547193SAlexey Kardashevskiy tce_table_size <<= 3; 236100547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 236200547193SAlexey Kardashevskiy } 236300547193SAlexey Kardashevskiy 236400547193SAlexey Kardashevskiy return bytes; 236500547193SAlexey Kardashevskiy } 236600547193SAlexey Kardashevskiy 2367f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2368cd15b048SBenjamin Herrenschmidt { 2369f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2370f87a8864SAlexey Kardashevskiy table_group); 237146d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 237246d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2373cd15b048SBenjamin Herrenschmidt 2374f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 237546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 237646d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2377cd15b048SBenjamin Herrenschmidt } 2378cd15b048SBenjamin Herrenschmidt 2379f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2380f87a8864SAlexey Kardashevskiy { 2381f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2382f87a8864SAlexey Kardashevskiy table_group); 2383f87a8864SAlexey Kardashevskiy 238446d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2385f87a8864SAlexey Kardashevskiy } 2386f87a8864SAlexey Kardashevskiy 2387f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 238800547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 23894793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 23904793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 23914793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2392f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2393f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2394f87a8864SAlexey Kardashevskiy }; 2395f87a8864SAlexey Kardashevskiy #endif 2396f87a8864SAlexey Kardashevskiy 23975780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 23985780fb04SAlexey Kardashevskiy { 23995780fb04SAlexey Kardashevskiy const __be64 *swinvp; 24005780fb04SAlexey Kardashevskiy 24015780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 24025780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 24035780fb04SAlexey Kardashevskiy if (!swinvp) 24045780fb04SAlexey Kardashevskiy return; 24055780fb04SAlexey Kardashevskiy 24065780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 24075780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 24085780fb04SAlexey Kardashevskiy } 24095780fb04SAlexey Kardashevskiy 2410bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2411bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 24123ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2413aca6913fSAlexey Kardashevskiy { 2414aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2415bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2416aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2417bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2418bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2419bbb845c4SAlexey Kardashevskiy long i; 2420aca6913fSAlexey Kardashevskiy 2421aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2422aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2423aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2424aca6913fSAlexey Kardashevskiy return NULL; 2425aca6913fSAlexey Kardashevskiy } 2426aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2427bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 24283ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2429bbb845c4SAlexey Kardashevskiy 2430bbb845c4SAlexey Kardashevskiy --levels; 2431bbb845c4SAlexey Kardashevskiy if (!levels) { 2432bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2433bbb845c4SAlexey Kardashevskiy return addr; 2434bbb845c4SAlexey Kardashevskiy } 2435bbb845c4SAlexey Kardashevskiy 2436bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2437bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 24383ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2439bbb845c4SAlexey Kardashevskiy if (!tmp) 2440bbb845c4SAlexey Kardashevskiy break; 2441bbb845c4SAlexey Kardashevskiy 2442bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2443bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2444bbb845c4SAlexey Kardashevskiy 2445bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2446bbb845c4SAlexey Kardashevskiy break; 2447bbb845c4SAlexey Kardashevskiy } 2448aca6913fSAlexey Kardashevskiy 2449aca6913fSAlexey Kardashevskiy return addr; 2450aca6913fSAlexey Kardashevskiy } 2451aca6913fSAlexey Kardashevskiy 2452bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2453bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2454bbb845c4SAlexey Kardashevskiy 2455aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2456bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2457bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2458aca6913fSAlexey Kardashevskiy { 2459aca6913fSAlexey Kardashevskiy void *addr; 24603ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2461aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2462aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2463aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2464aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2465aca6913fSAlexey Kardashevskiy 2466bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2467bbb845c4SAlexey Kardashevskiy return -EINVAL; 2468bbb845c4SAlexey Kardashevskiy 2469aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2470aca6913fSAlexey Kardashevskiy return -EINVAL; 2471aca6913fSAlexey Kardashevskiy 2472bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2473bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2474bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2475bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2476bbb845c4SAlexey Kardashevskiy 2477aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2478bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 24793ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2480bbb845c4SAlexey Kardashevskiy 2481bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2482aca6913fSAlexey Kardashevskiy if (!addr) 2483aca6913fSAlexey Kardashevskiy return -ENOMEM; 2484aca6913fSAlexey Kardashevskiy 2485bbb845c4SAlexey Kardashevskiy /* 2486bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2487bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2488bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2489bbb845c4SAlexey Kardashevskiy */ 2490bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2491bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2492bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2493bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2494bbb845c4SAlexey Kardashevskiy } 2495bbb845c4SAlexey Kardashevskiy 2496aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2497aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2498aca6913fSAlexey Kardashevskiy page_shift); 2499bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2500bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 25013ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2502aca6913fSAlexey Kardashevskiy 2503aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2504aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2505aca6913fSAlexey Kardashevskiy 2506aca6913fSAlexey Kardashevskiy return 0; 2507aca6913fSAlexey Kardashevskiy } 2508aca6913fSAlexey Kardashevskiy 2509bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2510bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2511bbb845c4SAlexey Kardashevskiy { 2512bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2513bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2514bbb845c4SAlexey Kardashevskiy 2515bbb845c4SAlexey Kardashevskiy if (level) { 2516bbb845c4SAlexey Kardashevskiy long i; 2517bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2518bbb845c4SAlexey Kardashevskiy 2519bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2520bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2521bbb845c4SAlexey Kardashevskiy 2522bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2523bbb845c4SAlexey Kardashevskiy continue; 2524bbb845c4SAlexey Kardashevskiy 2525bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2526bbb845c4SAlexey Kardashevskiy level - 1); 2527bbb845c4SAlexey Kardashevskiy } 2528bbb845c4SAlexey Kardashevskiy } 2529bbb845c4SAlexey Kardashevskiy 2530bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2531bbb845c4SAlexey Kardashevskiy } 2532bbb845c4SAlexey Kardashevskiy 2533aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2534aca6913fSAlexey Kardashevskiy { 2535bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2536bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2537bbb845c4SAlexey Kardashevskiy 2538aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2539aca6913fSAlexey Kardashevskiy return; 2540aca6913fSAlexey Kardashevskiy 2541bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2542bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2543aca6913fSAlexey Kardashevskiy } 2544aca6913fSAlexey Kardashevskiy 2545373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2546373f5657SGavin Shan struct pnv_ioda_pe *pe) 2547373f5657SGavin Shan { 2548373f5657SGavin Shan int64_t rc; 2549373f5657SGavin Shan 2550f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2551f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2552f87a8864SAlexey Kardashevskiy 2553b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2554b348aa65SAlexey Kardashevskiy pe->pe_number); 2555c5773822SAlexey Kardashevskiy 2556373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2557373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2558aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2559373f5657SGavin Shan 2560e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 25614793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 25624793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 25634793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 25644793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 25654793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 25664793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2567e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2568e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2569e5aad1e6SAlexey Kardashevskiy #endif 2570e5aad1e6SAlexey Kardashevskiy 257146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2572801846d1SGavin Shan if (rc) 257346d3e1e1SAlexey Kardashevskiy return; 257446d3e1e1SAlexey Kardashevskiy 257546d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 257646d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 257746d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 257846d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2579373f5657SGavin Shan } 2580373f5657SGavin Shan 2581cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2582184cd4a3SBenjamin Herrenschmidt { 2583184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 2584184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 25852b923ed1SGavin Shan unsigned int weight; 2586801846d1SGavin Shan 2587184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 2588184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 2589184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 2590184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 2591184cd4a3SBenjamin Herrenschmidt */ 25922b923ed1SGavin Shan pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n", 25932b923ed1SGavin Shan hose->global_number, phb->ioda.dma32_count); 2594184cd4a3SBenjamin Herrenschmidt 25955780fb04SAlexey Kardashevskiy pnv_pci_ioda_setup_opal_tce_kill(phb); 25965780fb04SAlexey Kardashevskiy 25972b923ed1SGavin Shan /* Walk our PE list and configure their DMA segments */ 2598801846d1SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2599801846d1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 2600801846d1SGavin Shan if (!weight) 2601184cd4a3SBenjamin Herrenschmidt continue; 2602801846d1SGavin Shan 2603373f5657SGavin Shan /* 2604373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 2605373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 2606373f5657SGavin Shan * the specific PE. 2607373f5657SGavin Shan */ 2608373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 26092b923ed1SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 26105d2aa710SAlistair Popple } else if (phb->type == PNV_PHB_IODA2) { 2611373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 2612373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 26135d2aa710SAlistair Popple } else if (phb->type == PNV_PHB_NPU) { 26145d2aa710SAlistair Popple /* 26155d2aa710SAlistair Popple * We initialise the DMA space for an NPU PHB 26165d2aa710SAlistair Popple * after setup of the PHB is complete as we 26175d2aa710SAlistair Popple * point the NPU TVT to the the same location 26185d2aa710SAlistair Popple * as the PHB3 TVT. 26195d2aa710SAlistair Popple */ 2620373f5657SGavin Shan } 2621184cd4a3SBenjamin Herrenschmidt } 2622184cd4a3SBenjamin Herrenschmidt } 2623184cd4a3SBenjamin Herrenschmidt 2624184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2625137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2626137436c9SGavin Shan { 2627137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2628137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2629137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2630137436c9SGavin Shan ioda.irq_chip); 2631137436c9SGavin Shan int64_t rc; 2632137436c9SGavin Shan 2633137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2634137436c9SGavin Shan WARN_ON_ONCE(rc); 2635137436c9SGavin Shan 2636137436c9SGavin Shan icp_native_eoi(d); 2637137436c9SGavin Shan } 2638137436c9SGavin Shan 2639fd9a1c26SIan Munsie 2640fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2641fd9a1c26SIan Munsie { 2642fd9a1c26SIan Munsie struct irq_data *idata; 2643fd9a1c26SIan Munsie struct irq_chip *ichip; 2644fd9a1c26SIan Munsie 2645fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2646fd9a1c26SIan Munsie return; 2647fd9a1c26SIan Munsie 2648fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2649fd9a1c26SIan Munsie /* 2650fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2651fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2652fd9a1c26SIan Munsie */ 2653fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2654fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2655fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2656fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2657fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2658fd9a1c26SIan Munsie } 2659fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2660fd9a1c26SIan Munsie } 2661fd9a1c26SIan Munsie 266280c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 266380c49c7eSIan Munsie 26646f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 266580c49c7eSIan Munsie { 266680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 266780c49c7eSIan Munsie 26686f963ec2SRyan Grimm return of_node_get(hose->dn); 266980c49c7eSIan Munsie } 26706f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 267180c49c7eSIan Munsie 26721212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 267380c49c7eSIan Munsie { 267480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 267580c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 267680c49c7eSIan Munsie struct pnv_ioda_pe *pe; 267780c49c7eSIan Munsie int rc; 267880c49c7eSIan Munsie 267980c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 268080c49c7eSIan Munsie if (!pe) 268180c49c7eSIan Munsie return -ENODEV; 268280c49c7eSIan Munsie 268380c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 268480c49c7eSIan Munsie 26851212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 268680c49c7eSIan Munsie if (rc) 268780c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 268880c49c7eSIan Munsie 268980c49c7eSIan Munsie return rc; 269080c49c7eSIan Munsie } 26911212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 269280c49c7eSIan Munsie 269380c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 269480c49c7eSIan Munsie * Returns the absolute hardware IRQ number 269580c49c7eSIan Munsie */ 269680c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 269780c49c7eSIan Munsie { 269880c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 269980c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 270080c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 270180c49c7eSIan Munsie 270280c49c7eSIan Munsie if (hwirq < 0) { 270380c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 270480c49c7eSIan Munsie return -ENOSPC; 270580c49c7eSIan Munsie } 270680c49c7eSIan Munsie 270780c49c7eSIan Munsie return phb->msi_base + hwirq; 270880c49c7eSIan Munsie } 270980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 271080c49c7eSIan Munsie 271180c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 271280c49c7eSIan Munsie { 271380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 271480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 271580c49c7eSIan Munsie 271680c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 271780c49c7eSIan Munsie } 271880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 271980c49c7eSIan Munsie 272080c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 272180c49c7eSIan Munsie struct pci_dev *dev) 272280c49c7eSIan Munsie { 272380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 272480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 272580c49c7eSIan Munsie int i, hwirq; 272680c49c7eSIan Munsie 272780c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 272880c49c7eSIan Munsie if (!irqs->range[i]) 272980c49c7eSIan Munsie continue; 273080c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 273180c49c7eSIan Munsie i, irqs->offset[i], 273280c49c7eSIan Munsie irqs->range[i]); 273380c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 273480c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 273580c49c7eSIan Munsie irqs->range[i]); 273680c49c7eSIan Munsie } 273780c49c7eSIan Munsie } 273880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 273980c49c7eSIan Munsie 274080c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 274180c49c7eSIan Munsie struct pci_dev *dev, int num) 274280c49c7eSIan Munsie { 274380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 274480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 274580c49c7eSIan Munsie int i, hwirq, try; 274680c49c7eSIan Munsie 274780c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 274880c49c7eSIan Munsie 274980c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 275080c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 275180c49c7eSIan Munsie try = num; 275280c49c7eSIan Munsie while (try) { 275380c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 275480c49c7eSIan Munsie if (hwirq >= 0) 275580c49c7eSIan Munsie break; 275680c49c7eSIan Munsie try /= 2; 275780c49c7eSIan Munsie } 275880c49c7eSIan Munsie if (!try) 275980c49c7eSIan Munsie goto fail; 276080c49c7eSIan Munsie 276180c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 276280c49c7eSIan Munsie irqs->range[i] = try; 276380c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 276480c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 276580c49c7eSIan Munsie num -= try; 276680c49c7eSIan Munsie } 276780c49c7eSIan Munsie if (num) 276880c49c7eSIan Munsie goto fail; 276980c49c7eSIan Munsie 277080c49c7eSIan Munsie return 0; 277180c49c7eSIan Munsie fail: 277280c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 277380c49c7eSIan Munsie return -ENOSPC; 277480c49c7eSIan Munsie } 277580c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 277680c49c7eSIan Munsie 277780c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 277880c49c7eSIan Munsie { 277980c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 278080c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 278180c49c7eSIan Munsie 278280c49c7eSIan Munsie return phb->msi_bmp.irq_count; 278380c49c7eSIan Munsie } 278480c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 278580c49c7eSIan Munsie 278680c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 278780c49c7eSIan Munsie unsigned int virq) 278880c49c7eSIan Munsie { 278980c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 279080c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 279180c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 279280c49c7eSIan Munsie struct pnv_ioda_pe *pe; 279380c49c7eSIan Munsie int rc; 279480c49c7eSIan Munsie 279580c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 279680c49c7eSIan Munsie return -ENODEV; 279780c49c7eSIan Munsie 279880c49c7eSIan Munsie /* Assign XIVE to PE */ 279980c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 280080c49c7eSIan Munsie if (rc) { 280180c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 280280c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 280380c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 280480c49c7eSIan Munsie return -EIO; 280580c49c7eSIan Munsie } 280680c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 280780c49c7eSIan Munsie 280880c49c7eSIan Munsie return 0; 280980c49c7eSIan Munsie } 281080c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 281180c49c7eSIan Munsie #endif 281280c49c7eSIan Munsie 2813184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2814137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2815137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2816184cd4a3SBenjamin Herrenschmidt { 2817184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2818184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 28193a1a4661SBenjamin Herrenschmidt __be32 data; 2820184cd4a3SBenjamin Herrenschmidt int rc; 2821184cd4a3SBenjamin Herrenschmidt 2822184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2823184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2824184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2825184cd4a3SBenjamin Herrenschmidt 2826184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2827184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2828184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2829184cd4a3SBenjamin Herrenschmidt 2830b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 283136074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2832b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2833b72c1f65SBenjamin Herrenschmidt 2834184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2835184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2836184cd4a3SBenjamin Herrenschmidt if (rc) { 2837184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2838184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2839184cd4a3SBenjamin Herrenschmidt return -EIO; 2840184cd4a3SBenjamin Herrenschmidt } 2841184cd4a3SBenjamin Herrenschmidt 2842184cd4a3SBenjamin Herrenschmidt if (is_64) { 28433a1a4661SBenjamin Herrenschmidt __be64 addr64; 28443a1a4661SBenjamin Herrenschmidt 2845184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2846184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2847184cd4a3SBenjamin Herrenschmidt if (rc) { 2848184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2849184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2850184cd4a3SBenjamin Herrenschmidt return -EIO; 2851184cd4a3SBenjamin Herrenschmidt } 28523a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28533a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2854184cd4a3SBenjamin Herrenschmidt } else { 28553a1a4661SBenjamin Herrenschmidt __be32 addr32; 28563a1a4661SBenjamin Herrenschmidt 2857184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2858184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2859184cd4a3SBenjamin Herrenschmidt if (rc) { 2860184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2861184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2862184cd4a3SBenjamin Herrenschmidt return -EIO; 2863184cd4a3SBenjamin Herrenschmidt } 2864184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28653a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2866184cd4a3SBenjamin Herrenschmidt } 28673a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2868184cd4a3SBenjamin Herrenschmidt 2869fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2870137436c9SGavin Shan 2871184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2872184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2873184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2874184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2875184cd4a3SBenjamin Herrenschmidt 2876184cd4a3SBenjamin Herrenschmidt return 0; 2877184cd4a3SBenjamin Herrenschmidt } 2878184cd4a3SBenjamin Herrenschmidt 2879184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2880184cd4a3SBenjamin Herrenschmidt { 2881fb1b55d6SGavin Shan unsigned int count; 2882184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2883184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2884184cd4a3SBenjamin Herrenschmidt if (!prop) { 2885184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2886184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2887184cd4a3SBenjamin Herrenschmidt } 2888184cd4a3SBenjamin Herrenschmidt if (!prop) 2889184cd4a3SBenjamin Herrenschmidt return; 2890184cd4a3SBenjamin Herrenschmidt 2891184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2892fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2893fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2894184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2895184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2896184cd4a3SBenjamin Herrenschmidt return; 2897184cd4a3SBenjamin Herrenschmidt } 2898fb1b55d6SGavin Shan 2899184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2900184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2901184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2902fb1b55d6SGavin Shan count, phb->msi_base); 2903184cd4a3SBenjamin Herrenschmidt } 2904184cd4a3SBenjamin Herrenschmidt #else 2905184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2906184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2907184cd4a3SBenjamin Herrenschmidt 29086e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29096e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29106e628c7dSWei Yang { 2911f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2912f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2913f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29146e628c7dSWei Yang struct resource *res; 29156e628c7dSWei Yang int i; 2916dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29176e628c7dSWei Yang struct pci_dn *pdn; 29185b88ec22SWei Yang int mul, total_vfs; 29196e628c7dSWei Yang 29206e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 29216e628c7dSWei Yang return; 29226e628c7dSWei Yang 29236e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29246e628c7dSWei Yang pdn->vfs_expanded = 0; 2925ee8222feSWei Yang pdn->m64_single_mode = false; 29266e628c7dSWei Yang 29275b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 292892b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2929dfcc8d45SWei Yang total_vf_bar_sz = 0; 29305b88ec22SWei Yang 29315b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29325b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29335b88ec22SWei Yang if (!res->flags || res->parent) 29345b88ec22SWei Yang continue; 29355b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 2936b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2937b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29385b88ec22SWei Yang i, res); 2939b0331854SWei Yang goto truncate_iov; 29405b88ec22SWei Yang } 29415b88ec22SWei Yang 2942dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2943dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29445b88ec22SWei Yang 2945f2dd0afeSWei Yang /* 2946f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2947f2dd0afeSWei Yang * power of two. 2948f2dd0afeSWei Yang * 2949f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2950f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2951f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2952f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2953f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2954f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2955f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2956f2dd0afeSWei Yang */ 2957dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29585b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2959dfcc8d45SWei Yang dev_info(&pdev->dev, 2960dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2961dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2962ee8222feSWei Yang pdn->m64_single_mode = true; 29635b88ec22SWei Yang break; 29645b88ec22SWei Yang } 29655b88ec22SWei Yang } 29665b88ec22SWei Yang 29676e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29686e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29696e628c7dSWei Yang if (!res->flags || res->parent) 29706e628c7dSWei Yang continue; 29716e628c7dSWei Yang 29726e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2973ee8222feSWei Yang /* 2974ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2975ee8222feSWei Yang * mode is 32MB. 2976ee8222feSWei Yang */ 2977ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2978ee8222feSWei Yang goto truncate_iov; 2979ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29805b88ec22SWei Yang res->end = res->start + size * mul - 1; 29816e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 29826e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 29835b88ec22SWei Yang i, res, mul); 29846e628c7dSWei Yang } 29855b88ec22SWei Yang pdn->vfs_expanded = mul; 2986b0331854SWei Yang 2987b0331854SWei Yang return; 2988b0331854SWei Yang 2989b0331854SWei Yang truncate_iov: 2990b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2991b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2992b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2993b0331854SWei Yang res->flags = 0; 2994b0331854SWei Yang res->end = res->start - 1; 2995b0331854SWei Yang } 29966e628c7dSWei Yang } 29976e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 29986e628c7dSWei Yang 299923e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 300023e79425SGavin Shan struct resource *res) 300111685becSGavin Shan { 300223e79425SGavin Shan struct pnv_phb *phb = pe->phb; 300311685becSGavin Shan struct pci_bus_region region; 300423e79425SGavin Shan int index; 300523e79425SGavin Shan int64_t rc; 300611685becSGavin Shan 300723e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 300823e79425SGavin Shan return; 300911685becSGavin Shan 301011685becSGavin Shan if (res->flags & IORESOURCE_IO) { 301111685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 301211685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 301311685becSGavin Shan index = region.start / phb->ioda.io_segsize; 301411685becSGavin Shan 301592b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 301611685becSGavin Shan region.start <= region.end) { 301711685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 301811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 301911685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 302011685becSGavin Shan if (rc != OPAL_SUCCESS) { 302123e79425SGavin Shan pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 302211685becSGavin Shan __func__, rc, index, pe->pe_number); 302311685becSGavin Shan break; 302411685becSGavin Shan } 302511685becSGavin Shan 302611685becSGavin Shan region.start += phb->ioda.io_segsize; 302711685becSGavin Shan index++; 302811685becSGavin Shan } 3029027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 3030027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 303111685becSGavin Shan region.start = res->start - 303223e79425SGavin Shan phb->hose->mem_offset[0] - 303311685becSGavin Shan phb->ioda.m32_pci_base; 303411685becSGavin Shan region.end = res->end - 303523e79425SGavin Shan phb->hose->mem_offset[0] - 303611685becSGavin Shan phb->ioda.m32_pci_base; 303711685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 303811685becSGavin Shan 303992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 304011685becSGavin Shan region.start <= region.end) { 304111685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 304211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 304311685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 304411685becSGavin Shan if (rc != OPAL_SUCCESS) { 304523e79425SGavin Shan pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 304611685becSGavin Shan __func__, rc, index, pe->pe_number); 304711685becSGavin Shan break; 304811685becSGavin Shan } 304911685becSGavin Shan 305011685becSGavin Shan region.start += phb->ioda.m32_segsize; 305111685becSGavin Shan index++; 305211685becSGavin Shan } 305311685becSGavin Shan } 305411685becSGavin Shan } 305523e79425SGavin Shan 305623e79425SGavin Shan /* 305723e79425SGavin Shan * This function is supposed to be called on basis of PE from top 305823e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 305923e79425SGavin Shan * parent PE could be overrided by its child PEs if necessary. 306023e79425SGavin Shan */ 306123e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 306223e79425SGavin Shan { 306369d733e7SGavin Shan struct pci_dev *pdev; 306423e79425SGavin Shan int i; 306523e79425SGavin Shan 306623e79425SGavin Shan /* 306723e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 306823e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 306923e79425SGavin Shan * be figured out later. 307023e79425SGavin Shan */ 307123e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 307223e79425SGavin Shan 307369d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 307469d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 307569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 307669d733e7SGavin Shan 307769d733e7SGavin Shan /* 307869d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 307969d733e7SGavin Shan * windows of the child bridges should be mapped to 308069d733e7SGavin Shan * the PE as well. 308169d733e7SGavin Shan */ 308269d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 308369d733e7SGavin Shan continue; 308469d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 308569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 308669d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 308769d733e7SGavin Shan } 308811685becSGavin Shan } 308911685becSGavin Shan 3090cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 309111685becSGavin Shan { 309211685becSGavin Shan struct pci_controller *tmp, *hose; 309311685becSGavin Shan struct pnv_phb *phb; 309411685becSGavin Shan struct pnv_ioda_pe *pe; 309511685becSGavin Shan 309611685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 309711685becSGavin Shan phb = hose->private_data; 30985d2aa710SAlistair Popple 30995d2aa710SAlistair Popple /* NPU PHB does not support IO or MMIO segmentation */ 31005d2aa710SAlistair Popple if (phb->type == PNV_PHB_NPU) 31015d2aa710SAlistair Popple continue; 31025d2aa710SAlistair Popple 310311685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 310423e79425SGavin Shan pnv_ioda_setup_pe_seg(pe); 310511685becSGavin Shan } 310611685becSGavin Shan } 310711685becSGavin Shan } 310811685becSGavin Shan 3109cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 311013395c48SGavin Shan { 311113395c48SGavin Shan struct pci_controller *hose, *tmp; 3112db1266c8SGavin Shan struct pnv_phb *phb; 311313395c48SGavin Shan 311413395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 311513395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 3116db1266c8SGavin Shan 3117db1266c8SGavin Shan /* Mark the PHB initialization done */ 3118db1266c8SGavin Shan phb = hose->private_data; 3119db1266c8SGavin Shan phb->initialized = 1; 312013395c48SGavin Shan } 312113395c48SGavin Shan } 312213395c48SGavin Shan 312337c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 312437c367f2SGavin Shan { 312537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 312637c367f2SGavin Shan struct pci_controller *hose, *tmp; 312737c367f2SGavin Shan struct pnv_phb *phb; 312837c367f2SGavin Shan char name[16]; 312937c367f2SGavin Shan 313037c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 313137c367f2SGavin Shan phb = hose->private_data; 313237c367f2SGavin Shan 313337c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 313437c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 313537c367f2SGavin Shan if (!phb->dbgfs) 313637c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 313737c367f2SGavin Shan __func__, hose->global_number); 313837c367f2SGavin Shan } 313937c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 314037c367f2SGavin Shan } 314137c367f2SGavin Shan 31425d2aa710SAlistair Popple static void pnv_npu_ioda_fixup(void) 31435d2aa710SAlistair Popple { 31445d2aa710SAlistair Popple bool enable_bypass; 31455d2aa710SAlistair Popple struct pci_controller *hose, *tmp; 31465d2aa710SAlistair Popple struct pnv_phb *phb; 31475d2aa710SAlistair Popple struct pnv_ioda_pe *pe; 3148801846d1SGavin Shan unsigned int weight; 31495d2aa710SAlistair Popple 31505d2aa710SAlistair Popple list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 31515d2aa710SAlistair Popple phb = hose->private_data; 31525d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 31535d2aa710SAlistair Popple continue; 31545d2aa710SAlistair Popple 3155801846d1SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3156801846d1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 3157801846d1SGavin Shan if (WARN_ON(!weight)) 3158801846d1SGavin Shan continue; 3159801846d1SGavin Shan 31605d2aa710SAlistair Popple enable_bypass = dma_get_mask(&pe->pdev->dev) == 31615d2aa710SAlistair Popple DMA_BIT_MASK(64); 31625d2aa710SAlistair Popple pnv_npu_init_dma_pe(pe); 31635d2aa710SAlistair Popple pnv_npu_dma_set_bypass(pe, enable_bypass); 31645d2aa710SAlistair Popple } 31655d2aa710SAlistair Popple } 31665d2aa710SAlistair Popple } 31675d2aa710SAlistair Popple 3168cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3169fb446ad0SGavin Shan { 3170fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 317111685becSGavin Shan pnv_pci_ioda_setup_seg(); 317213395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 3173e9cc17d4SGavin Shan 317437c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 317537c367f2SGavin Shan 3176e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3177e9cc17d4SGavin Shan eeh_init(); 3178dadcd6d6SMike Qiu eeh_addr_cache_build(); 3179e9cc17d4SGavin Shan #endif 31805d2aa710SAlistair Popple 31815d2aa710SAlistair Popple /* Link NPU IODA tables to their PCI devices. */ 31825d2aa710SAlistair Popple pnv_npu_ioda_fixup(); 3183fb446ad0SGavin Shan } 3184fb446ad0SGavin Shan 3185271fd03aSGavin Shan /* 3186271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3187271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3188271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3189271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3190271fd03aSGavin Shan * 1MiB for memory) will be returned. 3191271fd03aSGavin Shan * 3192271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3193271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3194271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3195271fd03aSGavin Shan * resources. 3196271fd03aSGavin Shan */ 3197271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3198271fd03aSGavin Shan unsigned long type) 3199271fd03aSGavin Shan { 3200271fd03aSGavin Shan struct pci_dev *bridge; 3201271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3202271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3203271fd03aSGavin Shan int num_pci_bridges = 0; 3204271fd03aSGavin Shan 3205271fd03aSGavin Shan bridge = bus->self; 3206271fd03aSGavin Shan while (bridge) { 3207271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3208271fd03aSGavin Shan num_pci_bridges++; 3209271fd03aSGavin Shan if (num_pci_bridges >= 2) 3210271fd03aSGavin Shan return 1; 3211271fd03aSGavin Shan } 3212271fd03aSGavin Shan 3213271fd03aSGavin Shan bridge = bridge->bus->self; 3214271fd03aSGavin Shan } 3215271fd03aSGavin Shan 3216262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 3217262af557SGuo Chao if (phb->ioda.m64_segsize && 3218262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 3219262af557SGuo Chao return phb->ioda.m64_segsize; 3220271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3221271fd03aSGavin Shan return phb->ioda.m32_segsize; 3222271fd03aSGavin Shan 3223271fd03aSGavin Shan return phb->ioda.io_segsize; 3224271fd03aSGavin Shan } 3225271fd03aSGavin Shan 32265350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 32275350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 32285350ab3fSWei Yang int resno) 32295350ab3fSWei Yang { 3230ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3231ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 32325350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 32337fbe7a93SWei Yang resource_size_t align; 32345350ab3fSWei Yang 32357fbe7a93SWei Yang /* 32367fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 32377fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 32387fbe7a93SWei Yang * BAR should be size aligned. 32397fbe7a93SWei Yang * 3240ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3241ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3242ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3243ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3244ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3245ee8222feSWei Yang * m64_segsize. 3246ee8222feSWei Yang * 32477fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 32487fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3249ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3250ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 32517fbe7a93SWei Yang */ 32525350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 32537fbe7a93SWei Yang if (!pdn->vfs_expanded) 32545350ab3fSWei Yang return align; 3255ee8222feSWei Yang if (pdn->m64_single_mode) 3256ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 32577fbe7a93SWei Yang 32587fbe7a93SWei Yang return pdn->vfs_expanded * align; 32595350ab3fSWei Yang } 32605350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 32615350ab3fSWei Yang 3262184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3263184cd4a3SBenjamin Herrenschmidt * assign a PE 3264184cd4a3SBenjamin Herrenschmidt */ 3265c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3266184cd4a3SBenjamin Herrenschmidt { 3267db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3268db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3269db1266c8SGavin Shan struct pci_dn *pdn; 3270184cd4a3SBenjamin Herrenschmidt 3271db1266c8SGavin Shan /* The function is probably called while the PEs have 3272db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3273db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3274db1266c8SGavin Shan * PEs isn't ready. 3275db1266c8SGavin Shan */ 3276db1266c8SGavin Shan if (!phb->initialized) 3277c88c2a18SDaniel Axtens return true; 3278db1266c8SGavin Shan 3279b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3280184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3281c88c2a18SDaniel Axtens return false; 3282db1266c8SGavin Shan 3283c88c2a18SDaniel Axtens return true; 3284184cd4a3SBenjamin Herrenschmidt } 3285184cd4a3SBenjamin Herrenschmidt 32867a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 328773ed148aSBenjamin Herrenschmidt { 32887a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 32897a8e6bbfSMichael Neuling 3290d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 329173ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 329273ed148aSBenjamin Herrenschmidt } 329373ed148aSBenjamin Herrenschmidt 329492ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 329592ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 32961bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 329792ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 329892ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 329992ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 330092ae0353SDaniel Axtens #endif 330192ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 330292ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 330392ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3304763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 330553522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 33067a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 330792ae0353SDaniel Axtens }; 330892ae0353SDaniel Axtens 33095d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 33105d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 33115d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 33125d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 33135d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 33145d2aa710SAlistair Popple #endif 33155d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 33165d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 33175d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 33185d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 33195d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 33205d2aa710SAlistair Popple }; 33215d2aa710SAlistair Popple 3322e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3323e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3324184cd4a3SBenjamin Herrenschmidt { 3325184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3326184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 33272b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 33282b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3329c681b93cSAlistair Popple const __be64 *prop64; 33303a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3331f1b7cc3eSGavin Shan int len; 33323fa23ff8SGavin Shan unsigned int segno; 3333184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3334184cd4a3SBenjamin Herrenschmidt void *aux; 3335184cd4a3SBenjamin Herrenschmidt long rc; 3336184cd4a3SBenjamin Herrenschmidt 3337aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3338184cd4a3SBenjamin Herrenschmidt 3339184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3340184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3341184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3342184cd4a3SBenjamin Herrenschmidt return; 3343184cd4a3SBenjamin Herrenschmidt } 3344184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3345184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3346184cd4a3SBenjamin Herrenschmidt 3347e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 334858d714ecSGavin Shan 334958d714ecSGavin Shan /* Allocate PCI controller */ 3350184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 335158d714ecSGavin Shan if (!phb->hose) { 335258d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3353184cd4a3SBenjamin Herrenschmidt np->full_name); 3354e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3355184cd4a3SBenjamin Herrenschmidt return; 3356184cd4a3SBenjamin Herrenschmidt } 3357184cd4a3SBenjamin Herrenschmidt 3358184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3359f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3360f1b7cc3eSGavin Shan if (prop32 && len == 8) { 33613a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 33623a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3363f1b7cc3eSGavin Shan } else { 3364f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3365184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3366184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3367f1b7cc3eSGavin Shan } 3368184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3369e9cc17d4SGavin Shan phb->hub_id = hub_id; 3370184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3371aa0c033fSGavin Shan phb->type = ioda_type; 3372781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3373184cd4a3SBenjamin Herrenschmidt 3374cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3375cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3376cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3377f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3378aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 33795d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 33805d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3381cee72d5bSBenjamin Herrenschmidt else 3382cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3383cee72d5bSBenjamin Herrenschmidt 3384aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 33852f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3386184cd4a3SBenjamin Herrenschmidt 3387aa0c033fSGavin Shan /* Get registers */ 3388184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 3389184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3390184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3391184cd4a3SBenjamin Herrenschmidt 3392184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 339392b8f137SGavin Shan phb->ioda.total_pe_num = 1; 339436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 339536954dc7SGavin Shan if (prop32) 339692b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 339736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 339836954dc7SGavin Shan if (prop32) 339992b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3400262af557SGuo Chao 3401262af557SGuo Chao /* Parse 64-bit MMIO range */ 3402262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3403262af557SGuo Chao 3404184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3405aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3406184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3407184cd4a3SBenjamin Herrenschmidt 340892b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 34093fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3410184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 341192b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3412184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3413184cd4a3SBenjamin Herrenschmidt 34142b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 34152b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 34162b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 34172b923ed1SGavin Shan 3418c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 341992b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 342093289d8cSGavin Shan m64map_off = size; 342193289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3422184cd4a3SBenjamin Herrenschmidt m32map_off = size; 342392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3424c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3425c35d2a8cSGavin Shan iomap_off = size; 342692b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 34272b923ed1SGavin Shan dma32map_off = size; 34282b923ed1SGavin Shan size += phb->ioda.dma32_count * 34292b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3430c35d2a8cSGavin Shan } 3431184cd4a3SBenjamin Herrenschmidt pemap_off = size; 343292b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3433e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3434184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 343593289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3436184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 343793289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 343893289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 34393fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 344093289d8cSGavin Shan } 34413fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3442184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 34433fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 34443fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 34452b923ed1SGavin Shan 34462b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 34472b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 34482b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 34493fa23ff8SGavin Shan } 3450184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 345192b8f137SGavin Shan set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); 3452184cd4a3SBenjamin Herrenschmidt 3453184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3454781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3455184cd4a3SBenjamin Herrenschmidt 3456184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 34572b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3458acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3459184cd4a3SBenjamin Herrenschmidt 3460aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3461184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3462184cd4a3SBenjamin Herrenschmidt window_type, 3463184cd4a3SBenjamin Herrenschmidt window_num, 3464184cd4a3SBenjamin Herrenschmidt starting_real_address, 3465184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3466184cd4a3SBenjamin Herrenschmidt segment_size); 3467184cd4a3SBenjamin Herrenschmidt #endif 3468184cd4a3SBenjamin Herrenschmidt 3469262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 347092b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3471262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3472262af557SGuo Chao if (phb->ioda.m64_size) 3473262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3474262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3475262af557SGuo Chao if (phb->ioda.io_size) 3476262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3477184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3478184cd4a3SBenjamin Herrenschmidt 3479262af557SGuo Chao 3480184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 348149dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 348249dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 348349dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3484184cd4a3SBenjamin Herrenschmidt 3485184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 3486184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3487184cd4a3SBenjamin Herrenschmidt 3488184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3489184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3490184cd4a3SBenjamin Herrenschmidt 3491c40a4210SGavin Shan /* 3492c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3493c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3494c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3495c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3496c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3497184cd4a3SBenjamin Herrenschmidt */ 3498fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 34995d2aa710SAlistair Popple 35005d2aa710SAlistair Popple if (phb->type == PNV_PHB_NPU) 35015d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 35025d2aa710SAlistair Popple else 350392ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3504ad30cb99SMichael Ellerman 35056e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 35066e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 35075350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3508ad30cb99SMichael Ellerman #endif 3509ad30cb99SMichael Ellerman 3510c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3511184cd4a3SBenjamin Herrenschmidt 3512184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3513d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3514184cd4a3SBenjamin Herrenschmidt if (rc) 3515f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3516361f2a2aSGavin Shan 3517361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3518361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3519361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3520361f2a2aSGavin Shan * transactions from previous kerenl. 3521361f2a2aSGavin Shan */ 3522361f2a2aSGavin Shan if (is_kdump_kernel()) { 3523361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3524cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3525cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3526361f2a2aSGavin Shan } 3527262af557SGuo Chao 35289e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 35299e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3530262af557SGuo Chao hose->mem_resources[1].flags = 0; 3531184cd4a3SBenjamin Herrenschmidt } 3532184cd4a3SBenjamin Herrenschmidt 353367975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3534aa0c033fSGavin Shan { 3535e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3536aa0c033fSGavin Shan } 3537aa0c033fSGavin Shan 35385d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 35395d2aa710SAlistair Popple { 35405d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 35415d2aa710SAlistair Popple } 35425d2aa710SAlistair Popple 3543184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3544184cd4a3SBenjamin Herrenschmidt { 3545184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3546c681b93cSAlistair Popple const __be64 *prop64; 3547184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3548184cd4a3SBenjamin Herrenschmidt 3549184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3550184cd4a3SBenjamin Herrenschmidt 3551184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3552184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3553184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3554184cd4a3SBenjamin Herrenschmidt return; 3555184cd4a3SBenjamin Herrenschmidt } 3556184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3557184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3558184cd4a3SBenjamin Herrenschmidt 3559184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3560184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3561184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3562184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3563e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3564184cd4a3SBenjamin Herrenschmidt } 3565184cd4a3SBenjamin Herrenschmidt } 3566