12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 357644d581SMichael Ellerman #include <asm/debugfs.h> 36262af557SGuo Chao #include <asm/firmware.h> 3780c49c7eSIan Munsie #include <asm/pnv-pci.h> 38aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 3980c49c7eSIan Munsie 40ec249dd8SMichael Neuling #include <misc/cxl-base.h> 41184cd4a3SBenjamin Herrenschmidt 42184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 43184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4444bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 45184cd4a3SBenjamin Herrenschmidt 4699451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4799451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 48acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 49781a868fSWei Yang 507f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 517f2c39e9SFrederic Barrat "NPU_OCAPI" }; 52aca6913fSAlexey Kardashevskiy 53c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54c498a4f9SChristoph Hellwig 557d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 566d31c2faSJoe Perches const char *fmt, ...) 576d31c2faSJoe Perches { 586d31c2faSJoe Perches struct va_format vaf; 596d31c2faSJoe Perches va_list args; 606d31c2faSJoe Perches char pfix[32]; 61184cd4a3SBenjamin Herrenschmidt 626d31c2faSJoe Perches va_start(args, fmt); 636d31c2faSJoe Perches 646d31c2faSJoe Perches vaf.fmt = fmt; 656d31c2faSJoe Perches vaf.va = &args; 666d31c2faSJoe Perches 67781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 686d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 69781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 706d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 716d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 72781a868fSWei Yang #ifdef CONFIG_PCI_IOV 73781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 74781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 75781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 76781a868fSWei Yang (pe->rid & 0xff00) >> 8, 77781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 78781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 796d31c2faSJoe Perches 801f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 816d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 826d31c2faSJoe Perches 836d31c2faSJoe Perches va_end(args); 846d31c2faSJoe Perches } 856d31c2faSJoe Perches 864e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8745baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 884e287840SThadeu Lima de Souza Cascardo 894e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 904e287840SThadeu Lima de Souza Cascardo { 914e287840SThadeu Lima de Souza Cascardo if (!str) 924e287840SThadeu Lima de Souza Cascardo return -EINVAL; 934e287840SThadeu Lima de Souza Cascardo 944e287840SThadeu Lima de Souza Cascardo while (*str) { 954e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 964e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 974e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 984e287840SThadeu Lima de Souza Cascardo break; 994e287840SThadeu Lima de Souza Cascardo } 1004e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1014e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1024e287840SThadeu Lima de Souza Cascardo str++; 1034e287840SThadeu Lima de Souza Cascardo } 1044e287840SThadeu Lima de Souza Cascardo 1054e287840SThadeu Lima de Souza Cascardo return 0; 1064e287840SThadeu Lima de Souza Cascardo } 1074e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1084e287840SThadeu Lima de Souza Cascardo 10945baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11045baee14SGuilherme G. Piccoli { 11145baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11245baee14SGuilherme G. Piccoli return 0; 11345baee14SGuilherme G. Piccoli } 11445baee14SGuilherme G. Piccoli 11545baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11645baee14SGuilherme G. Piccoli 1175958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 118262af557SGuo Chao { 1195958d19aSBenjamin Herrenschmidt /* 1205958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1215958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1225958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1235958d19aSBenjamin Herrenschmidt * 1245958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1255958d19aSBenjamin Herrenschmidt */ 1265958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1275958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 128262af557SGuo Chao } 129262af557SGuo Chao 130b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 131b79331a5SRussell Currey { 132b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 133b79331a5SRussell Currey 134b79331a5SRussell Currey return (resource_flags & flags) == flags; 135b79331a5SRussell Currey } 136b79331a5SRussell Currey 1371e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1381e916772SGavin Shan { 139313483ddSGavin Shan s64 rc; 140313483ddSGavin Shan 1411e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1421e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1431e916772SGavin Shan 144313483ddSGavin Shan /* 145313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 146313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 147313483ddSGavin Shan * PE is already in unfrozen state. 148313483ddSGavin Shan */ 149313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 150313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 151d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1521f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 153313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 154313483ddSGavin Shan 1551e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1561e916772SGavin Shan } 1571e916772SGavin Shan 1584b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1594b82ab18SGavin Shan { 16092b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1611f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1624b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1634b82ab18SGavin Shan return; 1644b82ab18SGavin Shan } 1654b82ab18SGavin Shan 166e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1671f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1684b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1694b82ab18SGavin Shan 1701e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1714b82ab18SGavin Shan } 1724b82ab18SGavin Shan 1731e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 174184cd4a3SBenjamin Herrenschmidt { 17560964816SAndrzej Hajda long pe; 176184cd4a3SBenjamin Herrenschmidt 1779fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1789fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1791e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 180184cd4a3SBenjamin Herrenschmidt } 181184cd4a3SBenjamin Herrenschmidt 1829fcd6f4aSGavin Shan return NULL; 1839fcd6f4aSGavin Shan } 1849fcd6f4aSGavin Shan 1851e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 186184cd4a3SBenjamin Herrenschmidt { 1871e916772SGavin Shan struct pnv_phb *phb = pe->phb; 188caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 189184cd4a3SBenjamin Herrenschmidt 1901e916772SGavin Shan WARN_ON(pe->pdev); 1910bd97167SAlexey Kardashevskiy WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */ 1920bd97167SAlexey Kardashevskiy kfree(pe->npucomp); 1931e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 194caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 195184cd4a3SBenjamin Herrenschmidt } 196184cd4a3SBenjamin Herrenschmidt 197262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 198262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 199262af557SGuo Chao { 200262af557SGuo Chao const char *desc; 201262af557SGuo Chao struct resource *r; 202262af557SGuo Chao s64 rc; 203262af557SGuo Chao 204262af557SGuo Chao /* Configure the default M64 BAR */ 205262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 206262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 207262af557SGuo Chao phb->ioda.m64_bar_idx, 208262af557SGuo Chao phb->ioda.m64_base, 209262af557SGuo Chao 0, /* unused */ 210262af557SGuo Chao phb->ioda.m64_size); 211262af557SGuo Chao if (rc != OPAL_SUCCESS) { 212262af557SGuo Chao desc = "configuring"; 213262af557SGuo Chao goto fail; 214262af557SGuo Chao } 215262af557SGuo Chao 216262af557SGuo Chao /* Enable the default M64 BAR */ 217262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 218262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 219262af557SGuo Chao phb->ioda.m64_bar_idx, 220262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 221262af557SGuo Chao if (rc != OPAL_SUCCESS) { 222262af557SGuo Chao desc = "enabling"; 223262af557SGuo Chao goto fail; 224262af557SGuo Chao } 225262af557SGuo Chao 226262af557SGuo Chao /* 22763803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22863803c39SGavin Shan * are first or last two PEs. 229262af557SGuo Chao */ 230262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23192b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23263803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23392b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23463803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 235262af557SGuo Chao else 2361f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23792b8f137SGavin Shan phb->ioda.reserved_pe_idx); 238262af557SGuo Chao 239262af557SGuo Chao return 0; 240262af557SGuo Chao 241262af557SGuo Chao fail: 242262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 243262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 244262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 245262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 246262af557SGuo Chao phb->ioda.m64_bar_idx, 247262af557SGuo Chao OPAL_DISABLE_M64); 248262af557SGuo Chao return -EIO; 249262af557SGuo Chao } 250262af557SGuo Chao 251c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25296a2f92bSGavin Shan unsigned long *pe_bitmap) 253262af557SGuo Chao { 25496a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25596a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 256262af557SGuo Chao struct resource *r; 25796a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25896a2f92bSGavin Shan int segno, i; 259262af557SGuo Chao 26096a2f92bSGavin Shan base = phb->ioda.m64_base; 26196a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26296a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26396a2f92bSGavin Shan r = &pdev->resource[i]; 2645958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 265262af557SGuo Chao continue; 266262af557SGuo Chao 26796a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 26896a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 26996a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27096a2f92bSGavin Shan if (pe_bitmap) 27196a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27296a2f92bSGavin Shan else 27396a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 274262af557SGuo Chao } 275262af557SGuo Chao } 276262af557SGuo Chao } 277262af557SGuo Chao 27899451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 27999451551SGavin Shan { 28099451551SGavin Shan struct resource *r; 28199451551SGavin Shan int index; 28299451551SGavin Shan 28399451551SGavin Shan /* 28499451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28599451551SGavin Shan * there are as many M64 segments as the maximum number of 28699451551SGavin Shan * PEs, which is 128. 28799451551SGavin Shan */ 28899451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 28999451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29099451551SGavin Shan int64_t rc; 29199451551SGavin Shan 29299451551SGavin Shan base = phb->ioda.m64_base + 29399451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29499451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29699451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29799451551SGavin Shan if (rc != OPAL_SUCCESS) { 2981f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 29999451551SGavin Shan rc, phb->hose->global_number, index); 30099451551SGavin Shan goto fail; 30199451551SGavin Shan } 30299451551SGavin Shan 30399451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30499451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30599451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30699451551SGavin Shan if (rc != OPAL_SUCCESS) { 3071f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30899451551SGavin Shan rc, phb->hose->global_number, index); 30999451551SGavin Shan goto fail; 31099451551SGavin Shan } 31199451551SGavin Shan } 31299451551SGavin Shan 31399451551SGavin Shan /* 31463803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31563803c39SGavin Shan * are first or last two PEs. 31699451551SGavin Shan */ 31799451551SGavin Shan r = &phb->hose->mem_resources[1]; 31899451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 31963803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32099451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32163803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32299451551SGavin Shan else 3231f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32499451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32599451551SGavin Shan 32699451551SGavin Shan return 0; 32799451551SGavin Shan 32899451551SGavin Shan fail: 32999451551SGavin Shan for ( ; index >= 0; index--) 33099451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33199451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33299451551SGavin Shan 33399451551SGavin Shan return -EIO; 33499451551SGavin Shan } 33599451551SGavin Shan 336c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33796a2f92bSGavin Shan unsigned long *pe_bitmap, 33896a2f92bSGavin Shan bool all) 339262af557SGuo Chao { 340262af557SGuo Chao struct pci_dev *pdev; 34196a2f92bSGavin Shan 34296a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 343c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34496a2f92bSGavin Shan 34596a2f92bSGavin Shan if (all && pdev->subordinate) 346c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34796a2f92bSGavin Shan pe_bitmap, all); 34896a2f92bSGavin Shan } 34996a2f92bSGavin Shan } 35096a2f92bSGavin Shan 3511e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 352262af557SGuo Chao { 35326ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35426ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 355262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 356262af557SGuo Chao unsigned long size, *pe_alloc; 35726ba248dSGavin Shan int i; 358262af557SGuo Chao 359262af557SGuo Chao /* Root bus shouldn't use M64 */ 360262af557SGuo Chao if (pci_is_root_bus(bus)) 3611e916772SGavin Shan return NULL; 362262af557SGuo Chao 363262af557SGuo Chao /* Allocate bitmap */ 36492b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 365262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 366262af557SGuo Chao if (!pe_alloc) { 367262af557SGuo Chao pr_warn("%s: Out of memory !\n", 368262af557SGuo Chao __func__); 3691e916772SGavin Shan return NULL; 370262af557SGuo Chao } 371262af557SGuo Chao 37226ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 373c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 374262af557SGuo Chao 375262af557SGuo Chao /* 376262af557SGuo Chao * the current bus might not own M64 window and that's all 377262af557SGuo Chao * contributed by its child buses. For the case, we needn't 378262af557SGuo Chao * pick M64 dependent PE#. 379262af557SGuo Chao */ 38092b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 381262af557SGuo Chao kfree(pe_alloc); 3821e916772SGavin Shan return NULL; 383262af557SGuo Chao } 384262af557SGuo Chao 385262af557SGuo Chao /* 386262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 387262af557SGuo Chao * PE's list to form compound PE. 388262af557SGuo Chao */ 389262af557SGuo Chao master_pe = NULL; 390262af557SGuo Chao i = -1; 39192b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39292b8f137SGavin Shan phb->ioda.total_pe_num) { 393262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 394262af557SGuo Chao 39593289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 396262af557SGuo Chao if (!master_pe) { 397262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 398262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 399262af557SGuo Chao master_pe = pe; 400262af557SGuo Chao } else { 401262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 402262af557SGuo Chao pe->master = master_pe; 403262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 404262af557SGuo Chao } 40599451551SGavin Shan 40699451551SGavin Shan /* 40799451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40899451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 40999451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41099451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41199451551SGavin Shan * segment and PE# on P7IOC. 41299451551SGavin Shan */ 41399451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41499451551SGavin Shan int64_t rc; 41599451551SGavin Shan 41699451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41799451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41899451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 41999451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42099451551SGavin Shan if (rc != OPAL_SUCCESS) 4211f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42299451551SGavin Shan __func__, rc, phb->hose->global_number, 42399451551SGavin Shan pe->pe_number); 42499451551SGavin Shan } 425262af557SGuo Chao } 426262af557SGuo Chao 427262af557SGuo Chao kfree(pe_alloc); 4281e916772SGavin Shan return master_pe; 429262af557SGuo Chao } 430262af557SGuo Chao 431262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 432262af557SGuo Chao { 433262af557SGuo Chao struct pci_controller *hose = phb->hose; 434262af557SGuo Chao struct device_node *dn = hose->dn; 435262af557SGuo Chao struct resource *res; 436a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4370e7736c6SGavin Shan const __be32 *r; 438262af557SGuo Chao u64 pci_addr; 439262af557SGuo Chao 44099451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4411665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4421665c4a8SGavin Shan return; 4431665c4a8SGavin Shan } 4441665c4a8SGavin Shan 445e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 446262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 447262af557SGuo Chao return; 448262af557SGuo Chao } 449262af557SGuo Chao 450262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 451262af557SGuo Chao if (!r) { 452b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 453b7c670d6SRob Herring dn); 454262af557SGuo Chao return; 455262af557SGuo Chao } 456262af557SGuo Chao 457a1339fafSBenjamin Herrenschmidt /* 458a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 459a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 460a1339fafSBenjamin Herrenschmidt */ 461a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 462a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 463a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 464a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 465a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 466a1339fafSBenjamin Herrenschmidt } 467a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 468a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 469a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 470a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 471a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 472a1339fafSBenjamin Herrenschmidt } 473a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 474a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 475a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 476a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 477a1339fafSBenjamin Herrenschmidt return; 478a1339fafSBenjamin Herrenschmidt } 479a1339fafSBenjamin Herrenschmidt 480a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 481262af557SGuo Chao res = &hose->mem_resources[1]; 482e80c4e7cSGavin Shan res->name = dn->full_name; 483262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 484262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 485262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 486262af557SGuo Chao pci_addr = of_read_number(r, 2); 487262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 488262af557SGuo Chao 489262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49092b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 491262af557SGuo Chao phb->ioda.m64_base = pci_addr; 492262af557SGuo Chao 493a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 494a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 495a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 496a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 497a1339fafSBenjamin Herrenschmidt 498a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 499a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 500e9863e68SWei Yang 501262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 502a1339fafSBenjamin Herrenschmidt m64_range[1]--; 503a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 504a1339fafSBenjamin Herrenschmidt 505a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 506a1339fafSBenjamin Herrenschmidt 507a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 508a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 509a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 510a1339fafSBenjamin Herrenschmidt 511a1339fafSBenjamin Herrenschmidt /* 512a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 513a1339fafSBenjamin Herrenschmidt * the IODA2 code. 514a1339fafSBenjamin Herrenschmidt */ 51599451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51699451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51799451551SGavin Shan else 518262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 519262af557SGuo Chao } 520262af557SGuo Chao 52149dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52249dec922SGavin Shan { 52349dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52449dec922SGavin Shan struct pnv_ioda_pe *slave; 52549dec922SGavin Shan s64 rc; 52649dec922SGavin Shan 52749dec922SGavin Shan /* Fetch master PE */ 52849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 52949dec922SGavin Shan pe = pe->master; 530ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 531ec8e4e9dSGavin Shan return; 532ec8e4e9dSGavin Shan 53349dec922SGavin Shan pe_no = pe->pe_number; 53449dec922SGavin Shan } 53549dec922SGavin Shan 53649dec922SGavin Shan /* Freeze master PE */ 53749dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53849dec922SGavin Shan pe_no, 53949dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54149dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54249dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54349dec922SGavin Shan return; 54449dec922SGavin Shan } 54549dec922SGavin Shan 54649dec922SGavin Shan /* Freeze slave PEs */ 54749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54849dec922SGavin Shan return; 54949dec922SGavin Shan 55049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55249dec922SGavin Shan slave->pe_number, 55349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55449dec922SGavin Shan if (rc != OPAL_SUCCESS) 55549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55649dec922SGavin Shan __func__, rc, phb->hose->global_number, 55749dec922SGavin Shan slave->pe_number); 55849dec922SGavin Shan } 55949dec922SGavin Shan } 56049dec922SGavin Shan 561e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56249dec922SGavin Shan { 56349dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56449dec922SGavin Shan s64 rc; 56549dec922SGavin Shan 56649dec922SGavin Shan /* Find master PE */ 56749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 56949dec922SGavin Shan pe = pe->master; 57049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57149dec922SGavin Shan pe_no = pe->pe_number; 57249dec922SGavin Shan } 57349dec922SGavin Shan 57449dec922SGavin Shan /* Clear frozen state for master PE */ 57549dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57749dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57849dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 57949dec922SGavin Shan return -EIO; 58049dec922SGavin Shan } 58149dec922SGavin Shan 58249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58349dec922SGavin Shan return 0; 58449dec922SGavin Shan 58549dec922SGavin Shan /* Clear frozen state for slave PEs */ 58649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58749dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58849dec922SGavin Shan slave->pe_number, 58949dec922SGavin Shan opt); 59049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59349dec922SGavin Shan slave->pe_number); 59449dec922SGavin Shan return -EIO; 59549dec922SGavin Shan } 59649dec922SGavin Shan } 59749dec922SGavin Shan 59849dec922SGavin Shan return 0; 59949dec922SGavin Shan } 60049dec922SGavin Shan 60149dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60249dec922SGavin Shan { 60349dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 604c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 605c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 60649dec922SGavin Shan s64 rc; 60749dec922SGavin Shan 60849dec922SGavin Shan /* Sanity check on PE number */ 60992b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61049dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61149dec922SGavin Shan 61249dec922SGavin Shan /* 61349dec922SGavin Shan * Fetch the master PE and the PE instance might be 61449dec922SGavin Shan * not initialized yet. 61549dec922SGavin Shan */ 61649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61849dec922SGavin Shan pe = pe->master; 61949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62049dec922SGavin Shan pe_no = pe->pe_number; 62149dec922SGavin Shan } 62249dec922SGavin Shan 62349dec922SGavin Shan /* Check the master PE */ 62449dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62549dec922SGavin Shan &state, &pcierr, NULL); 62649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62749dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62849dec922SGavin Shan "PHB#%x-PE#%x state\n", 62949dec922SGavin Shan __func__, rc, 63049dec922SGavin Shan phb->hose->global_number, pe_no); 63149dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63249dec922SGavin Shan } 63349dec922SGavin Shan 63449dec922SGavin Shan /* Check the slave PE */ 63549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63649dec922SGavin Shan return state; 63749dec922SGavin Shan 63849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 63949dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64049dec922SGavin Shan slave->pe_number, 64149dec922SGavin Shan &fstate, 64249dec922SGavin Shan &pcierr, 64349dec922SGavin Shan NULL); 64449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64549dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64649dec922SGavin Shan "PHB#%x-PE#%x state\n", 64749dec922SGavin Shan __func__, rc, 64849dec922SGavin Shan phb->hose->global_number, slave->pe_number); 64949dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65049dec922SGavin Shan } 65149dec922SGavin Shan 65249dec922SGavin Shan /* 65349dec922SGavin Shan * Override the result based on the ascending 65449dec922SGavin Shan * priority. 65549dec922SGavin Shan */ 65649dec922SGavin Shan if (fstate > state) 65749dec922SGavin Shan state = fstate; 65849dec922SGavin Shan } 65949dec922SGavin Shan 66049dec922SGavin Shan return state; 66149dec922SGavin Shan } 66249dec922SGavin Shan 663f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 664184cd4a3SBenjamin Herrenschmidt { 665184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 666184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 667b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 668184cd4a3SBenjamin Herrenschmidt 669184cd4a3SBenjamin Herrenschmidt if (!pdn) 670184cd4a3SBenjamin Herrenschmidt return NULL; 671184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 672184cd4a3SBenjamin Herrenschmidt return NULL; 673184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 674184cd4a3SBenjamin Herrenschmidt } 675184cd4a3SBenjamin Herrenschmidt 676b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 677b131a842SGavin Shan struct pnv_ioda_pe *parent, 678b131a842SGavin Shan struct pnv_ioda_pe *child, 679b131a842SGavin Shan bool is_add) 680b131a842SGavin Shan { 681b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 682b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 683b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 684b131a842SGavin Shan struct pnv_ioda_pe *slave; 685b131a842SGavin Shan long rc; 686b131a842SGavin Shan 687b131a842SGavin Shan /* Parent PE affects child PE */ 688b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 689b131a842SGavin Shan child->pe_number, op); 690b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 691b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 692b131a842SGavin Shan rc, desc); 693b131a842SGavin Shan return -ENXIO; 694b131a842SGavin Shan } 695b131a842SGavin Shan 696b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 697b131a842SGavin Shan return 0; 698b131a842SGavin Shan 699b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 700b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 701b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 702b131a842SGavin Shan slave->pe_number, op); 703b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 704b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 705b131a842SGavin Shan rc, desc); 706b131a842SGavin Shan return -ENXIO; 707b131a842SGavin Shan } 708b131a842SGavin Shan } 709b131a842SGavin Shan 710b131a842SGavin Shan return 0; 711b131a842SGavin Shan } 712b131a842SGavin Shan 713b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 714b131a842SGavin Shan struct pnv_ioda_pe *pe, 715b131a842SGavin Shan bool is_add) 716b131a842SGavin Shan { 717b131a842SGavin Shan struct pnv_ioda_pe *slave; 718781a868fSWei Yang struct pci_dev *pdev = NULL; 719b131a842SGavin Shan int ret; 720b131a842SGavin Shan 721b131a842SGavin Shan /* 722b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 723b131a842SGavin Shan * clear slave PE frozen state as well. 724b131a842SGavin Shan */ 725b131a842SGavin Shan if (is_add) { 726b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 727b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 728b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 729b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 730b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 731b131a842SGavin Shan slave->pe_number, 732b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 733b131a842SGavin Shan } 734b131a842SGavin Shan } 735b131a842SGavin Shan 736b131a842SGavin Shan /* 737b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 738b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 739b131a842SGavin Shan * originated from the PE might contribute to other 740b131a842SGavin Shan * PEs. 741b131a842SGavin Shan */ 742b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 743b131a842SGavin Shan if (ret) 744b131a842SGavin Shan return ret; 745b131a842SGavin Shan 746b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 747b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 748b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 749b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 750b131a842SGavin Shan if (ret) 751b131a842SGavin Shan return ret; 752b131a842SGavin Shan } 753b131a842SGavin Shan } 754b131a842SGavin Shan 755b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 756b131a842SGavin Shan pdev = pe->pbus->self; 757781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 758b131a842SGavin Shan pdev = pe->pdev->bus->self; 759781a868fSWei Yang #ifdef CONFIG_PCI_IOV 760781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 761283e2d8aSGavin Shan pdev = pe->parent_dev; 762781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 763b131a842SGavin Shan while (pdev) { 764b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 765b131a842SGavin Shan struct pnv_ioda_pe *parent; 766b131a842SGavin Shan 767b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 768b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 769b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 770b131a842SGavin Shan if (ret) 771b131a842SGavin Shan return ret; 772b131a842SGavin Shan } 773b131a842SGavin Shan 774b131a842SGavin Shan pdev = pdev->bus->self; 775b131a842SGavin Shan } 776b131a842SGavin Shan 777b131a842SGavin Shan return 0; 778b131a842SGavin Shan } 779b131a842SGavin Shan 780781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 781781a868fSWei Yang { 782781a868fSWei Yang struct pci_dev *parent; 783781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 784781a868fSWei Yang int64_t rc; 785781a868fSWei Yang long rid_end, rid; 786781a868fSWei Yang 787781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 788781a868fSWei Yang if (pe->pbus) { 789781a868fSWei Yang int count; 790781a868fSWei Yang 791781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 792781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 793781a868fSWei Yang parent = pe->pbus->self; 794781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 795781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 796781a868fSWei Yang else 797781a868fSWei Yang count = 1; 798781a868fSWei Yang 799781a868fSWei Yang switch(count) { 800781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 801781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 802781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 803781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 804781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 805781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 806781a868fSWei Yang default: 807781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 808781a868fSWei Yang count); 809781a868fSWei Yang /* Do an exact match only */ 810781a868fSWei Yang bcomp = OpalPciBusAll; 811781a868fSWei Yang } 812781a868fSWei Yang rid_end = pe->rid + (count << 8); 813781a868fSWei Yang } else { 81493e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 815781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 816781a868fSWei Yang parent = pe->parent_dev; 817781a868fSWei Yang else 81893e01a50SGavin Shan #endif 819781a868fSWei Yang parent = pe->pdev->bus->self; 820781a868fSWei Yang bcomp = OpalPciBusAll; 821781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 822781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 823781a868fSWei Yang rid_end = pe->rid + 1; 824781a868fSWei Yang } 825781a868fSWei Yang 826781a868fSWei Yang /* Clear the reverse map */ 827781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 828c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 829781a868fSWei Yang 830781a868fSWei Yang /* Release from all parents PELT-V */ 831781a868fSWei Yang while (parent) { 832781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 833781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 834781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 835781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 836781a868fSWei Yang /* XXX What to do in case of error ? */ 837781a868fSWei Yang } 838781a868fSWei Yang parent = parent->bus->self; 839781a868fSWei Yang } 840781a868fSWei Yang 841f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 842781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 843781a868fSWei Yang 844781a868fSWei Yang /* Disassociate PE in PELT */ 845781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 846781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 847781a868fSWei Yang if (rc) 8481e496391SJoe Perches pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 849781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 850781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 851781a868fSWei Yang if (rc) 8521e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 853781a868fSWei Yang 854781a868fSWei Yang pe->pbus = NULL; 855781a868fSWei Yang pe->pdev = NULL; 85693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 857781a868fSWei Yang pe->parent_dev = NULL; 85893e01a50SGavin Shan #endif 859781a868fSWei Yang 860781a868fSWei Yang return 0; 861781a868fSWei Yang } 862781a868fSWei Yang 863cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 864184cd4a3SBenjamin Herrenschmidt { 865184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 866184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 867184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 868184cd4a3SBenjamin Herrenschmidt 869184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 870184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 871184cd4a3SBenjamin Herrenschmidt int count; 872184cd4a3SBenjamin Herrenschmidt 873184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 874184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 875184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 876fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 877b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 878fb446ad0SGavin Shan else 879fb446ad0SGavin Shan count = 1; 880fb446ad0SGavin Shan 881184cd4a3SBenjamin Herrenschmidt switch(count) { 882184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 883184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 884184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 885184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 886184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 887184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 888184cd4a3SBenjamin Herrenschmidt default: 889781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 890781a868fSWei Yang count); 891184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 892184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 893184cd4a3SBenjamin Herrenschmidt } 894184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 895184cd4a3SBenjamin Herrenschmidt } else { 896781a868fSWei Yang #ifdef CONFIG_PCI_IOV 897781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 898781a868fSWei Yang parent = pe->parent_dev; 899781a868fSWei Yang else 900781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 901184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 902184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 903184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 904184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 905184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 906184cd4a3SBenjamin Herrenschmidt } 907184cd4a3SBenjamin Herrenschmidt 908631ad691SGavin Shan /* 909631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 910631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 911631ad691SGavin Shan * originated from the PE might contribute to other 912631ad691SGavin Shan * PEs. 913631ad691SGavin Shan */ 914184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 915184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 916184cd4a3SBenjamin Herrenschmidt if (rc) { 917184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 918184cd4a3SBenjamin Herrenschmidt return -ENXIO; 919184cd4a3SBenjamin Herrenschmidt } 920631ad691SGavin Shan 9215d2aa710SAlistair Popple /* 9225d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9235d2aa710SAlistair Popple * configuration on them. 9245d2aa710SAlistair Popple */ 9257f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 926b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 927184cd4a3SBenjamin Herrenschmidt 928184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 929184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 930184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 931184cd4a3SBenjamin Herrenschmidt 932184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9334773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9344773f76bSGavin Shan pe->mve_number = 0; 9354773f76bSGavin Shan goto out; 9364773f76bSGavin Shan } 9374773f76bSGavin Shan 938184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9394773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9404773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9411f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 942184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 943184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 944184cd4a3SBenjamin Herrenschmidt } else { 945184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 946cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 947184cd4a3SBenjamin Herrenschmidt if (rc) { 9481f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 949184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 950184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 951184cd4a3SBenjamin Herrenschmidt } 952184cd4a3SBenjamin Herrenschmidt } 953184cd4a3SBenjamin Herrenschmidt 9544773f76bSGavin Shan out: 955184cd4a3SBenjamin Herrenschmidt return 0; 956184cd4a3SBenjamin Herrenschmidt } 957184cd4a3SBenjamin Herrenschmidt 958781a868fSWei Yang #ifdef CONFIG_PCI_IOV 959781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 960781a868fSWei Yang { 961781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 962781a868fSWei Yang int i; 963781a868fSWei Yang struct resource *res, res2; 964781a868fSWei Yang resource_size_t size; 965781a868fSWei Yang u16 num_vfs; 966781a868fSWei Yang 967781a868fSWei Yang if (!dev->is_physfn) 968781a868fSWei Yang return -EINVAL; 969781a868fSWei Yang 970781a868fSWei Yang /* 971781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 972781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 973781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 974781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 975781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 976781a868fSWei Yang * range of PEs the VFs are in. 977781a868fSWei Yang */ 978781a868fSWei Yang num_vfs = pdn->num_vfs; 979781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 980781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 981781a868fSWei Yang if (!res->flags || !res->parent) 982781a868fSWei Yang continue; 983781a868fSWei Yang 984781a868fSWei Yang /* 985781a868fSWei Yang * The actual IOV BAR range is determined by the start address 986781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 987781a868fSWei Yang * make sure that after shifting, the range will not overlap 988781a868fSWei Yang * with another device. 989781a868fSWei Yang */ 990781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 991781a868fSWei Yang res2.flags = res->flags; 992781a868fSWei Yang res2.start = res->start + (size * offset); 993781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 994781a868fSWei Yang 995781a868fSWei Yang if (res2.end > res->end) { 996781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 997781a868fSWei Yang i, &res2, res, num_vfs, offset); 998781a868fSWei Yang return -EBUSY; 999781a868fSWei Yang } 1000781a868fSWei Yang } 1001781a868fSWei Yang 1002781a868fSWei Yang /* 1003d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1004d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1005d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1006d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1007d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1008d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1009781a868fSWei Yang */ 1010781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1011781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1012781a868fSWei Yang if (!res->flags || !res->parent) 1013781a868fSWei Yang continue; 1014781a868fSWei Yang 1015781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1016781a868fSWei Yang res2 = *res; 1017781a868fSWei Yang res->start += size * offset; 1018781a868fSWei Yang 101974703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 102074703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102174703cc4SWei Yang num_vfs, offset); 1022d6f934fdSAlexey Kardashevskiy 1023d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1024d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1025d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1026d6f934fdSAlexey Kardashevskiy } 1027d6f934fdSAlexey Kardashevskiy 1028781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1029d6f934fdSAlexey Kardashevskiy 1030d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1031d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1032d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1033d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1034d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1035d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1036d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1037d6f934fdSAlexey Kardashevskiy } 1038781a868fSWei Yang } 1039781a868fSWei Yang return 0; 1040781a868fSWei Yang } 1041781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1042781a868fSWei Yang 1043cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1044184cd4a3SBenjamin Herrenschmidt { 1045184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1046184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1047b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1048184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1049184cd4a3SBenjamin Herrenschmidt 1050184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1051184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1052184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1053184cd4a3SBenjamin Herrenschmidt return NULL; 1054184cd4a3SBenjamin Herrenschmidt } 1055184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1056184cd4a3SBenjamin Herrenschmidt return NULL; 1057184cd4a3SBenjamin Herrenschmidt 10581e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10591e916772SGavin Shan if (!pe) { 1060f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1061184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1062184cd4a3SBenjamin Herrenschmidt return NULL; 1063184cd4a3SBenjamin Herrenschmidt } 1064184cd4a3SBenjamin Herrenschmidt 1065184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1066184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1067184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1068184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1069184cd4a3SBenjamin Herrenschmidt * 1070184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1071184cd4a3SBenjamin Herrenschmidt */ 1072184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 10731e916772SGavin Shan pdn->pe_number = pe->pe_number; 10745d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1075184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1076184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1077184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1078184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1079184cd4a3SBenjamin Herrenschmidt 1080184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1081184cd4a3SBenjamin Herrenschmidt 1082184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1083184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10841e916772SGavin Shan pnv_ioda_free_pe(pe); 1085184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1086184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1087184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1088184cd4a3SBenjamin Herrenschmidt return NULL; 1089184cd4a3SBenjamin Herrenschmidt } 1090184cd4a3SBenjamin Herrenschmidt 10911d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10921d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10931d4e89cfSAlexey Kardashevskiy 1094184cd4a3SBenjamin Herrenschmidt return pe; 1095184cd4a3SBenjamin Herrenschmidt } 1096184cd4a3SBenjamin Herrenschmidt 1097184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1098184cd4a3SBenjamin Herrenschmidt { 1099184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1100184cd4a3SBenjamin Herrenschmidt 1101184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1102b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1103184cd4a3SBenjamin Herrenschmidt 1104184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1105184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1106184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1107184cd4a3SBenjamin Herrenschmidt continue; 1108184cd4a3SBenjamin Herrenschmidt } 1109ccd1c191SGavin Shan 1110ccd1c191SGavin Shan /* 1111ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1112ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1113ccd1c191SGavin Shan * again. 1114ccd1c191SGavin Shan */ 1115ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1116ccd1c191SGavin Shan continue; 1117ccd1c191SGavin Shan 1118c5f7700bSGavin Shan pe->device_count++; 1119184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1120fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1121184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1122184cd4a3SBenjamin Herrenschmidt } 1123184cd4a3SBenjamin Herrenschmidt } 1124184cd4a3SBenjamin Herrenschmidt 1125fb446ad0SGavin Shan /* 1126fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1127fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1128fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1129fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1130fb446ad0SGavin Shan */ 11311e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1132184cd4a3SBenjamin Herrenschmidt { 1133fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1134184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11351e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1136ccd1c191SGavin Shan unsigned int pe_num; 1137ccd1c191SGavin Shan 1138ccd1c191SGavin Shan /* 1139ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1140ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1141ccd1c191SGavin Shan */ 1142ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1143ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1144ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1145ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1146ccd1c191SGavin Shan return NULL; 1147ccd1c191SGavin Shan } 1148184cd4a3SBenjamin Herrenschmidt 114963803c39SGavin Shan /* PE number for root bus should have been reserved */ 115063803c39SGavin Shan if (pci_is_root_bus(bus) && 115163803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 115263803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 115363803c39SGavin Shan 1154262af557SGuo Chao /* Check if PE is determined by M64 */ 1155a25de7afSAlexey Kardashevskiy if (!pe) 1156a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1157262af557SGuo Chao 1158262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11591e916772SGavin Shan if (!pe) 11601e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1161262af557SGuo Chao 11621e916772SGavin Shan if (!pe) { 1163f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1164fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11651e916772SGavin Shan return NULL; 1166184cd4a3SBenjamin Herrenschmidt } 1167184cd4a3SBenjamin Herrenschmidt 1168262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1169184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1170184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1171184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1172b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1173184cd4a3SBenjamin Herrenschmidt 1174fb446ad0SGavin Shan if (all) 11751e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 11761e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 11771e496391SJoe Perches pe->pe_number); 1178fb446ad0SGavin Shan else 11791e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 11801e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1181184cd4a3SBenjamin Herrenschmidt 1182184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1183184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11841e916772SGavin Shan pnv_ioda_free_pe(pe); 1185184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11861e916772SGavin Shan return NULL; 1187184cd4a3SBenjamin Herrenschmidt } 1188184cd4a3SBenjamin Herrenschmidt 1189184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1190184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1191184cd4a3SBenjamin Herrenschmidt 11927ebdf956SGavin Shan /* Put PE to the list */ 11937ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11941e916772SGavin Shan 11951e916772SGavin Shan return pe; 1196184cd4a3SBenjamin Herrenschmidt } 1197184cd4a3SBenjamin Herrenschmidt 1198b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11995d2aa710SAlistair Popple { 1200b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1201b521549aSAlistair Popple long rid; 1202b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1203b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1204b521549aSAlistair Popple struct pci_dn *npu_pdn; 1205b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1206b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1207b521549aSAlistair Popple 1208b521549aSAlistair Popple /* 1209b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1210b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1211b521549aSAlistair Popple * which need to be assigned to four links, implying some 1212b521549aSAlistair Popple * links must share PEs. 1213b521549aSAlistair Popple * 1214b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1215b521549aSAlistair Popple * same GPU get assigned the same PE. 1216b521549aSAlistair Popple */ 1217b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 121892b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1219b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1220b521549aSAlistair Popple if (!pe->pdev) 1221b521549aSAlistair Popple continue; 1222b521549aSAlistair Popple 1223b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1224b521549aSAlistair Popple /* 1225b521549aSAlistair Popple * This device has the same peer GPU so should 1226b521549aSAlistair Popple * be assigned the same PE as the existing 1227b521549aSAlistair Popple * peer NPU. 1228b521549aSAlistair Popple */ 1229b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12301f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1231b521549aSAlistair Popple pci_dev_get(npu_pdev); 1232b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1233b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1234b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1235b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1236b521549aSAlistair Popple 1237b521549aSAlistair Popple /* Map the PE to this link */ 1238b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1239b521549aSAlistair Popple OpalPciBusAll, 1240b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1241b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1242b521549aSAlistair Popple OPAL_MAP_PE); 1243b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1244b521549aSAlistair Popple found_pe = true; 1245b521549aSAlistair Popple break; 1246b521549aSAlistair Popple } 1247b521549aSAlistair Popple } 1248b521549aSAlistair Popple 1249b521549aSAlistair Popple if (!found_pe) 1250b521549aSAlistair Popple /* 1251b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1252b521549aSAlistair Popple * one. 1253b521549aSAlistair Popple */ 1254b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1255b521549aSAlistair Popple else 1256b521549aSAlistair Popple return pe; 1257b521549aSAlistair Popple } 1258b521549aSAlistair Popple 1259b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1260b521549aSAlistair Popple { 12615d2aa710SAlistair Popple struct pci_dev *pdev; 12625d2aa710SAlistair Popple 12635d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1264b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12655d2aa710SAlistair Popple } 12665d2aa710SAlistair Popple 1267cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1268fb446ad0SGavin Shan { 12690e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1270262af557SGuo Chao struct pnv_phb *phb; 12717f2c39e9SFrederic Barrat struct pci_bus *bus; 12727f2c39e9SFrederic Barrat struct pci_dev *pdev; 12730e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1274fb446ad0SGavin Shan 12750e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1276262af557SGuo Chao phb = hose->private_data; 12777f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 127808f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 127908f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1280b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12811ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12820e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1283ccd1c191SGavin Shan } 12847f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_OCAPI) { 12857f2c39e9SFrederic Barrat bus = hose->bus; 12867f2c39e9SFrederic Barrat list_for_each_entry(pdev, &bus->devices, bus_list) 12877f2c39e9SFrederic Barrat pnv_ioda_setup_dev_PE(pdev); 12887f2c39e9SFrederic Barrat } 1289fb446ad0SGavin Shan } 12900e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 12910e759bd7SAlexey Kardashevskiy phb = hose->private_data; 12920e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 12930e759bd7SAlexey Kardashevskiy continue; 12940e759bd7SAlexey Kardashevskiy 12950e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 12960e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 12970e759bd7SAlexey Kardashevskiy } 1298fb446ad0SGavin Shan } 1299184cd4a3SBenjamin Herrenschmidt 1300a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1301ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1302781a868fSWei Yang { 1303781a868fSWei Yang struct pci_bus *bus; 1304781a868fSWei Yang struct pci_controller *hose; 1305781a868fSWei Yang struct pnv_phb *phb; 1306781a868fSWei Yang struct pci_dn *pdn; 130702639b0eSWei Yang int i, j; 1308ee8222feSWei Yang int m64_bars; 1309781a868fSWei Yang 1310781a868fSWei Yang bus = pdev->bus; 1311781a868fSWei Yang hose = pci_bus_to_host(bus); 1312781a868fSWei Yang phb = hose->private_data; 1313781a868fSWei Yang pdn = pci_get_pdn(pdev); 1314781a868fSWei Yang 1315ee8222feSWei Yang if (pdn->m64_single_mode) 1316ee8222feSWei Yang m64_bars = num_vfs; 1317ee8222feSWei Yang else 1318ee8222feSWei Yang m64_bars = 1; 1319ee8222feSWei Yang 132002639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1321ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1322ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1323781a868fSWei Yang continue; 1324781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1325ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1326ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1327ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1328781a868fSWei Yang } 1329781a868fSWei Yang 1330ee8222feSWei Yang kfree(pdn->m64_map); 1331781a868fSWei Yang return 0; 1332781a868fSWei Yang } 1333781a868fSWei Yang 133402639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1335781a868fSWei Yang { 1336781a868fSWei Yang struct pci_bus *bus; 1337781a868fSWei Yang struct pci_controller *hose; 1338781a868fSWei Yang struct pnv_phb *phb; 1339781a868fSWei Yang struct pci_dn *pdn; 1340781a868fSWei Yang unsigned int win; 1341781a868fSWei Yang struct resource *res; 134202639b0eSWei Yang int i, j; 1343781a868fSWei Yang int64_t rc; 134402639b0eSWei Yang int total_vfs; 134502639b0eSWei Yang resource_size_t size, start; 134602639b0eSWei Yang int pe_num; 1347ee8222feSWei Yang int m64_bars; 1348781a868fSWei Yang 1349781a868fSWei Yang bus = pdev->bus; 1350781a868fSWei Yang hose = pci_bus_to_host(bus); 1351781a868fSWei Yang phb = hose->private_data; 1352781a868fSWei Yang pdn = pci_get_pdn(pdev); 135302639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1354781a868fSWei Yang 1355ee8222feSWei Yang if (pdn->m64_single_mode) 1356ee8222feSWei Yang m64_bars = num_vfs; 1357ee8222feSWei Yang else 1358ee8222feSWei Yang m64_bars = 1; 135902639b0eSWei Yang 1360fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1361fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1362fb37e128SMarkus Elfring GFP_KERNEL); 1363ee8222feSWei Yang if (!pdn->m64_map) 1364ee8222feSWei Yang return -ENOMEM; 1365ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1366ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1367ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1368ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1369ee8222feSWei Yang 1370781a868fSWei Yang 1371781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1372781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1373781a868fSWei Yang if (!res->flags || !res->parent) 1374781a868fSWei Yang continue; 1375781a868fSWei Yang 1376ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1377781a868fSWei Yang do { 1378781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1379781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1380781a868fSWei Yang 1381781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1382781a868fSWei Yang goto m64_failed; 1383781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1384781a868fSWei Yang 1385ee8222feSWei Yang pdn->m64_map[j][i] = win; 138602639b0eSWei Yang 1387ee8222feSWei Yang if (pdn->m64_single_mode) { 138802639b0eSWei Yang size = pci_iov_resource_size(pdev, 138902639b0eSWei Yang PCI_IOV_RESOURCES + i); 139002639b0eSWei Yang start = res->start + size * j; 139102639b0eSWei Yang } else { 139202639b0eSWei Yang size = resource_size(res); 139302639b0eSWei Yang start = res->start; 139402639b0eSWei Yang } 1395781a868fSWei Yang 1396781a868fSWei Yang /* Map the M64 here */ 1397ee8222feSWei Yang if (pdn->m64_single_mode) { 1398be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 139902639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 140002639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1401ee8222feSWei Yang pdn->m64_map[j][i], 0); 140202639b0eSWei Yang } 140302639b0eSWei Yang 1404781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1405781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1406ee8222feSWei Yang pdn->m64_map[j][i], 140702639b0eSWei Yang start, 1408781a868fSWei Yang 0, /* unused */ 140902639b0eSWei Yang size); 141002639b0eSWei Yang 141102639b0eSWei Yang 1412781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1413781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1414781a868fSWei Yang win, rc); 1415781a868fSWei Yang goto m64_failed; 1416781a868fSWei Yang } 1417781a868fSWei Yang 1418ee8222feSWei Yang if (pdn->m64_single_mode) 1419781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1420ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 142102639b0eSWei Yang else 142202639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1423ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 142402639b0eSWei Yang 1425781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1426781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1427781a868fSWei Yang win, rc); 1428781a868fSWei Yang goto m64_failed; 1429781a868fSWei Yang } 1430781a868fSWei Yang } 143102639b0eSWei Yang } 1432781a868fSWei Yang return 0; 1433781a868fSWei Yang 1434781a868fSWei Yang m64_failed: 1435ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1436781a868fSWei Yang return -EBUSY; 1437781a868fSWei Yang } 1438781a868fSWei Yang 1439c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1440c035e37bSAlexey Kardashevskiy int num); 1441c035e37bSAlexey Kardashevskiy 1442781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1443781a868fSWei Yang { 1444781a868fSWei Yang struct iommu_table *tbl; 1445781a868fSWei Yang int64_t rc; 1446781a868fSWei Yang 1447b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1448c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1449781a868fSWei Yang if (rc) 14501e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 1451781a868fSWei Yang 1452c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14530eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14540eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14550eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1456ac9a5889SAlexey Kardashevskiy } 1457e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1458781a868fSWei Yang } 1459781a868fSWei Yang 1460ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1461781a868fSWei Yang { 1462781a868fSWei Yang struct pci_bus *bus; 1463781a868fSWei Yang struct pci_controller *hose; 1464781a868fSWei Yang struct pnv_phb *phb; 1465781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1466781a868fSWei Yang struct pci_dn *pdn; 1467781a868fSWei Yang 1468781a868fSWei Yang bus = pdev->bus; 1469781a868fSWei Yang hose = pci_bus_to_host(bus); 1470781a868fSWei Yang phb = hose->private_data; 147102639b0eSWei Yang pdn = pci_get_pdn(pdev); 1472781a868fSWei Yang 1473781a868fSWei Yang if (!pdev->is_physfn) 1474781a868fSWei Yang return; 1475781a868fSWei Yang 1476781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1477781a868fSWei Yang if (pe->parent_dev != pdev) 1478781a868fSWei Yang continue; 1479781a868fSWei Yang 1480781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1481781a868fSWei Yang 1482781a868fSWei Yang /* Remove from list */ 1483781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1484781a868fSWei Yang list_del(&pe->list); 1485781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1486781a868fSWei Yang 1487781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1488781a868fSWei Yang 14891e916772SGavin Shan pnv_ioda_free_pe(pe); 1490781a868fSWei Yang } 1491781a868fSWei Yang } 1492781a868fSWei Yang 1493781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1494781a868fSWei Yang { 1495781a868fSWei Yang struct pci_bus *bus; 1496781a868fSWei Yang struct pci_controller *hose; 1497781a868fSWei Yang struct pnv_phb *phb; 14981e916772SGavin Shan struct pnv_ioda_pe *pe; 1499781a868fSWei Yang struct pci_dn *pdn; 1500be283eebSWei Yang u16 num_vfs, i; 1501781a868fSWei Yang 1502781a868fSWei Yang bus = pdev->bus; 1503781a868fSWei Yang hose = pci_bus_to_host(bus); 1504781a868fSWei Yang phb = hose->private_data; 1505781a868fSWei Yang pdn = pci_get_pdn(pdev); 1506781a868fSWei Yang num_vfs = pdn->num_vfs; 1507781a868fSWei Yang 1508781a868fSWei Yang /* Release VF PEs */ 1509ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1510781a868fSWei Yang 1511781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1512ee8222feSWei Yang if (!pdn->m64_single_mode) 1513be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1514781a868fSWei Yang 1515781a868fSWei Yang /* Release M64 windows */ 1516ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1517781a868fSWei Yang 1518781a868fSWei Yang /* Release PE numbers */ 1519be283eebSWei Yang if (pdn->m64_single_mode) { 1520be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15211e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15221e916772SGavin Shan continue; 15231e916772SGavin Shan 15241e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15251e916772SGavin Shan pnv_ioda_free_pe(pe); 1526be283eebSWei Yang } 1527be283eebSWei Yang } else 1528be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1529be283eebSWei Yang /* Releasing pe_num_map */ 1530be283eebSWei Yang kfree(pdn->pe_num_map); 1531781a868fSWei Yang } 1532781a868fSWei Yang } 1533781a868fSWei Yang 1534781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1535781a868fSWei Yang struct pnv_ioda_pe *pe); 15365eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15370bd97167SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 15380bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, struct pci_bus *bus); 15390bd97167SAlexey Kardashevskiy 15405eada8a3SAlexey Kardashevskiy #endif 1541781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1542781a868fSWei Yang { 1543781a868fSWei Yang struct pci_bus *bus; 1544781a868fSWei Yang struct pci_controller *hose; 1545781a868fSWei Yang struct pnv_phb *phb; 1546781a868fSWei Yang struct pnv_ioda_pe *pe; 1547781a868fSWei Yang int pe_num; 1548781a868fSWei Yang u16 vf_index; 1549781a868fSWei Yang struct pci_dn *pdn; 1550781a868fSWei Yang 1551781a868fSWei Yang bus = pdev->bus; 1552781a868fSWei Yang hose = pci_bus_to_host(bus); 1553781a868fSWei Yang phb = hose->private_data; 1554781a868fSWei Yang pdn = pci_get_pdn(pdev); 1555781a868fSWei Yang 1556781a868fSWei Yang if (!pdev->is_physfn) 1557781a868fSWei Yang return; 1558781a868fSWei Yang 1559781a868fSWei Yang /* Reserve PE for each VF */ 1560781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1561be283eebSWei Yang if (pdn->m64_single_mode) 1562be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1563be283eebSWei Yang else 1564be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1565781a868fSWei Yang 1566781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1567781a868fSWei Yang pe->pe_number = pe_num; 1568781a868fSWei Yang pe->phb = phb; 1569781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1570781a868fSWei Yang pe->pbus = NULL; 1571781a868fSWei Yang pe->parent_dev = pdev; 1572781a868fSWei Yang pe->mve_number = -1; 1573781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1574781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1575781a868fSWei Yang 15761f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1577781a868fSWei Yang hose->global_number, pdev->bus->number, 1578781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1579781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1580781a868fSWei Yang 1581781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1582781a868fSWei Yang /* XXX What do we do here ? */ 15831e916772SGavin Shan pnv_ioda_free_pe(pe); 1584781a868fSWei Yang pe->pdev = NULL; 1585781a868fSWei Yang continue; 1586781a868fSWei Yang } 1587781a868fSWei Yang 1588781a868fSWei Yang /* Put PE to the list */ 1589781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1590781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1591781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1592781a868fSWei Yang 1593781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 15945eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15958f5b2734SAlexey Kardashevskiy iommu_register_group(&pe->table_group, 15968f5b2734SAlexey Kardashevskiy pe->phb->hose->global_number, pe->pe_number); 15970bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL); 15985eada8a3SAlexey Kardashevskiy #endif 1599781a868fSWei Yang } 1600781a868fSWei Yang } 1601781a868fSWei Yang 1602781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1603781a868fSWei Yang { 1604781a868fSWei Yang struct pci_bus *bus; 1605781a868fSWei Yang struct pci_controller *hose; 1606781a868fSWei Yang struct pnv_phb *phb; 16071e916772SGavin Shan struct pnv_ioda_pe *pe; 1608781a868fSWei Yang struct pci_dn *pdn; 1609781a868fSWei Yang int ret; 1610be283eebSWei Yang u16 i; 1611781a868fSWei Yang 1612781a868fSWei Yang bus = pdev->bus; 1613781a868fSWei Yang hose = pci_bus_to_host(bus); 1614781a868fSWei Yang phb = hose->private_data; 1615781a868fSWei Yang pdn = pci_get_pdn(pdev); 1616781a868fSWei Yang 1617781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1618b0331854SWei Yang if (!pdn->vfs_expanded) { 1619b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1620b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1621b0331854SWei Yang return -ENOSPC; 1622b0331854SWei Yang } 1623b0331854SWei Yang 1624ee8222feSWei Yang /* 1625ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1626ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1627ee8222feSWei Yang */ 1628ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1629ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1630ee8222feSWei Yang return -EBUSY; 1631ee8222feSWei Yang } 1632ee8222feSWei Yang 1633be283eebSWei Yang /* Allocating pe_num_map */ 1634be283eebSWei Yang if (pdn->m64_single_mode) 1635fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1636fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1637be283eebSWei Yang GFP_KERNEL); 1638be283eebSWei Yang else 1639be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1640be283eebSWei Yang 1641be283eebSWei Yang if (!pdn->pe_num_map) 1642be283eebSWei Yang return -ENOMEM; 1643be283eebSWei Yang 1644be283eebSWei Yang if (pdn->m64_single_mode) 1645be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1646be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1647be283eebSWei Yang 1648781a868fSWei Yang /* Calculate available PE for required VFs */ 1649be283eebSWei Yang if (pdn->m64_single_mode) { 1650be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16511e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16521e916772SGavin Shan if (!pe) { 1653be283eebSWei Yang ret = -EBUSY; 1654be283eebSWei Yang goto m64_failed; 1655be283eebSWei Yang } 16561e916772SGavin Shan 16571e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1658be283eebSWei Yang } 1659be283eebSWei Yang } else { 1660781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1661be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 166292b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1663781a868fSWei Yang 0, num_vfs, 0); 166492b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1665781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1666781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1667be283eebSWei Yang kfree(pdn->pe_num_map); 1668781a868fSWei Yang return -EBUSY; 1669781a868fSWei Yang } 1670be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1671781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1672be283eebSWei Yang } 1673be283eebSWei Yang pdn->num_vfs = num_vfs; 1674781a868fSWei Yang 1675781a868fSWei Yang /* Assign M64 window accordingly */ 167602639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1677781a868fSWei Yang if (ret) { 1678781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1679781a868fSWei Yang goto m64_failed; 1680781a868fSWei Yang } 1681781a868fSWei Yang 1682781a868fSWei Yang /* 1683781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1684781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1685781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1686781a868fSWei Yang */ 1687ee8222feSWei Yang if (!pdn->m64_single_mode) { 1688be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1689781a868fSWei Yang if (ret) 1690781a868fSWei Yang goto m64_failed; 1691781a868fSWei Yang } 169202639b0eSWei Yang } 1693781a868fSWei Yang 1694781a868fSWei Yang /* Setup VF PEs */ 1695781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1696781a868fSWei Yang 1697781a868fSWei Yang return 0; 1698781a868fSWei Yang 1699781a868fSWei Yang m64_failed: 1700be283eebSWei Yang if (pdn->m64_single_mode) { 1701be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 17021e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 17031e916772SGavin Shan continue; 17041e916772SGavin Shan 17051e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 17061e916772SGavin Shan pnv_ioda_free_pe(pe); 1707be283eebSWei Yang } 1708be283eebSWei Yang } else 1709be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1710be283eebSWei Yang 1711be283eebSWei Yang /* Releasing pe_num_map */ 1712be283eebSWei Yang kfree(pdn->pe_num_map); 1713781a868fSWei Yang 1714781a868fSWei Yang return ret; 1715781a868fSWei Yang } 1716781a868fSWei Yang 1717988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1718a8b2f828SGavin Shan { 1719781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1720781a868fSWei Yang 1721a8b2f828SGavin Shan /* Release PCI data */ 1722a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1723a8b2f828SGavin Shan return 0; 1724a8b2f828SGavin Shan } 1725a8b2f828SGavin Shan 1726988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1727a8b2f828SGavin Shan { 1728a8b2f828SGavin Shan /* Allocate PCI data */ 1729a8b2f828SGavin Shan add_dev_pci_data(pdev); 1730781a868fSWei Yang 1731ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1732a8b2f828SGavin Shan } 1733a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1734a8b2f828SGavin Shan 1735959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1736184cd4a3SBenjamin Herrenschmidt { 1737b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1738959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1739184cd4a3SBenjamin Herrenschmidt 1740959c9bddSGavin Shan /* 1741959c9bddSGavin Shan * The function can be called while the PE# 1742959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1743959c9bddSGavin Shan * case. 1744959c9bddSGavin Shan */ 1745959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1746959c9bddSGavin Shan return; 1747184cd4a3SBenjamin Herrenschmidt 1748959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1749cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17500617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1751b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17524617082eSAlexey Kardashevskiy /* 17534617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17544617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17554617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17564617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17574617082eSAlexey Kardashevskiy */ 1758184cd4a3SBenjamin Herrenschmidt } 1759184cd4a3SBenjamin Herrenschmidt 17608e3f1b1dSRussell Currey /* 17618e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17628e3f1b1dSRussell Currey * 17638e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17648e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17658e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17668e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17678e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17688e3f1b1dSRussell Currey * devices in TVE#0. 17698e3f1b1dSRussell Currey * 17708e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17718e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17728e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17738e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17748e3f1b1dSRussell Currey * 17758e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17768e3f1b1dSRussell Currey */ 17778e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17788e3f1b1dSRussell Currey { 17798e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17808e3f1b1dSRussell Currey struct page *table_pages; 17818e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 17828e3f1b1dSRussell Currey __be64 *tces; 17838e3f1b1dSRussell Currey s64 rc; 17848e3f1b1dSRussell Currey 17858e3f1b1dSRussell Currey /* 17868e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 17878e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 17888e3f1b1dSRussell Currey */ 17898e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 17908e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 17918e3f1b1dSRussell Currey table_size = tce_count << 3; 17928e3f1b1dSRussell Currey 17938e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 17948e3f1b1dSRussell Currey table_size = PAGE_SIZE; 17958e3f1b1dSRussell Currey 17968e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 17978e3f1b1dSRussell Currey get_order(table_size)); 17988e3f1b1dSRussell Currey if (!table_pages) 17998e3f1b1dSRussell Currey goto err; 18008e3f1b1dSRussell Currey 18018e3f1b1dSRussell Currey tces = page_address(table_pages); 18028e3f1b1dSRussell Currey if (!tces) 18038e3f1b1dSRussell Currey goto err; 18048e3f1b1dSRussell Currey 18058e3f1b1dSRussell Currey memset(tces, 0, table_size); 18068e3f1b1dSRussell Currey 18078e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18088e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18098e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18108e3f1b1dSRussell Currey } 18118e3f1b1dSRussell Currey 18128e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18138e3f1b1dSRussell Currey pe->pe_number, 18148e3f1b1dSRussell Currey /* reconfigure window 0 */ 18158e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18168e3f1b1dSRussell Currey 1, 18178e3f1b1dSRussell Currey __pa(tces), 18188e3f1b1dSRussell Currey table_size, 18198e3f1b1dSRussell Currey 1 << tce_order); 18208e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18218e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18228e3f1b1dSRussell Currey return 0; 18238e3f1b1dSRussell Currey } 18248e3f1b1dSRussell Currey err: 18258e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18268e3f1b1dSRussell Currey return -EIO; 18278e3f1b1dSRussell Currey } 18288e3f1b1dSRussell Currey 18292d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 18302d6ad41bSChristoph Hellwig u64 dma_mask) 1831cd15b048SBenjamin Herrenschmidt { 1832763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1833763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1834cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1835cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1836cd15b048SBenjamin Herrenschmidt 1837cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1838b511cdd1SAlexey Kardashevskiy return false; 1839cd15b048SBenjamin Herrenschmidt 1840cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1841cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 18422d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 18432d6ad41bSChristoph Hellwig if (dma_mask >= top) 18442d6ad41bSChristoph Hellwig return true; 1845cd15b048SBenjamin Herrenschmidt } 1846cd15b048SBenjamin Herrenschmidt 18478e3f1b1dSRussell Currey /* 18488e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18498e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18508e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18518e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18528e3f1b1dSRussell Currey */ 18538e3f1b1dSRussell Currey if (dma_mask >> 32 && 18548e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1855661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1856661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 18578e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18588e3f1b1dSRussell Currey /* Configure the bypass mode */ 18592d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18608e3f1b1dSRussell Currey if (rc) 1861b511cdd1SAlexey Kardashevskiy return false; 18628e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18630617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 18642d6ad41bSChristoph Hellwig return true; 1865cd15b048SBenjamin Herrenschmidt } 1866cd15b048SBenjamin Herrenschmidt 18672d6ad41bSChristoph Hellwig return false; 1868fe7e85c6SGavin Shan } 1869fe7e85c6SGavin Shan 18705eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 187174251fe2SBenjamin Herrenschmidt { 187274251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 187374251fe2SBenjamin Herrenschmidt 187474251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1875b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 18760617fc0cSChristoph Hellwig dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1877dff4a39eSGavin Shan 18785c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 18795eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 188074251fe2SBenjamin Herrenschmidt } 188174251fe2SBenjamin Herrenschmidt } 188274251fe2SBenjamin Herrenschmidt 1883fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1884fd141d1aSBenjamin Herrenschmidt bool real_mode) 1885fd141d1aSBenjamin Herrenschmidt { 1886fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1887fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1888fd141d1aSBenjamin Herrenschmidt } 1889fd141d1aSBenjamin Herrenschmidt 1890a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1891decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 18924cce9550SGavin Shan { 18930eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 18940eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 18950eaf4defSAlexey Kardashevskiy next); 18960eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1897b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1898fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 18994cce9550SGavin Shan unsigned long start, end, inc; 19004cce9550SGavin Shan 1901decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1902decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1903decbda25SAlexey Kardashevskiy npages - 1); 19044cce9550SGavin Shan 19054cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19064cce9550SGavin Shan start |= (1ull << 63); 19074cce9550SGavin Shan end |= (1ull << 63); 19084cce9550SGavin Shan inc = 16; 19094cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19104cce9550SGavin Shan 19114cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19124cce9550SGavin Shan while (start <= end) { 19138e0a1611SAlexey Kardashevskiy if (rm) 1914001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19158e0a1611SAlexey Kardashevskiy else 1916001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1917001ff2eeSMichael Ellerman 19184cce9550SGavin Shan start += inc; 19194cce9550SGavin Shan } 19204cce9550SGavin Shan 19214cce9550SGavin Shan /* 19224cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19234cce9550SGavin Shan * and we don't care on free() 19244cce9550SGavin Shan */ 19254cce9550SGavin Shan } 19264cce9550SGavin Shan 1927decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1928decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1929decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 193000085f1eSKrzysztof Kozlowski unsigned long attrs) 1931decbda25SAlexey Kardashevskiy { 1932decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1933decbda25SAlexey Kardashevskiy attrs); 1934decbda25SAlexey Kardashevskiy 193508acce1cSBenjamin Herrenschmidt if (!ret) 1936a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1937decbda25SAlexey Kardashevskiy 1938decbda25SAlexey Kardashevskiy return ret; 1939decbda25SAlexey Kardashevskiy } 1940decbda25SAlexey Kardashevskiy 194105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 194205c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 194305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 194405c6cfb9SAlexey Kardashevskiy { 1945a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 194605c6cfb9SAlexey Kardashevskiy 194708acce1cSBenjamin Herrenschmidt if (!ret) 1948a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 194905c6cfb9SAlexey Kardashevskiy 195005c6cfb9SAlexey Kardashevskiy return ret; 195105c6cfb9SAlexey Kardashevskiy } 1952a540aa56SAlexey Kardashevskiy 1953a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 1954a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 1955a540aa56SAlexey Kardashevskiy { 1956a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 1957a540aa56SAlexey Kardashevskiy 1958a540aa56SAlexey Kardashevskiy if (!ret) 1959a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 1960a540aa56SAlexey Kardashevskiy 1961a540aa56SAlexey Kardashevskiy return ret; 1962a540aa56SAlexey Kardashevskiy } 196305c6cfb9SAlexey Kardashevskiy #endif 196405c6cfb9SAlexey Kardashevskiy 1965decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1966decbda25SAlexey Kardashevskiy long npages) 1967decbda25SAlexey Kardashevskiy { 1968decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1969decbda25SAlexey Kardashevskiy 1970a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1971decbda25SAlexey Kardashevskiy } 1972decbda25SAlexey Kardashevskiy 1973da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1974decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 197505c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 197605c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 1977a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 1978090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 197905c6cfb9SAlexey Kardashevskiy #endif 1980decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1981da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1982da004c36SAlexey Kardashevskiy }; 1983da004c36SAlexey Kardashevskiy 1984a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1985a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1986a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1987bef9253fSAlexey Kardashevskiy 19886b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 19890bbcdb43SAlexey Kardashevskiy { 1990fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1991a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 19920bbcdb43SAlexey Kardashevskiy 19930bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 19940bbcdb43SAlexey Kardashevskiy if (rm) 1995001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 19960bbcdb43SAlexey Kardashevskiy else 1997001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 19980bbcdb43SAlexey Kardashevskiy } 19990bbcdb43SAlexey Kardashevskiy 2000a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20015780fb04SAlexey Kardashevskiy { 20025780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2003fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2004a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20055780fb04SAlexey Kardashevskiy 20065780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2007001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20085780fb04SAlexey Kardashevskiy } 20095780fb04SAlexey Kardashevskiy 2010fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2011fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2012fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20134cce9550SGavin Shan { 20144d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20154cce9550SGavin Shan unsigned long start, end, inc; 20164cce9550SGavin Shan 20174cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2018a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2019fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20204cce9550SGavin Shan end = start; 20214cce9550SGavin Shan 20224cce9550SGavin Shan /* Figure out the start, end and step */ 2023decbda25SAlexey Kardashevskiy start |= (index << shift); 2024decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2025b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20264cce9550SGavin Shan mb(); 20274cce9550SGavin Shan 20284cce9550SGavin Shan while (start <= end) { 20298e0a1611SAlexey Kardashevskiy if (rm) 2030001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 20318e0a1611SAlexey Kardashevskiy else 2032001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 20334cce9550SGavin Shan start += inc; 20344cce9550SGavin Shan } 20354cce9550SGavin Shan } 20364cce9550SGavin Shan 2037f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2038f0228c41SBenjamin Herrenschmidt { 2039f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2040f0228c41SBenjamin Herrenschmidt 2041f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2042f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2043f0228c41SBenjamin Herrenschmidt else 2044f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2045f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2046f0228c41SBenjamin Herrenschmidt } 2047f0228c41SBenjamin Herrenschmidt 2048e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2049e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2050e57080f1SAlexey Kardashevskiy { 2051e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2052e57080f1SAlexey Kardashevskiy 2053a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2054e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2055e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2056f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2057f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2058f0228c41SBenjamin Herrenschmidt 2059616badd2SAlistair Popple /* 2060616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2061616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2062616badd2SAlistair Popple * should go via the OPAL call. 2063616badd2SAlistair Popple */ 2064616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 20650bbcdb43SAlexey Kardashevskiy /* 20660bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 20670bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 20680bbcdb43SAlexey Kardashevskiy * the entire cache for it. 20690bbcdb43SAlexey Kardashevskiy */ 2070f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20715d2aa710SAlistair Popple continue; 20725d2aa710SAlistair Popple } 2073f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2074f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 207585674868SAlexey Kardashevskiy index, npages); 2076f0228c41SBenjamin Herrenschmidt else 2077f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2078f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2079f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2080f0228c41SBenjamin Herrenschmidt index << shift, npages); 2081e57080f1SAlexey Kardashevskiy } 2082e57080f1SAlexey Kardashevskiy } 2083e57080f1SAlexey Kardashevskiy 20846b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20856b3d12a9SAlistair Popple { 20866b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 20876b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20886b3d12a9SAlistair Popple else 20896b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 20906b3d12a9SAlistair Popple } 20916b3d12a9SAlistair Popple 2092decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2093decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2094decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 209500085f1eSKrzysztof Kozlowski unsigned long attrs) 20964cce9550SGavin Shan { 2097decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2098decbda25SAlexey Kardashevskiy attrs); 20994cce9550SGavin Shan 210008acce1cSBenjamin Herrenschmidt if (!ret) 2101decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2102decbda25SAlexey Kardashevskiy 2103decbda25SAlexey Kardashevskiy return ret; 2104decbda25SAlexey Kardashevskiy } 2105decbda25SAlexey Kardashevskiy 210605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 210705c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 210805c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 210905c6cfb9SAlexey Kardashevskiy { 2110a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 211105c6cfb9SAlexey Kardashevskiy 211208acce1cSBenjamin Herrenschmidt if (!ret) 211305c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 211405c6cfb9SAlexey Kardashevskiy 211505c6cfb9SAlexey Kardashevskiy return ret; 211605c6cfb9SAlexey Kardashevskiy } 2117a540aa56SAlexey Kardashevskiy 2118a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2119a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2120a540aa56SAlexey Kardashevskiy { 2121a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 2122a540aa56SAlexey Kardashevskiy 2123a540aa56SAlexey Kardashevskiy if (!ret) 2124a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2125a540aa56SAlexey Kardashevskiy 2126a540aa56SAlexey Kardashevskiy return ret; 2127a540aa56SAlexey Kardashevskiy } 212805c6cfb9SAlexey Kardashevskiy #endif 212905c6cfb9SAlexey Kardashevskiy 2130decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2131decbda25SAlexey Kardashevskiy long npages) 2132decbda25SAlexey Kardashevskiy { 2133decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2134decbda25SAlexey Kardashevskiy 2135decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 21364cce9550SGavin Shan } 21374cce9550SGavin Shan 2138da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2139decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 214005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 214105c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2142a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 2143090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 214405c6cfb9SAlexey Kardashevskiy #endif 2145decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2146da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2147da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 2148da004c36SAlexey Kardashevskiy }; 2149da004c36SAlexey Kardashevskiy 2150801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2151801846d1SGavin Shan { 2152801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2153801846d1SGavin Shan 2154801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2155801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2156801846d1SGavin Shan */ 2157801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2158801846d1SGavin Shan return 0; 2159801846d1SGavin Shan 2160801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2161801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2162801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2163801846d1SGavin Shan *weight += 3; 2164801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2165801846d1SGavin Shan *weight += 15; 2166801846d1SGavin Shan else 2167801846d1SGavin Shan *weight += 10; 2168801846d1SGavin Shan 2169801846d1SGavin Shan return 0; 2170801846d1SGavin Shan } 2171801846d1SGavin Shan 2172801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2173801846d1SGavin Shan { 2174801846d1SGavin Shan unsigned int weight = 0; 2175801846d1SGavin Shan 2176801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2177801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2178801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2179801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2180801846d1SGavin Shan return weight; 2181801846d1SGavin Shan } 2182801846d1SGavin Shan #endif 2183801846d1SGavin Shan 2184801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2185801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2186801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2187801846d1SGavin Shan struct pci_dev *pdev; 2188801846d1SGavin Shan 2189801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2190801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2191801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2192801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2193801846d1SGavin Shan } 2194801846d1SGavin Shan 2195801846d1SGavin Shan return weight; 2196801846d1SGavin Shan } 2197801846d1SGavin Shan 2198b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 21992b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2200184cd4a3SBenjamin Herrenschmidt { 2201184cd4a3SBenjamin Herrenschmidt 2202184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2203184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22042b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22052b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2206184cd4a3SBenjamin Herrenschmidt int64_t rc; 2207184cd4a3SBenjamin Herrenschmidt void *addr; 2208184cd4a3SBenjamin Herrenschmidt 2209184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2210184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2211184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22122b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22132b923ed1SGavin Shan if (!weight) 22142b923ed1SGavin Shan return; 2215184cd4a3SBenjamin Herrenschmidt 22162b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22172b923ed1SGavin Shan &total_weight); 22182b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22192b923ed1SGavin Shan if (!segs) 22202b923ed1SGavin Shan segs = 1; 22212b923ed1SGavin Shan 22222b923ed1SGavin Shan /* 22232b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22242b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22252b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22262b923ed1SGavin Shan * is allocated successfully. 22272b923ed1SGavin Shan */ 22282b923ed1SGavin Shan do { 22292b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22302b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22312b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22322b923ed1SGavin Shan IODA_INVALID_PE) 22332b923ed1SGavin Shan avail++; 22342b923ed1SGavin Shan } 22352b923ed1SGavin Shan 22362b923ed1SGavin Shan if (avail == segs) 22372b923ed1SGavin Shan goto found; 22382b923ed1SGavin Shan } 22392b923ed1SGavin Shan } while (--segs); 22402b923ed1SGavin Shan 22412b923ed1SGavin Shan if (!segs) { 22422b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 22432b923ed1SGavin Shan return; 22442b923ed1SGavin Shan } 22452b923ed1SGavin Shan 22462b923ed1SGavin Shan found: 22470eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 224882eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 224982eae1afSAlexey Kardashevskiy return; 225082eae1afSAlexey Kardashevskiy 2251b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2252b348aa65SAlexey Kardashevskiy pe->pe_number); 22530eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2254c5773822SAlexey Kardashevskiy 2255184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 22562b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 22572b923ed1SGavin Shan weight, total_weight, base, segs); 2258184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2259acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2260acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2261184cd4a3SBenjamin Herrenschmidt 2262184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2263184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2264184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2265184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2266acce971cSGavin Shan * 2267acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2268acce971cSGavin Shan * bytes 2269184cd4a3SBenjamin Herrenschmidt */ 2270acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2271184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2272acce971cSGavin Shan get_order(tce32_segsz * segs)); 2273184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2274184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2275184cd4a3SBenjamin Herrenschmidt goto fail; 2276184cd4a3SBenjamin Herrenschmidt } 2277184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2278acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2279184cd4a3SBenjamin Herrenschmidt 2280184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2281184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2282184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2283184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2284184cd4a3SBenjamin Herrenschmidt base + i, 1, 2285acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2286acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2287184cd4a3SBenjamin Herrenschmidt if (rc) { 22881e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 22891e496391SJoe Perches rc); 2290184cd4a3SBenjamin Herrenschmidt goto fail; 2291184cd4a3SBenjamin Herrenschmidt } 2292184cd4a3SBenjamin Herrenschmidt } 2293184cd4a3SBenjamin Herrenschmidt 22942b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 22952b923ed1SGavin Shan for (i = base; i < base + segs; i++) 22962b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 22972b923ed1SGavin Shan 2298184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2299acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2300acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2301acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2302184cd4a3SBenjamin Herrenschmidt 2303da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23044793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23054793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2306201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, phb->hose->node, 0, 0); 2307184cd4a3SBenjamin Herrenschmidt 2308f21b0a45SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 23095eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 231074251fe2SBenjamin Herrenschmidt 2311184cd4a3SBenjamin Herrenschmidt return; 2312184cd4a3SBenjamin Herrenschmidt fail: 2313184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2314184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2315acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23160eaf4defSAlexey Kardashevskiy if (tbl) { 23170eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2318e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23190eaf4defSAlexey Kardashevskiy } 2320184cd4a3SBenjamin Herrenschmidt } 2321184cd4a3SBenjamin Herrenschmidt 232243cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 232343cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 232443cb60abSAlexey Kardashevskiy { 232543cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 232643cb60abSAlexey Kardashevskiy table_group); 232743cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 232843cb60abSAlexey Kardashevskiy int64_t rc; 2329bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2330bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 233143cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 233243cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 233343cb60abSAlexey Kardashevskiy 23341e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 23351e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 233643cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 233743cb60abSAlexey Kardashevskiy 233843cb60abSAlexey Kardashevskiy /* 233943cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 234043cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 234143cb60abSAlexey Kardashevskiy */ 234243cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 234343cb60abSAlexey Kardashevskiy pe->pe_number, 23444793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2345bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 234643cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2347bbb845c4SAlexey Kardashevskiy size << 3, 234843cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 234943cb60abSAlexey Kardashevskiy if (rc) { 23501e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 235143cb60abSAlexey Kardashevskiy return rc; 235243cb60abSAlexey Kardashevskiy } 235343cb60abSAlexey Kardashevskiy 235443cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 235543cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2356ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 235743cb60abSAlexey Kardashevskiy 235843cb60abSAlexey Kardashevskiy return 0; 235943cb60abSAlexey Kardashevskiy } 236043cb60abSAlexey Kardashevskiy 2361c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2362cd15b048SBenjamin Herrenschmidt { 2363cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2364cd15b048SBenjamin Herrenschmidt int64_t rc; 2365cd15b048SBenjamin Herrenschmidt 2366cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2367cd15b048SBenjamin Herrenschmidt if (enable) { 2368cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2369cd15b048SBenjamin Herrenschmidt 2370cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2371cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2372cd15b048SBenjamin Herrenschmidt pe->pe_number, 2373cd15b048SBenjamin Herrenschmidt window_id, 2374cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2375cd15b048SBenjamin Herrenschmidt top); 2376cd15b048SBenjamin Herrenschmidt } else { 2377cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2378cd15b048SBenjamin Herrenschmidt pe->pe_number, 2379cd15b048SBenjamin Herrenschmidt window_id, 2380cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2381cd15b048SBenjamin Herrenschmidt 0); 2382cd15b048SBenjamin Herrenschmidt } 2383cd15b048SBenjamin Herrenschmidt if (rc) 2384cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2385cd15b048SBenjamin Herrenschmidt else 2386cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2387cd15b048SBenjamin Herrenschmidt } 2388cd15b048SBenjamin Herrenschmidt 23894793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 23904793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2391090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 23924793d65dSAlexey Kardashevskiy { 23934793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 23944793d65dSAlexey Kardashevskiy table_group); 23954793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 23964793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 23974793d65dSAlexey Kardashevskiy long ret; 23984793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 23994793d65dSAlexey Kardashevskiy 24004793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24014793d65dSAlexey Kardashevskiy if (!tbl) 24024793d65dSAlexey Kardashevskiy return -ENOMEM; 24034793d65dSAlexey Kardashevskiy 240411edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 240511edf116SAlexey Kardashevskiy 24064793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24074793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 2408090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 24094793d65dSAlexey Kardashevskiy if (ret) { 2410e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24114793d65dSAlexey Kardashevskiy return ret; 24124793d65dSAlexey Kardashevskiy } 24134793d65dSAlexey Kardashevskiy 24144793d65dSAlexey Kardashevskiy *ptbl = tbl; 24154793d65dSAlexey Kardashevskiy 24164793d65dSAlexey Kardashevskiy return 0; 24174793d65dSAlexey Kardashevskiy } 24184793d65dSAlexey Kardashevskiy 241946d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 242046d3e1e1SAlexey Kardashevskiy { 242146d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 242246d3e1e1SAlexey Kardashevskiy long rc; 2423201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 242446d3e1e1SAlexey Kardashevskiy 2425bb005455SNishanth Aravamudan /* 2426fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2427fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2428fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2429fa144869SNishanth Aravamudan */ 2430fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2431fa144869SNishanth Aravamudan 2432fa144869SNishanth Aravamudan /* 2433bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2434bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2435bb005455SNishanth Aravamudan * cause errors later. 2436bb005455SNishanth Aravamudan */ 2437201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 2438bb005455SNishanth Aravamudan 2439201ed7f3SAlexey Kardashevskiy /* 2440201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 2441201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 2442201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 2443201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 2444201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 2445201ed7f3SAlexey Kardashevskiy */ 2446201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 2447201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 2448201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 2449201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 2450201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 2451201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 2452201ed7f3SAlexey Kardashevskiy 2453201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 2454201ed7f3SAlexey Kardashevskiy levels += 1; 2455201ed7f3SAlexey Kardashevskiy /* 2456201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 2457201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 2458201ed7f3SAlexey Kardashevskiy */ 2459201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 2460201ed7f3SAlexey Kardashevskiy 2461201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 2462201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 246346d3e1e1SAlexey Kardashevskiy if (rc) { 246446d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 246546d3e1e1SAlexey Kardashevskiy rc); 246646d3e1e1SAlexey Kardashevskiy return rc; 246746d3e1e1SAlexey Kardashevskiy } 246846d3e1e1SAlexey Kardashevskiy 2469201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 2470201ed7f3SAlexey Kardashevskiy res_start = 0; 2471201ed7f3SAlexey Kardashevskiy res_end = 0; 2472201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 2473201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 2474201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 2475201ed7f3SAlexey Kardashevskiy } 2476201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end); 247746d3e1e1SAlexey Kardashevskiy 247846d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 247946d3e1e1SAlexey Kardashevskiy if (rc) { 248046d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 248146d3e1e1SAlexey Kardashevskiy rc); 2482e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 248346d3e1e1SAlexey Kardashevskiy return rc; 248446d3e1e1SAlexey Kardashevskiy } 248546d3e1e1SAlexey Kardashevskiy 248646d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 248746d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 248846d3e1e1SAlexey Kardashevskiy 24895636427dSAlexey Kardashevskiy /* 24905636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 24915636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 24925636427dSAlexey Kardashevskiy * from VFIO so do it here. 24935636427dSAlexey Kardashevskiy */ 24945636427dSAlexey Kardashevskiy if (pe->pdev) 24955636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 24965636427dSAlexey Kardashevskiy 249746d3e1e1SAlexey Kardashevskiy return 0; 249846d3e1e1SAlexey Kardashevskiy } 249946d3e1e1SAlexey Kardashevskiy 2500b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2501b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2502b5926430SAlexey Kardashevskiy int num) 2503b5926430SAlexey Kardashevskiy { 2504b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2505b5926430SAlexey Kardashevskiy table_group); 2506b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2507b5926430SAlexey Kardashevskiy long ret; 2508b5926430SAlexey Kardashevskiy 2509b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2510b5926430SAlexey Kardashevskiy 2511b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2512b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2513b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2514b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2515b5926430SAlexey Kardashevskiy if (ret) 2516b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2517b5926430SAlexey Kardashevskiy else 2518ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2519b5926430SAlexey Kardashevskiy 2520b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2521b5926430SAlexey Kardashevskiy 2522b5926430SAlexey Kardashevskiy return ret; 2523b5926430SAlexey Kardashevskiy } 2524b5926430SAlexey Kardashevskiy #endif 2525b5926430SAlexey Kardashevskiy 2526f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 25270bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 252800547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 252900547193SAlexey Kardashevskiy { 253000547193SAlexey Kardashevskiy unsigned long bytes = 0; 253100547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 253200547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 253300547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 253400547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 253500547193SAlexey Kardashevskiy unsigned long direct_table_size; 253600547193SAlexey Kardashevskiy 253700547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 253800547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 253900547193SAlexey Kardashevskiy return 0; 254000547193SAlexey Kardashevskiy 254100547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 254200547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 254300547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 254400547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 254500547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 254600547193SAlexey Kardashevskiy 254700547193SAlexey Kardashevskiy for ( ; levels; --levels) { 254800547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 254900547193SAlexey Kardashevskiy 255000547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 255100547193SAlexey Kardashevskiy tce_table_size <<= 3; 2552e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2553e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 255400547193SAlexey Kardashevskiy } 255500547193SAlexey Kardashevskiy 2556090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2557090bad39SAlexey Kardashevskiy } 2558090bad39SAlexey Kardashevskiy 2559090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2560090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2561090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2562090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2563090bad39SAlexey Kardashevskiy { 256411f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 2565090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 256611f5acceSAlexey Kardashevskiy 256711f5acceSAlexey Kardashevskiy if (!ret) 256811f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 256911f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 257011f5acceSAlexey Kardashevskiy return ret; 257100547193SAlexey Kardashevskiy } 257200547193SAlexey Kardashevskiy 2573f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2574cd15b048SBenjamin Herrenschmidt { 2575f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2576f87a8864SAlexey Kardashevskiy table_group); 257746d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 257846d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2579cd15b048SBenjamin Herrenschmidt 2580f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 258146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2582db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25835eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 25845636427dSAlexey Kardashevskiy else if (pe->pdev) 25855636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 2586e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2587cd15b048SBenjamin Herrenschmidt } 2588cd15b048SBenjamin Herrenschmidt 2589f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2590f87a8864SAlexey Kardashevskiy { 2591f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2592f87a8864SAlexey Kardashevskiy table_group); 2593f87a8864SAlexey Kardashevskiy 259446d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2595db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25965eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2597f87a8864SAlexey Kardashevskiy } 2598f87a8864SAlexey Kardashevskiy 2599f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 260000547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2601090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 26024793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 26034793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2604f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2605f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2606f87a8864SAlexey Kardashevskiy }; 2607b5cb9ab1SAlexey Kardashevskiy 26085eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe, 26090bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, 26105eada8a3SAlexey Kardashevskiy struct pci_bus *bus) 26115eada8a3SAlexey Kardashevskiy { 26125eada8a3SAlexey Kardashevskiy struct pci_dev *dev; 26135eada8a3SAlexey Kardashevskiy 26145eada8a3SAlexey Kardashevskiy list_for_each_entry(dev, &bus->devices, bus_list) { 26150bd97167SAlexey Kardashevskiy iommu_add_device(table_group, &dev->dev); 26165eada8a3SAlexey Kardashevskiy 26175eada8a3SAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 26185eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, 26190bd97167SAlexey Kardashevskiy table_group, dev->subordinate); 26205eada8a3SAlexey Kardashevskiy } 26215eada8a3SAlexey Kardashevskiy } 26225eada8a3SAlexey Kardashevskiy 26230bd97167SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 26240bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, struct pci_bus *bus) 26255eada8a3SAlexey Kardashevskiy { 26265eada8a3SAlexey Kardashevskiy 26275eada8a3SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 26280bd97167SAlexey Kardashevskiy iommu_add_device(table_group, &pe->pdev->dev); 26290bd97167SAlexey Kardashevskiy 26300bd97167SAlexey Kardashevskiy if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus) 26310bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group, 26320bd97167SAlexey Kardashevskiy bus); 26335eada8a3SAlexey Kardashevskiy } 26345eada8a3SAlexey Kardashevskiy 26350bd97167SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 26360bd97167SAlexey Kardashevskiy 2637b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2638b5cb9ab1SAlexey Kardashevskiy { 26390bd97167SAlexey Kardashevskiy struct pci_controller *hose; 2640b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 26410bd97167SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 2642b5cb9ab1SAlexey Kardashevskiy 2643b5cb9ab1SAlexey Kardashevskiy /* 26445eada8a3SAlexey Kardashevskiy * There are 4 types of PEs: 26455eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS: a downstream port with an adapter, 26465eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 26475eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it, 26485eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 26495eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_VF: a SRIOV virtual function, 26505eada8a3SAlexey Kardashevskiy * created from pnv_pcibios_sriov_enable(); 26515eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_DEV: an NPU or OCAPI device, 26525eada8a3SAlexey Kardashevskiy * created from pnv_pci_ioda_fixup(). 26535eada8a3SAlexey Kardashevskiy * 26545eada8a3SAlexey Kardashevskiy * Normally a PE is represented by an IOMMU group, however for 26555eada8a3SAlexey Kardashevskiy * devices with side channels the groups need to be more strict. 26565eada8a3SAlexey Kardashevskiy */ 26575eada8a3SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 26585eada8a3SAlexey Kardashevskiy phb = hose->private_data; 26595eada8a3SAlexey Kardashevskiy 26606bca5159SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK || 26616bca5159SFrederic Barrat phb->type == PNV_PHB_NPU_OCAPI) 26625eada8a3SAlexey Kardashevskiy continue; 26635eada8a3SAlexey Kardashevskiy 26640bd97167SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 26650bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group; 26660bd97167SAlexey Kardashevskiy 26670bd97167SAlexey Kardashevskiy table_group = pnv_try_setup_npu_table_group(pe); 26680bd97167SAlexey Kardashevskiy if (!table_group) { 26690bd97167SAlexey Kardashevskiy if (!pnv_pci_ioda_pe_dma_weight(pe)) 26700bd97167SAlexey Kardashevskiy continue; 26710bd97167SAlexey Kardashevskiy 26720bd97167SAlexey Kardashevskiy table_group = &pe->table_group; 26730bd97167SAlexey Kardashevskiy iommu_register_group(&pe->table_group, 26740bd97167SAlexey Kardashevskiy pe->phb->hose->global_number, 26750bd97167SAlexey Kardashevskiy pe->pe_number); 26760bd97167SAlexey Kardashevskiy } 26770bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe, table_group, 26780bd97167SAlexey Kardashevskiy pe->pbus); 26790bd97167SAlexey Kardashevskiy } 26805eada8a3SAlexey Kardashevskiy } 26815eada8a3SAlexey Kardashevskiy 26825eada8a3SAlexey Kardashevskiy /* 2683b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2684b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2685b5cb9ab1SAlexey Kardashevskiy */ 26860bd97167SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 26870bd97167SAlexey Kardashevskiy unsigned long pgsizes; 26880bd97167SAlexey Kardashevskiy 2689b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2690b5cb9ab1SAlexey Kardashevskiy 26917f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2692b5cb9ab1SAlexey Kardashevskiy continue; 2693b5cb9ab1SAlexey Kardashevskiy 26940bd97167SAlexey Kardashevskiy pgsizes = pnv_ioda_parse_tce_sizes(phb); 2695b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 26960bd97167SAlexey Kardashevskiy /* 26970bd97167SAlexey Kardashevskiy * IODA2 bridges get this set up from 26980bd97167SAlexey Kardashevskiy * pci_controller_ops::setup_bridge but NPU bridges 26990bd97167SAlexey Kardashevskiy * do not have this hook defined so we do it here. 27000bd97167SAlexey Kardashevskiy */ 27010bd97167SAlexey Kardashevskiy pe->table_group.pgsizes = pgsizes; 27020bd97167SAlexey Kardashevskiy pnv_npu_compound_attach(pe); 2703b5cb9ab1SAlexey Kardashevskiy } 2704b5cb9ab1SAlexey Kardashevskiy } 2705b5cb9ab1SAlexey Kardashevskiy } 2706b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2707b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2708f87a8864SAlexey Kardashevskiy #endif 2709f87a8864SAlexey Kardashevskiy 27107ef73cd3SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 27117ef73cd3SAlexey Kardashevskiy { 27127ef73cd3SAlexey Kardashevskiy struct pci_controller *hose = phb->hose; 27137ef73cd3SAlexey Kardashevskiy struct device_node *dn = hose->dn; 27147ef73cd3SAlexey Kardashevskiy unsigned long mask = 0; 27157ef73cd3SAlexey Kardashevskiy int i, rc, count; 27167ef73cd3SAlexey Kardashevskiy u32 val; 27177ef73cd3SAlexey Kardashevskiy 27187ef73cd3SAlexey Kardashevskiy count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 27197ef73cd3SAlexey Kardashevskiy if (count <= 0) { 27207ef73cd3SAlexey Kardashevskiy mask = SZ_4K | SZ_64K; 27217ef73cd3SAlexey Kardashevskiy /* Add 16M for POWER8 by default */ 27227ef73cd3SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_ARCH_207S) && 27237ef73cd3SAlexey Kardashevskiy !cpu_has_feature(CPU_FTR_ARCH_300)) 272400c376fdSAlexey Kardashevskiy mask |= SZ_16M | SZ_256M; 27257ef73cd3SAlexey Kardashevskiy return mask; 27267ef73cd3SAlexey Kardashevskiy } 27277ef73cd3SAlexey Kardashevskiy 27287ef73cd3SAlexey Kardashevskiy for (i = 0; i < count; i++) { 27297ef73cd3SAlexey Kardashevskiy rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 27307ef73cd3SAlexey Kardashevskiy i, &val); 27317ef73cd3SAlexey Kardashevskiy if (rc == 0) 27327ef73cd3SAlexey Kardashevskiy mask |= 1ULL << val; 27337ef73cd3SAlexey Kardashevskiy } 27347ef73cd3SAlexey Kardashevskiy 27357ef73cd3SAlexey Kardashevskiy return mask; 27367ef73cd3SAlexey Kardashevskiy } 27377ef73cd3SAlexey Kardashevskiy 2738373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2739373f5657SGavin Shan struct pnv_ioda_pe *pe) 2740373f5657SGavin Shan { 2741373f5657SGavin Shan int64_t rc; 2742373f5657SGavin Shan 2743ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2744ccd1c191SGavin Shan return; 2745ccd1c191SGavin Shan 2746f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2747f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2748f87a8864SAlexey Kardashevskiy 2749373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2750373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2751aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2752373f5657SGavin Shan 2753e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 27544793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 27554793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 27564793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 27574793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 27584793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 27597ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2760e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2761e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2762e5aad1e6SAlexey Kardashevskiy #endif 2763e5aad1e6SAlexey Kardashevskiy 276446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2765801846d1SGavin Shan if (rc) 276646d3e1e1SAlexey Kardashevskiy return; 276746d3e1e1SAlexey Kardashevskiy 276820f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 27695eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2770373f5657SGavin Shan } 2771373f5657SGavin Shan 27724ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2773137436c9SGavin Shan { 2774137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2775137436c9SGavin Shan ioda.irq_chip); 2776137436c9SGavin Shan 27774ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 27784ee11c1aSSuresh Warrier } 27794ee11c1aSSuresh Warrier 27804ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 27814ee11c1aSSuresh Warrier { 27824ee11c1aSSuresh Warrier int64_t rc; 27834ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 27844ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 27854ee11c1aSSuresh Warrier 27864ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2787137436c9SGavin Shan WARN_ON_ONCE(rc); 2788137436c9SGavin Shan 2789137436c9SGavin Shan icp_native_eoi(d); 2790137436c9SGavin Shan } 2791137436c9SGavin Shan 2792fd9a1c26SIan Munsie 2793f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2794fd9a1c26SIan Munsie { 2795fd9a1c26SIan Munsie struct irq_data *idata; 2796fd9a1c26SIan Munsie struct irq_chip *ichip; 2797fd9a1c26SIan Munsie 2798fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2799fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2800fd9a1c26SIan Munsie return; 2801fd9a1c26SIan Munsie 2802fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2803fd9a1c26SIan Munsie /* 2804fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2805fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2806fd9a1c26SIan Munsie */ 2807fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2808fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2809fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2810fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2811fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2812fd9a1c26SIan Munsie } 2813fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2814fd9a1c26SIan Munsie } 2815fd9a1c26SIan Munsie 28164ee11c1aSSuresh Warrier /* 28174ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 28184ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 28194ee11c1aSSuresh Warrier */ 28204ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 28214ee11c1aSSuresh Warrier { 28224ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 28234ee11c1aSSuresh Warrier } 28244ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 28254ee11c1aSSuresh Warrier 2826184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2827137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2828137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2829184cd4a3SBenjamin Herrenschmidt { 2830184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2831184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 28323a1a4661SBenjamin Herrenschmidt __be32 data; 2833184cd4a3SBenjamin Herrenschmidt int rc; 2834184cd4a3SBenjamin Herrenschmidt 2835184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2836184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2837184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2838184cd4a3SBenjamin Herrenschmidt 2839184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2840184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2841184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2842184cd4a3SBenjamin Herrenschmidt 2843b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 284436074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2845b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2846b72c1f65SBenjamin Herrenschmidt 2847184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2848184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2849184cd4a3SBenjamin Herrenschmidt if (rc) { 2850184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2851184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2852184cd4a3SBenjamin Herrenschmidt return -EIO; 2853184cd4a3SBenjamin Herrenschmidt } 2854184cd4a3SBenjamin Herrenschmidt 2855184cd4a3SBenjamin Herrenschmidt if (is_64) { 28563a1a4661SBenjamin Herrenschmidt __be64 addr64; 28573a1a4661SBenjamin Herrenschmidt 2858184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2859184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2860184cd4a3SBenjamin Herrenschmidt if (rc) { 2861184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2862184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2863184cd4a3SBenjamin Herrenschmidt return -EIO; 2864184cd4a3SBenjamin Herrenschmidt } 28653a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28663a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2867184cd4a3SBenjamin Herrenschmidt } else { 28683a1a4661SBenjamin Herrenschmidt __be32 addr32; 28693a1a4661SBenjamin Herrenschmidt 2870184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2871184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2872184cd4a3SBenjamin Herrenschmidt if (rc) { 2873184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2874184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2875184cd4a3SBenjamin Herrenschmidt return -EIO; 2876184cd4a3SBenjamin Herrenschmidt } 2877184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28783a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2879184cd4a3SBenjamin Herrenschmidt } 28803a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2881184cd4a3SBenjamin Herrenschmidt 2882f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2883137436c9SGavin Shan 2884184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 28851f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2886184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2887184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2888184cd4a3SBenjamin Herrenschmidt 2889184cd4a3SBenjamin Herrenschmidt return 0; 2890184cd4a3SBenjamin Herrenschmidt } 2891184cd4a3SBenjamin Herrenschmidt 2892184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2893184cd4a3SBenjamin Herrenschmidt { 2894fb1b55d6SGavin Shan unsigned int count; 2895184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2896184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2897184cd4a3SBenjamin Herrenschmidt if (!prop) { 2898184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2899184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2900184cd4a3SBenjamin Herrenschmidt } 2901184cd4a3SBenjamin Herrenschmidt if (!prop) 2902184cd4a3SBenjamin Herrenschmidt return; 2903184cd4a3SBenjamin Herrenschmidt 2904184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2905fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2906fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2907184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2908184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2909184cd4a3SBenjamin Herrenschmidt return; 2910184cd4a3SBenjamin Herrenschmidt } 2911fb1b55d6SGavin Shan 2912184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2913184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2914184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2915fb1b55d6SGavin Shan count, phb->msi_base); 2916184cd4a3SBenjamin Herrenschmidt } 2917184cd4a3SBenjamin Herrenschmidt 29186e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29196e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29206e628c7dSWei Yang { 2921f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2922f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2923f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29246e628c7dSWei Yang struct resource *res; 29256e628c7dSWei Yang int i; 2926dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29276e628c7dSWei Yang struct pci_dn *pdn; 29285b88ec22SWei Yang int mul, total_vfs; 29296e628c7dSWei Yang 293044bda4b7SHari Vyas if (!pdev->is_physfn || pci_dev_is_added(pdev)) 29316e628c7dSWei Yang return; 29326e628c7dSWei Yang 29336e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29346e628c7dSWei Yang pdn->vfs_expanded = 0; 2935ee8222feSWei Yang pdn->m64_single_mode = false; 29366e628c7dSWei Yang 29375b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 293892b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2939dfcc8d45SWei Yang total_vf_bar_sz = 0; 29405b88ec22SWei Yang 29415b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29425b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29435b88ec22SWei Yang if (!res->flags || res->parent) 29445b88ec22SWei Yang continue; 2945b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 2946b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2947b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29485b88ec22SWei Yang i, res); 2949b0331854SWei Yang goto truncate_iov; 29505b88ec22SWei Yang } 29515b88ec22SWei Yang 2952dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2953dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29545b88ec22SWei Yang 2955f2dd0afeSWei Yang /* 2956f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2957f2dd0afeSWei Yang * power of two. 2958f2dd0afeSWei Yang * 2959f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2960f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2961f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2962f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2963f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2964f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2965f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2966f2dd0afeSWei Yang */ 2967dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29685b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2969dfcc8d45SWei Yang dev_info(&pdev->dev, 2970dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2971dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2972ee8222feSWei Yang pdn->m64_single_mode = true; 29735b88ec22SWei Yang break; 29745b88ec22SWei Yang } 29755b88ec22SWei Yang } 29765b88ec22SWei Yang 29776e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29786e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29796e628c7dSWei Yang if (!res->flags || res->parent) 29806e628c7dSWei Yang continue; 29816e628c7dSWei Yang 29826e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2983ee8222feSWei Yang /* 2984ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2985ee8222feSWei Yang * mode is 32MB. 2986ee8222feSWei Yang */ 2987ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2988ee8222feSWei Yang goto truncate_iov; 2989ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29905b88ec22SWei Yang res->end = res->start + size * mul - 1; 29916e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 29926e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 29935b88ec22SWei Yang i, res, mul); 29946e628c7dSWei Yang } 29955b88ec22SWei Yang pdn->vfs_expanded = mul; 2996b0331854SWei Yang 2997b0331854SWei Yang return; 2998b0331854SWei Yang 2999b0331854SWei Yang truncate_iov: 3000b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3001b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3002b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3003b0331854SWei Yang res->flags = 0; 3004b0331854SWei Yang res->end = res->start - 1; 3005b0331854SWei Yang } 30066e628c7dSWei Yang } 30076e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 30086e628c7dSWei Yang 300923e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 301023e79425SGavin Shan struct resource *res) 301111685becSGavin Shan { 301223e79425SGavin Shan struct pnv_phb *phb = pe->phb; 301311685becSGavin Shan struct pci_bus_region region; 301423e79425SGavin Shan int index; 301523e79425SGavin Shan int64_t rc; 301611685becSGavin Shan 301723e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 301823e79425SGavin Shan return; 301911685becSGavin Shan 302011685becSGavin Shan if (res->flags & IORESOURCE_IO) { 302111685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 302211685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 302311685becSGavin Shan index = region.start / phb->ioda.io_segsize; 302411685becSGavin Shan 302592b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 302611685becSGavin Shan region.start <= region.end) { 302711685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 302811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 302911685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 303011685becSGavin Shan if (rc != OPAL_SUCCESS) { 30311f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 303211685becSGavin Shan __func__, rc, index, pe->pe_number); 303311685becSGavin Shan break; 303411685becSGavin Shan } 303511685becSGavin Shan 303611685becSGavin Shan region.start += phb->ioda.io_segsize; 303711685becSGavin Shan index++; 303811685becSGavin Shan } 3039027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 30405958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 304111685becSGavin Shan region.start = res->start - 304223e79425SGavin Shan phb->hose->mem_offset[0] - 304311685becSGavin Shan phb->ioda.m32_pci_base; 304411685becSGavin Shan region.end = res->end - 304523e79425SGavin Shan phb->hose->mem_offset[0] - 304611685becSGavin Shan phb->ioda.m32_pci_base; 304711685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 304811685becSGavin Shan 304992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 305011685becSGavin Shan region.start <= region.end) { 305111685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 305211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 305311685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 305411685becSGavin Shan if (rc != OPAL_SUCCESS) { 30551f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 305611685becSGavin Shan __func__, rc, index, pe->pe_number); 305711685becSGavin Shan break; 305811685becSGavin Shan } 305911685becSGavin Shan 306011685becSGavin Shan region.start += phb->ioda.m32_segsize; 306111685becSGavin Shan index++; 306211685becSGavin Shan } 306311685becSGavin Shan } 306411685becSGavin Shan } 306523e79425SGavin Shan 306623e79425SGavin Shan /* 306723e79425SGavin Shan * This function is supposed to be called on basis of PE from top 306823e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 306903671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 307023e79425SGavin Shan */ 307123e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 307223e79425SGavin Shan { 307369d733e7SGavin Shan struct pci_dev *pdev; 307423e79425SGavin Shan int i; 307523e79425SGavin Shan 307623e79425SGavin Shan /* 307723e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 307823e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 307923e79425SGavin Shan * be figured out later. 308023e79425SGavin Shan */ 308123e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 308223e79425SGavin Shan 308369d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 308469d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 308569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 308669d733e7SGavin Shan 308769d733e7SGavin Shan /* 308869d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 308969d733e7SGavin Shan * windows of the child bridges should be mapped to 309069d733e7SGavin Shan * the PE as well. 309169d733e7SGavin Shan */ 309269d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 309369d733e7SGavin Shan continue; 309469d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 309569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 309669d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 309769d733e7SGavin Shan } 309811685becSGavin Shan } 309911685becSGavin Shan 310098b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 310198b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 310298b665daSRussell Currey { 310398b665daSRussell Currey struct pci_controller *hose; 310498b665daSRussell Currey struct pnv_phb *phb; 310598b665daSRussell Currey s64 ret; 310698b665daSRussell Currey 310798b665daSRussell Currey if (val != 1ULL) 310898b665daSRussell Currey return -EINVAL; 310998b665daSRussell Currey 311098b665daSRussell Currey hose = (struct pci_controller *)data; 311198b665daSRussell Currey if (!hose || !hose->private_data) 311298b665daSRussell Currey return -ENODEV; 311398b665daSRussell Currey 311498b665daSRussell Currey phb = hose->private_data; 311598b665daSRussell Currey 311698b665daSRussell Currey /* Retrieve the diag data from firmware */ 31175cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 31185cb1f8fdSRussell Currey phb->diag_data_size); 311998b665daSRussell Currey if (ret != OPAL_SUCCESS) 312098b665daSRussell Currey return -EIO; 312198b665daSRussell Currey 312298b665daSRussell Currey /* Print the diag data to the kernel log */ 31235cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 312498b665daSRussell Currey return 0; 312598b665daSRussell Currey } 312698b665daSRussell Currey 312798b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 312898b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 312998b665daSRussell Currey 313098b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 313198b665daSRussell Currey 313237c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 313337c367f2SGavin Shan { 313437c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 313537c367f2SGavin Shan struct pci_controller *hose, *tmp; 313637c367f2SGavin Shan struct pnv_phb *phb; 313737c367f2SGavin Shan char name[16]; 313837c367f2SGavin Shan 313937c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 314037c367f2SGavin Shan phb = hose->private_data; 314137c367f2SGavin Shan 3142ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3143ccd1c191SGavin Shan phb->initialized = 1; 3144ccd1c191SGavin Shan 314537c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 314637c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 314798b665daSRussell Currey if (!phb->dbgfs) { 3148f2c2cbccSJoe Perches pr_warn("%s: Error on creating debugfs on PHB#%x\n", 314937c367f2SGavin Shan __func__, hose->global_number); 315098b665daSRussell Currey continue; 315198b665daSRussell Currey } 315298b665daSRussell Currey 315398b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 315498b665daSRussell Currey &pnv_pci_diag_data_fops); 315537c367f2SGavin Shan } 315637c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 315737c367f2SGavin Shan } 315837c367f2SGavin Shan 3159db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 3160db217319SBenjamin Herrenschmidt { 3161db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 3162db217319SBenjamin Herrenschmidt struct pci_bus *child; 3163db217319SBenjamin Herrenschmidt 3164db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 3165db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 3166db217319SBenjamin Herrenschmidt return; 3167db217319SBenjamin Herrenschmidt 3168db217319SBenjamin Herrenschmidt /* 3169db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 3170db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 3171db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 3172db217319SBenjamin Herrenschmidt * fixed. 3173db217319SBenjamin Herrenschmidt */ 3174db217319SBenjamin Herrenschmidt if (dev) { 3175db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 3176db217319SBenjamin Herrenschmidt if (rc) 3177db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 3178db217319SBenjamin Herrenschmidt pci_set_master(dev); 3179db217319SBenjamin Herrenschmidt } 3180db217319SBenjamin Herrenschmidt 3181db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 3182db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 3183db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 3184db217319SBenjamin Herrenschmidt } 3185db217319SBenjamin Herrenschmidt 3186db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 3187db217319SBenjamin Herrenschmidt { 3188db217319SBenjamin Herrenschmidt struct pci_controller *hose; 3189db217319SBenjamin Herrenschmidt 3190db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 3191db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 3192db217319SBenjamin Herrenschmidt } 3193db217319SBenjamin Herrenschmidt 3194cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3195fb446ad0SGavin Shan { 3196fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3197ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 319837c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 319937c367f2SGavin Shan 3200db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 3201db217319SBenjamin Herrenschmidt 3202e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3203b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3204e9cc17d4SGavin Shan #endif 3205fb446ad0SGavin Shan } 3206fb446ad0SGavin Shan 3207271fd03aSGavin Shan /* 3208271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3209271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3210271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3211271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3212271fd03aSGavin Shan * 1MiB for memory) will be returned. 3213271fd03aSGavin Shan * 3214271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3215271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3216271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3217271fd03aSGavin Shan * resources. 3218271fd03aSGavin Shan */ 3219271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3220271fd03aSGavin Shan unsigned long type) 3221271fd03aSGavin Shan { 3222271fd03aSGavin Shan struct pci_dev *bridge; 3223271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3224271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3225271fd03aSGavin Shan int num_pci_bridges = 0; 3226271fd03aSGavin Shan 3227271fd03aSGavin Shan bridge = bus->self; 3228271fd03aSGavin Shan while (bridge) { 3229271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3230271fd03aSGavin Shan num_pci_bridges++; 3231271fd03aSGavin Shan if (num_pci_bridges >= 2) 3232271fd03aSGavin Shan return 1; 3233271fd03aSGavin Shan } 3234271fd03aSGavin Shan 3235271fd03aSGavin Shan bridge = bridge->bus->self; 3236271fd03aSGavin Shan } 3237271fd03aSGavin Shan 32385958d19aSBenjamin Herrenschmidt /* 32395958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 32405958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 32415958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 32425958d19aSBenjamin Herrenschmidt */ 3243b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3244262af557SGuo Chao return phb->ioda.m64_segsize; 3245271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3246271fd03aSGavin Shan return phb->ioda.m32_segsize; 3247271fd03aSGavin Shan 3248271fd03aSGavin Shan return phb->ioda.io_segsize; 3249271fd03aSGavin Shan } 3250271fd03aSGavin Shan 325140e2a47eSGavin Shan /* 325240e2a47eSGavin Shan * We are updating root port or the upstream port of the 325340e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 325440e2a47eSGavin Shan * to accommodate the changes on required resources during 325540e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 325640e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 325740e2a47eSGavin Shan * root port. 325840e2a47eSGavin Shan */ 325940e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 326040e2a47eSGavin Shan unsigned long type) 326140e2a47eSGavin Shan { 326240e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 326340e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 326440e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 326540e2a47eSGavin Shan struct resource *r, *w; 326640e2a47eSGavin Shan bool msi_region = false; 326740e2a47eSGavin Shan int i; 326840e2a47eSGavin Shan 326940e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 327040e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 327140e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 327240e2a47eSGavin Shan return; 327340e2a47eSGavin Shan 327440e2a47eSGavin Shan /* Fixup the resources */ 327540e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 327640e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 327740e2a47eSGavin Shan if (!r->flags || !r->parent) 327840e2a47eSGavin Shan continue; 327940e2a47eSGavin Shan 328040e2a47eSGavin Shan w = NULL; 328140e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 328240e2a47eSGavin Shan w = &hose->io_resource; 32835958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 328440e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 328540e2a47eSGavin Shan phb->ioda.m64_segsize) 328640e2a47eSGavin Shan w = &hose->mem_resources[1]; 328740e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 328840e2a47eSGavin Shan w = &hose->mem_resources[0]; 328940e2a47eSGavin Shan msi_region = true; 329040e2a47eSGavin Shan } 329140e2a47eSGavin Shan 329240e2a47eSGavin Shan r->start = w->start; 329340e2a47eSGavin Shan r->end = w->end; 329440e2a47eSGavin Shan 329540e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 329640e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 329740e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 329840e2a47eSGavin Shan * 329940e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 330040e2a47eSGavin Shan * 32-bits bridge window. 330140e2a47eSGavin Shan */ 330240e2a47eSGavin Shan if (msi_region) { 330340e2a47eSGavin Shan r->end += 0x10000; 330440e2a47eSGavin Shan r->end -= 0x100000; 330540e2a47eSGavin Shan } 330640e2a47eSGavin Shan } 330740e2a47eSGavin Shan } 330840e2a47eSGavin Shan 3309ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3310ccd1c191SGavin Shan { 3311ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3312ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3313ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3314ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3315ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3316ccd1c191SGavin Shan 331740e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 331840e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 331940e2a47eSGavin Shan 332063803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 332163803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 332263803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 332363803c39SGavin Shan if (pe) { 332463803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 332563803c39SGavin Shan phb->ioda.root_pe_populated = true; 332663803c39SGavin Shan } 332763803c39SGavin Shan } 332863803c39SGavin Shan 3329ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3330ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3331ccd1c191SGavin Shan return; 3332ccd1c191SGavin Shan 3333ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3334a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 3335ccd1c191SGavin Shan 3336ccd1c191SGavin Shan /* 3337ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3338ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3339ccd1c191SGavin Shan * not allocate resources again. 3340ccd1c191SGavin Shan */ 3341ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3342ccd1c191SGavin Shan if (!pe) 3343ccd1c191SGavin Shan return; 3344ccd1c191SGavin Shan 3345ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3346ccd1c191SGavin Shan switch (phb->type) { 3347ccd1c191SGavin Shan case PNV_PHB_IODA1: 3348ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3349ccd1c191SGavin Shan break; 3350ccd1c191SGavin Shan case PNV_PHB_IODA2: 3351ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3352ccd1c191SGavin Shan break; 3353ccd1c191SGavin Shan default: 33541f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3355ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3356ccd1c191SGavin Shan } 3357ccd1c191SGavin Shan } 3358ccd1c191SGavin Shan 335938274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 336038274637SYongji Xie { 336138274637SYongji Xie return PAGE_SIZE; 336238274637SYongji Xie } 336338274637SYongji Xie 33645350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 33655350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 33665350ab3fSWei Yang int resno) 33675350ab3fSWei Yang { 3368ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3369ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 33705350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 33717fbe7a93SWei Yang resource_size_t align; 33725350ab3fSWei Yang 33737fbe7a93SWei Yang /* 33747fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 33757fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 33767fbe7a93SWei Yang * BAR should be size aligned. 33777fbe7a93SWei Yang * 3378ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3379ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3380ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3381ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3382ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3383ee8222feSWei Yang * m64_segsize. 3384ee8222feSWei Yang * 33857fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 33867fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3387ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3388ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 33897fbe7a93SWei Yang */ 33905350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 33917fbe7a93SWei Yang if (!pdn->vfs_expanded) 33925350ab3fSWei Yang return align; 3393ee8222feSWei Yang if (pdn->m64_single_mode) 3394ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 33957fbe7a93SWei Yang 33967fbe7a93SWei Yang return pdn->vfs_expanded * align; 33975350ab3fSWei Yang } 33985350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 33995350ab3fSWei Yang 3400184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3401184cd4a3SBenjamin Herrenschmidt * assign a PE 3402184cd4a3SBenjamin Herrenschmidt */ 34038bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3404184cd4a3SBenjamin Herrenschmidt { 3405db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3406db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3407db1266c8SGavin Shan struct pci_dn *pdn; 3408184cd4a3SBenjamin Herrenschmidt 3409db1266c8SGavin Shan /* The function is probably called while the PEs have 3410db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3411db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3412db1266c8SGavin Shan * PEs isn't ready. 3413db1266c8SGavin Shan */ 3414db1266c8SGavin Shan if (!phb->initialized) 3415c88c2a18SDaniel Axtens return true; 3416db1266c8SGavin Shan 3417b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3418184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3419c88c2a18SDaniel Axtens return false; 3420db1266c8SGavin Shan 3421c88c2a18SDaniel Axtens return true; 3422184cd4a3SBenjamin Herrenschmidt } 3423184cd4a3SBenjamin Herrenschmidt 3424c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3425c5f7700bSGavin Shan int num) 3426c5f7700bSGavin Shan { 3427c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3428c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3429c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3430c5f7700bSGavin Shan unsigned int idx; 3431c5f7700bSGavin Shan long rc; 3432c5f7700bSGavin Shan 3433c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3434c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3435c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3436c5f7700bSGavin Shan continue; 3437c5f7700bSGavin Shan 3438c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3439c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3440c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3441c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3442c5f7700bSGavin Shan rc, idx); 3443c5f7700bSGavin Shan return rc; 3444c5f7700bSGavin Shan } 3445c5f7700bSGavin Shan 3446c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3447c5f7700bSGavin Shan } 3448c5f7700bSGavin Shan 3449c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3450c5f7700bSGavin Shan return OPAL_SUCCESS; 3451c5f7700bSGavin Shan } 3452c5f7700bSGavin Shan 3453c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3454c5f7700bSGavin Shan { 3455c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3456c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3457c5f7700bSGavin Shan int64_t rc; 3458c5f7700bSGavin Shan 3459c5f7700bSGavin Shan if (!weight) 3460c5f7700bSGavin Shan return; 3461c5f7700bSGavin Shan 3462c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3463c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3464c5f7700bSGavin Shan return; 3465c5f7700bSGavin Shan 3466a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3467c5f7700bSGavin Shan if (pe->table_group.group) { 3468c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3469c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3470c5f7700bSGavin Shan } 3471c5f7700bSGavin Shan 3472c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3473e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3474c5f7700bSGavin Shan } 3475c5f7700bSGavin Shan 3476c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3477c5f7700bSGavin Shan { 3478c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3479c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3480c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3481c5f7700bSGavin Shan int64_t rc; 3482c5f7700bSGavin Shan #endif 3483c5f7700bSGavin Shan 3484c5f7700bSGavin Shan if (!weight) 3485c5f7700bSGavin Shan return; 3486c5f7700bSGavin Shan 3487c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3488c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3489c5f7700bSGavin Shan if (rc) 34901e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 3491c5f7700bSGavin Shan #endif 3492c5f7700bSGavin Shan 3493c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3494c5f7700bSGavin Shan if (pe->table_group.group) { 3495c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3496c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3497c5f7700bSGavin Shan } 3498c5f7700bSGavin Shan 3499e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3500c5f7700bSGavin Shan } 3501c5f7700bSGavin Shan 3502c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3503c5f7700bSGavin Shan unsigned short win, 3504c5f7700bSGavin Shan unsigned int *map) 3505c5f7700bSGavin Shan { 3506c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3507c5f7700bSGavin Shan int idx; 3508c5f7700bSGavin Shan int64_t rc; 3509c5f7700bSGavin Shan 3510c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3511c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3512c5f7700bSGavin Shan continue; 3513c5f7700bSGavin Shan 3514c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3515c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3516c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3517c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3518c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3519c5f7700bSGavin Shan else 3520c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3521c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3522c5f7700bSGavin Shan 3523c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 35241e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 3525c5f7700bSGavin Shan rc, win, idx); 3526c5f7700bSGavin Shan 3527c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3528c5f7700bSGavin Shan } 3529c5f7700bSGavin Shan } 3530c5f7700bSGavin Shan 3531c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3532c5f7700bSGavin Shan { 3533c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3534c5f7700bSGavin Shan 3535c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3536c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3537c5f7700bSGavin Shan phb->ioda.io_segmap); 3538c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3539c5f7700bSGavin Shan phb->ioda.m32_segmap); 3540c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3541c5f7700bSGavin Shan phb->ioda.m64_segmap); 3542c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3543c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3544c5f7700bSGavin Shan phb->ioda.m32_segmap); 3545c5f7700bSGavin Shan } 3546c5f7700bSGavin Shan } 3547c5f7700bSGavin Shan 3548c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3549c5f7700bSGavin Shan { 3550c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3551c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3552c5f7700bSGavin Shan 3553c5f7700bSGavin Shan list_del(&pe->list); 3554c5f7700bSGavin Shan switch (phb->type) { 3555c5f7700bSGavin Shan case PNV_PHB_IODA1: 3556c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3557c5f7700bSGavin Shan break; 3558c5f7700bSGavin Shan case PNV_PHB_IODA2: 3559c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3560c5f7700bSGavin Shan break; 3561c5f7700bSGavin Shan default: 3562c5f7700bSGavin Shan WARN_ON(1); 3563c5f7700bSGavin Shan } 3564c5f7700bSGavin Shan 3565c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3566c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3567b314427aSGavin Shan 3568b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3569b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3570b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3571b314427aSGavin Shan list_del(&slave->list); 3572b314427aSGavin Shan pnv_ioda_free_pe(slave); 3573b314427aSGavin Shan } 3574b314427aSGavin Shan } 3575b314427aSGavin Shan 35766eaed166SGavin Shan /* 35776eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 35786eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 35796eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 35806eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 35816eaed166SGavin Shan */ 35826eaed166SGavin Shan if (phb->ioda.root_pe_populated && 35836eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 35846eaed166SGavin Shan phb->ioda.root_pe_populated = false; 35856eaed166SGavin Shan else 3586c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3587c5f7700bSGavin Shan } 3588c5f7700bSGavin Shan 3589c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3590c5f7700bSGavin Shan { 3591c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3592c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3593c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3594c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3595c5f7700bSGavin Shan 3596c5f7700bSGavin Shan if (pdev->is_virtfn) 3597c5f7700bSGavin Shan return; 3598c5f7700bSGavin Shan 3599c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3600c5f7700bSGavin Shan return; 3601c5f7700bSGavin Shan 360229bf282dSGavin Shan /* 360329bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 360429bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 360529bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 360629bf282dSGavin Shan * device count is decreased on removing devices while failing to 360729bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 360829bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 360929bf282dSGavin Shan */ 3610c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 361129bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 361229bf282dSGavin Shan 3613c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3614c5f7700bSGavin Shan if (pe->device_count == 0) 3615c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3616c5f7700bSGavin Shan } 3617c5f7700bSGavin Shan 3618ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 3619ab7032e7SAlexey Kardashevskiy { 3620ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 3621ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 3622ab7032e7SAlexey Kardashevskiy 3623ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 3624ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 3625ab7032e7SAlexey Kardashevskiy } 3626ab7032e7SAlexey Kardashevskiy 36277a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 362873ed148aSBenjamin Herrenschmidt { 36297a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 36307a8e6bbfSMichael Neuling 3631d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 363273ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 363373ed148aSBenjamin Herrenschmidt } 363473ed148aSBenjamin Herrenschmidt 363592ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 363692ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 36371bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 36382d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 363992ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 364092ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 364192ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3642c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 364392ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3644ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 364592ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36467a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 364792ae0353SDaniel Axtens }; 364892ae0353SDaniel Axtens 36495d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 36505d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 36515d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 36525d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 36535d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 36545d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 36555d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36565d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 3657ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 36585d2aa710SAlistair Popple }; 36595d2aa710SAlistair Popple 36607f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 36617f2c39e9SFrederic Barrat .enable_device_hook = pnv_pci_enable_device_hook, 36627f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 36637f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36647f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 36657f2c39e9SFrederic Barrat }; 36667f2c39e9SFrederic Barrat 3667e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3668e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3669184cd4a3SBenjamin Herrenschmidt { 3670184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3671184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 36722b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 36732b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3674fd141d1aSBenjamin Herrenschmidt struct resource r; 3675c681b93cSAlistair Popple const __be64 *prop64; 36763a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3677f1b7cc3eSGavin Shan int len; 36783fa23ff8SGavin Shan unsigned int segno; 3679184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3680184cd4a3SBenjamin Herrenschmidt void *aux; 3681184cd4a3SBenjamin Herrenschmidt long rc; 3682184cd4a3SBenjamin Herrenschmidt 368308a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 368408a45b32SBenjamin Herrenschmidt return; 368508a45b32SBenjamin Herrenschmidt 3686b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3687184cd4a3SBenjamin Herrenschmidt 3688184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3689184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3690184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3691184cd4a3SBenjamin Herrenschmidt return; 3692184cd4a3SBenjamin Herrenschmidt } 3693184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3694184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3695184cd4a3SBenjamin Herrenschmidt 36967e1c4e27SMike Rapoport phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 36978a7f97b9SMike Rapoport if (!phb) 36988a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 36998a7f97b9SMike Rapoport sizeof(*phb)); 370058d714ecSGavin Shan 370158d714ecSGavin Shan /* Allocate PCI controller */ 3702184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 370358d714ecSGavin Shan if (!phb->hose) { 3704b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3705b7c670d6SRob Herring np); 3706e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3707184cd4a3SBenjamin Herrenschmidt return; 3708184cd4a3SBenjamin Herrenschmidt } 3709184cd4a3SBenjamin Herrenschmidt 3710184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3711f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3712f1b7cc3eSGavin Shan if (prop32 && len == 8) { 37133a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 37143a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3715f1b7cc3eSGavin Shan } else { 3716b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3717184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3718184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3719f1b7cc3eSGavin Shan } 3720184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3721e9cc17d4SGavin Shan phb->hub_id = hub_id; 3722184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3723aa0c033fSGavin Shan phb->type = ioda_type; 3724781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3725184cd4a3SBenjamin Herrenschmidt 3726cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3727cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3728cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3729f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3730aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 37315d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 37325d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3733616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3734616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3735cee72d5bSBenjamin Herrenschmidt else 3736cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3737cee72d5bSBenjamin Herrenschmidt 37385cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 37395cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 37405cb1f8fdSRussell Currey if (prop32) 37415cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 37425cb1f8fdSRussell Currey else 37435cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 37445cb1f8fdSRussell Currey 37457e1c4e27SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 37468a7f97b9SMike Rapoport if (!phb->diag_data) 37478a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 37488a7f97b9SMike Rapoport phb->diag_data_size); 37495cb1f8fdSRussell Currey 3750aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 37512f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3752184cd4a3SBenjamin Herrenschmidt 3753aa0c033fSGavin Shan /* Get registers */ 3754fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3755fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3756fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3757184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3758184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3759fd141d1aSBenjamin Herrenschmidt } 3760577c8c88SGavin Shan 3761184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 376292b8f137SGavin Shan phb->ioda.total_pe_num = 1; 376336954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 376436954dc7SGavin Shan if (prop32) 376592b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 376636954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 376736954dc7SGavin Shan if (prop32) 376892b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3769262af557SGuo Chao 3770c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3771c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3772c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3773c127562aSGavin Shan 3774262af557SGuo Chao /* Parse 64-bit MMIO range */ 3775262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3776262af557SGuo Chao 3777184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3778aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3779184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3780184cd4a3SBenjamin Herrenschmidt 378192b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 37823fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3783184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 378492b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3785184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3786184cd4a3SBenjamin Herrenschmidt 37872b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 37882b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 37892b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 37902b923ed1SGavin Shan 3791c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 379292a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 379392a86756SAlexey Kardashevskiy sizeof(unsigned long)); 379493289d8cSGavin Shan m64map_off = size; 379593289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3796184cd4a3SBenjamin Herrenschmidt m32map_off = size; 379792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3798c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3799c35d2a8cSGavin Shan iomap_off = size; 380092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 38012b923ed1SGavin Shan dma32map_off = size; 38022b923ed1SGavin Shan size += phb->ioda.dma32_count * 38032b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3804c35d2a8cSGavin Shan } 3805184cd4a3SBenjamin Herrenschmidt pemap_off = size; 380692b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 38077e1c4e27SMike Rapoport aux = memblock_alloc(size, SMP_CACHE_BYTES); 38088a7f97b9SMike Rapoport if (!aux) 38098a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3810184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 381193289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3812184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 381393289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 381493289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 38153fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 381693289d8cSGavin Shan } 38173fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3818184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 38193fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 38203fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 38212b923ed1SGavin Shan 38222b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 38232b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 38242b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 38253fa23ff8SGavin Shan } 3826184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 382763803c39SGavin Shan 382863803c39SGavin Shan /* 382963803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 383063803c39SGavin Shan * M64 resources consumed by its child devices. To pick 383163803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 383263803c39SGavin Shan */ 383363803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 383463803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 383563803c39SGavin Shan phb->ioda.root_pe_idx = 1; 383663803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 383763803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 383863803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 383963803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 384063803c39SGavin Shan } else { 384163803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 384263803c39SGavin Shan } 3843184cd4a3SBenjamin Herrenschmidt 3844184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3845781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3846184cd4a3SBenjamin Herrenschmidt 3847184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 38482b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3849acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3850184cd4a3SBenjamin Herrenschmidt 3851aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3852184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3853184cd4a3SBenjamin Herrenschmidt window_type, 3854184cd4a3SBenjamin Herrenschmidt window_num, 3855184cd4a3SBenjamin Herrenschmidt starting_real_address, 3856184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3857184cd4a3SBenjamin Herrenschmidt segment_size); 3858184cd4a3SBenjamin Herrenschmidt #endif 3859184cd4a3SBenjamin Herrenschmidt 3860262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 386192b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3862262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3863262af557SGuo Chao if (phb->ioda.m64_size) 3864262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3865262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3866262af557SGuo Chao if (phb->ioda.io_size) 3867262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3868184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3869184cd4a3SBenjamin Herrenschmidt 3870262af557SGuo Chao 3871184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 387249dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 387349dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 387449dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3875184cd4a3SBenjamin Herrenschmidt 3876184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3877184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3878184cd4a3SBenjamin Herrenschmidt 3879c40a4210SGavin Shan /* 3880c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3881c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3882c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3883c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3884c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3885184cd4a3SBenjamin Herrenschmidt */ 3886fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 38875d2aa710SAlistair Popple 38887f2c39e9SFrederic Barrat switch (phb->type) { 38897f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 38905d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 38917f2c39e9SFrederic Barrat break; 38927f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 38937f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 38947f2c39e9SFrederic Barrat break; 38957f2c39e9SFrederic Barrat default: 3896f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 389792ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3898f9f83456SAlexey Kardashevskiy } 3899ad30cb99SMichael Ellerman 390038274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 390138274637SYongji Xie 39026e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 39036e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 39045350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3905988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3906988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3907ad30cb99SMichael Ellerman #endif 3908ad30cb99SMichael Ellerman 3909c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3910184cd4a3SBenjamin Herrenschmidt 3911184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3912d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3913184cd4a3SBenjamin Herrenschmidt if (rc) 3914f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3915361f2a2aSGavin Shan 39166060e9eaSAndrew Donnellan /* 39176060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3918361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3919361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 392045baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3921b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3922b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3923b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3924b174b4fbSOliver O'Halloran * boot. 3925361f2a2aSGavin Shan */ 3926b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3927361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3928cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3929cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3930361f2a2aSGavin Shan } 3931262af557SGuo Chao 39329e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 39339e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3934262af557SGuo Chao hose->mem_resources[1].flags = 0; 3935184cd4a3SBenjamin Herrenschmidt } 3936184cd4a3SBenjamin Herrenschmidt 393767975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3938aa0c033fSGavin Shan { 3939e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3940aa0c033fSGavin Shan } 3941aa0c033fSGavin Shan 39425d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 39435d2aa710SAlistair Popple { 39447f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 39455d2aa710SAlistair Popple } 39465d2aa710SAlistair Popple 39477f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 39487f2c39e9SFrederic Barrat { 39497f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3950184cd4a3SBenjamin Herrenschmidt } 3951184cd4a3SBenjamin Herrenschmidt 3952228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3953228c2f41SAndrew Donnellan { 3954228c2f41SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3955228c2f41SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 3956228c2f41SAndrew Donnellan 3957228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3958228c2f41SAndrew Donnellan return; 3959228c2f41SAndrew Donnellan 3960228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3961228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3962228c2f41SAndrew Donnellan } 3963228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3964228c2f41SAndrew Donnellan 3965184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3966184cd4a3SBenjamin Herrenschmidt { 3967184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3968184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 3969184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3970184cd4a3SBenjamin Herrenschmidt 3971b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3972184cd4a3SBenjamin Herrenschmidt 3973184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3974184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3975184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3976184cd4a3SBenjamin Herrenschmidt return; 3977184cd4a3SBenjamin Herrenschmidt } 3978184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3979184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3980184cd4a3SBenjamin Herrenschmidt 3981184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3982184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3983184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3984184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3985184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3986184cd4a3SBenjamin Herrenschmidt } 3987184cd4a3SBenjamin Herrenschmidt } 3988