1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 5199451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5299451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54781a868fSWei Yang 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 57bbb845c4SAlexey Kardashevskiy 589497a1c1SGavin Shan static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; 59aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 60aca6913fSAlexey Kardashevskiy 617d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 626d31c2faSJoe Perches const char *fmt, ...) 636d31c2faSJoe Perches { 646d31c2faSJoe Perches struct va_format vaf; 656d31c2faSJoe Perches va_list args; 666d31c2faSJoe Perches char pfix[32]; 67184cd4a3SBenjamin Herrenschmidt 686d31c2faSJoe Perches va_start(args, fmt); 696d31c2faSJoe Perches 706d31c2faSJoe Perches vaf.fmt = fmt; 716d31c2faSJoe Perches vaf.va = &args; 726d31c2faSJoe Perches 73781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 746d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 75781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 766d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 776d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 78781a868fSWei Yang #ifdef CONFIG_PCI_IOV 79781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 80781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 81781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 82781a868fSWei Yang (pe->rid & 0xff00) >> 8, 83781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 84781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 856d31c2faSJoe Perches 861f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 876d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 886d31c2faSJoe Perches 896d31c2faSJoe Perches va_end(args); 906d31c2faSJoe Perches } 916d31c2faSJoe Perches 924e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 934e287840SThadeu Lima de Souza Cascardo 944e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 954e287840SThadeu Lima de Souza Cascardo { 964e287840SThadeu Lima de Souza Cascardo if (!str) 974e287840SThadeu Lima de Souza Cascardo return -EINVAL; 984e287840SThadeu Lima de Souza Cascardo 994e287840SThadeu Lima de Souza Cascardo while (*str) { 1004e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1014e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1024e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1034e287840SThadeu Lima de Souza Cascardo break; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1064e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1074e287840SThadeu Lima de Souza Cascardo str++; 1084e287840SThadeu Lima de Souza Cascardo } 1094e287840SThadeu Lima de Souza Cascardo 1104e287840SThadeu Lima de Souza Cascardo return 0; 1114e287840SThadeu Lima de Souza Cascardo } 1124e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1134e287840SThadeu Lima de Souza Cascardo 1145958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 115262af557SGuo Chao { 1165958d19aSBenjamin Herrenschmidt /* 1175958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1185958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1195958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1205958d19aSBenjamin Herrenschmidt * 1215958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1225958d19aSBenjamin Herrenschmidt */ 1235958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1245958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 125262af557SGuo Chao } 126262af557SGuo Chao 127b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 128b79331a5SRussell Currey { 129b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 130b79331a5SRussell Currey 131b79331a5SRussell Currey return (resource_flags & flags) == flags; 132b79331a5SRussell Currey } 133b79331a5SRussell Currey 1341e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1351e916772SGavin Shan { 136313483ddSGavin Shan s64 rc; 137313483ddSGavin Shan 1381e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1391e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1401e916772SGavin Shan 141313483ddSGavin Shan /* 142313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 143313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 144313483ddSGavin Shan * PE is already in unfrozen state. 145313483ddSGavin Shan */ 146313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 147313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 148d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1491f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 150313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 151313483ddSGavin Shan 1521e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1531e916772SGavin Shan } 1541e916772SGavin Shan 1554b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1564b82ab18SGavin Shan { 15792b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1581f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1594b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1604b82ab18SGavin Shan return; 1614b82ab18SGavin Shan } 1624b82ab18SGavin Shan 163e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1641f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1654b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1664b82ab18SGavin Shan 1671e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1684b82ab18SGavin Shan } 1694b82ab18SGavin Shan 1701e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 171184cd4a3SBenjamin Herrenschmidt { 17260964816SAndrzej Hajda long pe; 173184cd4a3SBenjamin Herrenschmidt 1749fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1759fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1761e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 177184cd4a3SBenjamin Herrenschmidt } 178184cd4a3SBenjamin Herrenschmidt 1799fcd6f4aSGavin Shan return NULL; 1809fcd6f4aSGavin Shan } 1819fcd6f4aSGavin Shan 1821e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 183184cd4a3SBenjamin Herrenschmidt { 1841e916772SGavin Shan struct pnv_phb *phb = pe->phb; 185caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 186184cd4a3SBenjamin Herrenschmidt 1871e916772SGavin Shan WARN_ON(pe->pdev); 1881e916772SGavin Shan 1891e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 190caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 191184cd4a3SBenjamin Herrenschmidt } 192184cd4a3SBenjamin Herrenschmidt 193262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 194262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 195262af557SGuo Chao { 196262af557SGuo Chao const char *desc; 197262af557SGuo Chao struct resource *r; 198262af557SGuo Chao s64 rc; 199262af557SGuo Chao 200262af557SGuo Chao /* Configure the default M64 BAR */ 201262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 202262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 203262af557SGuo Chao phb->ioda.m64_bar_idx, 204262af557SGuo Chao phb->ioda.m64_base, 205262af557SGuo Chao 0, /* unused */ 206262af557SGuo Chao phb->ioda.m64_size); 207262af557SGuo Chao if (rc != OPAL_SUCCESS) { 208262af557SGuo Chao desc = "configuring"; 209262af557SGuo Chao goto fail; 210262af557SGuo Chao } 211262af557SGuo Chao 212262af557SGuo Chao /* Enable the default M64 BAR */ 213262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 214262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 215262af557SGuo Chao phb->ioda.m64_bar_idx, 216262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 217262af557SGuo Chao if (rc != OPAL_SUCCESS) { 218262af557SGuo Chao desc = "enabling"; 219262af557SGuo Chao goto fail; 220262af557SGuo Chao } 221262af557SGuo Chao 222262af557SGuo Chao /* 22363803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22463803c39SGavin Shan * are first or last two PEs. 225262af557SGuo Chao */ 226262af557SGuo Chao r = &phb->hose->mem_resources[1]; 22792b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 22863803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 22992b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23063803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 231262af557SGuo Chao else 2321f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23392b8f137SGavin Shan phb->ioda.reserved_pe_idx); 234262af557SGuo Chao 235262af557SGuo Chao return 0; 236262af557SGuo Chao 237262af557SGuo Chao fail: 238262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 239262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 240262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 241262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 242262af557SGuo Chao phb->ioda.m64_bar_idx, 243262af557SGuo Chao OPAL_DISABLE_M64); 244262af557SGuo Chao return -EIO; 245262af557SGuo Chao } 246262af557SGuo Chao 247c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 24896a2f92bSGavin Shan unsigned long *pe_bitmap) 249262af557SGuo Chao { 25096a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25196a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 252262af557SGuo Chao struct resource *r; 25396a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25496a2f92bSGavin Shan int segno, i; 255262af557SGuo Chao 25696a2f92bSGavin Shan base = phb->ioda.m64_base; 25796a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 25896a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 25996a2f92bSGavin Shan r = &pdev->resource[i]; 2605958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 261262af557SGuo Chao continue; 262262af557SGuo Chao 26396a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 26496a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 26596a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 26696a2f92bSGavin Shan if (pe_bitmap) 26796a2f92bSGavin Shan set_bit(segno, pe_bitmap); 26896a2f92bSGavin Shan else 26996a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 270262af557SGuo Chao } 271262af557SGuo Chao } 272262af557SGuo Chao } 273262af557SGuo Chao 27499451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 27599451551SGavin Shan { 27699451551SGavin Shan struct resource *r; 27799451551SGavin Shan int index; 27899451551SGavin Shan 27999451551SGavin Shan /* 28099451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28199451551SGavin Shan * there are as many M64 segments as the maximum number of 28299451551SGavin Shan * PEs, which is 128. 28399451551SGavin Shan */ 28499451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 28599451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 28699451551SGavin Shan int64_t rc; 28799451551SGavin Shan 28899451551SGavin Shan base = phb->ioda.m64_base + 28999451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29099451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29199451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29299451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29399451551SGavin Shan if (rc != OPAL_SUCCESS) { 2941f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 29599451551SGavin Shan rc, phb->hose->global_number, index); 29699451551SGavin Shan goto fail; 29799451551SGavin Shan } 29899451551SGavin Shan 29999451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30199451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30299451551SGavin Shan if (rc != OPAL_SUCCESS) { 3031f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30499451551SGavin Shan rc, phb->hose->global_number, index); 30599451551SGavin Shan goto fail; 30699451551SGavin Shan } 30799451551SGavin Shan } 30899451551SGavin Shan 30999451551SGavin Shan /* 31063803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31163803c39SGavin Shan * are first or last two PEs. 31299451551SGavin Shan */ 31399451551SGavin Shan r = &phb->hose->mem_resources[1]; 31499451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 31563803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 31699451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 31763803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 31899451551SGavin Shan else 3191f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32099451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32199451551SGavin Shan 32299451551SGavin Shan return 0; 32399451551SGavin Shan 32499451551SGavin Shan fail: 32599451551SGavin Shan for ( ; index >= 0; index--) 32699451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 32799451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 32899451551SGavin Shan 32999451551SGavin Shan return -EIO; 33099451551SGavin Shan } 33199451551SGavin Shan 332c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33396a2f92bSGavin Shan unsigned long *pe_bitmap, 33496a2f92bSGavin Shan bool all) 335262af557SGuo Chao { 336262af557SGuo Chao struct pci_dev *pdev; 33796a2f92bSGavin Shan 33896a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 339c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34096a2f92bSGavin Shan 34196a2f92bSGavin Shan if (all && pdev->subordinate) 342c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34396a2f92bSGavin Shan pe_bitmap, all); 34496a2f92bSGavin Shan } 34596a2f92bSGavin Shan } 34696a2f92bSGavin Shan 3471e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 348262af557SGuo Chao { 34926ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35026ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 351262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 352262af557SGuo Chao unsigned long size, *pe_alloc; 35326ba248dSGavin Shan int i; 354262af557SGuo Chao 355262af557SGuo Chao /* Root bus shouldn't use M64 */ 356262af557SGuo Chao if (pci_is_root_bus(bus)) 3571e916772SGavin Shan return NULL; 358262af557SGuo Chao 359262af557SGuo Chao /* Allocate bitmap */ 36092b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 361262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 362262af557SGuo Chao if (!pe_alloc) { 363262af557SGuo Chao pr_warn("%s: Out of memory !\n", 364262af557SGuo Chao __func__); 3651e916772SGavin Shan return NULL; 366262af557SGuo Chao } 367262af557SGuo Chao 36826ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 369c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 370262af557SGuo Chao 371262af557SGuo Chao /* 372262af557SGuo Chao * the current bus might not own M64 window and that's all 373262af557SGuo Chao * contributed by its child buses. For the case, we needn't 374262af557SGuo Chao * pick M64 dependent PE#. 375262af557SGuo Chao */ 37692b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 377262af557SGuo Chao kfree(pe_alloc); 3781e916772SGavin Shan return NULL; 379262af557SGuo Chao } 380262af557SGuo Chao 381262af557SGuo Chao /* 382262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 383262af557SGuo Chao * PE's list to form compound PE. 384262af557SGuo Chao */ 385262af557SGuo Chao master_pe = NULL; 386262af557SGuo Chao i = -1; 38792b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 38892b8f137SGavin Shan phb->ioda.total_pe_num) { 389262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 390262af557SGuo Chao 39193289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 392262af557SGuo Chao if (!master_pe) { 393262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 394262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 395262af557SGuo Chao master_pe = pe; 396262af557SGuo Chao } else { 397262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 398262af557SGuo Chao pe->master = master_pe; 399262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 400262af557SGuo Chao } 40199451551SGavin Shan 40299451551SGavin Shan /* 40399451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40499451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 40599451551SGavin Shan * between M64 segment and PE#. In order to have same logic 40699451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 40799451551SGavin Shan * segment and PE# on P7IOC. 40899451551SGavin Shan */ 40999451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41099451551SGavin Shan int64_t rc; 41199451551SGavin Shan 41299451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41399451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41499451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 41599451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 41699451551SGavin Shan if (rc != OPAL_SUCCESS) 4171f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 41899451551SGavin Shan __func__, rc, phb->hose->global_number, 41999451551SGavin Shan pe->pe_number); 42099451551SGavin Shan } 421262af557SGuo Chao } 422262af557SGuo Chao 423262af557SGuo Chao kfree(pe_alloc); 4241e916772SGavin Shan return master_pe; 425262af557SGuo Chao } 426262af557SGuo Chao 427262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 428262af557SGuo Chao { 429262af557SGuo Chao struct pci_controller *hose = phb->hose; 430262af557SGuo Chao struct device_node *dn = hose->dn; 431262af557SGuo Chao struct resource *res; 432a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4330e7736c6SGavin Shan const __be32 *r; 434262af557SGuo Chao u64 pci_addr; 435262af557SGuo Chao 43699451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4371665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4381665c4a8SGavin Shan return; 4391665c4a8SGavin Shan } 4401665c4a8SGavin Shan 441e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 442262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 443262af557SGuo Chao return; 444262af557SGuo Chao } 445262af557SGuo Chao 446262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 447262af557SGuo Chao if (!r) { 448262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 449262af557SGuo Chao dn->full_name); 450262af557SGuo Chao return; 451262af557SGuo Chao } 452262af557SGuo Chao 453a1339fafSBenjamin Herrenschmidt /* 454a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 455a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 456a1339fafSBenjamin Herrenschmidt */ 457a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 458a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 459a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 460a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 461a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 462a1339fafSBenjamin Herrenschmidt } 463a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 464a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 465a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 466a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 467a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 468a1339fafSBenjamin Herrenschmidt } 469a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 470a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 471a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 472a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 473a1339fafSBenjamin Herrenschmidt return; 474a1339fafSBenjamin Herrenschmidt } 475a1339fafSBenjamin Herrenschmidt 476a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 477262af557SGuo Chao res = &hose->mem_resources[1]; 478e80c4e7cSGavin Shan res->name = dn->full_name; 479262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 480262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 481262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 482262af557SGuo Chao pci_addr = of_read_number(r, 2); 483262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 484262af557SGuo Chao 485262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 48692b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 487262af557SGuo Chao phb->ioda.m64_base = pci_addr; 488262af557SGuo Chao 489a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 490a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 491a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 492a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 493a1339fafSBenjamin Herrenschmidt 494a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 495a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 496e9863e68SWei Yang 497262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 498a1339fafSBenjamin Herrenschmidt m64_range[1]--; 499a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 500a1339fafSBenjamin Herrenschmidt 501a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 502a1339fafSBenjamin Herrenschmidt 503a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 504a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 505a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 506a1339fafSBenjamin Herrenschmidt 507a1339fafSBenjamin Herrenschmidt /* 508a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 509a1339fafSBenjamin Herrenschmidt * the IODA2 code. 510a1339fafSBenjamin Herrenschmidt */ 51199451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51299451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51399451551SGavin Shan else 514262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 515c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 516c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 517262af557SGuo Chao } 518262af557SGuo Chao 51949dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52049dec922SGavin Shan { 52149dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52249dec922SGavin Shan struct pnv_ioda_pe *slave; 52349dec922SGavin Shan s64 rc; 52449dec922SGavin Shan 52549dec922SGavin Shan /* Fetch master PE */ 52649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 52749dec922SGavin Shan pe = pe->master; 528ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 529ec8e4e9dSGavin Shan return; 530ec8e4e9dSGavin Shan 53149dec922SGavin Shan pe_no = pe->pe_number; 53249dec922SGavin Shan } 53349dec922SGavin Shan 53449dec922SGavin Shan /* Freeze master PE */ 53549dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53649dec922SGavin Shan pe_no, 53749dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 53849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 53949dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54049dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54149dec922SGavin Shan return; 54249dec922SGavin Shan } 54349dec922SGavin Shan 54449dec922SGavin Shan /* Freeze slave PEs */ 54549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54649dec922SGavin Shan return; 54749dec922SGavin Shan 54849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 54949dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55049dec922SGavin Shan slave->pe_number, 55149dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55249dec922SGavin Shan if (rc != OPAL_SUCCESS) 55349dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55449dec922SGavin Shan __func__, rc, phb->hose->global_number, 55549dec922SGavin Shan slave->pe_number); 55649dec922SGavin Shan } 55749dec922SGavin Shan } 55849dec922SGavin Shan 559e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56049dec922SGavin Shan { 56149dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56249dec922SGavin Shan s64 rc; 56349dec922SGavin Shan 56449dec922SGavin Shan /* Find master PE */ 56549dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 56749dec922SGavin Shan pe = pe->master; 56849dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 56949dec922SGavin Shan pe_no = pe->pe_number; 57049dec922SGavin Shan } 57149dec922SGavin Shan 57249dec922SGavin Shan /* Clear frozen state for master PE */ 57349dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57549dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57649dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 57749dec922SGavin Shan return -EIO; 57849dec922SGavin Shan } 57949dec922SGavin Shan 58049dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58149dec922SGavin Shan return 0; 58249dec922SGavin Shan 58349dec922SGavin Shan /* Clear frozen state for slave PEs */ 58449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58549dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58649dec922SGavin Shan slave->pe_number, 58749dec922SGavin Shan opt); 58849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58949dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59049dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59149dec922SGavin Shan slave->pe_number); 59249dec922SGavin Shan return -EIO; 59349dec922SGavin Shan } 59449dec922SGavin Shan } 59549dec922SGavin Shan 59649dec922SGavin Shan return 0; 59749dec922SGavin Shan } 59849dec922SGavin Shan 59949dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60049dec922SGavin Shan { 60149dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 60249dec922SGavin Shan u8 fstate, state; 60349dec922SGavin Shan __be16 pcierr; 60449dec922SGavin Shan s64 rc; 60549dec922SGavin Shan 60649dec922SGavin Shan /* Sanity check on PE number */ 60792b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 60849dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 60949dec922SGavin Shan 61049dec922SGavin Shan /* 61149dec922SGavin Shan * Fetch the master PE and the PE instance might be 61249dec922SGavin Shan * not initialized yet. 61349dec922SGavin Shan */ 61449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61649dec922SGavin Shan pe = pe->master; 61749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 61849dec922SGavin Shan pe_no = pe->pe_number; 61949dec922SGavin Shan } 62049dec922SGavin Shan 62149dec922SGavin Shan /* Check the master PE */ 62249dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62349dec922SGavin Shan &state, &pcierr, NULL); 62449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62549dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62649dec922SGavin Shan "PHB#%x-PE#%x state\n", 62749dec922SGavin Shan __func__, rc, 62849dec922SGavin Shan phb->hose->global_number, pe_no); 62949dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63049dec922SGavin Shan } 63149dec922SGavin Shan 63249dec922SGavin Shan /* Check the slave PE */ 63349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63449dec922SGavin Shan return state; 63549dec922SGavin Shan 63649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 63749dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 63849dec922SGavin Shan slave->pe_number, 63949dec922SGavin Shan &fstate, 64049dec922SGavin Shan &pcierr, 64149dec922SGavin Shan NULL); 64249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64349dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64449dec922SGavin Shan "PHB#%x-PE#%x state\n", 64549dec922SGavin Shan __func__, rc, 64649dec922SGavin Shan phb->hose->global_number, slave->pe_number); 64749dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 64849dec922SGavin Shan } 64949dec922SGavin Shan 65049dec922SGavin Shan /* 65149dec922SGavin Shan * Override the result based on the ascending 65249dec922SGavin Shan * priority. 65349dec922SGavin Shan */ 65449dec922SGavin Shan if (fstate > state) 65549dec922SGavin Shan state = fstate; 65649dec922SGavin Shan } 65749dec922SGavin Shan 65849dec922SGavin Shan return state; 65949dec922SGavin Shan } 66049dec922SGavin Shan 661184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 662184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 663184cd4a3SBenjamin Herrenschmidt */ 664184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 665f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 666184cd4a3SBenjamin Herrenschmidt { 667184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 668184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 669b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 670184cd4a3SBenjamin Herrenschmidt 671184cd4a3SBenjamin Herrenschmidt if (!pdn) 672184cd4a3SBenjamin Herrenschmidt return NULL; 673184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 674184cd4a3SBenjamin Herrenschmidt return NULL; 675184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 676184cd4a3SBenjamin Herrenschmidt } 677184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 678184cd4a3SBenjamin Herrenschmidt 679b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 680b131a842SGavin Shan struct pnv_ioda_pe *parent, 681b131a842SGavin Shan struct pnv_ioda_pe *child, 682b131a842SGavin Shan bool is_add) 683b131a842SGavin Shan { 684b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 685b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 686b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 687b131a842SGavin Shan struct pnv_ioda_pe *slave; 688b131a842SGavin Shan long rc; 689b131a842SGavin Shan 690b131a842SGavin Shan /* Parent PE affects child PE */ 691b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 692b131a842SGavin Shan child->pe_number, op); 693b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 694b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 695b131a842SGavin Shan rc, desc); 696b131a842SGavin Shan return -ENXIO; 697b131a842SGavin Shan } 698b131a842SGavin Shan 699b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 700b131a842SGavin Shan return 0; 701b131a842SGavin Shan 702b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 703b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 704b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 705b131a842SGavin Shan slave->pe_number, op); 706b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 707b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 708b131a842SGavin Shan rc, desc); 709b131a842SGavin Shan return -ENXIO; 710b131a842SGavin Shan } 711b131a842SGavin Shan } 712b131a842SGavin Shan 713b131a842SGavin Shan return 0; 714b131a842SGavin Shan } 715b131a842SGavin Shan 716b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 717b131a842SGavin Shan struct pnv_ioda_pe *pe, 718b131a842SGavin Shan bool is_add) 719b131a842SGavin Shan { 720b131a842SGavin Shan struct pnv_ioda_pe *slave; 721781a868fSWei Yang struct pci_dev *pdev = NULL; 722b131a842SGavin Shan int ret; 723b131a842SGavin Shan 724b131a842SGavin Shan /* 725b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 726b131a842SGavin Shan * clear slave PE frozen state as well. 727b131a842SGavin Shan */ 728b131a842SGavin Shan if (is_add) { 729b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 730b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 731b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 732b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 733b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 734b131a842SGavin Shan slave->pe_number, 735b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 736b131a842SGavin Shan } 737b131a842SGavin Shan } 738b131a842SGavin Shan 739b131a842SGavin Shan /* 740b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 741b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 742b131a842SGavin Shan * originated from the PE might contribute to other 743b131a842SGavin Shan * PEs. 744b131a842SGavin Shan */ 745b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 746b131a842SGavin Shan if (ret) 747b131a842SGavin Shan return ret; 748b131a842SGavin Shan 749b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 750b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 751b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 752b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 753b131a842SGavin Shan if (ret) 754b131a842SGavin Shan return ret; 755b131a842SGavin Shan } 756b131a842SGavin Shan } 757b131a842SGavin Shan 758b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 759b131a842SGavin Shan pdev = pe->pbus->self; 760781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 761b131a842SGavin Shan pdev = pe->pdev->bus->self; 762781a868fSWei Yang #ifdef CONFIG_PCI_IOV 763781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 764283e2d8aSGavin Shan pdev = pe->parent_dev; 765781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 766b131a842SGavin Shan while (pdev) { 767b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 768b131a842SGavin Shan struct pnv_ioda_pe *parent; 769b131a842SGavin Shan 770b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 771b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 772b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 773b131a842SGavin Shan if (ret) 774b131a842SGavin Shan return ret; 775b131a842SGavin Shan } 776b131a842SGavin Shan 777b131a842SGavin Shan pdev = pdev->bus->self; 778b131a842SGavin Shan } 779b131a842SGavin Shan 780b131a842SGavin Shan return 0; 781b131a842SGavin Shan } 782b131a842SGavin Shan 783781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 784781a868fSWei Yang { 785781a868fSWei Yang struct pci_dev *parent; 786781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 787781a868fSWei Yang int64_t rc; 788781a868fSWei Yang long rid_end, rid; 789781a868fSWei Yang 790781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 791781a868fSWei Yang if (pe->pbus) { 792781a868fSWei Yang int count; 793781a868fSWei Yang 794781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 795781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 796781a868fSWei Yang parent = pe->pbus->self; 797781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 798781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 799781a868fSWei Yang else 800781a868fSWei Yang count = 1; 801781a868fSWei Yang 802781a868fSWei Yang switch(count) { 803781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 804781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 805781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 806781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 807781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 808781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 809781a868fSWei Yang default: 810781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 811781a868fSWei Yang count); 812781a868fSWei Yang /* Do an exact match only */ 813781a868fSWei Yang bcomp = OpalPciBusAll; 814781a868fSWei Yang } 815781a868fSWei Yang rid_end = pe->rid + (count << 8); 816781a868fSWei Yang } else { 81793e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 818781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 819781a868fSWei Yang parent = pe->parent_dev; 820781a868fSWei Yang else 82193e01a50SGavin Shan #endif 822781a868fSWei Yang parent = pe->pdev->bus->self; 823781a868fSWei Yang bcomp = OpalPciBusAll; 824781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 825781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 826781a868fSWei Yang rid_end = pe->rid + 1; 827781a868fSWei Yang } 828781a868fSWei Yang 829781a868fSWei Yang /* Clear the reverse map */ 830781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 831c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 832781a868fSWei Yang 833781a868fSWei Yang /* Release from all parents PELT-V */ 834781a868fSWei Yang while (parent) { 835781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 836781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 837781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 838781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 839781a868fSWei Yang /* XXX What to do in case of error ? */ 840781a868fSWei Yang } 841781a868fSWei Yang parent = parent->bus->self; 842781a868fSWei Yang } 843781a868fSWei Yang 844f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 845781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 846781a868fSWei Yang 847781a868fSWei Yang /* Disassociate PE in PELT */ 848781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 849781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 850781a868fSWei Yang if (rc) 851781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 852781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 853781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 854781a868fSWei Yang if (rc) 855781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 856781a868fSWei Yang 857781a868fSWei Yang pe->pbus = NULL; 858781a868fSWei Yang pe->pdev = NULL; 85993e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 860781a868fSWei Yang pe->parent_dev = NULL; 86193e01a50SGavin Shan #endif 862781a868fSWei Yang 863781a868fSWei Yang return 0; 864781a868fSWei Yang } 865781a868fSWei Yang 866cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 867184cd4a3SBenjamin Herrenschmidt { 868184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 869184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 870184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 871184cd4a3SBenjamin Herrenschmidt 872184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 873184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 874184cd4a3SBenjamin Herrenschmidt int count; 875184cd4a3SBenjamin Herrenschmidt 876184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 877184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 878184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 879fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 880b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 881fb446ad0SGavin Shan else 882fb446ad0SGavin Shan count = 1; 883fb446ad0SGavin Shan 884184cd4a3SBenjamin Herrenschmidt switch(count) { 885184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 886184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 887184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 888184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 889184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 890184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 891184cd4a3SBenjamin Herrenschmidt default: 892781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 893781a868fSWei Yang count); 894184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 895184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 896184cd4a3SBenjamin Herrenschmidt } 897184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 898184cd4a3SBenjamin Herrenschmidt } else { 899781a868fSWei Yang #ifdef CONFIG_PCI_IOV 900781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 901781a868fSWei Yang parent = pe->parent_dev; 902781a868fSWei Yang else 903781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 904184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 905184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 906184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 907184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 908184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 909184cd4a3SBenjamin Herrenschmidt } 910184cd4a3SBenjamin Herrenschmidt 911631ad691SGavin Shan /* 912631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 913631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 914631ad691SGavin Shan * originated from the PE might contribute to other 915631ad691SGavin Shan * PEs. 916631ad691SGavin Shan */ 917184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 918184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 919184cd4a3SBenjamin Herrenschmidt if (rc) { 920184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 921184cd4a3SBenjamin Herrenschmidt return -ENXIO; 922184cd4a3SBenjamin Herrenschmidt } 923631ad691SGavin Shan 9245d2aa710SAlistair Popple /* 9255d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9265d2aa710SAlistair Popple * configuration on them. 9275d2aa710SAlistair Popple */ 9285d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 929b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 930184cd4a3SBenjamin Herrenschmidt 931184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 932184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 933184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 934184cd4a3SBenjamin Herrenschmidt 935184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9364773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9374773f76bSGavin Shan pe->mve_number = 0; 9384773f76bSGavin Shan goto out; 9394773f76bSGavin Shan } 9404773f76bSGavin Shan 941184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9424773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9434773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9441f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 945184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 946184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 947184cd4a3SBenjamin Herrenschmidt } else { 948184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 949cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 950184cd4a3SBenjamin Herrenschmidt if (rc) { 9511f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 952184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 953184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 954184cd4a3SBenjamin Herrenschmidt } 955184cd4a3SBenjamin Herrenschmidt } 956184cd4a3SBenjamin Herrenschmidt 9574773f76bSGavin Shan out: 958184cd4a3SBenjamin Herrenschmidt return 0; 959184cd4a3SBenjamin Herrenschmidt } 960184cd4a3SBenjamin Herrenschmidt 961781a868fSWei Yang #ifdef CONFIG_PCI_IOV 962781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 963781a868fSWei Yang { 964781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 965781a868fSWei Yang int i; 966781a868fSWei Yang struct resource *res, res2; 967781a868fSWei Yang resource_size_t size; 968781a868fSWei Yang u16 num_vfs; 969781a868fSWei Yang 970781a868fSWei Yang if (!dev->is_physfn) 971781a868fSWei Yang return -EINVAL; 972781a868fSWei Yang 973781a868fSWei Yang /* 974781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 975781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 976781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 977781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 978781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 979781a868fSWei Yang * range of PEs the VFs are in. 980781a868fSWei Yang */ 981781a868fSWei Yang num_vfs = pdn->num_vfs; 982781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 983781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 984781a868fSWei Yang if (!res->flags || !res->parent) 985781a868fSWei Yang continue; 986781a868fSWei Yang 987781a868fSWei Yang /* 988781a868fSWei Yang * The actual IOV BAR range is determined by the start address 989781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 990781a868fSWei Yang * make sure that after shifting, the range will not overlap 991781a868fSWei Yang * with another device. 992781a868fSWei Yang */ 993781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 994781a868fSWei Yang res2.flags = res->flags; 995781a868fSWei Yang res2.start = res->start + (size * offset); 996781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 997781a868fSWei Yang 998781a868fSWei Yang if (res2.end > res->end) { 999781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1000781a868fSWei Yang i, &res2, res, num_vfs, offset); 1001781a868fSWei Yang return -EBUSY; 1002781a868fSWei Yang } 1003781a868fSWei Yang } 1004781a868fSWei Yang 1005781a868fSWei Yang /* 1006781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 1007781a868fSWei Yang * offset is a positive value. It looks like the device return some 1008781a868fSWei Yang * mmio back to the system, which actually no one could use it. 1009781a868fSWei Yang */ 1010781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1011781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1012781a868fSWei Yang if (!res->flags || !res->parent) 1013781a868fSWei Yang continue; 1014781a868fSWei Yang 1015781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1016781a868fSWei Yang res2 = *res; 1017781a868fSWei Yang res->start += size * offset; 1018781a868fSWei Yang 101974703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 102074703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102174703cc4SWei Yang num_vfs, offset); 1022781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1023781a868fSWei Yang } 1024781a868fSWei Yang return 0; 1025781a868fSWei Yang } 1026781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1027781a868fSWei Yang 1028cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1029184cd4a3SBenjamin Herrenschmidt { 1030184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1031184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1032b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1033184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1034184cd4a3SBenjamin Herrenschmidt 1035184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1036184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1037184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1038184cd4a3SBenjamin Herrenschmidt return NULL; 1039184cd4a3SBenjamin Herrenschmidt } 1040184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1041184cd4a3SBenjamin Herrenschmidt return NULL; 1042184cd4a3SBenjamin Herrenschmidt 10431e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10441e916772SGavin Shan if (!pe) { 1045184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 1046184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1047184cd4a3SBenjamin Herrenschmidt return NULL; 1048184cd4a3SBenjamin Herrenschmidt } 1049184cd4a3SBenjamin Herrenschmidt 1050184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1051184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1052184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1053184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1054184cd4a3SBenjamin Herrenschmidt * 1055184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1056184cd4a3SBenjamin Herrenschmidt */ 1057184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 1058184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 10591e916772SGavin Shan pdn->pe_number = pe->pe_number; 10605d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1061184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1062184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1063184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1064184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1065184cd4a3SBenjamin Herrenschmidt 1066184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1067184cd4a3SBenjamin Herrenschmidt 1068184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1069184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10701e916772SGavin Shan pnv_ioda_free_pe(pe); 1071184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1072184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1073184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1074184cd4a3SBenjamin Herrenschmidt return NULL; 1075184cd4a3SBenjamin Herrenschmidt } 1076184cd4a3SBenjamin Herrenschmidt 10771d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10781d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10791d4e89cfSAlexey Kardashevskiy 1080184cd4a3SBenjamin Herrenschmidt return pe; 1081184cd4a3SBenjamin Herrenschmidt } 1082184cd4a3SBenjamin Herrenschmidt 1083184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1084184cd4a3SBenjamin Herrenschmidt { 1085184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1086184cd4a3SBenjamin Herrenschmidt 1087184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1088b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1089184cd4a3SBenjamin Herrenschmidt 1090184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1091184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1092184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1093184cd4a3SBenjamin Herrenschmidt continue; 1094184cd4a3SBenjamin Herrenschmidt } 1095ccd1c191SGavin Shan 1096ccd1c191SGavin Shan /* 1097ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1098ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1099ccd1c191SGavin Shan * again. 1100ccd1c191SGavin Shan */ 1101ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1102ccd1c191SGavin Shan continue; 1103ccd1c191SGavin Shan 1104c5f7700bSGavin Shan pe->device_count++; 110594973b24SAlistair Popple pdn->pcidev = dev; 1106184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1107fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1108184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1109184cd4a3SBenjamin Herrenschmidt } 1110184cd4a3SBenjamin Herrenschmidt } 1111184cd4a3SBenjamin Herrenschmidt 1112fb446ad0SGavin Shan /* 1113fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1114fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1115fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1116fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1117fb446ad0SGavin Shan */ 11181e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1119184cd4a3SBenjamin Herrenschmidt { 1120fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1121184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11221e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1123ccd1c191SGavin Shan unsigned int pe_num; 1124ccd1c191SGavin Shan 1125ccd1c191SGavin Shan /* 1126ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1127ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1128ccd1c191SGavin Shan */ 1129ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1130ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1131ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1132ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1133ccd1c191SGavin Shan return NULL; 1134ccd1c191SGavin Shan } 1135184cd4a3SBenjamin Herrenschmidt 113663803c39SGavin Shan /* PE number for root bus should have been reserved */ 113763803c39SGavin Shan if (pci_is_root_bus(bus) && 113863803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 113963803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 114063803c39SGavin Shan 1141262af557SGuo Chao /* Check if PE is determined by M64 */ 114263803c39SGavin Shan if (!pe && phb->pick_m64_pe) 11431e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1144262af557SGuo Chao 1145262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11461e916772SGavin Shan if (!pe) 11471e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1148262af557SGuo Chao 11491e916772SGavin Shan if (!pe) { 1150fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1151fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11521e916772SGavin Shan return NULL; 1153184cd4a3SBenjamin Herrenschmidt } 1154184cd4a3SBenjamin Herrenschmidt 1155262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1156184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1157184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1158184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1159b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1160184cd4a3SBenjamin Herrenschmidt 1161fb446ad0SGavin Shan if (all) 11621f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11631e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1164fb446ad0SGavin Shan else 11651f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11661e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1167184cd4a3SBenjamin Herrenschmidt 1168184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1169184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11701e916772SGavin Shan pnv_ioda_free_pe(pe); 1171184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11721e916772SGavin Shan return NULL; 1173184cd4a3SBenjamin Herrenschmidt } 1174184cd4a3SBenjamin Herrenschmidt 1175184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1176184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1177184cd4a3SBenjamin Herrenschmidt 11787ebdf956SGavin Shan /* Put PE to the list */ 11797ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11801e916772SGavin Shan 11811e916772SGavin Shan return pe; 1182184cd4a3SBenjamin Herrenschmidt } 1183184cd4a3SBenjamin Herrenschmidt 1184b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11855d2aa710SAlistair Popple { 1186b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1187b521549aSAlistair Popple long rid; 1188b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1189b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1190b521549aSAlistair Popple struct pci_dn *npu_pdn; 1191b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1192b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1193b521549aSAlistair Popple 1194b521549aSAlistair Popple /* 1195b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1196b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1197b521549aSAlistair Popple * which need to be assigned to four links, implying some 1198b521549aSAlistair Popple * links must share PEs. 1199b521549aSAlistair Popple * 1200b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1201b521549aSAlistair Popple * same GPU get assigned the same PE. 1202b521549aSAlistair Popple */ 1203b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 120492b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1205b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1206b521549aSAlistair Popple if (!pe->pdev) 1207b521549aSAlistair Popple continue; 1208b521549aSAlistair Popple 1209b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1210b521549aSAlistair Popple /* 1211b521549aSAlistair Popple * This device has the same peer GPU so should 1212b521549aSAlistair Popple * be assigned the same PE as the existing 1213b521549aSAlistair Popple * peer NPU. 1214b521549aSAlistair Popple */ 1215b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12161f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1217b521549aSAlistair Popple pci_dev_get(npu_pdev); 1218b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1219b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1220b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1221b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1222b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1223b521549aSAlistair Popple 1224b521549aSAlistair Popple /* Map the PE to this link */ 1225b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1226b521549aSAlistair Popple OpalPciBusAll, 1227b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1228b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1229b521549aSAlistair Popple OPAL_MAP_PE); 1230b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1231b521549aSAlistair Popple found_pe = true; 1232b521549aSAlistair Popple break; 1233b521549aSAlistair Popple } 1234b521549aSAlistair Popple } 1235b521549aSAlistair Popple 1236b521549aSAlistair Popple if (!found_pe) 1237b521549aSAlistair Popple /* 1238b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1239b521549aSAlistair Popple * one. 1240b521549aSAlistair Popple */ 1241b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1242b521549aSAlistair Popple else 1243b521549aSAlistair Popple return pe; 1244b521549aSAlistair Popple } 1245b521549aSAlistair Popple 1246b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1247b521549aSAlistair Popple { 12485d2aa710SAlistair Popple struct pci_dev *pdev; 12495d2aa710SAlistair Popple 12505d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1251b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12525d2aa710SAlistair Popple } 12535d2aa710SAlistair Popple 1254cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1255fb446ad0SGavin Shan { 1256fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1257262af557SGuo Chao struct pnv_phb *phb; 1258fb446ad0SGavin Shan 1259fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1260262af557SGuo Chao phb = hose->private_data; 126108f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 126208f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 126308f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1264b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 1265ccd1c191SGavin Shan } 1266fb446ad0SGavin Shan } 1267fb446ad0SGavin Shan } 1268184cd4a3SBenjamin Herrenschmidt 1269a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1270ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1271781a868fSWei Yang { 1272781a868fSWei Yang struct pci_bus *bus; 1273781a868fSWei Yang struct pci_controller *hose; 1274781a868fSWei Yang struct pnv_phb *phb; 1275781a868fSWei Yang struct pci_dn *pdn; 127602639b0eSWei Yang int i, j; 1277ee8222feSWei Yang int m64_bars; 1278781a868fSWei Yang 1279781a868fSWei Yang bus = pdev->bus; 1280781a868fSWei Yang hose = pci_bus_to_host(bus); 1281781a868fSWei Yang phb = hose->private_data; 1282781a868fSWei Yang pdn = pci_get_pdn(pdev); 1283781a868fSWei Yang 1284ee8222feSWei Yang if (pdn->m64_single_mode) 1285ee8222feSWei Yang m64_bars = num_vfs; 1286ee8222feSWei Yang else 1287ee8222feSWei Yang m64_bars = 1; 1288ee8222feSWei Yang 128902639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1290ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1291ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1292781a868fSWei Yang continue; 1293781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1294ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1295ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1296ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1297781a868fSWei Yang } 1298781a868fSWei Yang 1299ee8222feSWei Yang kfree(pdn->m64_map); 1300781a868fSWei Yang return 0; 1301781a868fSWei Yang } 1302781a868fSWei Yang 130302639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1304781a868fSWei Yang { 1305781a868fSWei Yang struct pci_bus *bus; 1306781a868fSWei Yang struct pci_controller *hose; 1307781a868fSWei Yang struct pnv_phb *phb; 1308781a868fSWei Yang struct pci_dn *pdn; 1309781a868fSWei Yang unsigned int win; 1310781a868fSWei Yang struct resource *res; 131102639b0eSWei Yang int i, j; 1312781a868fSWei Yang int64_t rc; 131302639b0eSWei Yang int total_vfs; 131402639b0eSWei Yang resource_size_t size, start; 131502639b0eSWei Yang int pe_num; 1316ee8222feSWei Yang int m64_bars; 1317781a868fSWei Yang 1318781a868fSWei Yang bus = pdev->bus; 1319781a868fSWei Yang hose = pci_bus_to_host(bus); 1320781a868fSWei Yang phb = hose->private_data; 1321781a868fSWei Yang pdn = pci_get_pdn(pdev); 132202639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1323781a868fSWei Yang 1324ee8222feSWei Yang if (pdn->m64_single_mode) 1325ee8222feSWei Yang m64_bars = num_vfs; 1326ee8222feSWei Yang else 1327ee8222feSWei Yang m64_bars = 1; 132802639b0eSWei Yang 1329ee8222feSWei Yang pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1330ee8222feSWei Yang if (!pdn->m64_map) 1331ee8222feSWei Yang return -ENOMEM; 1332ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1333ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1334ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1335ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1336ee8222feSWei Yang 1337781a868fSWei Yang 1338781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1339781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1340781a868fSWei Yang if (!res->flags || !res->parent) 1341781a868fSWei Yang continue; 1342781a868fSWei Yang 1343ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1344781a868fSWei Yang do { 1345781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1346781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1347781a868fSWei Yang 1348781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1349781a868fSWei Yang goto m64_failed; 1350781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1351781a868fSWei Yang 1352ee8222feSWei Yang pdn->m64_map[j][i] = win; 135302639b0eSWei Yang 1354ee8222feSWei Yang if (pdn->m64_single_mode) { 135502639b0eSWei Yang size = pci_iov_resource_size(pdev, 135602639b0eSWei Yang PCI_IOV_RESOURCES + i); 135702639b0eSWei Yang start = res->start + size * j; 135802639b0eSWei Yang } else { 135902639b0eSWei Yang size = resource_size(res); 136002639b0eSWei Yang start = res->start; 136102639b0eSWei Yang } 1362781a868fSWei Yang 1363781a868fSWei Yang /* Map the M64 here */ 1364ee8222feSWei Yang if (pdn->m64_single_mode) { 1365be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 136602639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 136702639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1368ee8222feSWei Yang pdn->m64_map[j][i], 0); 136902639b0eSWei Yang } 137002639b0eSWei Yang 1371781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1372781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1373ee8222feSWei Yang pdn->m64_map[j][i], 137402639b0eSWei Yang start, 1375781a868fSWei Yang 0, /* unused */ 137602639b0eSWei Yang size); 137702639b0eSWei Yang 137802639b0eSWei Yang 1379781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1380781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1381781a868fSWei Yang win, rc); 1382781a868fSWei Yang goto m64_failed; 1383781a868fSWei Yang } 1384781a868fSWei Yang 1385ee8222feSWei Yang if (pdn->m64_single_mode) 1386781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1387ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 138802639b0eSWei Yang else 138902639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1390ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 139102639b0eSWei Yang 1392781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1393781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1394781a868fSWei Yang win, rc); 1395781a868fSWei Yang goto m64_failed; 1396781a868fSWei Yang } 1397781a868fSWei Yang } 139802639b0eSWei Yang } 1399781a868fSWei Yang return 0; 1400781a868fSWei Yang 1401781a868fSWei Yang m64_failed: 1402ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1403781a868fSWei Yang return -EBUSY; 1404781a868fSWei Yang } 1405781a868fSWei Yang 1406c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1407c035e37bSAlexey Kardashevskiy int num); 1408c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1409c035e37bSAlexey Kardashevskiy 1410781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1411781a868fSWei Yang { 1412781a868fSWei Yang struct iommu_table *tbl; 1413781a868fSWei Yang int64_t rc; 1414781a868fSWei Yang 1415b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1416c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1417781a868fSWei Yang if (rc) 1418781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1419781a868fSWei Yang 1420c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14210eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14220eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14230eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1424ac9a5889SAlexey Kardashevskiy } 1425aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1426781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1427781a868fSWei Yang } 1428781a868fSWei Yang 1429ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1430781a868fSWei Yang { 1431781a868fSWei Yang struct pci_bus *bus; 1432781a868fSWei Yang struct pci_controller *hose; 1433781a868fSWei Yang struct pnv_phb *phb; 1434781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1435781a868fSWei Yang struct pci_dn *pdn; 1436781a868fSWei Yang 1437781a868fSWei Yang bus = pdev->bus; 1438781a868fSWei Yang hose = pci_bus_to_host(bus); 1439781a868fSWei Yang phb = hose->private_data; 144002639b0eSWei Yang pdn = pci_get_pdn(pdev); 1441781a868fSWei Yang 1442781a868fSWei Yang if (!pdev->is_physfn) 1443781a868fSWei Yang return; 1444781a868fSWei Yang 1445781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1446781a868fSWei Yang if (pe->parent_dev != pdev) 1447781a868fSWei Yang continue; 1448781a868fSWei Yang 1449781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1450781a868fSWei Yang 1451781a868fSWei Yang /* Remove from list */ 1452781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1453781a868fSWei Yang list_del(&pe->list); 1454781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1455781a868fSWei Yang 1456781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1457781a868fSWei Yang 14581e916772SGavin Shan pnv_ioda_free_pe(pe); 1459781a868fSWei Yang } 1460781a868fSWei Yang } 1461781a868fSWei Yang 1462781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1463781a868fSWei Yang { 1464781a868fSWei Yang struct pci_bus *bus; 1465781a868fSWei Yang struct pci_controller *hose; 1466781a868fSWei Yang struct pnv_phb *phb; 14671e916772SGavin Shan struct pnv_ioda_pe *pe; 1468781a868fSWei Yang struct pci_dn *pdn; 1469781a868fSWei Yang struct pci_sriov *iov; 1470be283eebSWei Yang u16 num_vfs, i; 1471781a868fSWei Yang 1472781a868fSWei Yang bus = pdev->bus; 1473781a868fSWei Yang hose = pci_bus_to_host(bus); 1474781a868fSWei Yang phb = hose->private_data; 1475781a868fSWei Yang pdn = pci_get_pdn(pdev); 1476781a868fSWei Yang iov = pdev->sriov; 1477781a868fSWei Yang num_vfs = pdn->num_vfs; 1478781a868fSWei Yang 1479781a868fSWei Yang /* Release VF PEs */ 1480ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1481781a868fSWei Yang 1482781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1483ee8222feSWei Yang if (!pdn->m64_single_mode) 1484be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1485781a868fSWei Yang 1486781a868fSWei Yang /* Release M64 windows */ 1487ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1488781a868fSWei Yang 1489781a868fSWei Yang /* Release PE numbers */ 1490be283eebSWei Yang if (pdn->m64_single_mode) { 1491be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 14921e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 14931e916772SGavin Shan continue; 14941e916772SGavin Shan 14951e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 14961e916772SGavin Shan pnv_ioda_free_pe(pe); 1497be283eebSWei Yang } 1498be283eebSWei Yang } else 1499be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1500be283eebSWei Yang /* Releasing pe_num_map */ 1501be283eebSWei Yang kfree(pdn->pe_num_map); 1502781a868fSWei Yang } 1503781a868fSWei Yang } 1504781a868fSWei Yang 1505781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1506781a868fSWei Yang struct pnv_ioda_pe *pe); 1507781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1508781a868fSWei Yang { 1509781a868fSWei Yang struct pci_bus *bus; 1510781a868fSWei Yang struct pci_controller *hose; 1511781a868fSWei Yang struct pnv_phb *phb; 1512781a868fSWei Yang struct pnv_ioda_pe *pe; 1513781a868fSWei Yang int pe_num; 1514781a868fSWei Yang u16 vf_index; 1515781a868fSWei Yang struct pci_dn *pdn; 1516781a868fSWei Yang 1517781a868fSWei Yang bus = pdev->bus; 1518781a868fSWei Yang hose = pci_bus_to_host(bus); 1519781a868fSWei Yang phb = hose->private_data; 1520781a868fSWei Yang pdn = pci_get_pdn(pdev); 1521781a868fSWei Yang 1522781a868fSWei Yang if (!pdev->is_physfn) 1523781a868fSWei Yang return; 1524781a868fSWei Yang 1525781a868fSWei Yang /* Reserve PE for each VF */ 1526781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1527be283eebSWei Yang if (pdn->m64_single_mode) 1528be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1529be283eebSWei Yang else 1530be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1531781a868fSWei Yang 1532781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1533781a868fSWei Yang pe->pe_number = pe_num; 1534781a868fSWei Yang pe->phb = phb; 1535781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1536781a868fSWei Yang pe->pbus = NULL; 1537781a868fSWei Yang pe->parent_dev = pdev; 1538781a868fSWei Yang pe->mve_number = -1; 1539781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1540781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1541781a868fSWei Yang 15421f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1543781a868fSWei Yang hose->global_number, pdev->bus->number, 1544781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1545781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1546781a868fSWei Yang 1547781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1548781a868fSWei Yang /* XXX What do we do here ? */ 15491e916772SGavin Shan pnv_ioda_free_pe(pe); 1550781a868fSWei Yang pe->pdev = NULL; 1551781a868fSWei Yang continue; 1552781a868fSWei Yang } 1553781a868fSWei Yang 1554781a868fSWei Yang /* Put PE to the list */ 1555781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1556781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1557781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1558781a868fSWei Yang 1559781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1560781a868fSWei Yang } 1561781a868fSWei Yang } 1562781a868fSWei Yang 1563781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1564781a868fSWei Yang { 1565781a868fSWei Yang struct pci_bus *bus; 1566781a868fSWei Yang struct pci_controller *hose; 1567781a868fSWei Yang struct pnv_phb *phb; 15681e916772SGavin Shan struct pnv_ioda_pe *pe; 1569781a868fSWei Yang struct pci_dn *pdn; 1570781a868fSWei Yang int ret; 1571be283eebSWei Yang u16 i; 1572781a868fSWei Yang 1573781a868fSWei Yang bus = pdev->bus; 1574781a868fSWei Yang hose = pci_bus_to_host(bus); 1575781a868fSWei Yang phb = hose->private_data; 1576781a868fSWei Yang pdn = pci_get_pdn(pdev); 1577781a868fSWei Yang 1578781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1579b0331854SWei Yang if (!pdn->vfs_expanded) { 1580b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1581b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1582b0331854SWei Yang return -ENOSPC; 1583b0331854SWei Yang } 1584b0331854SWei Yang 1585ee8222feSWei Yang /* 1586ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1587ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1588ee8222feSWei Yang */ 1589ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1590ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1591ee8222feSWei Yang return -EBUSY; 1592ee8222feSWei Yang } 1593ee8222feSWei Yang 1594be283eebSWei Yang /* Allocating pe_num_map */ 1595be283eebSWei Yang if (pdn->m64_single_mode) 1596be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1597be283eebSWei Yang GFP_KERNEL); 1598be283eebSWei Yang else 1599be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1600be283eebSWei Yang 1601be283eebSWei Yang if (!pdn->pe_num_map) 1602be283eebSWei Yang return -ENOMEM; 1603be283eebSWei Yang 1604be283eebSWei Yang if (pdn->m64_single_mode) 1605be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1606be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1607be283eebSWei Yang 1608781a868fSWei Yang /* Calculate available PE for required VFs */ 1609be283eebSWei Yang if (pdn->m64_single_mode) { 1610be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16111e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16121e916772SGavin Shan if (!pe) { 1613be283eebSWei Yang ret = -EBUSY; 1614be283eebSWei Yang goto m64_failed; 1615be283eebSWei Yang } 16161e916772SGavin Shan 16171e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1618be283eebSWei Yang } 1619be283eebSWei Yang } else { 1620781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1621be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 162292b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1623781a868fSWei Yang 0, num_vfs, 0); 162492b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1625781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1626781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1627be283eebSWei Yang kfree(pdn->pe_num_map); 1628781a868fSWei Yang return -EBUSY; 1629781a868fSWei Yang } 1630be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1631781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1632be283eebSWei Yang } 1633be283eebSWei Yang pdn->num_vfs = num_vfs; 1634781a868fSWei Yang 1635781a868fSWei Yang /* Assign M64 window accordingly */ 163602639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1637781a868fSWei Yang if (ret) { 1638781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1639781a868fSWei Yang goto m64_failed; 1640781a868fSWei Yang } 1641781a868fSWei Yang 1642781a868fSWei Yang /* 1643781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1644781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1645781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1646781a868fSWei Yang */ 1647ee8222feSWei Yang if (!pdn->m64_single_mode) { 1648be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1649781a868fSWei Yang if (ret) 1650781a868fSWei Yang goto m64_failed; 1651781a868fSWei Yang } 165202639b0eSWei Yang } 1653781a868fSWei Yang 1654781a868fSWei Yang /* Setup VF PEs */ 1655781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1656781a868fSWei Yang 1657781a868fSWei Yang return 0; 1658781a868fSWei Yang 1659781a868fSWei Yang m64_failed: 1660be283eebSWei Yang if (pdn->m64_single_mode) { 1661be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16621e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16631e916772SGavin Shan continue; 16641e916772SGavin Shan 16651e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16661e916772SGavin Shan pnv_ioda_free_pe(pe); 1667be283eebSWei Yang } 1668be283eebSWei Yang } else 1669be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1670be283eebSWei Yang 1671be283eebSWei Yang /* Releasing pe_num_map */ 1672be283eebSWei Yang kfree(pdn->pe_num_map); 1673781a868fSWei Yang 1674781a868fSWei Yang return ret; 1675781a868fSWei Yang } 1676781a868fSWei Yang 1677a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1678a8b2f828SGavin Shan { 1679781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1680781a868fSWei Yang 1681a8b2f828SGavin Shan /* Release PCI data */ 1682a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1683a8b2f828SGavin Shan return 0; 1684a8b2f828SGavin Shan } 1685a8b2f828SGavin Shan 1686a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1687a8b2f828SGavin Shan { 1688a8b2f828SGavin Shan /* Allocate PCI data */ 1689a8b2f828SGavin Shan add_dev_pci_data(pdev); 1690781a868fSWei Yang 1691ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1692a8b2f828SGavin Shan } 1693a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1694a8b2f828SGavin Shan 1695959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1696184cd4a3SBenjamin Herrenschmidt { 1697b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1698959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1699184cd4a3SBenjamin Herrenschmidt 1700959c9bddSGavin Shan /* 1701959c9bddSGavin Shan * The function can be called while the PE# 1702959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1703959c9bddSGavin Shan * case. 1704959c9bddSGavin Shan */ 1705959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1706959c9bddSGavin Shan return; 1707184cd4a3SBenjamin Herrenschmidt 1708959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1709cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17100e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1711b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17124617082eSAlexey Kardashevskiy /* 17134617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17144617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17154617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17164617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17174617082eSAlexey Kardashevskiy */ 1718184cd4a3SBenjamin Herrenschmidt } 1719184cd4a3SBenjamin Herrenschmidt 1720763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1721cd15b048SBenjamin Herrenschmidt { 1722763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1723763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1724cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1725cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1726cd15b048SBenjamin Herrenschmidt uint64_t top; 1727cd15b048SBenjamin Herrenschmidt bool bypass = false; 1728cd15b048SBenjamin Herrenschmidt 1729cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1730cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1731cd15b048SBenjamin Herrenschmidt 1732cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1733cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1734cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1735cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1736cd15b048SBenjamin Herrenschmidt } 1737cd15b048SBenjamin Herrenschmidt 1738cd15b048SBenjamin Herrenschmidt if (bypass) { 1739cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1740cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1741cd15b048SBenjamin Herrenschmidt } else { 1742cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1743cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1744cd15b048SBenjamin Herrenschmidt } 1745a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 17465d2aa710SAlistair Popple 17475d2aa710SAlistair Popple /* Update peer npu devices */ 1748f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 17495d2aa710SAlistair Popple 1750cd15b048SBenjamin Herrenschmidt return 0; 1751cd15b048SBenjamin Herrenschmidt } 1752cd15b048SBenjamin Herrenschmidt 175353522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1754fe7e85c6SGavin Shan { 175553522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 175653522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1757fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1758fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1759fe7e85c6SGavin Shan u64 end, mask; 1760fe7e85c6SGavin Shan 1761fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1762fe7e85c6SGavin Shan return 0; 1763fe7e85c6SGavin Shan 1764fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1765fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1766fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1767fe7e85c6SGavin Shan 1768fe7e85c6SGavin Shan 1769fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1770fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1771fe7e85c6SGavin Shan mask += mask - 1; 1772fe7e85c6SGavin Shan 1773fe7e85c6SGavin Shan return mask; 1774fe7e85c6SGavin Shan } 1775fe7e85c6SGavin Shan 1776dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1777ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 177874251fe2SBenjamin Herrenschmidt { 177974251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 178074251fe2SBenjamin Herrenschmidt 178174251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1782b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1783e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 17844617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1785dff4a39eSGavin Shan 17865c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1787ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 178874251fe2SBenjamin Herrenschmidt } 178974251fe2SBenjamin Herrenschmidt } 179074251fe2SBenjamin Herrenschmidt 1791fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1792fd141d1aSBenjamin Herrenschmidt bool real_mode) 1793fd141d1aSBenjamin Herrenschmidt { 1794fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1795fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1796fd141d1aSBenjamin Herrenschmidt } 1797fd141d1aSBenjamin Herrenschmidt 1798a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1799decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 18004cce9550SGavin Shan { 18010eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 18020eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 18030eaf4defSAlexey Kardashevskiy next); 18040eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1805b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1806fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 18074cce9550SGavin Shan unsigned long start, end, inc; 18084cce9550SGavin Shan 1809decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1810decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1811decbda25SAlexey Kardashevskiy npages - 1); 18124cce9550SGavin Shan 18134cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 18144cce9550SGavin Shan start |= (1ull << 63); 18154cce9550SGavin Shan end |= (1ull << 63); 18164cce9550SGavin Shan inc = 16; 18174cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 18184cce9550SGavin Shan 18194cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 18204cce9550SGavin Shan while (start <= end) { 18218e0a1611SAlexey Kardashevskiy if (rm) 18223ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18238e0a1611SAlexey Kardashevskiy else 18243a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18254cce9550SGavin Shan start += inc; 18264cce9550SGavin Shan } 18274cce9550SGavin Shan 18284cce9550SGavin Shan /* 18294cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 18304cce9550SGavin Shan * and we don't care on free() 18314cce9550SGavin Shan */ 18324cce9550SGavin Shan } 18334cce9550SGavin Shan 1834decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1835decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1836decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 183700085f1eSKrzysztof Kozlowski unsigned long attrs) 1838decbda25SAlexey Kardashevskiy { 1839decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1840decbda25SAlexey Kardashevskiy attrs); 1841decbda25SAlexey Kardashevskiy 184208acce1cSBenjamin Herrenschmidt if (!ret) 1843a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1844decbda25SAlexey Kardashevskiy 1845decbda25SAlexey Kardashevskiy return ret; 1846decbda25SAlexey Kardashevskiy } 1847decbda25SAlexey Kardashevskiy 184805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 184905c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 185005c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 185105c6cfb9SAlexey Kardashevskiy { 185205c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 185305c6cfb9SAlexey Kardashevskiy 185408acce1cSBenjamin Herrenschmidt if (!ret) 1855a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 185605c6cfb9SAlexey Kardashevskiy 185705c6cfb9SAlexey Kardashevskiy return ret; 185805c6cfb9SAlexey Kardashevskiy } 185905c6cfb9SAlexey Kardashevskiy #endif 186005c6cfb9SAlexey Kardashevskiy 1861decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1862decbda25SAlexey Kardashevskiy long npages) 1863decbda25SAlexey Kardashevskiy { 1864decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1865decbda25SAlexey Kardashevskiy 1866a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1867decbda25SAlexey Kardashevskiy } 1868decbda25SAlexey Kardashevskiy 1869da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1870decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 187105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 187205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 187305c6cfb9SAlexey Kardashevskiy #endif 1874decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1875da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1876da004c36SAlexey Kardashevskiy }; 1877da004c36SAlexey Kardashevskiy 1878a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1879a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1880a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1881bef9253fSAlexey Kardashevskiy 1882a34ab7c3SBenjamin Herrenschmidt void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 18830bbcdb43SAlexey Kardashevskiy { 1884fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1885a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 18860bbcdb43SAlexey Kardashevskiy 18870bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 18880bbcdb43SAlexey Kardashevskiy if (rm) 1889fd141d1aSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(val), invalidate); 18900bbcdb43SAlexey Kardashevskiy else 1891fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 18920bbcdb43SAlexey Kardashevskiy } 18930bbcdb43SAlexey Kardashevskiy 1894a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 18955780fb04SAlexey Kardashevskiy { 18965780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1897fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1898a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 18995780fb04SAlexey Kardashevskiy 19005780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1901fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 19025780fb04SAlexey Kardashevskiy } 19035780fb04SAlexey Kardashevskiy 1904fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1905fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1906fd141d1aSBenjamin Herrenschmidt unsigned long npages) 19074cce9550SGavin Shan { 19084d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19094cce9550SGavin Shan unsigned long start, end, inc; 19104cce9550SGavin Shan 19114cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1912a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1913fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 19144cce9550SGavin Shan end = start; 19154cce9550SGavin Shan 19164cce9550SGavin Shan /* Figure out the start, end and step */ 1917decbda25SAlexey Kardashevskiy start |= (index << shift); 1918decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1919b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 19204cce9550SGavin Shan mb(); 19214cce9550SGavin Shan 19224cce9550SGavin Shan while (start <= end) { 19238e0a1611SAlexey Kardashevskiy if (rm) 19243ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 19258e0a1611SAlexey Kardashevskiy else 19263a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 19274cce9550SGavin Shan start += inc; 19284cce9550SGavin Shan } 19294cce9550SGavin Shan } 19304cce9550SGavin Shan 1931f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1932f0228c41SBenjamin Herrenschmidt { 1933f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1934f0228c41SBenjamin Herrenschmidt 1935f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1936f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1937f0228c41SBenjamin Herrenschmidt else 1938f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1939f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1940f0228c41SBenjamin Herrenschmidt } 1941f0228c41SBenjamin Herrenschmidt 1942e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1943e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1944e57080f1SAlexey Kardashevskiy { 1945e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1946e57080f1SAlexey Kardashevskiy 1947e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1948e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1949e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1950f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1951f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1952f0228c41SBenjamin Herrenschmidt 1953f0228c41SBenjamin Herrenschmidt if (phb->type == PNV_PHB_NPU) { 19540bbcdb43SAlexey Kardashevskiy /* 19550bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 19560bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 19570bbcdb43SAlexey Kardashevskiy * the entire cache for it. 19580bbcdb43SAlexey Kardashevskiy */ 1959f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 19605d2aa710SAlistair Popple continue; 19615d2aa710SAlistair Popple } 1962f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1963f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 196485674868SAlexey Kardashevskiy index, npages); 1965f0228c41SBenjamin Herrenschmidt else if (rm) 1966f0228c41SBenjamin Herrenschmidt opal_rm_pci_tce_kill(phb->opal_id, 1967f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1968f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1969f0228c41SBenjamin Herrenschmidt index << shift, npages); 1970f0228c41SBenjamin Herrenschmidt else 1971f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 1972f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1973f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1974f0228c41SBenjamin Herrenschmidt index << shift, npages); 1975e57080f1SAlexey Kardashevskiy } 1976e57080f1SAlexey Kardashevskiy } 1977e57080f1SAlexey Kardashevskiy 1978decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1979decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1980decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 198100085f1eSKrzysztof Kozlowski unsigned long attrs) 19824cce9550SGavin Shan { 1983decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1984decbda25SAlexey Kardashevskiy attrs); 19854cce9550SGavin Shan 198608acce1cSBenjamin Herrenschmidt if (!ret) 1987decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1988decbda25SAlexey Kardashevskiy 1989decbda25SAlexey Kardashevskiy return ret; 1990decbda25SAlexey Kardashevskiy } 1991decbda25SAlexey Kardashevskiy 199205c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 199305c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 199405c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 199505c6cfb9SAlexey Kardashevskiy { 199605c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 199705c6cfb9SAlexey Kardashevskiy 199808acce1cSBenjamin Herrenschmidt if (!ret) 199905c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 200005c6cfb9SAlexey Kardashevskiy 200105c6cfb9SAlexey Kardashevskiy return ret; 200205c6cfb9SAlexey Kardashevskiy } 200305c6cfb9SAlexey Kardashevskiy #endif 200405c6cfb9SAlexey Kardashevskiy 2005decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2006decbda25SAlexey Kardashevskiy long npages) 2007decbda25SAlexey Kardashevskiy { 2008decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2009decbda25SAlexey Kardashevskiy 2010decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 20114cce9550SGavin Shan } 20124cce9550SGavin Shan 20134793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 20144793d65dSAlexey Kardashevskiy { 20154793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 20164793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 20174793d65dSAlexey Kardashevskiy } 20184793d65dSAlexey Kardashevskiy 2019da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2020decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 202105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 202205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 202305c6cfb9SAlexey Kardashevskiy #endif 2024decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2025da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 20264793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 2027da004c36SAlexey Kardashevskiy }; 2028da004c36SAlexey Kardashevskiy 2029801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2030801846d1SGavin Shan { 2031801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2032801846d1SGavin Shan 2033801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2034801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2035801846d1SGavin Shan */ 2036801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2037801846d1SGavin Shan return 0; 2038801846d1SGavin Shan 2039801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2040801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2041801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2042801846d1SGavin Shan *weight += 3; 2043801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2044801846d1SGavin Shan *weight += 15; 2045801846d1SGavin Shan else 2046801846d1SGavin Shan *weight += 10; 2047801846d1SGavin Shan 2048801846d1SGavin Shan return 0; 2049801846d1SGavin Shan } 2050801846d1SGavin Shan 2051801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2052801846d1SGavin Shan { 2053801846d1SGavin Shan unsigned int weight = 0; 2054801846d1SGavin Shan 2055801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2056801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2057801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2058801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2059801846d1SGavin Shan return weight; 2060801846d1SGavin Shan } 2061801846d1SGavin Shan #endif 2062801846d1SGavin Shan 2063801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2064801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2065801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2066801846d1SGavin Shan struct pci_dev *pdev; 2067801846d1SGavin Shan 2068801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2069801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2070801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2071801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2072801846d1SGavin Shan } 2073801846d1SGavin Shan 2074801846d1SGavin Shan return weight; 2075801846d1SGavin Shan } 2076801846d1SGavin Shan 2077b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 20782b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2079184cd4a3SBenjamin Herrenschmidt { 2080184cd4a3SBenjamin Herrenschmidt 2081184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2082184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 20832b923ed1SGavin Shan unsigned int weight, total_weight = 0; 20842b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2085184cd4a3SBenjamin Herrenschmidt int64_t rc; 2086184cd4a3SBenjamin Herrenschmidt void *addr; 2087184cd4a3SBenjamin Herrenschmidt 2088184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2089184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2090184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 20912b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 20922b923ed1SGavin Shan if (!weight) 20932b923ed1SGavin Shan return; 2094184cd4a3SBenjamin Herrenschmidt 20952b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 20962b923ed1SGavin Shan &total_weight); 20972b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 20982b923ed1SGavin Shan if (!segs) 20992b923ed1SGavin Shan segs = 1; 21002b923ed1SGavin Shan 21012b923ed1SGavin Shan /* 21022b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 21032b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 21042b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 21052b923ed1SGavin Shan * is allocated successfully. 21062b923ed1SGavin Shan */ 21072b923ed1SGavin Shan do { 21082b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 21092b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 21102b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 21112b923ed1SGavin Shan IODA_INVALID_PE) 21122b923ed1SGavin Shan avail++; 21132b923ed1SGavin Shan } 21142b923ed1SGavin Shan 21152b923ed1SGavin Shan if (avail == segs) 21162b923ed1SGavin Shan goto found; 21172b923ed1SGavin Shan } 21182b923ed1SGavin Shan } while (--segs); 21192b923ed1SGavin Shan 21202b923ed1SGavin Shan if (!segs) { 21212b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 21222b923ed1SGavin Shan return; 21232b923ed1SGavin Shan } 21242b923ed1SGavin Shan 21252b923ed1SGavin Shan found: 21260eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 2127b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2128b348aa65SAlexey Kardashevskiy pe->pe_number); 21290eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2130c5773822SAlexey Kardashevskiy 2131184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 21322b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 21332b923ed1SGavin Shan weight, total_weight, base, segs); 2134184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2135acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2136acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2137184cd4a3SBenjamin Herrenschmidt 2138184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2139184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2140184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2141184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2142acce971cSGavin Shan * 2143acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2144acce971cSGavin Shan * bytes 2145184cd4a3SBenjamin Herrenschmidt */ 2146acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2147184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2148acce971cSGavin Shan get_order(tce32_segsz * segs)); 2149184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2150184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2151184cd4a3SBenjamin Herrenschmidt goto fail; 2152184cd4a3SBenjamin Herrenschmidt } 2153184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2154acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2155184cd4a3SBenjamin Herrenschmidt 2156184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2157184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2158184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2159184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2160184cd4a3SBenjamin Herrenschmidt base + i, 1, 2161acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2162acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2163184cd4a3SBenjamin Herrenschmidt if (rc) { 2164184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2165184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2166184cd4a3SBenjamin Herrenschmidt goto fail; 2167184cd4a3SBenjamin Herrenschmidt } 2168184cd4a3SBenjamin Herrenschmidt } 2169184cd4a3SBenjamin Herrenschmidt 21702b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 21712b923ed1SGavin Shan for (i = base; i < base + segs; i++) 21722b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 21732b923ed1SGavin Shan 2174184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2175acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2176acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2177acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2178184cd4a3SBenjamin Herrenschmidt 2179da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 21804793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 21814793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2182184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2183184cd4a3SBenjamin Herrenschmidt 2184781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 21854617082eSAlexey Kardashevskiy /* 21864617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 21874617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 21884617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 21894617082eSAlexey Kardashevskiy */ 21904617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 21914617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2192c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2193ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 219474251fe2SBenjamin Herrenschmidt 2195184cd4a3SBenjamin Herrenschmidt return; 2196184cd4a3SBenjamin Herrenschmidt fail: 2197184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2198184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2199acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 22000eaf4defSAlexey Kardashevskiy if (tbl) { 22010eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 22020eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 22030eaf4defSAlexey Kardashevskiy } 2204184cd4a3SBenjamin Herrenschmidt } 2205184cd4a3SBenjamin Herrenschmidt 220643cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 220743cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 220843cb60abSAlexey Kardashevskiy { 220943cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 221043cb60abSAlexey Kardashevskiy table_group); 221143cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 221243cb60abSAlexey Kardashevskiy int64_t rc; 2213bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2214bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 221543cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 221643cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 221743cb60abSAlexey Kardashevskiy 22184793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 221943cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 222043cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 222143cb60abSAlexey Kardashevskiy 222243cb60abSAlexey Kardashevskiy /* 222343cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 222443cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 222543cb60abSAlexey Kardashevskiy */ 222643cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 222743cb60abSAlexey Kardashevskiy pe->pe_number, 22284793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2229bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 223043cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2231bbb845c4SAlexey Kardashevskiy size << 3, 223243cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 223343cb60abSAlexey Kardashevskiy if (rc) { 223443cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 223543cb60abSAlexey Kardashevskiy return rc; 223643cb60abSAlexey Kardashevskiy } 223743cb60abSAlexey Kardashevskiy 223843cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 223943cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2240ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 224143cb60abSAlexey Kardashevskiy 224243cb60abSAlexey Kardashevskiy return 0; 224343cb60abSAlexey Kardashevskiy } 224443cb60abSAlexey Kardashevskiy 2245f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2246cd15b048SBenjamin Herrenschmidt { 2247cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2248cd15b048SBenjamin Herrenschmidt int64_t rc; 2249cd15b048SBenjamin Herrenschmidt 2250cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2251cd15b048SBenjamin Herrenschmidt if (enable) { 2252cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2253cd15b048SBenjamin Herrenschmidt 2254cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2255cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2256cd15b048SBenjamin Herrenschmidt pe->pe_number, 2257cd15b048SBenjamin Herrenschmidt window_id, 2258cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2259cd15b048SBenjamin Herrenschmidt top); 2260cd15b048SBenjamin Herrenschmidt } else { 2261cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2262cd15b048SBenjamin Herrenschmidt pe->pe_number, 2263cd15b048SBenjamin Herrenschmidt window_id, 2264cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2265cd15b048SBenjamin Herrenschmidt 0); 2266cd15b048SBenjamin Herrenschmidt } 2267cd15b048SBenjamin Herrenschmidt if (rc) 2268cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2269cd15b048SBenjamin Herrenschmidt else 2270cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2271cd15b048SBenjamin Herrenschmidt } 2272cd15b048SBenjamin Herrenschmidt 22734793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 22744793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 22754793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 22764793d65dSAlexey Kardashevskiy 22774793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 22784793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 22794793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 22804793d65dSAlexey Kardashevskiy { 22814793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 22824793d65dSAlexey Kardashevskiy table_group); 22834793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 22844793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 22854793d65dSAlexey Kardashevskiy long ret; 22864793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 22874793d65dSAlexey Kardashevskiy 22884793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 22894793d65dSAlexey Kardashevskiy if (!tbl) 22904793d65dSAlexey Kardashevskiy return -ENOMEM; 22914793d65dSAlexey Kardashevskiy 22924793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 22934793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 22944793d65dSAlexey Kardashevskiy levels, tbl); 22954793d65dSAlexey Kardashevskiy if (ret) { 22964793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 22974793d65dSAlexey Kardashevskiy return ret; 22984793d65dSAlexey Kardashevskiy } 22994793d65dSAlexey Kardashevskiy 23004793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 23014793d65dSAlexey Kardashevskiy 23024793d65dSAlexey Kardashevskiy *ptbl = tbl; 23034793d65dSAlexey Kardashevskiy 23044793d65dSAlexey Kardashevskiy return 0; 23054793d65dSAlexey Kardashevskiy } 23064793d65dSAlexey Kardashevskiy 230746d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 230846d3e1e1SAlexey Kardashevskiy { 230946d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 231046d3e1e1SAlexey Kardashevskiy long rc; 231146d3e1e1SAlexey Kardashevskiy 2312bb005455SNishanth Aravamudan /* 2313fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2314fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2315fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2316fa144869SNishanth Aravamudan */ 2317fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2318fa144869SNishanth Aravamudan 2319fa144869SNishanth Aravamudan /* 2320bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2321bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2322bb005455SNishanth Aravamudan * cause errors later. 2323bb005455SNishanth Aravamudan */ 2324fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2325bb005455SNishanth Aravamudan 232646d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 232746d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2328bb005455SNishanth Aravamudan window_size, 232946d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 233046d3e1e1SAlexey Kardashevskiy if (rc) { 233146d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 233246d3e1e1SAlexey Kardashevskiy rc); 233346d3e1e1SAlexey Kardashevskiy return rc; 233446d3e1e1SAlexey Kardashevskiy } 233546d3e1e1SAlexey Kardashevskiy 233646d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 233746d3e1e1SAlexey Kardashevskiy 233846d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 233946d3e1e1SAlexey Kardashevskiy if (rc) { 234046d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 234146d3e1e1SAlexey Kardashevskiy rc); 234246d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 234346d3e1e1SAlexey Kardashevskiy return rc; 234446d3e1e1SAlexey Kardashevskiy } 234546d3e1e1SAlexey Kardashevskiy 234646d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 234746d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 234846d3e1e1SAlexey Kardashevskiy 234946d3e1e1SAlexey Kardashevskiy /* 235046d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 235146d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 235246d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 235346d3e1e1SAlexey Kardashevskiy */ 235446d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 235546d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 235646d3e1e1SAlexey Kardashevskiy 235746d3e1e1SAlexey Kardashevskiy return 0; 235846d3e1e1SAlexey Kardashevskiy } 235946d3e1e1SAlexey Kardashevskiy 2360b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2361b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2362b5926430SAlexey Kardashevskiy int num) 2363b5926430SAlexey Kardashevskiy { 2364b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2365b5926430SAlexey Kardashevskiy table_group); 2366b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2367b5926430SAlexey Kardashevskiy long ret; 2368b5926430SAlexey Kardashevskiy 2369b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2370b5926430SAlexey Kardashevskiy 2371b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2372b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2373b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2374b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2375b5926430SAlexey Kardashevskiy if (ret) 2376b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2377b5926430SAlexey Kardashevskiy else 2378ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2379b5926430SAlexey Kardashevskiy 2380b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2381b5926430SAlexey Kardashevskiy 2382b5926430SAlexey Kardashevskiy return ret; 2383b5926430SAlexey Kardashevskiy } 2384b5926430SAlexey Kardashevskiy #endif 2385b5926430SAlexey Kardashevskiy 2386f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 238700547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 238800547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 238900547193SAlexey Kardashevskiy { 239000547193SAlexey Kardashevskiy unsigned long bytes = 0; 239100547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 239200547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 239300547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 239400547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 239500547193SAlexey Kardashevskiy unsigned long direct_table_size; 239600547193SAlexey Kardashevskiy 239700547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 239800547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 239900547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 240000547193SAlexey Kardashevskiy return 0; 240100547193SAlexey Kardashevskiy 240200547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 240300547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 240400547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 240500547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 240600547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 240700547193SAlexey Kardashevskiy 240800547193SAlexey Kardashevskiy for ( ; levels; --levels) { 240900547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 241000547193SAlexey Kardashevskiy 241100547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 241200547193SAlexey Kardashevskiy tce_table_size <<= 3; 241300547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 241400547193SAlexey Kardashevskiy } 241500547193SAlexey Kardashevskiy 241600547193SAlexey Kardashevskiy return bytes; 241700547193SAlexey Kardashevskiy } 241800547193SAlexey Kardashevskiy 2419f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2420cd15b048SBenjamin Herrenschmidt { 2421f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2422f87a8864SAlexey Kardashevskiy table_group); 242346d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 242446d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2425cd15b048SBenjamin Herrenschmidt 2426f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 242746d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 242846d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2429cd15b048SBenjamin Herrenschmidt } 2430cd15b048SBenjamin Herrenschmidt 2431f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2432f87a8864SAlexey Kardashevskiy { 2433f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2434f87a8864SAlexey Kardashevskiy table_group); 2435f87a8864SAlexey Kardashevskiy 243646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2437f87a8864SAlexey Kardashevskiy } 2438f87a8864SAlexey Kardashevskiy 2439f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 244000547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 24414793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 24424793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 24434793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2444f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2445f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2446f87a8864SAlexey Kardashevskiy }; 2447b5cb9ab1SAlexey Kardashevskiy 2448b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2449b5cb9ab1SAlexey Kardashevskiy { 2450b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2451b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2452b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2453b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2454b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2455b5cb9ab1SAlexey Kardashevskiy 2456b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2457b5cb9ab1SAlexey Kardashevskiy return 0; 2458b5cb9ab1SAlexey Kardashevskiy 2459b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2460b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2461b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2462b5cb9ab1SAlexey Kardashevskiy return 0; 2463b5cb9ab1SAlexey Kardashevskiy 2464b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2465b5cb9ab1SAlexey Kardashevskiy 2466b5cb9ab1SAlexey Kardashevskiy return 1; 2467b5cb9ab1SAlexey Kardashevskiy } 2468b5cb9ab1SAlexey Kardashevskiy 2469b5cb9ab1SAlexey Kardashevskiy /* 2470b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2471b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2472b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2473b5cb9ab1SAlexey Kardashevskiy */ 2474b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2475b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2476b5cb9ab1SAlexey Kardashevskiy { 2477b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2478b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2479b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2480b5cb9ab1SAlexey Kardashevskiy 2481b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2482b5cb9ab1SAlexey Kardashevskiy 2483b5cb9ab1SAlexey Kardashevskiy return npe; 2484b5cb9ab1SAlexey Kardashevskiy } 2485b5cb9ab1SAlexey Kardashevskiy 2486b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2487b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2488b5cb9ab1SAlexey Kardashevskiy { 2489b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2490b5cb9ab1SAlexey Kardashevskiy 2491b5cb9ab1SAlexey Kardashevskiy if (ret) 2492b5cb9ab1SAlexey Kardashevskiy return ret; 2493b5cb9ab1SAlexey Kardashevskiy 2494b5cb9ab1SAlexey Kardashevskiy ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2495b5cb9ab1SAlexey Kardashevskiy if (ret) 2496b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2497b5cb9ab1SAlexey Kardashevskiy 2498b5cb9ab1SAlexey Kardashevskiy return ret; 2499b5cb9ab1SAlexey Kardashevskiy } 2500b5cb9ab1SAlexey Kardashevskiy 2501b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2502b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2503b5cb9ab1SAlexey Kardashevskiy int num) 2504b5cb9ab1SAlexey Kardashevskiy { 2505b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2506b5cb9ab1SAlexey Kardashevskiy 2507b5cb9ab1SAlexey Kardashevskiy if (ret) 2508b5cb9ab1SAlexey Kardashevskiy return ret; 2509b5cb9ab1SAlexey Kardashevskiy 2510b5cb9ab1SAlexey Kardashevskiy return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2511b5cb9ab1SAlexey Kardashevskiy } 2512b5cb9ab1SAlexey Kardashevskiy 2513b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2514b5cb9ab1SAlexey Kardashevskiy { 2515b5cb9ab1SAlexey Kardashevskiy /* 2516b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2517b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2518b5cb9ab1SAlexey Kardashevskiy */ 2519b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2520b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2521b5cb9ab1SAlexey Kardashevskiy } 2522b5cb9ab1SAlexey Kardashevskiy 2523b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2524b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2525b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2526b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2527b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2528b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2529b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2530b5cb9ab1SAlexey Kardashevskiy }; 2531b5cb9ab1SAlexey Kardashevskiy 2532b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2533b5cb9ab1SAlexey Kardashevskiy { 2534b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2535b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2536b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2537b5cb9ab1SAlexey Kardashevskiy 2538b5cb9ab1SAlexey Kardashevskiy /* 2539b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2540b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2541b5cb9ab1SAlexey Kardashevskiy */ 2542b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2543b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2544b5cb9ab1SAlexey Kardashevskiy 2545b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2546b5cb9ab1SAlexey Kardashevskiy continue; 2547b5cb9ab1SAlexey Kardashevskiy 2548b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2549b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2550b5cb9ab1SAlexey Kardashevskiy if (gpe) 2551b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2552b5cb9ab1SAlexey Kardashevskiy } 2553b5cb9ab1SAlexey Kardashevskiy } 2554b5cb9ab1SAlexey Kardashevskiy } 2555b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2556b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2557f87a8864SAlexey Kardashevskiy #endif 2558f87a8864SAlexey Kardashevskiy 2559bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2560bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 25613ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2562aca6913fSAlexey Kardashevskiy { 2563aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2564bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2565aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2566bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2567bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2568bbb845c4SAlexey Kardashevskiy long i; 2569aca6913fSAlexey Kardashevskiy 2570aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2571aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2572aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2573aca6913fSAlexey Kardashevskiy return NULL; 2574aca6913fSAlexey Kardashevskiy } 2575aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2576bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 25773ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2578bbb845c4SAlexey Kardashevskiy 2579bbb845c4SAlexey Kardashevskiy --levels; 2580bbb845c4SAlexey Kardashevskiy if (!levels) { 2581bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2582bbb845c4SAlexey Kardashevskiy return addr; 2583bbb845c4SAlexey Kardashevskiy } 2584bbb845c4SAlexey Kardashevskiy 2585bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2586bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 25873ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2588bbb845c4SAlexey Kardashevskiy if (!tmp) 2589bbb845c4SAlexey Kardashevskiy break; 2590bbb845c4SAlexey Kardashevskiy 2591bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2592bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2593bbb845c4SAlexey Kardashevskiy 2594bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2595bbb845c4SAlexey Kardashevskiy break; 2596bbb845c4SAlexey Kardashevskiy } 2597aca6913fSAlexey Kardashevskiy 2598aca6913fSAlexey Kardashevskiy return addr; 2599aca6913fSAlexey Kardashevskiy } 2600aca6913fSAlexey Kardashevskiy 2601bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2602bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2603bbb845c4SAlexey Kardashevskiy 2604aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2605bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2606bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2607aca6913fSAlexey Kardashevskiy { 2608aca6913fSAlexey Kardashevskiy void *addr; 26093ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2610aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2611aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2612aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2613aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2614aca6913fSAlexey Kardashevskiy 2615bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2616bbb845c4SAlexey Kardashevskiy return -EINVAL; 2617bbb845c4SAlexey Kardashevskiy 2618aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2619aca6913fSAlexey Kardashevskiy return -EINVAL; 2620aca6913fSAlexey Kardashevskiy 2621bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2622bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2623bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2624bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2625bbb845c4SAlexey Kardashevskiy 2626aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2627bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 26283ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2629bbb845c4SAlexey Kardashevskiy 2630bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2631aca6913fSAlexey Kardashevskiy if (!addr) 2632aca6913fSAlexey Kardashevskiy return -ENOMEM; 2633aca6913fSAlexey Kardashevskiy 2634bbb845c4SAlexey Kardashevskiy /* 2635bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2636bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2637bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2638bbb845c4SAlexey Kardashevskiy */ 2639bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2640bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2641bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2642bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2643bbb845c4SAlexey Kardashevskiy } 2644bbb845c4SAlexey Kardashevskiy 2645aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2646aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2647aca6913fSAlexey Kardashevskiy page_shift); 2648bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2649bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 26503ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2651aca6913fSAlexey Kardashevskiy 2652aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2653aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2654aca6913fSAlexey Kardashevskiy 2655aca6913fSAlexey Kardashevskiy return 0; 2656aca6913fSAlexey Kardashevskiy } 2657aca6913fSAlexey Kardashevskiy 2658bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2659bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2660bbb845c4SAlexey Kardashevskiy { 2661bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2662bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2663bbb845c4SAlexey Kardashevskiy 2664bbb845c4SAlexey Kardashevskiy if (level) { 2665bbb845c4SAlexey Kardashevskiy long i; 2666bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2667bbb845c4SAlexey Kardashevskiy 2668bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2669bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2670bbb845c4SAlexey Kardashevskiy 2671bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2672bbb845c4SAlexey Kardashevskiy continue; 2673bbb845c4SAlexey Kardashevskiy 2674bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2675bbb845c4SAlexey Kardashevskiy level - 1); 2676bbb845c4SAlexey Kardashevskiy } 2677bbb845c4SAlexey Kardashevskiy } 2678bbb845c4SAlexey Kardashevskiy 2679bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2680bbb845c4SAlexey Kardashevskiy } 2681bbb845c4SAlexey Kardashevskiy 2682aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2683aca6913fSAlexey Kardashevskiy { 2684bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2685bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2686bbb845c4SAlexey Kardashevskiy 2687aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2688aca6913fSAlexey Kardashevskiy return; 2689aca6913fSAlexey Kardashevskiy 2690bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2691bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2692aca6913fSAlexey Kardashevskiy } 2693aca6913fSAlexey Kardashevskiy 2694373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2695373f5657SGavin Shan struct pnv_ioda_pe *pe) 2696373f5657SGavin Shan { 2697373f5657SGavin Shan int64_t rc; 2698373f5657SGavin Shan 2699ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2700ccd1c191SGavin Shan return; 2701ccd1c191SGavin Shan 2702f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2703f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2704f87a8864SAlexey Kardashevskiy 2705b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2706b348aa65SAlexey Kardashevskiy pe->pe_number); 2707c5773822SAlexey Kardashevskiy 2708373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2709373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2710aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2711373f5657SGavin Shan 2712e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 27134793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 27144793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 27154793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 27164793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 27174793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 27184793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2719e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2720e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2721e5aad1e6SAlexey Kardashevskiy #endif 2722e5aad1e6SAlexey Kardashevskiy 272346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2724801846d1SGavin Shan if (rc) 272546d3e1e1SAlexey Kardashevskiy return; 272646d3e1e1SAlexey Kardashevskiy 272746d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 272846d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 272946d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 273046d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2731373f5657SGavin Shan } 2732373f5657SGavin Shan 2733184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 27344ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2735137436c9SGavin Shan { 2736137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2737137436c9SGavin Shan ioda.irq_chip); 2738137436c9SGavin Shan 27394ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 27404ee11c1aSSuresh Warrier } 27414ee11c1aSSuresh Warrier 27424ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 27434ee11c1aSSuresh Warrier { 27444ee11c1aSSuresh Warrier int64_t rc; 27454ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 27464ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 27474ee11c1aSSuresh Warrier 27484ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2749137436c9SGavin Shan WARN_ON_ONCE(rc); 2750137436c9SGavin Shan 2751137436c9SGavin Shan icp_native_eoi(d); 2752137436c9SGavin Shan } 2753137436c9SGavin Shan 2754fd9a1c26SIan Munsie 2755f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2756fd9a1c26SIan Munsie { 2757fd9a1c26SIan Munsie struct irq_data *idata; 2758fd9a1c26SIan Munsie struct irq_chip *ichip; 2759fd9a1c26SIan Munsie 2760fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2761fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2762fd9a1c26SIan Munsie return; 2763fd9a1c26SIan Munsie 2764fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2765fd9a1c26SIan Munsie /* 2766fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2767fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2768fd9a1c26SIan Munsie */ 2769fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2770fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2771fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2772fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2773fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2774fd9a1c26SIan Munsie } 2775fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2776fd9a1c26SIan Munsie } 2777fd9a1c26SIan Munsie 27784ee11c1aSSuresh Warrier /* 27794ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 27804ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 27814ee11c1aSSuresh Warrier */ 27824ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 27834ee11c1aSSuresh Warrier { 27844ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 27854ee11c1aSSuresh Warrier } 27864ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 27874ee11c1aSSuresh Warrier 2788184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2789137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2790137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2791184cd4a3SBenjamin Herrenschmidt { 2792184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2793184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 27943a1a4661SBenjamin Herrenschmidt __be32 data; 2795184cd4a3SBenjamin Herrenschmidt int rc; 2796184cd4a3SBenjamin Herrenschmidt 2797184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2798184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2799184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2800184cd4a3SBenjamin Herrenschmidt 2801184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2802184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2803184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2804184cd4a3SBenjamin Herrenschmidt 2805b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 280636074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2807b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2808b72c1f65SBenjamin Herrenschmidt 2809184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2810184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2811184cd4a3SBenjamin Herrenschmidt if (rc) { 2812184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2813184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2814184cd4a3SBenjamin Herrenschmidt return -EIO; 2815184cd4a3SBenjamin Herrenschmidt } 2816184cd4a3SBenjamin Herrenschmidt 2817184cd4a3SBenjamin Herrenschmidt if (is_64) { 28183a1a4661SBenjamin Herrenschmidt __be64 addr64; 28193a1a4661SBenjamin Herrenschmidt 2820184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2821184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2822184cd4a3SBenjamin Herrenschmidt if (rc) { 2823184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2824184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2825184cd4a3SBenjamin Herrenschmidt return -EIO; 2826184cd4a3SBenjamin Herrenschmidt } 28273a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28283a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2829184cd4a3SBenjamin Herrenschmidt } else { 28303a1a4661SBenjamin Herrenschmidt __be32 addr32; 28313a1a4661SBenjamin Herrenschmidt 2832184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2833184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2834184cd4a3SBenjamin Herrenschmidt if (rc) { 2835184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2836184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2837184cd4a3SBenjamin Herrenschmidt return -EIO; 2838184cd4a3SBenjamin Herrenschmidt } 2839184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28403a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2841184cd4a3SBenjamin Herrenschmidt } 28423a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2843184cd4a3SBenjamin Herrenschmidt 2844f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2845137436c9SGavin Shan 2846184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 28471f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2848184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2849184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2850184cd4a3SBenjamin Herrenschmidt 2851184cd4a3SBenjamin Herrenschmidt return 0; 2852184cd4a3SBenjamin Herrenschmidt } 2853184cd4a3SBenjamin Herrenschmidt 2854184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2855184cd4a3SBenjamin Herrenschmidt { 2856fb1b55d6SGavin Shan unsigned int count; 2857184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2858184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2859184cd4a3SBenjamin Herrenschmidt if (!prop) { 2860184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2861184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2862184cd4a3SBenjamin Herrenschmidt } 2863184cd4a3SBenjamin Herrenschmidt if (!prop) 2864184cd4a3SBenjamin Herrenschmidt return; 2865184cd4a3SBenjamin Herrenschmidt 2866184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2867fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2868fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2869184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2870184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2871184cd4a3SBenjamin Herrenschmidt return; 2872184cd4a3SBenjamin Herrenschmidt } 2873fb1b55d6SGavin Shan 2874184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2875184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2876184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2877fb1b55d6SGavin Shan count, phb->msi_base); 2878184cd4a3SBenjamin Herrenschmidt } 2879184cd4a3SBenjamin Herrenschmidt #else 2880184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2881184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2882184cd4a3SBenjamin Herrenschmidt 28836e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 28846e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 28856e628c7dSWei Yang { 2886f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2887f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2888f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 28896e628c7dSWei Yang struct resource *res; 28906e628c7dSWei Yang int i; 2891dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 28926e628c7dSWei Yang struct pci_dn *pdn; 28935b88ec22SWei Yang int mul, total_vfs; 28946e628c7dSWei Yang 28956e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 28966e628c7dSWei Yang return; 28976e628c7dSWei Yang 28986e628c7dSWei Yang pdn = pci_get_pdn(pdev); 28996e628c7dSWei Yang pdn->vfs_expanded = 0; 2900ee8222feSWei Yang pdn->m64_single_mode = false; 29016e628c7dSWei Yang 29025b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 290392b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2904dfcc8d45SWei Yang total_vf_bar_sz = 0; 29055b88ec22SWei Yang 29065b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29075b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29085b88ec22SWei Yang if (!res->flags || res->parent) 29095b88ec22SWei Yang continue; 2910b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 2911b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2912b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29135b88ec22SWei Yang i, res); 2914b0331854SWei Yang goto truncate_iov; 29155b88ec22SWei Yang } 29165b88ec22SWei Yang 2917dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2918dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29195b88ec22SWei Yang 2920f2dd0afeSWei Yang /* 2921f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2922f2dd0afeSWei Yang * power of two. 2923f2dd0afeSWei Yang * 2924f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2925f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2926f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2927f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2928f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2929f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2930f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2931f2dd0afeSWei Yang */ 2932dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29335b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2934dfcc8d45SWei Yang dev_info(&pdev->dev, 2935dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2936dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2937ee8222feSWei Yang pdn->m64_single_mode = true; 29385b88ec22SWei Yang break; 29395b88ec22SWei Yang } 29405b88ec22SWei Yang } 29415b88ec22SWei Yang 29426e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29436e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29446e628c7dSWei Yang if (!res->flags || res->parent) 29456e628c7dSWei Yang continue; 29466e628c7dSWei Yang 29476e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2948ee8222feSWei Yang /* 2949ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2950ee8222feSWei Yang * mode is 32MB. 2951ee8222feSWei Yang */ 2952ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2953ee8222feSWei Yang goto truncate_iov; 2954ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29555b88ec22SWei Yang res->end = res->start + size * mul - 1; 29566e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 29576e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 29585b88ec22SWei Yang i, res, mul); 29596e628c7dSWei Yang } 29605b88ec22SWei Yang pdn->vfs_expanded = mul; 2961b0331854SWei Yang 2962b0331854SWei Yang return; 2963b0331854SWei Yang 2964b0331854SWei Yang truncate_iov: 2965b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2966b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2967b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2968b0331854SWei Yang res->flags = 0; 2969b0331854SWei Yang res->end = res->start - 1; 2970b0331854SWei Yang } 29716e628c7dSWei Yang } 29726e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 29736e628c7dSWei Yang 297423e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 297523e79425SGavin Shan struct resource *res) 297611685becSGavin Shan { 297723e79425SGavin Shan struct pnv_phb *phb = pe->phb; 297811685becSGavin Shan struct pci_bus_region region; 297923e79425SGavin Shan int index; 298023e79425SGavin Shan int64_t rc; 298111685becSGavin Shan 298223e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 298323e79425SGavin Shan return; 298411685becSGavin Shan 298511685becSGavin Shan if (res->flags & IORESOURCE_IO) { 298611685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 298711685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 298811685becSGavin Shan index = region.start / phb->ioda.io_segsize; 298911685becSGavin Shan 299092b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 299111685becSGavin Shan region.start <= region.end) { 299211685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 299311685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 299411685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 299511685becSGavin Shan if (rc != OPAL_SUCCESS) { 29961f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 299711685becSGavin Shan __func__, rc, index, pe->pe_number); 299811685becSGavin Shan break; 299911685becSGavin Shan } 300011685becSGavin Shan 300111685becSGavin Shan region.start += phb->ioda.io_segsize; 300211685becSGavin Shan index++; 300311685becSGavin Shan } 3004027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 30055958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 300611685becSGavin Shan region.start = res->start - 300723e79425SGavin Shan phb->hose->mem_offset[0] - 300811685becSGavin Shan phb->ioda.m32_pci_base; 300911685becSGavin Shan region.end = res->end - 301023e79425SGavin Shan phb->hose->mem_offset[0] - 301111685becSGavin Shan phb->ioda.m32_pci_base; 301211685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 301311685becSGavin Shan 301492b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 301511685becSGavin Shan region.start <= region.end) { 301611685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 301711685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 301811685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 301911685becSGavin Shan if (rc != OPAL_SUCCESS) { 30201f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 302111685becSGavin Shan __func__, rc, index, pe->pe_number); 302211685becSGavin Shan break; 302311685becSGavin Shan } 302411685becSGavin Shan 302511685becSGavin Shan region.start += phb->ioda.m32_segsize; 302611685becSGavin Shan index++; 302711685becSGavin Shan } 302811685becSGavin Shan } 302911685becSGavin Shan } 303023e79425SGavin Shan 303123e79425SGavin Shan /* 303223e79425SGavin Shan * This function is supposed to be called on basis of PE from top 303323e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 303423e79425SGavin Shan * parent PE could be overrided by its child PEs if necessary. 303523e79425SGavin Shan */ 303623e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 303723e79425SGavin Shan { 303869d733e7SGavin Shan struct pci_dev *pdev; 303923e79425SGavin Shan int i; 304023e79425SGavin Shan 304123e79425SGavin Shan /* 304223e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 304323e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 304423e79425SGavin Shan * be figured out later. 304523e79425SGavin Shan */ 304623e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 304723e79425SGavin Shan 304869d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 304969d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 305069d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 305169d733e7SGavin Shan 305269d733e7SGavin Shan /* 305369d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 305469d733e7SGavin Shan * windows of the child bridges should be mapped to 305569d733e7SGavin Shan * the PE as well. 305669d733e7SGavin Shan */ 305769d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 305869d733e7SGavin Shan continue; 305969d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 306069d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 306169d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 306269d733e7SGavin Shan } 306311685becSGavin Shan } 306411685becSGavin Shan 306598b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 306698b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 306798b665daSRussell Currey { 306898b665daSRussell Currey struct pci_controller *hose; 306998b665daSRussell Currey struct pnv_phb *phb; 307098b665daSRussell Currey s64 ret; 307198b665daSRussell Currey 307298b665daSRussell Currey if (val != 1ULL) 307398b665daSRussell Currey return -EINVAL; 307498b665daSRussell Currey 307598b665daSRussell Currey hose = (struct pci_controller *)data; 307698b665daSRussell Currey if (!hose || !hose->private_data) 307798b665daSRussell Currey return -ENODEV; 307898b665daSRussell Currey 307998b665daSRussell Currey phb = hose->private_data; 308098b665daSRussell Currey 308198b665daSRussell Currey /* Retrieve the diag data from firmware */ 308298b665daSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, 308398b665daSRussell Currey PNV_PCI_DIAG_BUF_SIZE); 308498b665daSRussell Currey if (ret != OPAL_SUCCESS) 308598b665daSRussell Currey return -EIO; 308698b665daSRussell Currey 308798b665daSRussell Currey /* Print the diag data to the kernel log */ 308898b665daSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); 308998b665daSRussell Currey return 0; 309098b665daSRussell Currey } 309198b665daSRussell Currey 309298b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 309398b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 309498b665daSRussell Currey 309598b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 309698b665daSRussell Currey 309737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 309837c367f2SGavin Shan { 309937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 310037c367f2SGavin Shan struct pci_controller *hose, *tmp; 310137c367f2SGavin Shan struct pnv_phb *phb; 310237c367f2SGavin Shan char name[16]; 310337c367f2SGavin Shan 310437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 310537c367f2SGavin Shan phb = hose->private_data; 310637c367f2SGavin Shan 3107ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3108ccd1c191SGavin Shan phb->initialized = 1; 3109ccd1c191SGavin Shan 311037c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 311137c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 311298b665daSRussell Currey if (!phb->dbgfs) { 311337c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 311437c367f2SGavin Shan __func__, hose->global_number); 311598b665daSRussell Currey continue; 311698b665daSRussell Currey } 311798b665daSRussell Currey 311898b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 311998b665daSRussell Currey &pnv_pci_diag_data_fops); 312037c367f2SGavin Shan } 312137c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 312237c367f2SGavin Shan } 312337c367f2SGavin Shan 3124cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3125fb446ad0SGavin Shan { 3126fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3127ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 312837c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 312937c367f2SGavin Shan 3130e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3131e9cc17d4SGavin Shan eeh_init(); 3132dadcd6d6SMike Qiu eeh_addr_cache_build(); 3133e9cc17d4SGavin Shan #endif 3134fb446ad0SGavin Shan } 3135fb446ad0SGavin Shan 3136271fd03aSGavin Shan /* 3137271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3138271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3139271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3140271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3141271fd03aSGavin Shan * 1MiB for memory) will be returned. 3142271fd03aSGavin Shan * 3143271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3144271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3145271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3146271fd03aSGavin Shan * resources. 3147271fd03aSGavin Shan */ 3148271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3149271fd03aSGavin Shan unsigned long type) 3150271fd03aSGavin Shan { 3151271fd03aSGavin Shan struct pci_dev *bridge; 3152271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3153271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3154271fd03aSGavin Shan int num_pci_bridges = 0; 3155271fd03aSGavin Shan 3156271fd03aSGavin Shan bridge = bus->self; 3157271fd03aSGavin Shan while (bridge) { 3158271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3159271fd03aSGavin Shan num_pci_bridges++; 3160271fd03aSGavin Shan if (num_pci_bridges >= 2) 3161271fd03aSGavin Shan return 1; 3162271fd03aSGavin Shan } 3163271fd03aSGavin Shan 3164271fd03aSGavin Shan bridge = bridge->bus->self; 3165271fd03aSGavin Shan } 3166271fd03aSGavin Shan 31675958d19aSBenjamin Herrenschmidt /* 31685958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 31695958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 31705958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 31715958d19aSBenjamin Herrenschmidt */ 3172b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3173262af557SGuo Chao return phb->ioda.m64_segsize; 3174271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3175271fd03aSGavin Shan return phb->ioda.m32_segsize; 3176271fd03aSGavin Shan 3177271fd03aSGavin Shan return phb->ioda.io_segsize; 3178271fd03aSGavin Shan } 3179271fd03aSGavin Shan 318040e2a47eSGavin Shan /* 318140e2a47eSGavin Shan * We are updating root port or the upstream port of the 318240e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 318340e2a47eSGavin Shan * to accommodate the changes on required resources during 318440e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 318540e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 318640e2a47eSGavin Shan * root port. 318740e2a47eSGavin Shan */ 318840e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 318940e2a47eSGavin Shan unsigned long type) 319040e2a47eSGavin Shan { 319140e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 319240e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 319340e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 319440e2a47eSGavin Shan struct resource *r, *w; 319540e2a47eSGavin Shan bool msi_region = false; 319640e2a47eSGavin Shan int i; 319740e2a47eSGavin Shan 319840e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 319940e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 320040e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 320140e2a47eSGavin Shan return; 320240e2a47eSGavin Shan 320340e2a47eSGavin Shan /* Fixup the resources */ 320440e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 320540e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 320640e2a47eSGavin Shan if (!r->flags || !r->parent) 320740e2a47eSGavin Shan continue; 320840e2a47eSGavin Shan 320940e2a47eSGavin Shan w = NULL; 321040e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 321140e2a47eSGavin Shan w = &hose->io_resource; 32125958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 321340e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 321440e2a47eSGavin Shan phb->ioda.m64_segsize) 321540e2a47eSGavin Shan w = &hose->mem_resources[1]; 321640e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 321740e2a47eSGavin Shan w = &hose->mem_resources[0]; 321840e2a47eSGavin Shan msi_region = true; 321940e2a47eSGavin Shan } 322040e2a47eSGavin Shan 322140e2a47eSGavin Shan r->start = w->start; 322240e2a47eSGavin Shan r->end = w->end; 322340e2a47eSGavin Shan 322440e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 322540e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 322640e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 322740e2a47eSGavin Shan * 322840e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 322940e2a47eSGavin Shan * 32-bits bridge window. 323040e2a47eSGavin Shan */ 323140e2a47eSGavin Shan if (msi_region) { 323240e2a47eSGavin Shan r->end += 0x10000; 323340e2a47eSGavin Shan r->end -= 0x100000; 323440e2a47eSGavin Shan } 323540e2a47eSGavin Shan } 323640e2a47eSGavin Shan } 323740e2a47eSGavin Shan 3238ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3239ccd1c191SGavin Shan { 3240ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3241ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3242ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3243ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3244ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3245ccd1c191SGavin Shan 324640e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 324740e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 324840e2a47eSGavin Shan 324963803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 325063803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 325163803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 325263803c39SGavin Shan if (pe) { 325363803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 325463803c39SGavin Shan phb->ioda.root_pe_populated = true; 325563803c39SGavin Shan } 325663803c39SGavin Shan } 325763803c39SGavin Shan 3258ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3259ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3260ccd1c191SGavin Shan return; 3261ccd1c191SGavin Shan 3262ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3263ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3264ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3265ccd1c191SGavin Shan 3266ccd1c191SGavin Shan /* 3267ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3268ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3269ccd1c191SGavin Shan * not allocate resources again. 3270ccd1c191SGavin Shan */ 3271ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3272ccd1c191SGavin Shan if (!pe) 3273ccd1c191SGavin Shan return; 3274ccd1c191SGavin Shan 3275ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3276ccd1c191SGavin Shan switch (phb->type) { 3277ccd1c191SGavin Shan case PNV_PHB_IODA1: 3278ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3279ccd1c191SGavin Shan break; 3280ccd1c191SGavin Shan case PNV_PHB_IODA2: 3281ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3282ccd1c191SGavin Shan break; 3283ccd1c191SGavin Shan default: 32841f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3285ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3286ccd1c191SGavin Shan } 3287ccd1c191SGavin Shan } 3288ccd1c191SGavin Shan 32895350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 32905350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 32915350ab3fSWei Yang int resno) 32925350ab3fSWei Yang { 3293ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3294ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 32955350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 32967fbe7a93SWei Yang resource_size_t align; 32975350ab3fSWei Yang 32987fbe7a93SWei Yang /* 32997fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 33007fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 33017fbe7a93SWei Yang * BAR should be size aligned. 33027fbe7a93SWei Yang * 3303ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3304ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3305ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3306ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3307ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3308ee8222feSWei Yang * m64_segsize. 3309ee8222feSWei Yang * 33107fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 33117fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3312ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3313ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 33147fbe7a93SWei Yang */ 33155350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 33167fbe7a93SWei Yang if (!pdn->vfs_expanded) 33175350ab3fSWei Yang return align; 3318ee8222feSWei Yang if (pdn->m64_single_mode) 3319ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 33207fbe7a93SWei Yang 33217fbe7a93SWei Yang return pdn->vfs_expanded * align; 33225350ab3fSWei Yang } 33235350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 33245350ab3fSWei Yang 3325184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3326184cd4a3SBenjamin Herrenschmidt * assign a PE 3327184cd4a3SBenjamin Herrenschmidt */ 33284361b034SIan Munsie bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3329184cd4a3SBenjamin Herrenschmidt { 3330db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3331db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3332db1266c8SGavin Shan struct pci_dn *pdn; 3333184cd4a3SBenjamin Herrenschmidt 3334db1266c8SGavin Shan /* The function is probably called while the PEs have 3335db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3336db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3337db1266c8SGavin Shan * PEs isn't ready. 3338db1266c8SGavin Shan */ 3339db1266c8SGavin Shan if (!phb->initialized) 3340c88c2a18SDaniel Axtens return true; 3341db1266c8SGavin Shan 3342b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3343184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3344c88c2a18SDaniel Axtens return false; 3345db1266c8SGavin Shan 3346c88c2a18SDaniel Axtens return true; 3347184cd4a3SBenjamin Herrenschmidt } 3348184cd4a3SBenjamin Herrenschmidt 3349c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3350c5f7700bSGavin Shan int num) 3351c5f7700bSGavin Shan { 3352c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3353c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3354c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3355c5f7700bSGavin Shan unsigned int idx; 3356c5f7700bSGavin Shan long rc; 3357c5f7700bSGavin Shan 3358c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3359c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3360c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3361c5f7700bSGavin Shan continue; 3362c5f7700bSGavin Shan 3363c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3364c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3365c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3366c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3367c5f7700bSGavin Shan rc, idx); 3368c5f7700bSGavin Shan return rc; 3369c5f7700bSGavin Shan } 3370c5f7700bSGavin Shan 3371c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3372c5f7700bSGavin Shan } 3373c5f7700bSGavin Shan 3374c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3375c5f7700bSGavin Shan return OPAL_SUCCESS; 3376c5f7700bSGavin Shan } 3377c5f7700bSGavin Shan 3378c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3379c5f7700bSGavin Shan { 3380c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3381c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3382c5f7700bSGavin Shan int64_t rc; 3383c5f7700bSGavin Shan 3384c5f7700bSGavin Shan if (!weight) 3385c5f7700bSGavin Shan return; 3386c5f7700bSGavin Shan 3387c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3388c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3389c5f7700bSGavin Shan return; 3390c5f7700bSGavin Shan 3391a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3392c5f7700bSGavin Shan if (pe->table_group.group) { 3393c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3394c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3395c5f7700bSGavin Shan } 3396c5f7700bSGavin Shan 3397c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3398c5f7700bSGavin Shan iommu_free_table(tbl, "pnv"); 3399c5f7700bSGavin Shan } 3400c5f7700bSGavin Shan 3401c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3402c5f7700bSGavin Shan { 3403c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3404c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3405c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3406c5f7700bSGavin Shan int64_t rc; 3407c5f7700bSGavin Shan #endif 3408c5f7700bSGavin Shan 3409c5f7700bSGavin Shan if (!weight) 3410c5f7700bSGavin Shan return; 3411c5f7700bSGavin Shan 3412c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3413c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3414c5f7700bSGavin Shan if (rc) 3415c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3416c5f7700bSGavin Shan #endif 3417c5f7700bSGavin Shan 3418c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3419c5f7700bSGavin Shan if (pe->table_group.group) { 3420c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3421c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3422c5f7700bSGavin Shan } 3423c5f7700bSGavin Shan 3424c5f7700bSGavin Shan pnv_pci_ioda2_table_free_pages(tbl); 3425c5f7700bSGavin Shan iommu_free_table(tbl, "pnv"); 3426c5f7700bSGavin Shan } 3427c5f7700bSGavin Shan 3428c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3429c5f7700bSGavin Shan unsigned short win, 3430c5f7700bSGavin Shan unsigned int *map) 3431c5f7700bSGavin Shan { 3432c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3433c5f7700bSGavin Shan int idx; 3434c5f7700bSGavin Shan int64_t rc; 3435c5f7700bSGavin Shan 3436c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3437c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3438c5f7700bSGavin Shan continue; 3439c5f7700bSGavin Shan 3440c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3441c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3442c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3443c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3444c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3445c5f7700bSGavin Shan else 3446c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3447c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3448c5f7700bSGavin Shan 3449c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3450c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3451c5f7700bSGavin Shan rc, win, idx); 3452c5f7700bSGavin Shan 3453c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3454c5f7700bSGavin Shan } 3455c5f7700bSGavin Shan } 3456c5f7700bSGavin Shan 3457c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3458c5f7700bSGavin Shan { 3459c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3460c5f7700bSGavin Shan 3461c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3462c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3463c5f7700bSGavin Shan phb->ioda.io_segmap); 3464c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3465c5f7700bSGavin Shan phb->ioda.m32_segmap); 3466c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3467c5f7700bSGavin Shan phb->ioda.m64_segmap); 3468c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3469c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3470c5f7700bSGavin Shan phb->ioda.m32_segmap); 3471c5f7700bSGavin Shan } 3472c5f7700bSGavin Shan } 3473c5f7700bSGavin Shan 3474c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3475c5f7700bSGavin Shan { 3476c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3477c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3478c5f7700bSGavin Shan 3479c5f7700bSGavin Shan list_del(&pe->list); 3480c5f7700bSGavin Shan switch (phb->type) { 3481c5f7700bSGavin Shan case PNV_PHB_IODA1: 3482c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3483c5f7700bSGavin Shan break; 3484c5f7700bSGavin Shan case PNV_PHB_IODA2: 3485c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3486c5f7700bSGavin Shan break; 3487c5f7700bSGavin Shan default: 3488c5f7700bSGavin Shan WARN_ON(1); 3489c5f7700bSGavin Shan } 3490c5f7700bSGavin Shan 3491c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3492c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3493b314427aSGavin Shan 3494b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3495b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3496b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3497b314427aSGavin Shan list_del(&slave->list); 3498b314427aSGavin Shan pnv_ioda_free_pe(slave); 3499b314427aSGavin Shan } 3500b314427aSGavin Shan } 3501b314427aSGavin Shan 35026eaed166SGavin Shan /* 35036eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 35046eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 35056eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 35066eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 35076eaed166SGavin Shan */ 35086eaed166SGavin Shan if (phb->ioda.root_pe_populated && 35096eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 35106eaed166SGavin Shan phb->ioda.root_pe_populated = false; 35116eaed166SGavin Shan else 3512c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3513c5f7700bSGavin Shan } 3514c5f7700bSGavin Shan 3515c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3516c5f7700bSGavin Shan { 3517c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3518c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3519c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3520c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3521c5f7700bSGavin Shan 3522c5f7700bSGavin Shan if (pdev->is_virtfn) 3523c5f7700bSGavin Shan return; 3524c5f7700bSGavin Shan 3525c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3526c5f7700bSGavin Shan return; 3527c5f7700bSGavin Shan 352829bf282dSGavin Shan /* 352929bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 353029bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 353129bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 353229bf282dSGavin Shan * device count is decreased on removing devices while failing to 353329bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 353429bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 353529bf282dSGavin Shan */ 3536c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 353729bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 353829bf282dSGavin Shan 3539c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3540c5f7700bSGavin Shan if (pe->device_count == 0) 3541c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3542c5f7700bSGavin Shan } 3543c5f7700bSGavin Shan 35447a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 354573ed148aSBenjamin Herrenschmidt { 35467a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 35477a8e6bbfSMichael Neuling 3548d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 354973ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 355073ed148aSBenjamin Herrenschmidt } 355173ed148aSBenjamin Herrenschmidt 355292ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 355392ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 35541bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 355592ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 355692ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 355792ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 355892ae0353SDaniel Axtens #endif 355992ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3560c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 356192ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3562ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 356392ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3564763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 356553522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 35667a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 356792ae0353SDaniel Axtens }; 356892ae0353SDaniel Axtens 3569f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3570f9f83456SAlexey Kardashevskiy { 3571f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3572f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3573f9f83456SAlexey Kardashevskiy __func__); 3574f9f83456SAlexey Kardashevskiy return -EPERM; 3575f9f83456SAlexey Kardashevskiy } 3576f9f83456SAlexey Kardashevskiy 35775d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 35785d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 35795d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 35805d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 35815d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 35825d2aa710SAlistair Popple #endif 35835d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 35845d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 35855d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35865d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 35875d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 35885d2aa710SAlistair Popple }; 35895d2aa710SAlistair Popple 35904361b034SIan Munsie #ifdef CONFIG_CXL_BASE 35914361b034SIan Munsie const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 35924361b034SIan Munsie .dma_dev_setup = pnv_pci_dma_dev_setup, 35934361b034SIan Munsie .dma_bus_setup = pnv_pci_dma_bus_setup, 3594a2f67d5eSIan Munsie #ifdef CONFIG_PCI_MSI 3595a2f67d5eSIan Munsie .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3596a2f67d5eSIan Munsie .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3597a2f67d5eSIan Munsie #endif 35984361b034SIan Munsie .enable_device_hook = pnv_cxl_enable_device_hook, 35994361b034SIan Munsie .disable_device = pnv_cxl_disable_device, 36004361b034SIan Munsie .release_device = pnv_pci_release_device, 36014361b034SIan Munsie .window_alignment = pnv_pci_window_alignment, 36024361b034SIan Munsie .setup_bridge = pnv_pci_setup_bridge, 36034361b034SIan Munsie .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36044361b034SIan Munsie .dma_set_mask = pnv_pci_ioda_dma_set_mask, 36054361b034SIan Munsie .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 36064361b034SIan Munsie .shutdown = pnv_pci_ioda_shutdown, 36074361b034SIan Munsie }; 36084361b034SIan Munsie #endif 36094361b034SIan Munsie 3610e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3611e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3612184cd4a3SBenjamin Herrenschmidt { 3613184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3614184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 36152b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 36162b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3617fd141d1aSBenjamin Herrenschmidt struct resource r; 3618c681b93cSAlistair Popple const __be64 *prop64; 36193a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3620f1b7cc3eSGavin Shan int len; 36213fa23ff8SGavin Shan unsigned int segno; 3622184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3623184cd4a3SBenjamin Herrenschmidt void *aux; 3624184cd4a3SBenjamin Herrenschmidt long rc; 3625184cd4a3SBenjamin Herrenschmidt 362608a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 362708a45b32SBenjamin Herrenschmidt return; 362808a45b32SBenjamin Herrenschmidt 36299497a1c1SGavin Shan pr_info("Initializing %s PHB (%s)\n", 36309497a1c1SGavin Shan pnv_phb_names[ioda_type], of_node_full_name(np)); 3631184cd4a3SBenjamin Herrenschmidt 3632184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3633184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3634184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3635184cd4a3SBenjamin Herrenschmidt return; 3636184cd4a3SBenjamin Herrenschmidt } 3637184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3638184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3639184cd4a3SBenjamin Herrenschmidt 3640e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 364158d714ecSGavin Shan 364258d714ecSGavin Shan /* Allocate PCI controller */ 3643184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 364458d714ecSGavin Shan if (!phb->hose) { 364558d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3646184cd4a3SBenjamin Herrenschmidt np->full_name); 3647e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3648184cd4a3SBenjamin Herrenschmidt return; 3649184cd4a3SBenjamin Herrenschmidt } 3650184cd4a3SBenjamin Herrenschmidt 3651184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3652f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3653f1b7cc3eSGavin Shan if (prop32 && len == 8) { 36543a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 36553a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3656f1b7cc3eSGavin Shan } else { 3657f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3658184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3659184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3660f1b7cc3eSGavin Shan } 3661184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3662e9cc17d4SGavin Shan phb->hub_id = hub_id; 3663184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3664aa0c033fSGavin Shan phb->type = ioda_type; 3665781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3666184cd4a3SBenjamin Herrenschmidt 3667cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3668cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3669cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3670f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3671aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 36725d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 36735d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3674cee72d5bSBenjamin Herrenschmidt else 3675cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3676cee72d5bSBenjamin Herrenschmidt 3677aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 36782f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3679184cd4a3SBenjamin Herrenschmidt 3680aa0c033fSGavin Shan /* Get registers */ 3681fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3682fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3683fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3684184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3685184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3686fd141d1aSBenjamin Herrenschmidt } 3687577c8c88SGavin Shan 3688184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 368992b8f137SGavin Shan phb->ioda.total_pe_num = 1; 369036954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 369136954dc7SGavin Shan if (prop32) 369292b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 369336954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 369436954dc7SGavin Shan if (prop32) 369592b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3696262af557SGuo Chao 3697c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3698c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3699c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3700c127562aSGavin Shan 3701262af557SGuo Chao /* Parse 64-bit MMIO range */ 3702262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3703262af557SGuo Chao 3704184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3705aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3706184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3707184cd4a3SBenjamin Herrenschmidt 370892b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 37093fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3710184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 371192b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3712184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3713184cd4a3SBenjamin Herrenschmidt 37142b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 37152b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 37162b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 37172b923ed1SGavin Shan 3718c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 371992a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 372092a86756SAlexey Kardashevskiy sizeof(unsigned long)); 372193289d8cSGavin Shan m64map_off = size; 372293289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3723184cd4a3SBenjamin Herrenschmidt m32map_off = size; 372492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3725c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3726c35d2a8cSGavin Shan iomap_off = size; 372792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 37282b923ed1SGavin Shan dma32map_off = size; 37292b923ed1SGavin Shan size += phb->ioda.dma32_count * 37302b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3731c35d2a8cSGavin Shan } 3732184cd4a3SBenjamin Herrenschmidt pemap_off = size; 373392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3734e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3735184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 373693289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3737184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 373893289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 373993289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 37403fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 374193289d8cSGavin Shan } 37423fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3743184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 37443fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 37453fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 37462b923ed1SGavin Shan 37472b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 37482b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 37492b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 37503fa23ff8SGavin Shan } 3751184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 375263803c39SGavin Shan 375363803c39SGavin Shan /* 375463803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 375563803c39SGavin Shan * M64 resources consumed by its child devices. To pick 375663803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 375763803c39SGavin Shan */ 375863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 375963803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 376063803c39SGavin Shan phb->ioda.root_pe_idx = 1; 376163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 376263803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 376363803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 376463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 376563803c39SGavin Shan } else { 376663803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 376763803c39SGavin Shan } 3768184cd4a3SBenjamin Herrenschmidt 3769184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3770781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3771184cd4a3SBenjamin Herrenschmidt 3772184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 37732b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3774acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3775184cd4a3SBenjamin Herrenschmidt 3776aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3777184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3778184cd4a3SBenjamin Herrenschmidt window_type, 3779184cd4a3SBenjamin Herrenschmidt window_num, 3780184cd4a3SBenjamin Herrenschmidt starting_real_address, 3781184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3782184cd4a3SBenjamin Herrenschmidt segment_size); 3783184cd4a3SBenjamin Herrenschmidt #endif 3784184cd4a3SBenjamin Herrenschmidt 3785262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 378692b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3787262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3788262af557SGuo Chao if (phb->ioda.m64_size) 3789262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3790262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3791262af557SGuo Chao if (phb->ioda.io_size) 3792262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3793184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3794184cd4a3SBenjamin Herrenschmidt 3795262af557SGuo Chao 3796184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 379749dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 379849dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 379949dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3800184cd4a3SBenjamin Herrenschmidt 3801184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3802184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3803184cd4a3SBenjamin Herrenschmidt 3804c40a4210SGavin Shan /* 3805c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3806c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3807c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3808c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3809c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3810184cd4a3SBenjamin Herrenschmidt */ 3811fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 38125d2aa710SAlistair Popple 3813f9f83456SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU) { 38145d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 3815f9f83456SAlexey Kardashevskiy } else { 3816f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 381792ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3818f9f83456SAlexey Kardashevskiy } 3819ad30cb99SMichael Ellerman 38206e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 38216e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 38225350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3823ad30cb99SMichael Ellerman #endif 3824ad30cb99SMichael Ellerman 3825c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3826184cd4a3SBenjamin Herrenschmidt 3827184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3828d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3829184cd4a3SBenjamin Herrenschmidt if (rc) 3830f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3831361f2a2aSGavin Shan 38326060e9eaSAndrew Donnellan /* 38336060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3834361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3835361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 38366060e9eaSAndrew Donnellan * transactions from previous kernel. 3837361f2a2aSGavin Shan */ 3838361f2a2aSGavin Shan if (is_kdump_kernel()) { 3839361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3840cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3841cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3842361f2a2aSGavin Shan } 3843262af557SGuo Chao 38449e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 38459e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3846262af557SGuo Chao hose->mem_resources[1].flags = 0; 3847184cd4a3SBenjamin Herrenschmidt } 3848184cd4a3SBenjamin Herrenschmidt 384967975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3850aa0c033fSGavin Shan { 3851e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3852aa0c033fSGavin Shan } 3853aa0c033fSGavin Shan 38545d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 38555d2aa710SAlistair Popple { 38565d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 38575d2aa710SAlistair Popple } 38585d2aa710SAlistair Popple 3859184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3860184cd4a3SBenjamin Herrenschmidt { 3861184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3862c681b93cSAlistair Popple const __be64 *prop64; 3863184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3864184cd4a3SBenjamin Herrenschmidt 3865184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3866184cd4a3SBenjamin Herrenschmidt 3867184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3868184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3869184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3870184cd4a3SBenjamin Herrenschmidt return; 3871184cd4a3SBenjamin Herrenschmidt } 3872184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3873184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3874184cd4a3SBenjamin Herrenschmidt 3875184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3876184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3877184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3878184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3879e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3880184cd4a3SBenjamin Herrenschmidt } 3881184cd4a3SBenjamin Herrenschmidt } 3882