1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 35184cd4a3SBenjamin Herrenschmidt 36184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 37184cd4a3SBenjamin Herrenschmidt #include "pci.h" 38184cd4a3SBenjamin Herrenschmidt 39184cd4a3SBenjamin Herrenschmidt #define define_pe_printk_level(func, kern_level) \ 40184cd4a3SBenjamin Herrenschmidt static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ 41184cd4a3SBenjamin Herrenschmidt { \ 42184cd4a3SBenjamin Herrenschmidt struct va_format vaf; \ 43184cd4a3SBenjamin Herrenschmidt va_list args; \ 44490e078dSGavin Shan char pfix[32]; \ 45184cd4a3SBenjamin Herrenschmidt int r; \ 46184cd4a3SBenjamin Herrenschmidt \ 47184cd4a3SBenjamin Herrenschmidt va_start(args, fmt); \ 48184cd4a3SBenjamin Herrenschmidt \ 49184cd4a3SBenjamin Herrenschmidt vaf.fmt = fmt; \ 50184cd4a3SBenjamin Herrenschmidt vaf.va = &args; \ 51184cd4a3SBenjamin Herrenschmidt \ 52490e078dSGavin Shan if (pe->pdev) \ 53490e078dSGavin Shan strlcpy(pfix, dev_name(&pe->pdev->dev), \ 54490e078dSGavin Shan sizeof(pfix)); \ 55490e078dSGavin Shan else \ 56490e078dSGavin Shan sprintf(pfix, "%04x:%02x ", \ 57490e078dSGavin Shan pci_domain_nr(pe->pbus), \ 58490e078dSGavin Shan pe->pbus->number); \ 59490e078dSGavin Shan r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ 60490e078dSGavin Shan pfix, pe->pe_number, &vaf); \ 61490e078dSGavin Shan \ 62184cd4a3SBenjamin Herrenschmidt va_end(args); \ 63184cd4a3SBenjamin Herrenschmidt \ 64184cd4a3SBenjamin Herrenschmidt return r; \ 65184cd4a3SBenjamin Herrenschmidt } \ 66184cd4a3SBenjamin Herrenschmidt 67184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_err, KERN_ERR); 68184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_warn, KERN_WARNING); 69184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_info, KERN_INFO); 70184cd4a3SBenjamin Herrenschmidt 71184cd4a3SBenjamin Herrenschmidt static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev) 72184cd4a3SBenjamin Herrenschmidt { 73184cd4a3SBenjamin Herrenschmidt struct device_node *np; 74184cd4a3SBenjamin Herrenschmidt 75184cd4a3SBenjamin Herrenschmidt np = pci_device_to_OF_node(dev); 76184cd4a3SBenjamin Herrenschmidt if (!np) 77184cd4a3SBenjamin Herrenschmidt return NULL; 78184cd4a3SBenjamin Herrenschmidt return PCI_DN(np); 79184cd4a3SBenjamin Herrenschmidt } 80184cd4a3SBenjamin Herrenschmidt 81cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 82184cd4a3SBenjamin Herrenschmidt { 83184cd4a3SBenjamin Herrenschmidt unsigned long pe; 84184cd4a3SBenjamin Herrenschmidt 85184cd4a3SBenjamin Herrenschmidt do { 86184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 87184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 88184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 89184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 90184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 91184cd4a3SBenjamin Herrenschmidt 92184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 93184cd4a3SBenjamin Herrenschmidt return pe; 94184cd4a3SBenjamin Herrenschmidt } 95184cd4a3SBenjamin Herrenschmidt 96cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 97184cd4a3SBenjamin Herrenschmidt { 98184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 99184cd4a3SBenjamin Herrenschmidt 100184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 101184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 102184cd4a3SBenjamin Herrenschmidt } 103184cd4a3SBenjamin Herrenschmidt 104184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 105184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 106184cd4a3SBenjamin Herrenschmidt */ 107184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 108cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 109184cd4a3SBenjamin Herrenschmidt { 110184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 111184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 112184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 113184cd4a3SBenjamin Herrenschmidt 114184cd4a3SBenjamin Herrenschmidt if (!pdn) 115184cd4a3SBenjamin Herrenschmidt return NULL; 116184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 117184cd4a3SBenjamin Herrenschmidt return NULL; 118184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 119184cd4a3SBenjamin Herrenschmidt } 120184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 121184cd4a3SBenjamin Herrenschmidt 122cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 123184cd4a3SBenjamin Herrenschmidt { 124184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 125184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 126184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 127184cd4a3SBenjamin Herrenschmidt 128184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 129184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 130184cd4a3SBenjamin Herrenschmidt int count; 131184cd4a3SBenjamin Herrenschmidt 132184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 133184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 134184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 135fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 136b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 137fb446ad0SGavin Shan else 138fb446ad0SGavin Shan count = 1; 139fb446ad0SGavin Shan 140184cd4a3SBenjamin Herrenschmidt switch(count) { 141184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 142184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 143184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 144184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 145184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 146184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 147184cd4a3SBenjamin Herrenschmidt default: 148184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 149184cd4a3SBenjamin Herrenschmidt " unsupported\n", 150184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 151184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 152184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 153184cd4a3SBenjamin Herrenschmidt } 154184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 155184cd4a3SBenjamin Herrenschmidt } else { 156184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 157184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 158184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 159184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 160184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 161184cd4a3SBenjamin Herrenschmidt } 162184cd4a3SBenjamin Herrenschmidt 163184cd4a3SBenjamin Herrenschmidt /* Associate PE in PELT */ 164184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 165184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 166184cd4a3SBenjamin Herrenschmidt if (rc) { 167184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 168184cd4a3SBenjamin Herrenschmidt return -ENXIO; 169184cd4a3SBenjamin Herrenschmidt } 170184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 171184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 172184cd4a3SBenjamin Herrenschmidt 173184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 174184cd4a3SBenjamin Herrenschmidt while (parent) { 175184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(parent); 176184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 177184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 178cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 179184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 180184cd4a3SBenjamin Herrenschmidt } 181184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 182184cd4a3SBenjamin Herrenschmidt } 183184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 184184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 185184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 186184cd4a3SBenjamin Herrenschmidt 187184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 188184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 189184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 190184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 191184cd4a3SBenjamin Herrenschmidt pe->pe_number); 192184cd4a3SBenjamin Herrenschmidt if (rc) { 193184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 194184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 195184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 196184cd4a3SBenjamin Herrenschmidt } else { 197184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 198cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 199184cd4a3SBenjamin Herrenschmidt if (rc) { 200184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 201184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 202184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 203184cd4a3SBenjamin Herrenschmidt } 204184cd4a3SBenjamin Herrenschmidt } 205184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 206184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 207184cd4a3SBenjamin Herrenschmidt 208184cd4a3SBenjamin Herrenschmidt return 0; 209184cd4a3SBenjamin Herrenschmidt } 210184cd4a3SBenjamin Herrenschmidt 211cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 212184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 213184cd4a3SBenjamin Herrenschmidt { 214184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 215184cd4a3SBenjamin Herrenschmidt 2167ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 217184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 2187ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 219184cd4a3SBenjamin Herrenschmidt return; 220184cd4a3SBenjamin Herrenschmidt } 221184cd4a3SBenjamin Herrenschmidt } 2227ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 223184cd4a3SBenjamin Herrenschmidt } 224184cd4a3SBenjamin Herrenschmidt 225184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 226184cd4a3SBenjamin Herrenschmidt { 227184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 228184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 229184cd4a3SBenjamin Herrenschmidt */ 230184cd4a3SBenjamin Herrenschmidt 231184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 232184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 233184cd4a3SBenjamin Herrenschmidt return 0; 234184cd4a3SBenjamin Herrenschmidt 235184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 236184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 237184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 238184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 239184cd4a3SBenjamin Herrenschmidt return 3; 240184cd4a3SBenjamin Herrenschmidt 241184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 242184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 243184cd4a3SBenjamin Herrenschmidt return 15; 244184cd4a3SBenjamin Herrenschmidt 245184cd4a3SBenjamin Herrenschmidt /* Default */ 246184cd4a3SBenjamin Herrenschmidt return 10; 247184cd4a3SBenjamin Herrenschmidt } 248184cd4a3SBenjamin Herrenschmidt 249fb446ad0SGavin Shan #if 0 250cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 251184cd4a3SBenjamin Herrenschmidt { 252184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 253184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 254184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 255184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 256184cd4a3SBenjamin Herrenschmidt int pe_num; 257184cd4a3SBenjamin Herrenschmidt 258184cd4a3SBenjamin Herrenschmidt if (!pdn) { 259184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 260184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 261184cd4a3SBenjamin Herrenschmidt return NULL; 262184cd4a3SBenjamin Herrenschmidt } 263184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 264184cd4a3SBenjamin Herrenschmidt return NULL; 265184cd4a3SBenjamin Herrenschmidt 266184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 267184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 268184cd4a3SBenjamin Herrenschmidt pe_num = 0; 269184cd4a3SBenjamin Herrenschmidt else 270184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 271184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 272184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 273184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 274184cd4a3SBenjamin Herrenschmidt return NULL; 275184cd4a3SBenjamin Herrenschmidt } 276184cd4a3SBenjamin Herrenschmidt 277184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 278184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 279184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 280184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 281184cd4a3SBenjamin Herrenschmidt * 282184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 283184cd4a3SBenjamin Herrenschmidt */ 284184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 285184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 286184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 287184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 288184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 289184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 290184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 291184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 292184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 293184cd4a3SBenjamin Herrenschmidt 294184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 295184cd4a3SBenjamin Herrenschmidt 296184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 297184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 298184cd4a3SBenjamin Herrenschmidt if (pe_num) 299184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 300184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 301184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 302184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 303184cd4a3SBenjamin Herrenschmidt return NULL; 304184cd4a3SBenjamin Herrenschmidt } 305184cd4a3SBenjamin Herrenschmidt 306184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 307184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 308184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 309184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 310184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 311184cd4a3SBenjamin Herrenschmidt } 312184cd4a3SBenjamin Herrenschmidt 313184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 314184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 315184cd4a3SBenjamin Herrenschmidt 316184cd4a3SBenjamin Herrenschmidt return pe; 317184cd4a3SBenjamin Herrenschmidt } 318fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 319184cd4a3SBenjamin Herrenschmidt 320184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 321184cd4a3SBenjamin Herrenschmidt { 322184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 323184cd4a3SBenjamin Herrenschmidt 324184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 325184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 326184cd4a3SBenjamin Herrenschmidt 327184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 328184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 329184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 330184cd4a3SBenjamin Herrenschmidt continue; 331184cd4a3SBenjamin Herrenschmidt } 332184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 333184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 334184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 335184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 336fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 337184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 338184cd4a3SBenjamin Herrenschmidt } 339184cd4a3SBenjamin Herrenschmidt } 340184cd4a3SBenjamin Herrenschmidt 341fb446ad0SGavin Shan /* 342fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 343fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 344fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 345fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 346fb446ad0SGavin Shan */ 347cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 348184cd4a3SBenjamin Herrenschmidt { 349fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 350184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 351184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 352184cd4a3SBenjamin Herrenschmidt int pe_num; 353184cd4a3SBenjamin Herrenschmidt 354184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 355184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 356fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 357fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 358184cd4a3SBenjamin Herrenschmidt return; 359184cd4a3SBenjamin Herrenschmidt } 360184cd4a3SBenjamin Herrenschmidt 361184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 362fb446ad0SGavin Shan pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 363184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 364184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 365184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 366184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 367b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 368184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 369184cd4a3SBenjamin Herrenschmidt 370fb446ad0SGavin Shan if (all) 371fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 372fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 373fb446ad0SGavin Shan else 374fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 375fb446ad0SGavin Shan bus->busn_res.start, pe_num); 376184cd4a3SBenjamin Herrenschmidt 377184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 378184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 379184cd4a3SBenjamin Herrenschmidt if (pe_num) 380184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 381184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 382184cd4a3SBenjamin Herrenschmidt return; 383184cd4a3SBenjamin Herrenschmidt } 384184cd4a3SBenjamin Herrenschmidt 385184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 386184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 387184cd4a3SBenjamin Herrenschmidt 3887ebdf956SGavin Shan /* Put PE to the list */ 3897ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 3907ebdf956SGavin Shan 391184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 392184cd4a3SBenjamin Herrenschmidt * below the bridge 393184cd4a3SBenjamin Herrenschmidt */ 394184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 395184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 396184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 397184cd4a3SBenjamin Herrenschmidt } 398184cd4a3SBenjamin Herrenschmidt 399184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 400184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 401184cd4a3SBenjamin Herrenschmidt } 402184cd4a3SBenjamin Herrenschmidt 403cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 404184cd4a3SBenjamin Herrenschmidt { 405184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 406fb446ad0SGavin Shan 407fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 408184cd4a3SBenjamin Herrenschmidt 409184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 410fb446ad0SGavin Shan if (dev->subordinate) { 41162f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 412fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 413fb446ad0SGavin Shan else 414184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 415184cd4a3SBenjamin Herrenschmidt } 416184cd4a3SBenjamin Herrenschmidt } 417fb446ad0SGavin Shan } 418fb446ad0SGavin Shan 419fb446ad0SGavin Shan /* 420fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 421fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 422fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 423fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 424fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 425fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 426fb446ad0SGavin Shan */ 427cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 428fb446ad0SGavin Shan { 429fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 430fb446ad0SGavin Shan 431fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 432fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 433fb446ad0SGavin Shan } 434fb446ad0SGavin Shan } 435184cd4a3SBenjamin Herrenschmidt 436cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *dev) 437184cd4a3SBenjamin Herrenschmidt { 438184cd4a3SBenjamin Herrenschmidt /* We delay DMA setup after we have assigned all PE# */ 439184cd4a3SBenjamin Herrenschmidt } 440184cd4a3SBenjamin Herrenschmidt 441cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 442184cd4a3SBenjamin Herrenschmidt { 443184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 444184cd4a3SBenjamin Herrenschmidt 445184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 446184cd4a3SBenjamin Herrenschmidt set_iommu_table_base(&dev->dev, &pe->tce32_table); 447184cd4a3SBenjamin Herrenschmidt if (dev->subordinate) 448184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, dev->subordinate); 449184cd4a3SBenjamin Herrenschmidt } 450184cd4a3SBenjamin Herrenschmidt } 451184cd4a3SBenjamin Herrenschmidt 452cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 453cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 454184cd4a3SBenjamin Herrenschmidt unsigned int segs) 455184cd4a3SBenjamin Herrenschmidt { 456184cd4a3SBenjamin Herrenschmidt 457184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 458184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 459184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 460184cd4a3SBenjamin Herrenschmidt unsigned int i; 461184cd4a3SBenjamin Herrenschmidt int64_t rc; 462184cd4a3SBenjamin Herrenschmidt void *addr; 463184cd4a3SBenjamin Herrenschmidt 464184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 465184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 466184cd4a3SBenjamin Herrenschmidt 467184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 468184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 469184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 470184cd4a3SBenjamin Herrenschmidt 471184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 472184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 473184cd4a3SBenjamin Herrenschmidt return; 474184cd4a3SBenjamin Herrenschmidt 475184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 476184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 477184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 478184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 479184cd4a3SBenjamin Herrenschmidt 480184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 481184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 482184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 483184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 484184cd4a3SBenjamin Herrenschmidt */ 485184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 486184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 487184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 488184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 489184cd4a3SBenjamin Herrenschmidt goto fail; 490184cd4a3SBenjamin Herrenschmidt } 491184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 492184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 493184cd4a3SBenjamin Herrenschmidt 494184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 495184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 496184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 497184cd4a3SBenjamin Herrenschmidt pe->pe_number, 498184cd4a3SBenjamin Herrenschmidt base + i, 1, 499184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 500184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 501184cd4a3SBenjamin Herrenschmidt if (rc) { 502184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 503184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 504184cd4a3SBenjamin Herrenschmidt goto fail; 505184cd4a3SBenjamin Herrenschmidt } 506184cd4a3SBenjamin Herrenschmidt } 507184cd4a3SBenjamin Herrenschmidt 508184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 509184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 510184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 511184cd4a3SBenjamin Herrenschmidt base << 28); 512184cd4a3SBenjamin Herrenschmidt 513184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 514184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 515184cd4a3SBenjamin Herrenschmidt if (swinvp) { 516184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 517184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 518184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 519184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 520184cd4a3SBenjamin Herrenschmidt */ 521184cd4a3SBenjamin Herrenschmidt tbl->it_busno = 0; 522184cd4a3SBenjamin Herrenschmidt tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 523184cd4a3SBenjamin Herrenschmidt tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE 524184cd4a3SBenjamin Herrenschmidt | TCE_PCI_SWINV_PAIR; 525184cd4a3SBenjamin Herrenschmidt } 526184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 527184cd4a3SBenjamin Herrenschmidt 528184cd4a3SBenjamin Herrenschmidt if (pe->pdev) 529184cd4a3SBenjamin Herrenschmidt set_iommu_table_base(&pe->pdev->dev, tbl); 530184cd4a3SBenjamin Herrenschmidt else 531184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, pe->pbus); 532184cd4a3SBenjamin Herrenschmidt 533184cd4a3SBenjamin Herrenschmidt return; 534184cd4a3SBenjamin Herrenschmidt fail: 535184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 536184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 537184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 538184cd4a3SBenjamin Herrenschmidt if (tce_mem) 539184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 540184cd4a3SBenjamin Herrenschmidt } 541184cd4a3SBenjamin Herrenschmidt 542cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 543184cd4a3SBenjamin Herrenschmidt { 544184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 545184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 546184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 547184cd4a3SBenjamin Herrenschmidt 548184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 549184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 550184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 551184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 552184cd4a3SBenjamin Herrenschmidt */ 553184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 554184cd4a3SBenjamin Herrenschmidt residual = 0; 555184cd4a3SBenjamin Herrenschmidt else 556184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 557184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 558184cd4a3SBenjamin Herrenschmidt 559184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 560184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 561184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 562184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 563184cd4a3SBenjamin Herrenschmidt 564184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 565184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 566184cd4a3SBenjamin Herrenschmidt * weight 567184cd4a3SBenjamin Herrenschmidt */ 568184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 569184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 570184cd4a3SBenjamin Herrenschmidt base = 0; 5717ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 572184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 573184cd4a3SBenjamin Herrenschmidt continue; 574184cd4a3SBenjamin Herrenschmidt if (!remaining) { 575184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 576184cd4a3SBenjamin Herrenschmidt continue; 577184cd4a3SBenjamin Herrenschmidt } 578184cd4a3SBenjamin Herrenschmidt segs = 1; 579184cd4a3SBenjamin Herrenschmidt if (residual) { 580184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 581184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 582184cd4a3SBenjamin Herrenschmidt segs = remaining; 583184cd4a3SBenjamin Herrenschmidt } 584184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 585184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 586184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 587184cd4a3SBenjamin Herrenschmidt remaining -= segs; 588184cd4a3SBenjamin Herrenschmidt base += segs; 589184cd4a3SBenjamin Herrenschmidt } 590184cd4a3SBenjamin Herrenschmidt } 591184cd4a3SBenjamin Herrenschmidt 592184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 593137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 594137436c9SGavin Shan { 595137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 596137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 597137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 598137436c9SGavin Shan ioda.irq_chip); 599137436c9SGavin Shan int64_t rc; 600137436c9SGavin Shan 601137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 602137436c9SGavin Shan WARN_ON_ONCE(rc); 603137436c9SGavin Shan 604137436c9SGavin Shan icp_native_eoi(d); 605137436c9SGavin Shan } 606137436c9SGavin Shan 607184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 608137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 609137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 610184cd4a3SBenjamin Herrenschmidt { 611184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 612137436c9SGavin Shan struct irq_data *idata; 613137436c9SGavin Shan struct irq_chip *ichip; 614184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 615184cd4a3SBenjamin Herrenschmidt uint64_t addr64; 616184cd4a3SBenjamin Herrenschmidt uint32_t addr32, data; 617184cd4a3SBenjamin Herrenschmidt int rc; 618184cd4a3SBenjamin Herrenschmidt 619184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 620184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 621184cd4a3SBenjamin Herrenschmidt return -ENXIO; 622184cd4a3SBenjamin Herrenschmidt 623184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 624184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 625184cd4a3SBenjamin Herrenschmidt return -ENXIO; 626184cd4a3SBenjamin Herrenschmidt 627184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 628184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 629184cd4a3SBenjamin Herrenschmidt if (rc) { 630184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 631184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 632184cd4a3SBenjamin Herrenschmidt return -EIO; 633184cd4a3SBenjamin Herrenschmidt } 634184cd4a3SBenjamin Herrenschmidt 635184cd4a3SBenjamin Herrenschmidt if (is_64) { 636184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 637184cd4a3SBenjamin Herrenschmidt &addr64, &data); 638184cd4a3SBenjamin Herrenschmidt if (rc) { 639184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 640184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 641184cd4a3SBenjamin Herrenschmidt return -EIO; 642184cd4a3SBenjamin Herrenschmidt } 643184cd4a3SBenjamin Herrenschmidt msg->address_hi = addr64 >> 32; 644184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr64 & 0xfffffffful; 645184cd4a3SBenjamin Herrenschmidt } else { 646184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 647184cd4a3SBenjamin Herrenschmidt &addr32, &data); 648184cd4a3SBenjamin Herrenschmidt if (rc) { 649184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 650184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 651184cd4a3SBenjamin Herrenschmidt return -EIO; 652184cd4a3SBenjamin Herrenschmidt } 653184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 654184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr32; 655184cd4a3SBenjamin Herrenschmidt } 656184cd4a3SBenjamin Herrenschmidt msg->data = data; 657184cd4a3SBenjamin Herrenschmidt 658137436c9SGavin Shan /* 659137436c9SGavin Shan * Change the IRQ chip for the MSI interrupts on PHB3. 660137436c9SGavin Shan * The corresponding IRQ chip should be populated for 661137436c9SGavin Shan * the first time. 662137436c9SGavin Shan */ 663137436c9SGavin Shan if (phb->type == PNV_PHB_IODA2) { 664137436c9SGavin Shan if (!phb->ioda.irq_chip_init) { 665137436c9SGavin Shan idata = irq_get_irq_data(virq); 666137436c9SGavin Shan ichip = irq_data_get_irq_chip(idata); 667137436c9SGavin Shan phb->ioda.irq_chip_init = 1; 668137436c9SGavin Shan phb->ioda.irq_chip = *ichip; 669137436c9SGavin Shan phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 670137436c9SGavin Shan } 671137436c9SGavin Shan 672137436c9SGavin Shan irq_set_chip(virq, &phb->ioda.irq_chip); 673137436c9SGavin Shan } 674137436c9SGavin Shan 675184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 676184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 677184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 678184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 679184cd4a3SBenjamin Herrenschmidt 680184cd4a3SBenjamin Herrenschmidt return 0; 681184cd4a3SBenjamin Herrenschmidt } 682184cd4a3SBenjamin Herrenschmidt 683184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 684184cd4a3SBenjamin Herrenschmidt { 685fb1b55d6SGavin Shan unsigned int count; 686184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 687184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 688184cd4a3SBenjamin Herrenschmidt if (!prop) { 689184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 690184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 691184cd4a3SBenjamin Herrenschmidt } 692184cd4a3SBenjamin Herrenschmidt if (!prop) 693184cd4a3SBenjamin Herrenschmidt return; 694184cd4a3SBenjamin Herrenschmidt 695184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 696fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 697fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 698184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 699184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 700184cd4a3SBenjamin Herrenschmidt return; 701184cd4a3SBenjamin Herrenschmidt } 702fb1b55d6SGavin Shan 703184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 704184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 705184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 706fb1b55d6SGavin Shan count, phb->msi_base); 707184cd4a3SBenjamin Herrenschmidt } 708184cd4a3SBenjamin Herrenschmidt #else 709184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 710184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 711184cd4a3SBenjamin Herrenschmidt 71211685becSGavin Shan /* 71311685becSGavin Shan * This function is supposed to be called on basis of PE from top 71411685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 71511685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 71611685becSGavin Shan */ 717cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 71811685becSGavin Shan struct pnv_ioda_pe *pe) 71911685becSGavin Shan { 72011685becSGavin Shan struct pnv_phb *phb = hose->private_data; 72111685becSGavin Shan struct pci_bus_region region; 72211685becSGavin Shan struct resource *res; 72311685becSGavin Shan int i, index; 72411685becSGavin Shan int rc; 72511685becSGavin Shan 72611685becSGavin Shan /* 72711685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 72811685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 72911685becSGavin Shan * be figured out later. 73011685becSGavin Shan */ 73111685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 73211685becSGavin Shan 73311685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 73411685becSGavin Shan if (!res || !res->flags || 73511685becSGavin Shan res->start > res->end) 73611685becSGavin Shan continue; 73711685becSGavin Shan 73811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 73911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 74011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 74111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 74211685becSGavin Shan 74311685becSGavin Shan while (index < phb->ioda.total_pe && 74411685becSGavin Shan region.start <= region.end) { 74511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 74611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 74711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 74811685becSGavin Shan if (rc != OPAL_SUCCESS) { 74911685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 75011685becSGavin Shan "segment #%d to PE#%d\n", 75111685becSGavin Shan __func__, rc, index, pe->pe_number); 75211685becSGavin Shan break; 75311685becSGavin Shan } 75411685becSGavin Shan 75511685becSGavin Shan region.start += phb->ioda.io_segsize; 75611685becSGavin Shan index++; 75711685becSGavin Shan } 75811685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 75911685becSGavin Shan region.start = res->start - 76011685becSGavin Shan hose->pci_mem_offset - 76111685becSGavin Shan phb->ioda.m32_pci_base; 76211685becSGavin Shan region.end = res->end - 76311685becSGavin Shan hose->pci_mem_offset - 76411685becSGavin Shan phb->ioda.m32_pci_base; 76511685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 76611685becSGavin Shan 76711685becSGavin Shan while (index < phb->ioda.total_pe && 76811685becSGavin Shan region.start <= region.end) { 76911685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 77011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 77111685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 77211685becSGavin Shan if (rc != OPAL_SUCCESS) { 77311685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 77411685becSGavin Shan "segment#%d to PE#%d", 77511685becSGavin Shan __func__, rc, index, pe->pe_number); 77611685becSGavin Shan break; 77711685becSGavin Shan } 77811685becSGavin Shan 77911685becSGavin Shan region.start += phb->ioda.m32_segsize; 78011685becSGavin Shan index++; 78111685becSGavin Shan } 78211685becSGavin Shan } 78311685becSGavin Shan } 78411685becSGavin Shan } 78511685becSGavin Shan 786cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 78711685becSGavin Shan { 78811685becSGavin Shan struct pci_controller *tmp, *hose; 78911685becSGavin Shan struct pnv_phb *phb; 79011685becSGavin Shan struct pnv_ioda_pe *pe; 79111685becSGavin Shan 79211685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 79311685becSGavin Shan phb = hose->private_data; 79411685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 79511685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 79611685becSGavin Shan } 79711685becSGavin Shan } 79811685becSGavin Shan } 79911685becSGavin Shan 800cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 80113395c48SGavin Shan { 80213395c48SGavin Shan struct pci_controller *hose, *tmp; 803db1266c8SGavin Shan struct pnv_phb *phb; 80413395c48SGavin Shan 80513395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 80613395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 807db1266c8SGavin Shan 808db1266c8SGavin Shan /* Mark the PHB initialization done */ 809db1266c8SGavin Shan phb = hose->private_data; 810db1266c8SGavin Shan phb->initialized = 1; 81113395c48SGavin Shan } 81213395c48SGavin Shan } 81313395c48SGavin Shan 814cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 815fb446ad0SGavin Shan { 816fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 81711685becSGavin Shan pnv_pci_ioda_setup_seg(); 81813395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 819fb446ad0SGavin Shan } 820fb446ad0SGavin Shan 821271fd03aSGavin Shan /* 822271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 823271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 824271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 825271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 826271fd03aSGavin Shan * 1MiB for memory) will be returned. 827271fd03aSGavin Shan * 828271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 829271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 830271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 831271fd03aSGavin Shan * resources. 832271fd03aSGavin Shan */ 833271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 834271fd03aSGavin Shan unsigned long type) 835271fd03aSGavin Shan { 836271fd03aSGavin Shan struct pci_dev *bridge; 837271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 838271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 839271fd03aSGavin Shan int num_pci_bridges = 0; 840271fd03aSGavin Shan 841271fd03aSGavin Shan bridge = bus->self; 842271fd03aSGavin Shan while (bridge) { 843271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 844271fd03aSGavin Shan num_pci_bridges++; 845271fd03aSGavin Shan if (num_pci_bridges >= 2) 846271fd03aSGavin Shan return 1; 847271fd03aSGavin Shan } 848271fd03aSGavin Shan 849271fd03aSGavin Shan bridge = bridge->bus->self; 850271fd03aSGavin Shan } 851271fd03aSGavin Shan 852271fd03aSGavin Shan /* We need support prefetchable memory window later */ 853271fd03aSGavin Shan if (type & IORESOURCE_MEM) 854271fd03aSGavin Shan return phb->ioda.m32_segsize; 855271fd03aSGavin Shan 856271fd03aSGavin Shan return phb->ioda.io_segsize; 857271fd03aSGavin Shan } 858271fd03aSGavin Shan 859184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 860184cd4a3SBenjamin Herrenschmidt * assign a PE 861184cd4a3SBenjamin Herrenschmidt */ 862cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 863184cd4a3SBenjamin Herrenschmidt { 864db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 865db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 866db1266c8SGavin Shan struct pci_dn *pdn; 867184cd4a3SBenjamin Herrenschmidt 868db1266c8SGavin Shan /* The function is probably called while the PEs have 869db1266c8SGavin Shan * not be created yet. For example, resource reassignment 870db1266c8SGavin Shan * during PCI probe period. We just skip the check if 871db1266c8SGavin Shan * PEs isn't ready. 872db1266c8SGavin Shan */ 873db1266c8SGavin Shan if (!phb->initialized) 874db1266c8SGavin Shan return 0; 875db1266c8SGavin Shan 876db1266c8SGavin Shan pdn = pnv_ioda_get_pdn(dev); 877184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 878184cd4a3SBenjamin Herrenschmidt return -EINVAL; 879db1266c8SGavin Shan 880184cd4a3SBenjamin Herrenschmidt return 0; 881184cd4a3SBenjamin Herrenschmidt } 882184cd4a3SBenjamin Herrenschmidt 883184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 884184cd4a3SBenjamin Herrenschmidt u32 devfn) 885184cd4a3SBenjamin Herrenschmidt { 886184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 887184cd4a3SBenjamin Herrenschmidt } 888184cd4a3SBenjamin Herrenschmidt 889aa0c033fSGavin Shan void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type) 890184cd4a3SBenjamin Herrenschmidt { 891184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 892184cd4a3SBenjamin Herrenschmidt static int primary = 1; 893184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 894184cd4a3SBenjamin Herrenschmidt unsigned long size, m32map_off, iomap_off, pemap_off; 895184cd4a3SBenjamin Herrenschmidt const u64 *prop64; 896aa0c033fSGavin Shan const u32 *prop32; 897184cd4a3SBenjamin Herrenschmidt u64 phb_id; 898184cd4a3SBenjamin Herrenschmidt void *aux; 899184cd4a3SBenjamin Herrenschmidt long rc; 900184cd4a3SBenjamin Herrenschmidt 901aa0c033fSGavin Shan pr_info(" Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 902184cd4a3SBenjamin Herrenschmidt 903184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 904184cd4a3SBenjamin Herrenschmidt if (!prop64) { 905184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 906184cd4a3SBenjamin Herrenschmidt return; 907184cd4a3SBenjamin Herrenschmidt } 908184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 909184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 910184cd4a3SBenjamin Herrenschmidt 911184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 912184cd4a3SBenjamin Herrenschmidt if (phb) { 913184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 914184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 915184cd4a3SBenjamin Herrenschmidt } 916184cd4a3SBenjamin Herrenschmidt if (!phb || !phb->hose) { 917184cd4a3SBenjamin Herrenschmidt pr_err("PCI: Failed to allocate PCI controller for %s\n", 918184cd4a3SBenjamin Herrenschmidt np->full_name); 919184cd4a3SBenjamin Herrenschmidt return; 920184cd4a3SBenjamin Herrenschmidt } 921184cd4a3SBenjamin Herrenschmidt 922184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 923184cd4a3SBenjamin Herrenschmidt /* XXX Use device-tree */ 924184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 925184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 926184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 927184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 928aa0c033fSGavin Shan phb->type = ioda_type; 929184cd4a3SBenjamin Herrenschmidt 930cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 931cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 932cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 933aa0c033fSGavin Shan else if (of_device_is_compatible(np, "ibm,p8-pciex")) 934aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 935cee72d5bSBenjamin Herrenschmidt else 936cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 937cee72d5bSBenjamin Herrenschmidt 938aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 939184cd4a3SBenjamin Herrenschmidt pci_process_bridge_OF_ranges(phb->hose, np, primary); 940184cd4a3SBenjamin Herrenschmidt primary = 0; 941184cd4a3SBenjamin Herrenschmidt 942aa0c033fSGavin Shan /* Get registers */ 943184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 944184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 945184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 946184cd4a3SBenjamin Herrenschmidt 947184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 948aa0c033fSGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 949aa0c033fSGavin Shan if (!prop32) 950aa0c033fSGavin Shan phb->ioda.total_pe = 1; 951aa0c033fSGavin Shan else 952aa0c033fSGavin Shan phb->ioda.total_pe = *prop32; 953184cd4a3SBenjamin Herrenschmidt 954184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 955aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 956184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 957184cd4a3SBenjamin Herrenschmidt 958184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 959184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - 960184cd4a3SBenjamin Herrenschmidt hose->pci_mem_offset; 961184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 962184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 963184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 964184cd4a3SBenjamin Herrenschmidt 965aa0c033fSGavin Shan /* Allocate aux data & arrays 966aa0c033fSGavin Shan * 967aa0c033fSGavin Shan * XXX TODO: Don't allocate io segmap on PHB3 968aa0c033fSGavin Shan */ 969184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 970184cd4a3SBenjamin Herrenschmidt m32map_off = size; 971e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 972184cd4a3SBenjamin Herrenschmidt iomap_off = size; 973e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 974184cd4a3SBenjamin Herrenschmidt pemap_off = size; 975184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 976184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 977184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 978184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 979184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 980184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 981184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 982184cd4a3SBenjamin Herrenschmidt set_bit(0, phb->ioda.pe_alloc); 983184cd4a3SBenjamin Herrenschmidt 9847ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 985184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 986184cd4a3SBenjamin Herrenschmidt 987184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 988184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 989184cd4a3SBenjamin Herrenschmidt 990184cd4a3SBenjamin Herrenschmidt /* Clear unusable m64 */ 991184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].flags = 0; 992184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].start = 0; 993184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].end = 0; 994184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].flags = 0; 995184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].start = 0; 996184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].end = 0; 997184cd4a3SBenjamin Herrenschmidt 998aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 999184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1000184cd4a3SBenjamin Herrenschmidt window_type, 1001184cd4a3SBenjamin Herrenschmidt window_num, 1002184cd4a3SBenjamin Herrenschmidt starting_real_address, 1003184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1004184cd4a3SBenjamin Herrenschmidt segment_size); 1005184cd4a3SBenjamin Herrenschmidt #endif 1006184cd4a3SBenjamin Herrenschmidt 1007184cd4a3SBenjamin Herrenschmidt pr_info(" %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n", 1008184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 1009184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size, phb->ioda.m32_segsize, 1010184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1011184cd4a3SBenjamin Herrenschmidt 1012184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 1013184cd4a3SBenjamin Herrenschmidt 1014184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1015184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1016184cd4a3SBenjamin Herrenschmidt 1017184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1018184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1019184cd4a3SBenjamin Herrenschmidt 1020184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1021184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1022184cd4a3SBenjamin Herrenschmidt 1023c40a4210SGavin Shan /* 1024c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1025c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1026c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1027c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1028c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1029184cd4a3SBenjamin Herrenschmidt */ 1030fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1031184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1032271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1033c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1034184cd4a3SBenjamin Herrenschmidt 1035184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1036f11fe552SBenjamin Herrenschmidt rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); 1037184cd4a3SBenjamin Herrenschmidt if (rc) 1038f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1039aa0c033fSGavin Shan 1040aa0c033fSGavin Shan /* 1041aa0c033fSGavin Shan * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset 1042aa0c033fSGavin Shan * has cleared the RTT which has the same effect 1043aa0c033fSGavin Shan */ 1044aa0c033fSGavin Shan if (ioda_type == PNV_PHB_IODA1) 1045184cd4a3SBenjamin Herrenschmidt opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE); 1046184cd4a3SBenjamin Herrenschmidt } 1047184cd4a3SBenjamin Herrenschmidt 1048aa0c033fSGavin Shan void pnv_pci_init_ioda2_phb(struct device_node *np) 1049aa0c033fSGavin Shan { 1050aa0c033fSGavin Shan pnv_pci_init_ioda_phb(np, PNV_PHB_IODA2); 1051aa0c033fSGavin Shan } 1052aa0c033fSGavin Shan 1053184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 1054184cd4a3SBenjamin Herrenschmidt { 1055184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 1056184cd4a3SBenjamin Herrenschmidt const u64 *prop64; 1057184cd4a3SBenjamin Herrenschmidt u64 hub_id; 1058184cd4a3SBenjamin Herrenschmidt 1059184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1060184cd4a3SBenjamin Herrenschmidt 1061184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1062184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1063184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1064184cd4a3SBenjamin Herrenschmidt return; 1065184cd4a3SBenjamin Herrenschmidt } 1066184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 1067184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1068184cd4a3SBenjamin Herrenschmidt 1069184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 1070184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 1071184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 1072184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1073aa0c033fSGavin Shan pnv_pci_init_ioda_phb(phbn, PNV_PHB_IODA1); 1074184cd4a3SBenjamin Herrenschmidt } 1075184cd4a3SBenjamin Herrenschmidt } 1076