12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 357644d581SMichael Ellerman #include <asm/debugfs.h> 36262af557SGuo Chao #include <asm/firmware.h> 3780c49c7eSIan Munsie #include <asm/pnv-pci.h> 38aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 39*0fcfe224SCédric Le Goater #include <asm/xive.h> 4080c49c7eSIan Munsie 41ec249dd8SMichael Neuling #include <misc/cxl-base.h> 42184cd4a3SBenjamin Herrenschmidt 43184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 44184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4544bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 46184cd4a3SBenjamin Herrenschmidt 4799451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4899451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 49acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 50781a868fSWei Yang 51562d1e20SChristoph Hellwig static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_OCAPI" }; 52aca6913fSAlexey Kardashevskiy 53c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus); 55c498a4f9SChristoph Hellwig 567d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 576d31c2faSJoe Perches const char *fmt, ...) 586d31c2faSJoe Perches { 596d31c2faSJoe Perches struct va_format vaf; 606d31c2faSJoe Perches va_list args; 616d31c2faSJoe Perches char pfix[32]; 62184cd4a3SBenjamin Herrenschmidt 636d31c2faSJoe Perches va_start(args, fmt); 646d31c2faSJoe Perches 656d31c2faSJoe Perches vaf.fmt = fmt; 666d31c2faSJoe Perches vaf.va = &args; 676d31c2faSJoe Perches 68781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 696d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 70781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 716d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 726d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 73781a868fSWei Yang #ifdef CONFIG_PCI_IOV 74781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 75781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 76781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 77781a868fSWei Yang (pe->rid & 0xff00) >> 8, 78781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 79781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 806d31c2faSJoe Perches 811f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 826d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 836d31c2faSJoe Perches 846d31c2faSJoe Perches va_end(args); 856d31c2faSJoe Perches } 866d31c2faSJoe Perches 874e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8845baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 894e287840SThadeu Lima de Souza Cascardo 904e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 914e287840SThadeu Lima de Souza Cascardo { 924e287840SThadeu Lima de Souza Cascardo if (!str) 934e287840SThadeu Lima de Souza Cascardo return -EINVAL; 944e287840SThadeu Lima de Souza Cascardo 954e287840SThadeu Lima de Souza Cascardo while (*str) { 964e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 974e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 984e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 994e287840SThadeu Lima de Souza Cascardo break; 1004e287840SThadeu Lima de Souza Cascardo } 1014e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1024e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1034e287840SThadeu Lima de Souza Cascardo str++; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo 1064e287840SThadeu Lima de Souza Cascardo return 0; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1094e287840SThadeu Lima de Souza Cascardo 11045baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11145baee14SGuilherme G. Piccoli { 11245baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11345baee14SGuilherme G. Piccoli return 0; 11445baee14SGuilherme G. Piccoli } 11545baee14SGuilherme G. Piccoli 11645baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11745baee14SGuilherme G. Piccoli 1181e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1191e916772SGavin Shan { 120313483ddSGavin Shan s64 rc; 121313483ddSGavin Shan 1221e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1231e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 12401e12629SOliver O'Halloran phb->ioda.pe_array[pe_no].dma_setup_done = false; 1251e916772SGavin Shan 126313483ddSGavin Shan /* 127313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 128313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 129313483ddSGavin Shan * PE is already in unfrozen state. 130313483ddSGavin Shan */ 131313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 132313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 133d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1341f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 135313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 136313483ddSGavin Shan 1371e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1381e916772SGavin Shan } 1391e916772SGavin Shan 1404b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1414b82ab18SGavin Shan { 14292b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1431f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1444b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1454b82ab18SGavin Shan return; 1464b82ab18SGavin Shan } 1474b82ab18SGavin Shan 148a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 149e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1501f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1514b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 152a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 1534b82ab18SGavin Shan 1541e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1554b82ab18SGavin Shan } 1564b82ab18SGavin Shan 157a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count) 158184cd4a3SBenjamin Herrenschmidt { 159a4bc676eSOliver O'Halloran struct pnv_ioda_pe *ret = NULL; 160a4bc676eSOliver O'Halloran int run = 0, pe, i; 161184cd4a3SBenjamin Herrenschmidt 162a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 163a4bc676eSOliver O'Halloran 164a4bc676eSOliver O'Halloran /* scan backwards for a run of @count cleared bits */ 1659fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 166a4bc676eSOliver O'Halloran if (test_bit(pe, phb->ioda.pe_alloc)) { 167a4bc676eSOliver O'Halloran run = 0; 168a4bc676eSOliver O'Halloran continue; 169184cd4a3SBenjamin Herrenschmidt } 170184cd4a3SBenjamin Herrenschmidt 171a4bc676eSOliver O'Halloran run++; 172a4bc676eSOliver O'Halloran if (run == count) 173a4bc676eSOliver O'Halloran break; 174a4bc676eSOliver O'Halloran } 175a4bc676eSOliver O'Halloran if (run != count) 176a4bc676eSOliver O'Halloran goto out; 177a4bc676eSOliver O'Halloran 178a4bc676eSOliver O'Halloran for (i = pe; i < pe + count; i++) { 179a4bc676eSOliver O'Halloran set_bit(i, phb->ioda.pe_alloc); 180a4bc676eSOliver O'Halloran pnv_ioda_init_pe(phb, i); 181a4bc676eSOliver O'Halloran } 182a4bc676eSOliver O'Halloran ret = &phb->ioda.pe_array[pe]; 183a4bc676eSOliver O'Halloran 184a4bc676eSOliver O'Halloran out: 185a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 186a4bc676eSOliver O'Halloran return ret; 1879fcd6f4aSGavin Shan } 1889fcd6f4aSGavin Shan 18937b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 190184cd4a3SBenjamin Herrenschmidt { 1911e916772SGavin Shan struct pnv_phb *phb = pe->phb; 192caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 193184cd4a3SBenjamin Herrenschmidt 1941e916772SGavin Shan WARN_ON(pe->pdev); 1951e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 196a4bc676eSOliver O'Halloran 197a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 198caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 199a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 200184cd4a3SBenjamin Herrenschmidt } 201184cd4a3SBenjamin Herrenschmidt 202262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 203262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 204262af557SGuo Chao { 205262af557SGuo Chao const char *desc; 206262af557SGuo Chao struct resource *r; 207262af557SGuo Chao s64 rc; 208262af557SGuo Chao 209262af557SGuo Chao /* Configure the default M64 BAR */ 210262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 211262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 212262af557SGuo Chao phb->ioda.m64_bar_idx, 213262af557SGuo Chao phb->ioda.m64_base, 214262af557SGuo Chao 0, /* unused */ 215262af557SGuo Chao phb->ioda.m64_size); 216262af557SGuo Chao if (rc != OPAL_SUCCESS) { 217262af557SGuo Chao desc = "configuring"; 218262af557SGuo Chao goto fail; 219262af557SGuo Chao } 220262af557SGuo Chao 221262af557SGuo Chao /* Enable the default M64 BAR */ 222262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 223262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 224262af557SGuo Chao phb->ioda.m64_bar_idx, 225262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 226262af557SGuo Chao if (rc != OPAL_SUCCESS) { 227262af557SGuo Chao desc = "enabling"; 228262af557SGuo Chao goto fail; 229262af557SGuo Chao } 230262af557SGuo Chao 231262af557SGuo Chao /* 23263803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23363803c39SGavin Shan * are first or last two PEs. 234262af557SGuo Chao */ 235262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23692b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23763803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23892b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23963803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 240262af557SGuo Chao else 2411f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 24292b8f137SGavin Shan phb->ioda.reserved_pe_idx); 243262af557SGuo Chao 244262af557SGuo Chao return 0; 245262af557SGuo Chao 246262af557SGuo Chao fail: 247262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 248262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 249262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 250262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 251262af557SGuo Chao phb->ioda.m64_bar_idx, 252262af557SGuo Chao OPAL_DISABLE_M64); 253262af557SGuo Chao return -EIO; 254262af557SGuo Chao } 255262af557SGuo Chao 256c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25796a2f92bSGavin Shan unsigned long *pe_bitmap) 258262af557SGuo Chao { 2595609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 260262af557SGuo Chao struct resource *r; 26196a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26296a2f92bSGavin Shan int segno, i; 263262af557SGuo Chao 26496a2f92bSGavin Shan base = phb->ioda.m64_base; 26596a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26696a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26796a2f92bSGavin Shan r = &pdev->resource[i]; 2685958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 269262af557SGuo Chao continue; 270262af557SGuo Chao 271e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 272b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 27396a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27496a2f92bSGavin Shan if (pe_bitmap) 27596a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27696a2f92bSGavin Shan else 27796a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 278262af557SGuo Chao } 279262af557SGuo Chao } 280262af557SGuo Chao } 281262af557SGuo Chao 28299451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28399451551SGavin Shan { 28499451551SGavin Shan struct resource *r; 28599451551SGavin Shan int index; 28699451551SGavin Shan 28799451551SGavin Shan /* 28899451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28999451551SGavin Shan * there are as many M64 segments as the maximum number of 29099451551SGavin Shan * PEs, which is 128. 29199451551SGavin Shan */ 29299451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29399451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29499451551SGavin Shan int64_t rc; 29599451551SGavin Shan 29699451551SGavin Shan base = phb->ioda.m64_base + 29799451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29899451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 30099451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 30199451551SGavin Shan if (rc != OPAL_SUCCESS) { 3021f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30399451551SGavin Shan rc, phb->hose->global_number, index); 30499451551SGavin Shan goto fail; 30599451551SGavin Shan } 30699451551SGavin Shan 30799451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30899451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30999451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 31099451551SGavin Shan if (rc != OPAL_SUCCESS) { 3111f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31299451551SGavin Shan rc, phb->hose->global_number, index); 31399451551SGavin Shan goto fail; 31499451551SGavin Shan } 31599451551SGavin Shan } 31699451551SGavin Shan 31736963365SOliver O'Halloran for (index = 0; index < phb->ioda.total_pe_num; index++) { 31836963365SOliver O'Halloran int64_t rc; 31936963365SOliver O'Halloran 32036963365SOliver O'Halloran /* 32136963365SOliver O'Halloran * P7IOC supports M64DT, which helps mapping M64 segment 32236963365SOliver O'Halloran * to one particular PE#. However, PHB3 has fixed mapping 32336963365SOliver O'Halloran * between M64 segment and PE#. In order to have same logic 32436963365SOliver O'Halloran * for P7IOC and PHB3, we enforce fixed mapping between M64 32536963365SOliver O'Halloran * segment and PE# on P7IOC. 32636963365SOliver O'Halloran */ 32736963365SOliver O'Halloran rc = opal_pci_map_pe_mmio_window(phb->opal_id, 32836963365SOliver O'Halloran index, OPAL_M64_WINDOW_TYPE, 32936963365SOliver O'Halloran index / PNV_IODA1_M64_SEGS, 33036963365SOliver O'Halloran index % PNV_IODA1_M64_SEGS); 33136963365SOliver O'Halloran if (rc != OPAL_SUCCESS) { 33236963365SOliver O'Halloran pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 33336963365SOliver O'Halloran __func__, rc, phb->hose->global_number, 33436963365SOliver O'Halloran index); 33536963365SOliver O'Halloran goto fail; 33636963365SOliver O'Halloran } 33736963365SOliver O'Halloran } 33836963365SOliver O'Halloran 33999451551SGavin Shan /* 34063803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 34163803c39SGavin Shan * are first or last two PEs. 34299451551SGavin Shan */ 34399451551SGavin Shan r = &phb->hose->mem_resources[1]; 34499451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 34563803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 34699451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 34763803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 34899451551SGavin Shan else 3491f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 35099451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 35199451551SGavin Shan 35299451551SGavin Shan return 0; 35399451551SGavin Shan 35499451551SGavin Shan fail: 35599451551SGavin Shan for ( ; index >= 0; index--) 35699451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 35799451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 35899451551SGavin Shan 35999451551SGavin Shan return -EIO; 36099451551SGavin Shan } 36199451551SGavin Shan 362c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 36396a2f92bSGavin Shan unsigned long *pe_bitmap, 36496a2f92bSGavin Shan bool all) 365262af557SGuo Chao { 366262af557SGuo Chao struct pci_dev *pdev; 36796a2f92bSGavin Shan 36896a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 369c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 37096a2f92bSGavin Shan 37196a2f92bSGavin Shan if (all && pdev->subordinate) 372c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 37396a2f92bSGavin Shan pe_bitmap, all); 37496a2f92bSGavin Shan } 37596a2f92bSGavin Shan } 37696a2f92bSGavin Shan 3771e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 378262af557SGuo Chao { 3795609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 380262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 381262af557SGuo Chao unsigned long size, *pe_alloc; 38226ba248dSGavin Shan int i; 383262af557SGuo Chao 384262af557SGuo Chao /* Root bus shouldn't use M64 */ 385262af557SGuo Chao if (pci_is_root_bus(bus)) 3861e916772SGavin Shan return NULL; 387262af557SGuo Chao 388262af557SGuo Chao /* Allocate bitmap */ 389b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 390262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 391262af557SGuo Chao if (!pe_alloc) { 392262af557SGuo Chao pr_warn("%s: Out of memory !\n", 393262af557SGuo Chao __func__); 3941e916772SGavin Shan return NULL; 395262af557SGuo Chao } 396262af557SGuo Chao 39726ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 398c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 399262af557SGuo Chao 400262af557SGuo Chao /* 401262af557SGuo Chao * the current bus might not own M64 window and that's all 402262af557SGuo Chao * contributed by its child buses. For the case, we needn't 403262af557SGuo Chao * pick M64 dependent PE#. 404262af557SGuo Chao */ 40592b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 406262af557SGuo Chao kfree(pe_alloc); 4071e916772SGavin Shan return NULL; 408262af557SGuo Chao } 409262af557SGuo Chao 410262af557SGuo Chao /* 411262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 412262af557SGuo Chao * PE's list to form compound PE. 413262af557SGuo Chao */ 414262af557SGuo Chao master_pe = NULL; 415262af557SGuo Chao i = -1; 41692b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 41792b8f137SGavin Shan phb->ioda.total_pe_num) { 418262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 419262af557SGuo Chao 42093289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 421262af557SGuo Chao if (!master_pe) { 422262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 423262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 424262af557SGuo Chao master_pe = pe; 425262af557SGuo Chao } else { 426262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 427262af557SGuo Chao pe->master = master_pe; 428262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 429262af557SGuo Chao } 430262af557SGuo Chao } 431262af557SGuo Chao 432262af557SGuo Chao kfree(pe_alloc); 4331e916772SGavin Shan return master_pe; 434262af557SGuo Chao } 435262af557SGuo Chao 436262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 437262af557SGuo Chao { 438262af557SGuo Chao struct pci_controller *hose = phb->hose; 439262af557SGuo Chao struct device_node *dn = hose->dn; 440262af557SGuo Chao struct resource *res; 441a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4420e7736c6SGavin Shan const __be32 *r; 443262af557SGuo Chao u64 pci_addr; 444262af557SGuo Chao 44599451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4461665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4471665c4a8SGavin Shan return; 4481665c4a8SGavin Shan } 4491665c4a8SGavin Shan 450e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 451262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 452262af557SGuo Chao return; 453262af557SGuo Chao } 454262af557SGuo Chao 455262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 456262af557SGuo Chao if (!r) { 457b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 458b7c670d6SRob Herring dn); 459262af557SGuo Chao return; 460262af557SGuo Chao } 461262af557SGuo Chao 462a1339fafSBenjamin Herrenschmidt /* 463a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 464a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 465a1339fafSBenjamin Herrenschmidt */ 466a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 467a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 468a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 469a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 470a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 471a1339fafSBenjamin Herrenschmidt } 472a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 473a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 474a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 475a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 476a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 477a1339fafSBenjamin Herrenschmidt } 478a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 479a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 480a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 481a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 482a1339fafSBenjamin Herrenschmidt return; 483a1339fafSBenjamin Herrenschmidt } 484a1339fafSBenjamin Herrenschmidt 485a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 486262af557SGuo Chao res = &hose->mem_resources[1]; 487e80c4e7cSGavin Shan res->name = dn->full_name; 488262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 489262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 490262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 491262af557SGuo Chao pci_addr = of_read_number(r, 2); 492262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 493262af557SGuo Chao 494262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49592b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 496262af557SGuo Chao phb->ioda.m64_base = pci_addr; 497262af557SGuo Chao 498a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 499a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 500a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 501a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 502a1339fafSBenjamin Herrenschmidt 503a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 504a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 505e9863e68SWei Yang 506262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 507a1339fafSBenjamin Herrenschmidt m64_range[1]--; 508a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 509a1339fafSBenjamin Herrenschmidt 510a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 511a1339fafSBenjamin Herrenschmidt 512a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 513a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 514a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 515a1339fafSBenjamin Herrenschmidt 516a1339fafSBenjamin Herrenschmidt /* 517a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 518a1339fafSBenjamin Herrenschmidt * the IODA2 code. 519a1339fafSBenjamin Herrenschmidt */ 52099451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 52199451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 52299451551SGavin Shan else 523262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 524262af557SGuo Chao } 525262af557SGuo Chao 52649dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52749dec922SGavin Shan { 52849dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52949dec922SGavin Shan struct pnv_ioda_pe *slave; 53049dec922SGavin Shan s64 rc; 53149dec922SGavin Shan 53249dec922SGavin Shan /* Fetch master PE */ 53349dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53449dec922SGavin Shan pe = pe->master; 535ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 536ec8e4e9dSGavin Shan return; 537ec8e4e9dSGavin Shan 53849dec922SGavin Shan pe_no = pe->pe_number; 53949dec922SGavin Shan } 54049dec922SGavin Shan 54149dec922SGavin Shan /* Freeze master PE */ 54249dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54349dec922SGavin Shan pe_no, 54449dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54649dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54749dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54849dec922SGavin Shan return; 54949dec922SGavin Shan } 55049dec922SGavin Shan 55149dec922SGavin Shan /* Freeze slave PEs */ 55249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55349dec922SGavin Shan return; 55449dec922SGavin Shan 55549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55649dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55749dec922SGavin Shan slave->pe_number, 55849dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55949dec922SGavin Shan if (rc != OPAL_SUCCESS) 56049dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 56149dec922SGavin Shan __func__, rc, phb->hose->global_number, 56249dec922SGavin Shan slave->pe_number); 56349dec922SGavin Shan } 56449dec922SGavin Shan } 56549dec922SGavin Shan 566e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56749dec922SGavin Shan { 56849dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56949dec922SGavin Shan s64 rc; 57049dec922SGavin Shan 57149dec922SGavin Shan /* Find master PE */ 57249dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57349dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57449dec922SGavin Shan pe = pe->master; 57549dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57649dec922SGavin Shan pe_no = pe->pe_number; 57749dec922SGavin Shan } 57849dec922SGavin Shan 57949dec922SGavin Shan /* Clear frozen state for master PE */ 58049dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 58149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58249dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58349dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58449dec922SGavin Shan return -EIO; 58549dec922SGavin Shan } 58649dec922SGavin Shan 58749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58849dec922SGavin Shan return 0; 58949dec922SGavin Shan 59049dec922SGavin Shan /* Clear frozen state for slave PEs */ 59149dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59249dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59349dec922SGavin Shan slave->pe_number, 59449dec922SGavin Shan opt); 59549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59649dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59749dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59849dec922SGavin Shan slave->pe_number); 59949dec922SGavin Shan return -EIO; 60049dec922SGavin Shan } 60149dec922SGavin Shan } 60249dec922SGavin Shan 60349dec922SGavin Shan return 0; 60449dec922SGavin Shan } 60549dec922SGavin Shan 60649dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60749dec922SGavin Shan { 60849dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 609c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 610c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 61149dec922SGavin Shan s64 rc; 61249dec922SGavin Shan 61349dec922SGavin Shan /* Sanity check on PE number */ 61492b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61549dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61649dec922SGavin Shan 61749dec922SGavin Shan /* 61849dec922SGavin Shan * Fetch the master PE and the PE instance might be 61949dec922SGavin Shan * not initialized yet. 62049dec922SGavin Shan */ 62149dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62349dec922SGavin Shan pe = pe->master; 62449dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62549dec922SGavin Shan pe_no = pe->pe_number; 62649dec922SGavin Shan } 62749dec922SGavin Shan 62849dec922SGavin Shan /* Check the master PE */ 62949dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 63049dec922SGavin Shan &state, &pcierr, NULL); 63149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63249dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63349dec922SGavin Shan "PHB#%x-PE#%x state\n", 63449dec922SGavin Shan __func__, rc, 63549dec922SGavin Shan phb->hose->global_number, pe_no); 63649dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63749dec922SGavin Shan } 63849dec922SGavin Shan 63949dec922SGavin Shan /* Check the slave PE */ 64049dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 64149dec922SGavin Shan return state; 64249dec922SGavin Shan 64349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64449dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64549dec922SGavin Shan slave->pe_number, 64649dec922SGavin Shan &fstate, 64749dec922SGavin Shan &pcierr, 64849dec922SGavin Shan NULL); 64949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 65049dec922SGavin Shan pr_warn("%s: Failure %lld getting " 65149dec922SGavin Shan "PHB#%x-PE#%x state\n", 65249dec922SGavin Shan __func__, rc, 65349dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65449dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65549dec922SGavin Shan } 65649dec922SGavin Shan 65749dec922SGavin Shan /* 65849dec922SGavin Shan * Override the result based on the ascending 65949dec922SGavin Shan * priority. 66049dec922SGavin Shan */ 66149dec922SGavin Shan if (fstate > state) 66249dec922SGavin Shan state = fstate; 66349dec922SGavin Shan } 66449dec922SGavin Shan 66549dec922SGavin Shan return state; 66649dec922SGavin Shan } 66749dec922SGavin Shan 668a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 669a8d7d5fcSOliver O'Halloran { 670a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn]; 671a8d7d5fcSOliver O'Halloran 672a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE) 673a8d7d5fcSOliver O'Halloran return NULL; 674a8d7d5fcSOliver O'Halloran 675a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number]; 676a8d7d5fcSOliver O'Halloran } 677a8d7d5fcSOliver O'Halloran 678f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 679184cd4a3SBenjamin Herrenschmidt { 6805609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 681b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 682184cd4a3SBenjamin Herrenschmidt 683184cd4a3SBenjamin Herrenschmidt if (!pdn) 684184cd4a3SBenjamin Herrenschmidt return NULL; 685184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 686184cd4a3SBenjamin Herrenschmidt return NULL; 687184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 688184cd4a3SBenjamin Herrenschmidt } 689184cd4a3SBenjamin Herrenschmidt 690b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 691b131a842SGavin Shan struct pnv_ioda_pe *parent, 692b131a842SGavin Shan struct pnv_ioda_pe *child, 693b131a842SGavin Shan bool is_add) 694b131a842SGavin Shan { 695b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 696b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 697b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 698b131a842SGavin Shan struct pnv_ioda_pe *slave; 699b131a842SGavin Shan long rc; 700b131a842SGavin Shan 701b131a842SGavin Shan /* Parent PE affects child PE */ 702b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 703b131a842SGavin Shan child->pe_number, op); 704b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 705b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 706b131a842SGavin Shan rc, desc); 707b131a842SGavin Shan return -ENXIO; 708b131a842SGavin Shan } 709b131a842SGavin Shan 710b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 711b131a842SGavin Shan return 0; 712b131a842SGavin Shan 713b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 714b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 715b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 716b131a842SGavin Shan slave->pe_number, op); 717b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 718b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 719b131a842SGavin Shan rc, desc); 720b131a842SGavin Shan return -ENXIO; 721b131a842SGavin Shan } 722b131a842SGavin Shan } 723b131a842SGavin Shan 724b131a842SGavin Shan return 0; 725b131a842SGavin Shan } 726b131a842SGavin Shan 727b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 728b131a842SGavin Shan struct pnv_ioda_pe *pe, 729b131a842SGavin Shan bool is_add) 730b131a842SGavin Shan { 731b131a842SGavin Shan struct pnv_ioda_pe *slave; 732781a868fSWei Yang struct pci_dev *pdev = NULL; 733b131a842SGavin Shan int ret; 734b131a842SGavin Shan 735b131a842SGavin Shan /* 736b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 737b131a842SGavin Shan * clear slave PE frozen state as well. 738b131a842SGavin Shan */ 739b131a842SGavin Shan if (is_add) { 740b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 741b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 742b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 743b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 744b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 745b131a842SGavin Shan slave->pe_number, 746b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 747b131a842SGavin Shan } 748b131a842SGavin Shan } 749b131a842SGavin Shan 750b131a842SGavin Shan /* 751b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 752b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 753b131a842SGavin Shan * originated from the PE might contribute to other 754b131a842SGavin Shan * PEs. 755b131a842SGavin Shan */ 756b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 757b131a842SGavin Shan if (ret) 758b131a842SGavin Shan return ret; 759b131a842SGavin Shan 760b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 761b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 762b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 763b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 764b131a842SGavin Shan if (ret) 765b131a842SGavin Shan return ret; 766b131a842SGavin Shan } 767b131a842SGavin Shan } 768b131a842SGavin Shan 769b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 770b131a842SGavin Shan pdev = pe->pbus->self; 771781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 772b131a842SGavin Shan pdev = pe->pdev->bus->self; 773781a868fSWei Yang #ifdef CONFIG_PCI_IOV 774781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 775283e2d8aSGavin Shan pdev = pe->parent_dev; 776781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 777b131a842SGavin Shan while (pdev) { 778b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 779b131a842SGavin Shan struct pnv_ioda_pe *parent; 780b131a842SGavin Shan 781b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 782b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 783b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 784b131a842SGavin Shan if (ret) 785b131a842SGavin Shan return ret; 786b131a842SGavin Shan } 787b131a842SGavin Shan 788b131a842SGavin Shan pdev = pdev->bus->self; 789b131a842SGavin Shan } 790b131a842SGavin Shan 791b131a842SGavin Shan return 0; 792b131a842SGavin Shan } 793b131a842SGavin Shan 794f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 795f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 796f724385fSFrederic Barrat struct pci_dev *parent) 797f724385fSFrederic Barrat { 798f724385fSFrederic Barrat int64_t rc; 799f724385fSFrederic Barrat 800f724385fSFrederic Barrat while (parent) { 801f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 802f724385fSFrederic Barrat 803f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 804f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 805f724385fSFrederic Barrat pe->pe_number, 806f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 807f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 808f724385fSFrederic Barrat } 809f724385fSFrederic Barrat parent = parent->bus->self; 810f724385fSFrederic Barrat } 811f724385fSFrederic Barrat 812f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 813f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 814f724385fSFrederic Barrat 815f724385fSFrederic Barrat /* Disassociate PE in PELT */ 816f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 817f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 818f724385fSFrederic Barrat if (rc) 819f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 820f724385fSFrederic Barrat } 821f724385fSFrederic Barrat 82237b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 823781a868fSWei Yang { 824781a868fSWei Yang struct pci_dev *parent; 825781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 826781a868fSWei Yang int64_t rc; 827781a868fSWei Yang long rid_end, rid; 828781a868fSWei Yang 829781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 830781a868fSWei Yang if (pe->pbus) { 831781a868fSWei Yang int count; 832781a868fSWei Yang 833781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 834781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 835781a868fSWei Yang parent = pe->pbus->self; 836781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 837552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 838781a868fSWei Yang else 839781a868fSWei Yang count = 1; 840781a868fSWei Yang 841781a868fSWei Yang switch(count) { 842781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 843781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 844781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 845781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 846781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 847781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 848781a868fSWei Yang default: 849781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 850781a868fSWei Yang count); 851781a868fSWei Yang /* Do an exact match only */ 852781a868fSWei Yang bcomp = OpalPciBusAll; 853781a868fSWei Yang } 854781a868fSWei Yang rid_end = pe->rid + (count << 8); 855781a868fSWei Yang } else { 85693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 857781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 858781a868fSWei Yang parent = pe->parent_dev; 859781a868fSWei Yang else 86093e01a50SGavin Shan #endif 861781a868fSWei Yang parent = pe->pdev->bus->self; 862781a868fSWei Yang bcomp = OpalPciBusAll; 863781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 864781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 865781a868fSWei Yang rid_end = pe->rid + 1; 866781a868fSWei Yang } 867781a868fSWei Yang 868781a868fSWei Yang /* Clear the reverse map */ 869781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 870c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 871781a868fSWei Yang 872f724385fSFrederic Barrat /* 873f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 874f724385fSFrederic Barrat * table 875f724385fSFrederic Barrat */ 876562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI) 877f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 878781a868fSWei Yang 879781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 880781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 881781a868fSWei Yang if (rc) 8821e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 883781a868fSWei Yang 884781a868fSWei Yang pe->pbus = NULL; 885781a868fSWei Yang pe->pdev = NULL; 88693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 887781a868fSWei Yang pe->parent_dev = NULL; 88893e01a50SGavin Shan #endif 889781a868fSWei Yang 890781a868fSWei Yang return 0; 891781a868fSWei Yang } 892781a868fSWei Yang 89337b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 894184cd4a3SBenjamin Herrenschmidt { 895184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 896184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 897184cd4a3SBenjamin Herrenschmidt 898184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 899184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 900184cd4a3SBenjamin Herrenschmidt int count; 901184cd4a3SBenjamin Herrenschmidt 902184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 903184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 904fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 905552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 906fb446ad0SGavin Shan else 907fb446ad0SGavin Shan count = 1; 908fb446ad0SGavin Shan 909184cd4a3SBenjamin Herrenschmidt switch(count) { 910184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 911184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 912184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 913184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 914184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 915184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 916184cd4a3SBenjamin Herrenschmidt default: 917781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 918781a868fSWei Yang count); 919184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 920184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 921184cd4a3SBenjamin Herrenschmidt } 922184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 923184cd4a3SBenjamin Herrenschmidt } else { 924184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 925184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 926184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 927184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 928184cd4a3SBenjamin Herrenschmidt } 929184cd4a3SBenjamin Herrenschmidt 930631ad691SGavin Shan /* 931631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 932631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 933631ad691SGavin Shan * originated from the PE might contribute to other 934631ad691SGavin Shan * PEs. 935631ad691SGavin Shan */ 936184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 937184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 938184cd4a3SBenjamin Herrenschmidt if (rc) { 939184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 940184cd4a3SBenjamin Herrenschmidt return -ENXIO; 941184cd4a3SBenjamin Herrenschmidt } 942631ad691SGavin Shan 9435d2aa710SAlistair Popple /* 9445d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9455d2aa710SAlistair Popple * configuration on them. 9465d2aa710SAlistair Popple */ 947562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI) 948b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 949184cd4a3SBenjamin Herrenschmidt 950184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 951184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 952184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 953184cd4a3SBenjamin Herrenschmidt 954184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9554773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9564773f76bSGavin Shan pe->mve_number = 0; 9574773f76bSGavin Shan goto out; 9584773f76bSGavin Shan } 9594773f76bSGavin Shan 960184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9614773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9624773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9631f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 964184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 965184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 966184cd4a3SBenjamin Herrenschmidt } else { 967184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 968cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 969184cd4a3SBenjamin Herrenschmidt if (rc) { 9701f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 971184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 972184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 973184cd4a3SBenjamin Herrenschmidt } 974184cd4a3SBenjamin Herrenschmidt } 975184cd4a3SBenjamin Herrenschmidt 9764773f76bSGavin Shan out: 977184cd4a3SBenjamin Herrenschmidt return 0; 978184cd4a3SBenjamin Herrenschmidt } 979184cd4a3SBenjamin Herrenschmidt 980cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 981184cd4a3SBenjamin Herrenschmidt { 9825609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 983b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 984184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 985184cd4a3SBenjamin Herrenschmidt 986184cd4a3SBenjamin Herrenschmidt if (!pdn) { 987184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 988184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 989184cd4a3SBenjamin Herrenschmidt return NULL; 990184cd4a3SBenjamin Herrenschmidt } 991184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 992184cd4a3SBenjamin Herrenschmidt return NULL; 993184cd4a3SBenjamin Herrenschmidt 994a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 9951e916772SGavin Shan if (!pe) { 996f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 997184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 998184cd4a3SBenjamin Herrenschmidt return NULL; 999184cd4a3SBenjamin Herrenschmidt } 1000184cd4a3SBenjamin Herrenschmidt 100105dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 100205dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 1003562d1e20SChristoph Hellwig * destroyed at the same time. 1004184cd4a3SBenjamin Herrenschmidt * 1005184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1006184cd4a3SBenjamin Herrenschmidt */ 10071e916772SGavin Shan pdn->pe_number = pe->pe_number; 10085d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1009184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1010184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1011184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1012184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1013f724385fSFrederic Barrat pe->device_count++; 1014184cd4a3SBenjamin Herrenschmidt 1015184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1016184cd4a3SBenjamin Herrenschmidt 1017184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1018184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10191e916772SGavin Shan pnv_ioda_free_pe(pe); 1020184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1021184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1022184cd4a3SBenjamin Herrenschmidt return NULL; 1023184cd4a3SBenjamin Herrenschmidt } 1024184cd4a3SBenjamin Herrenschmidt 10251d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 102680f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 10271d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 102880f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 1029184cd4a3SBenjamin Herrenschmidt return pe; 1030184cd4a3SBenjamin Herrenschmidt } 1031184cd4a3SBenjamin Herrenschmidt 1032fb446ad0SGavin Shan /* 1033fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1034fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1035fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1036fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1037fb446ad0SGavin Shan */ 10381e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1039184cd4a3SBenjamin Herrenschmidt { 10405609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 10411e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1042ccd1c191SGavin Shan unsigned int pe_num; 1043ccd1c191SGavin Shan 1044ccd1c191SGavin Shan /* 1045ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1046ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1047ccd1c191SGavin Shan */ 1048ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 10496ae8aedfSOliver O'Halloran if (WARN_ON(pe_num != IODA_INVALID_PE)) { 1050ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1051ccd1c191SGavin Shan return NULL; 1052ccd1c191SGavin Shan } 1053184cd4a3SBenjamin Herrenschmidt 105463803c39SGavin Shan /* PE number for root bus should have been reserved */ 1055718d249aSOliver O'Halloran if (pci_is_root_bus(bus)) 105663803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 105763803c39SGavin Shan 1058262af557SGuo Chao /* Check if PE is determined by M64 */ 1059a25de7afSAlexey Kardashevskiy if (!pe) 1060a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1061262af557SGuo Chao 1062262af557SGuo Chao /* The PE number isn't pinned by M64 */ 10631e916772SGavin Shan if (!pe) 1064a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 1065262af557SGuo Chao 10661e916772SGavin Shan if (!pe) { 1067f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1068fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 10691e916772SGavin Shan return NULL; 1070184cd4a3SBenjamin Herrenschmidt } 1071184cd4a3SBenjamin Herrenschmidt 1072262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1073184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1074184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1075184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1076b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1077184cd4a3SBenjamin Herrenschmidt 1078fb446ad0SGavin Shan if (all) 10791e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 10801e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 10811e496391SJoe Perches pe->pe_number); 1082fb446ad0SGavin Shan else 10831e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 10841e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1085184cd4a3SBenjamin Herrenschmidt 1086184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1087184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10881e916772SGavin Shan pnv_ioda_free_pe(pe); 1089184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 10901e916772SGavin Shan return NULL; 1091184cd4a3SBenjamin Herrenschmidt } 1092184cd4a3SBenjamin Herrenschmidt 10937ebdf956SGavin Shan /* Put PE to the list */ 10947ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10951e916772SGavin Shan 10961e916772SGavin Shan return pe; 1097184cd4a3SBenjamin Herrenschmidt } 1098184cd4a3SBenjamin Herrenschmidt 109901e12629SOliver O'Halloran static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 110001e12629SOliver O'Halloran struct pnv_ioda_pe *pe); 110101e12629SOliver O'Halloran 11020a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1103184cd4a3SBenjamin Herrenschmidt { 11045609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1105b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1106959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1107184cd4a3SBenjamin Herrenschmidt 1108dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */ 1109dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1110dc3d8f85SOliver O'Halloran if (!pe) { 1111dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1112dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn)) 1113959c9bddSGavin Shan return; 1114184cd4a3SBenjamin Herrenschmidt 1115dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus); 1116dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1117dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1118dc3d8f85SOliver O'Halloran 1119dc3d8f85SOliver O'Halloran 1120dc3d8f85SOliver O'Halloran /* 1121dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly 1122dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device. 1123dc3d8f85SOliver O'Halloran */ 1124dc3d8f85SOliver O'Halloran if (WARN_ON(!pe)) 1125dc3d8f85SOliver O'Halloran return; 1126dc3d8f85SOliver O'Halloran } else { 1127dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1128dc3d8f85SOliver O'Halloran } 1129dc3d8f85SOliver O'Halloran 113001e12629SOliver O'Halloran /* 113101e12629SOliver O'Halloran * We assume that bridges *probably* don't need to do any DMA so we can 113201e12629SOliver O'Halloran * skip allocating a TCE table, etc unless we get a non-bridge device. 113301e12629SOliver O'Halloran */ 113401e12629SOliver O'Halloran if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { 113501e12629SOliver O'Halloran switch (phb->type) { 113601e12629SOliver O'Halloran case PNV_PHB_IODA1: 113701e12629SOliver O'Halloran pnv_pci_ioda1_setup_dma_pe(phb, pe); 113801e12629SOliver O'Halloran break; 113901e12629SOliver O'Halloran case PNV_PHB_IODA2: 114001e12629SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe); 114101e12629SOliver O'Halloran break; 114201e12629SOliver O'Halloran default: 114301e12629SOliver O'Halloran pr_warn("%s: No DMA for PHB#%x (type %d)\n", 114401e12629SOliver O'Halloran __func__, phb->hose->global_number, phb->type); 114501e12629SOliver O'Halloran } 114601e12629SOliver O'Halloran } 114701e12629SOliver O'Halloran 1148dc3d8f85SOliver O'Halloran if (pdn) 1149dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number; 1150dc3d8f85SOliver O'Halloran pe->device_count++; 1151dc3d8f85SOliver O'Halloran 1152cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 11530617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1154b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 115584d8cc07SOliver O'Halloran 115684d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */ 115784d8cc07SOliver O'Halloran if (pe->table_group.group) 115884d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev); 1159184cd4a3SBenjamin Herrenschmidt } 1160184cd4a3SBenjamin Herrenschmidt 11618e3f1b1dSRussell Currey /* 11628e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 11638e3f1b1dSRussell Currey * 11648e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 11658e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 11668e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 11678e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 11688e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 11698e3f1b1dSRussell Currey * devices in TVE#0. 11708e3f1b1dSRussell Currey * 11718e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 11728e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 11738e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 11748e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 11758e3f1b1dSRussell Currey * 11768e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 11778e3f1b1dSRussell Currey */ 11788e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 11798e3f1b1dSRussell Currey { 11808e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 11818e3f1b1dSRussell Currey struct page *table_pages; 11828e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 11838e3f1b1dSRussell Currey __be64 *tces; 11848e3f1b1dSRussell Currey s64 rc; 11858e3f1b1dSRussell Currey 11868e3f1b1dSRussell Currey /* 11878e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 11888e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 11898e3f1b1dSRussell Currey */ 11908e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 11918e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 11928e3f1b1dSRussell Currey table_size = tce_count << 3; 11938e3f1b1dSRussell Currey 11948e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 11958e3f1b1dSRussell Currey table_size = PAGE_SIZE; 11968e3f1b1dSRussell Currey 11978e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 11988e3f1b1dSRussell Currey get_order(table_size)); 11998e3f1b1dSRussell Currey if (!table_pages) 12008e3f1b1dSRussell Currey goto err; 12018e3f1b1dSRussell Currey 12028e3f1b1dSRussell Currey tces = page_address(table_pages); 12038e3f1b1dSRussell Currey if (!tces) 12048e3f1b1dSRussell Currey goto err; 12058e3f1b1dSRussell Currey 12068e3f1b1dSRussell Currey memset(tces, 0, table_size); 12078e3f1b1dSRussell Currey 12088e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 12098e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 12108e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 12118e3f1b1dSRussell Currey } 12128e3f1b1dSRussell Currey 12138e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 12148e3f1b1dSRussell Currey pe->pe_number, 12158e3f1b1dSRussell Currey /* reconfigure window 0 */ 12168e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 12178e3f1b1dSRussell Currey 1, 12188e3f1b1dSRussell Currey __pa(tces), 12198e3f1b1dSRussell Currey table_size, 12208e3f1b1dSRussell Currey 1 << tce_order); 12218e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 12228e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 12238e3f1b1dSRussell Currey return 0; 12248e3f1b1dSRussell Currey } 12258e3f1b1dSRussell Currey err: 12268e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 12278e3f1b1dSRussell Currey return -EIO; 12288e3f1b1dSRussell Currey } 12298e3f1b1dSRussell Currey 12302d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 12312d6ad41bSChristoph Hellwig u64 dma_mask) 1232cd15b048SBenjamin Herrenschmidt { 12335609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1234cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1235cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1236cd15b048SBenjamin Herrenschmidt 1237cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1238b511cdd1SAlexey Kardashevskiy return false; 1239cd15b048SBenjamin Herrenschmidt 1240cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1241cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 12422d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 12432d6ad41bSChristoph Hellwig if (dma_mask >= top) 12442d6ad41bSChristoph Hellwig return true; 1245cd15b048SBenjamin Herrenschmidt } 1246cd15b048SBenjamin Herrenschmidt 12478e3f1b1dSRussell Currey /* 12488e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 12498e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 12508e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 12518e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 12528e3f1b1dSRussell Currey */ 12538e3f1b1dSRussell Currey if (dma_mask >> 32 && 12548e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1255661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1256661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 12578e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 12588e3f1b1dSRussell Currey /* Configure the bypass mode */ 12592d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 12608e3f1b1dSRussell Currey if (rc) 1261b511cdd1SAlexey Kardashevskiy return false; 12628e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 12630617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 12642d6ad41bSChristoph Hellwig return true; 1265cd15b048SBenjamin Herrenschmidt } 1266cd15b048SBenjamin Herrenschmidt 12672d6ad41bSChristoph Hellwig return false; 1268fe7e85c6SGavin Shan } 1269fe7e85c6SGavin Shan 1270fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1271fd141d1aSBenjamin Herrenschmidt bool real_mode) 1272fd141d1aSBenjamin Herrenschmidt { 1273fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1274fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1275fd141d1aSBenjamin Herrenschmidt } 1276fd141d1aSBenjamin Herrenschmidt 1277a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1278decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 12794cce9550SGavin Shan { 12800eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 12810eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 12820eaf4defSAlexey Kardashevskiy next); 12830eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1284b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1285fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 12864cce9550SGavin Shan unsigned long start, end, inc; 12874cce9550SGavin Shan 1288decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1289decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1290decbda25SAlexey Kardashevskiy npages - 1); 12914cce9550SGavin Shan 12924cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 12934cce9550SGavin Shan start |= (1ull << 63); 12944cce9550SGavin Shan end |= (1ull << 63); 12954cce9550SGavin Shan inc = 16; 12964cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 12974cce9550SGavin Shan 12984cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 12994cce9550SGavin Shan while (start <= end) { 13008e0a1611SAlexey Kardashevskiy if (rm) 1301001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 13028e0a1611SAlexey Kardashevskiy else 1303001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1304001ff2eeSMichael Ellerman 13054cce9550SGavin Shan start += inc; 13064cce9550SGavin Shan } 13074cce9550SGavin Shan 13084cce9550SGavin Shan /* 13094cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 13104cce9550SGavin Shan * and we don't care on free() 13114cce9550SGavin Shan */ 13124cce9550SGavin Shan } 13134cce9550SGavin Shan 1314decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1315decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1316decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 131700085f1eSKrzysztof Kozlowski unsigned long attrs) 1318decbda25SAlexey Kardashevskiy { 1319decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1320decbda25SAlexey Kardashevskiy attrs); 1321decbda25SAlexey Kardashevskiy 132208acce1cSBenjamin Herrenschmidt if (!ret) 1323a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1324decbda25SAlexey Kardashevskiy 1325decbda25SAlexey Kardashevskiy return ret; 1326decbda25SAlexey Kardashevskiy } 1327decbda25SAlexey Kardashevskiy 132805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 132935872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 133035872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 133135872480SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 133235872480SAlexey Kardashevskiy bool realmode) 133305c6cfb9SAlexey Kardashevskiy { 133435872480SAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1335a540aa56SAlexey Kardashevskiy } 133605c6cfb9SAlexey Kardashevskiy #endif 133705c6cfb9SAlexey Kardashevskiy 1338decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1339decbda25SAlexey Kardashevskiy long npages) 1340decbda25SAlexey Kardashevskiy { 1341decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1342decbda25SAlexey Kardashevskiy 1343a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1344decbda25SAlexey Kardashevskiy } 1345decbda25SAlexey Kardashevskiy 1346da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1347decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 134805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 134935872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 135035872480SAlexey Kardashevskiy .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1351090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 135205c6cfb9SAlexey Kardashevskiy #endif 1353decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1354da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1355da004c36SAlexey Kardashevskiy }; 1356da004c36SAlexey Kardashevskiy 1357a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1358a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1359a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1360bef9253fSAlexey Kardashevskiy 1361a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 13625780fb04SAlexey Kardashevskiy { 13635780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1364fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1365a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 13665780fb04SAlexey Kardashevskiy 13675780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1368001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 13695780fb04SAlexey Kardashevskiy } 13705780fb04SAlexey Kardashevskiy 1371fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1372fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1373fd141d1aSBenjamin Herrenschmidt unsigned long npages) 13744cce9550SGavin Shan { 13754d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 13764cce9550SGavin Shan unsigned long start, end, inc; 13774cce9550SGavin Shan 13784cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1379a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1380fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 13814cce9550SGavin Shan end = start; 13824cce9550SGavin Shan 13834cce9550SGavin Shan /* Figure out the start, end and step */ 1384decbda25SAlexey Kardashevskiy start |= (index << shift); 1385decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1386b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 13874cce9550SGavin Shan mb(); 13884cce9550SGavin Shan 13894cce9550SGavin Shan while (start <= end) { 13908e0a1611SAlexey Kardashevskiy if (rm) 1391001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 13928e0a1611SAlexey Kardashevskiy else 1393001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 13944cce9550SGavin Shan start += inc; 13954cce9550SGavin Shan } 13964cce9550SGavin Shan } 13974cce9550SGavin Shan 1398f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1399f0228c41SBenjamin Herrenschmidt { 1400f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1401f0228c41SBenjamin Herrenschmidt 1402f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1403f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1404f0228c41SBenjamin Herrenschmidt else 1405f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1406f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1407f0228c41SBenjamin Herrenschmidt } 1408f0228c41SBenjamin Herrenschmidt 1409e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1410e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1411e57080f1SAlexey Kardashevskiy { 1412e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1413e57080f1SAlexey Kardashevskiy 1414a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1415e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1416e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1417f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1418f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1419f0228c41SBenjamin Herrenschmidt 1420f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1421f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 142285674868SAlexey Kardashevskiy index, npages); 1423f0228c41SBenjamin Herrenschmidt else 1424f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 1425f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1426f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1427f0228c41SBenjamin Herrenschmidt index << shift, npages); 1428e57080f1SAlexey Kardashevskiy } 1429e57080f1SAlexey Kardashevskiy } 1430e57080f1SAlexey Kardashevskiy 1431decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1432decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1433decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 143400085f1eSKrzysztof Kozlowski unsigned long attrs) 14354cce9550SGavin Shan { 1436decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1437decbda25SAlexey Kardashevskiy attrs); 14384cce9550SGavin Shan 143908acce1cSBenjamin Herrenschmidt if (!ret) 1440decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1441decbda25SAlexey Kardashevskiy 1442decbda25SAlexey Kardashevskiy return ret; 1443decbda25SAlexey Kardashevskiy } 1444decbda25SAlexey Kardashevskiy 1445decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1446decbda25SAlexey Kardashevskiy long npages) 1447decbda25SAlexey Kardashevskiy { 1448decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1449decbda25SAlexey Kardashevskiy 1450decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 14514cce9550SGavin Shan } 14524cce9550SGavin Shan 1453da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1454decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 145505c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 145635872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 145735872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 1458090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 145905c6cfb9SAlexey Kardashevskiy #endif 1460decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1461da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1462da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 1463da004c36SAlexey Kardashevskiy }; 1464da004c36SAlexey Kardashevskiy 1465801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1466801846d1SGavin Shan { 1467801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1468801846d1SGavin Shan 1469801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1470801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1471801846d1SGavin Shan */ 1472801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1473801846d1SGavin Shan return 0; 1474801846d1SGavin Shan 1475801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1476801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1477801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1478801846d1SGavin Shan *weight += 3; 1479801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1480801846d1SGavin Shan *weight += 15; 1481801846d1SGavin Shan else 1482801846d1SGavin Shan *weight += 10; 1483801846d1SGavin Shan 1484801846d1SGavin Shan return 0; 1485801846d1SGavin Shan } 1486801846d1SGavin Shan 1487801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1488801846d1SGavin Shan { 1489801846d1SGavin Shan unsigned int weight = 0; 1490801846d1SGavin Shan 1491801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 1492801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 1493801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1494801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1495801846d1SGavin Shan return weight; 1496801846d1SGavin Shan } 1497801846d1SGavin Shan #endif 1498801846d1SGavin Shan 1499801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1500801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1501801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1502801846d1SGavin Shan struct pci_dev *pdev; 1503801846d1SGavin Shan 1504801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1505801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1506801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1507801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1508801846d1SGavin Shan } 1509801846d1SGavin Shan 1510801846d1SGavin Shan return weight; 1511801846d1SGavin Shan } 1512801846d1SGavin Shan 1513b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 15142b923ed1SGavin Shan struct pnv_ioda_pe *pe) 1515184cd4a3SBenjamin Herrenschmidt { 1516184cd4a3SBenjamin Herrenschmidt 1517184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1518184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 15192b923ed1SGavin Shan unsigned int weight, total_weight = 0; 15202b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 1521184cd4a3SBenjamin Herrenschmidt int64_t rc; 1522184cd4a3SBenjamin Herrenschmidt void *addr; 1523184cd4a3SBenjamin Herrenschmidt 1524184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1525184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1526184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 15272b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 15282b923ed1SGavin Shan if (!weight) 15292b923ed1SGavin Shan return; 1530184cd4a3SBenjamin Herrenschmidt 15312b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 15322b923ed1SGavin Shan &total_weight); 15332b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 15342b923ed1SGavin Shan if (!segs) 15352b923ed1SGavin Shan segs = 1; 15362b923ed1SGavin Shan 15372b923ed1SGavin Shan /* 15382b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 15392b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 15402b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 15412b923ed1SGavin Shan * is allocated successfully. 15422b923ed1SGavin Shan */ 15432b923ed1SGavin Shan do { 15442b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 15452b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 15462b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 15472b923ed1SGavin Shan IODA_INVALID_PE) 15482b923ed1SGavin Shan avail++; 15492b923ed1SGavin Shan } 15502b923ed1SGavin Shan 15512b923ed1SGavin Shan if (avail == segs) 15522b923ed1SGavin Shan goto found; 15532b923ed1SGavin Shan } 15542b923ed1SGavin Shan } while (--segs); 15552b923ed1SGavin Shan 15562b923ed1SGavin Shan if (!segs) { 15572b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 15582b923ed1SGavin Shan return; 15592b923ed1SGavin Shan } 15602b923ed1SGavin Shan 15612b923ed1SGavin Shan found: 15620eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 156382eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 156482eae1afSAlexey Kardashevskiy return; 156582eae1afSAlexey Kardashevskiy 1566b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1567b348aa65SAlexey Kardashevskiy pe->pe_number); 15680eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1569c5773822SAlexey Kardashevskiy 1570184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 15712b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 15722b923ed1SGavin Shan weight, total_weight, base, segs); 1573184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1574acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1575acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 1576184cd4a3SBenjamin Herrenschmidt 1577184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1578184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1579184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1580184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1581acce971cSGavin Shan * 1582acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 1583acce971cSGavin Shan * bytes 1584184cd4a3SBenjamin Herrenschmidt */ 1585acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 1586184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1587acce971cSGavin Shan get_order(tce32_segsz * segs)); 1588184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1589184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1590184cd4a3SBenjamin Herrenschmidt goto fail; 1591184cd4a3SBenjamin Herrenschmidt } 1592184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1593acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 1594184cd4a3SBenjamin Herrenschmidt 1595184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1596184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1597184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1598184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1599184cd4a3SBenjamin Herrenschmidt base + i, 1, 1600acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 1601acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 1602184cd4a3SBenjamin Herrenschmidt if (rc) { 16031e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 16041e496391SJoe Perches rc); 1605184cd4a3SBenjamin Herrenschmidt goto fail; 1606184cd4a3SBenjamin Herrenschmidt } 1607184cd4a3SBenjamin Herrenschmidt } 1608184cd4a3SBenjamin Herrenschmidt 16092b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 16102b923ed1SGavin Shan for (i = base; i < base + segs; i++) 16112b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 16122b923ed1SGavin Shan 1613184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1614acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 1615acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1616acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 1617184cd4a3SBenjamin Herrenschmidt 1618da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 16194793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 16204793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 16214be518d8SAlexey Kardashevskiy if (!iommu_init_table(tbl, phb->hose->node, 0, 0)) 16224be518d8SAlexey Kardashevskiy panic("Failed to initialize iommu table"); 1623184cd4a3SBenjamin Herrenschmidt 162401e12629SOliver O'Halloran pe->dma_setup_done = true; 1625184cd4a3SBenjamin Herrenschmidt return; 1626184cd4a3SBenjamin Herrenschmidt fail: 1627184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1628184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1629acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 16300eaf4defSAlexey Kardashevskiy if (tbl) { 16310eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 1632e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 16330eaf4defSAlexey Kardashevskiy } 1634184cd4a3SBenjamin Herrenschmidt } 1635184cd4a3SBenjamin Herrenschmidt 163643cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 163743cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 163843cb60abSAlexey Kardashevskiy { 163943cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 164043cb60abSAlexey Kardashevskiy table_group); 164143cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 164243cb60abSAlexey Kardashevskiy int64_t rc; 1643bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1644bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 164543cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 164643cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 164743cb60abSAlexey Kardashevskiy 16481e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 16491e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 165043cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 165143cb60abSAlexey Kardashevskiy 165243cb60abSAlexey Kardashevskiy /* 165343cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 165443cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 165543cb60abSAlexey Kardashevskiy */ 165643cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 165743cb60abSAlexey Kardashevskiy pe->pe_number, 16584793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 1659bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 166043cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 1661bbb845c4SAlexey Kardashevskiy size << 3, 166243cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 166343cb60abSAlexey Kardashevskiy if (rc) { 16641e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 166543cb60abSAlexey Kardashevskiy return rc; 166643cb60abSAlexey Kardashevskiy } 166743cb60abSAlexey Kardashevskiy 166843cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 166943cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 1670ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 167143cb60abSAlexey Kardashevskiy 167243cb60abSAlexey Kardashevskiy return 0; 167343cb60abSAlexey Kardashevskiy } 167443cb60abSAlexey Kardashevskiy 1675c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1676cd15b048SBenjamin Herrenschmidt { 1677cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1678cd15b048SBenjamin Herrenschmidt int64_t rc; 1679cd15b048SBenjamin Herrenschmidt 1680cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1681cd15b048SBenjamin Herrenschmidt if (enable) { 1682cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1683cd15b048SBenjamin Herrenschmidt 1684cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1685cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1686cd15b048SBenjamin Herrenschmidt pe->pe_number, 1687cd15b048SBenjamin Herrenschmidt window_id, 1688cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1689cd15b048SBenjamin Herrenschmidt top); 1690cd15b048SBenjamin Herrenschmidt } else { 1691cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1692cd15b048SBenjamin Herrenschmidt pe->pe_number, 1693cd15b048SBenjamin Herrenschmidt window_id, 1694cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1695cd15b048SBenjamin Herrenschmidt 0); 1696cd15b048SBenjamin Herrenschmidt } 1697cd15b048SBenjamin Herrenschmidt if (rc) 1698cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1699cd15b048SBenjamin Herrenschmidt else 1700cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1701cd15b048SBenjamin Herrenschmidt } 1702cd15b048SBenjamin Herrenschmidt 17034793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 17044793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1705090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 17064793d65dSAlexey Kardashevskiy { 17074793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 17084793d65dSAlexey Kardashevskiy table_group); 17094793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 17104793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 17114793d65dSAlexey Kardashevskiy long ret; 17124793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 17134793d65dSAlexey Kardashevskiy 17144793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 17154793d65dSAlexey Kardashevskiy if (!tbl) 17164793d65dSAlexey Kardashevskiy return -ENOMEM; 17174793d65dSAlexey Kardashevskiy 171811edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 171911edf116SAlexey Kardashevskiy 17204793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 17214793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 1722090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 17234793d65dSAlexey Kardashevskiy if (ret) { 1724e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 17254793d65dSAlexey Kardashevskiy return ret; 17264793d65dSAlexey Kardashevskiy } 17274793d65dSAlexey Kardashevskiy 17284793d65dSAlexey Kardashevskiy *ptbl = tbl; 17294793d65dSAlexey Kardashevskiy 17304793d65dSAlexey Kardashevskiy return 0; 17314793d65dSAlexey Kardashevskiy } 17324793d65dSAlexey Kardashevskiy 173346d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 173446d3e1e1SAlexey Kardashevskiy { 173546d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 173646d3e1e1SAlexey Kardashevskiy long rc; 1737201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 173846d3e1e1SAlexey Kardashevskiy 1739bb005455SNishanth Aravamudan /* 1740fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 1741fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 1742fa144869SNishanth Aravamudan * of 2, which will cause errors later. 1743fa144869SNishanth Aravamudan */ 1744fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 1745fa144869SNishanth Aravamudan 1746fa144869SNishanth Aravamudan /* 1747bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 1748bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 1749bb005455SNishanth Aravamudan * cause errors later. 1750bb005455SNishanth Aravamudan */ 1751201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 1752bb005455SNishanth Aravamudan 1753201ed7f3SAlexey Kardashevskiy /* 1754201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 1755201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 1756201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 1757201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 1758201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 1759201ed7f3SAlexey Kardashevskiy */ 1760201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 1761201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 1762201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 1763201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 1764201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 1765201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 1766201ed7f3SAlexey Kardashevskiy 1767201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 1768201ed7f3SAlexey Kardashevskiy levels += 1; 1769201ed7f3SAlexey Kardashevskiy /* 1770201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 1771201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 1772201ed7f3SAlexey Kardashevskiy */ 1773201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 1774201ed7f3SAlexey Kardashevskiy 1775201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 1776201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 177746d3e1e1SAlexey Kardashevskiy if (rc) { 177846d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 177946d3e1e1SAlexey Kardashevskiy rc); 178046d3e1e1SAlexey Kardashevskiy return rc; 178146d3e1e1SAlexey Kardashevskiy } 178246d3e1e1SAlexey Kardashevskiy 1783201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 1784201ed7f3SAlexey Kardashevskiy res_start = 0; 1785201ed7f3SAlexey Kardashevskiy res_end = 0; 1786201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 1787201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 1788201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 1789201ed7f3SAlexey Kardashevskiy } 179046d3e1e1SAlexey Kardashevskiy 17914be518d8SAlexey Kardashevskiy if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) 179246d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 17934be518d8SAlexey Kardashevskiy else 17944be518d8SAlexey Kardashevskiy rc = -ENOMEM; 179546d3e1e1SAlexey Kardashevskiy if (rc) { 17964be518d8SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); 1797e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 17984be518d8SAlexey Kardashevskiy tbl = NULL; /* This clears iommu_table_base below */ 179946d3e1e1SAlexey Kardashevskiy } 180046d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 180146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 180246d3e1e1SAlexey Kardashevskiy 18035636427dSAlexey Kardashevskiy /* 18045636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 18055636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 18065636427dSAlexey Kardashevskiy * from VFIO so do it here. 18075636427dSAlexey Kardashevskiy */ 18085636427dSAlexey Kardashevskiy if (pe->pdev) 18095636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 18105636427dSAlexey Kardashevskiy 181146d3e1e1SAlexey Kardashevskiy return 0; 181246d3e1e1SAlexey Kardashevskiy } 181346d3e1e1SAlexey Kardashevskiy 1814b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1815b5926430SAlexey Kardashevskiy int num) 1816b5926430SAlexey Kardashevskiy { 1817b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1818b5926430SAlexey Kardashevskiy table_group); 1819b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 1820b5926430SAlexey Kardashevskiy long ret; 1821b5926430SAlexey Kardashevskiy 1822b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 1823b5926430SAlexey Kardashevskiy 1824b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1825b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 1826b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 1827b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 1828b5926430SAlexey Kardashevskiy if (ret) 1829b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 1830b5926430SAlexey Kardashevskiy else 1831ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 1832b5926430SAlexey Kardashevskiy 1833b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 1834b5926430SAlexey Kardashevskiy 1835b5926430SAlexey Kardashevskiy return ret; 1836b5926430SAlexey Kardashevskiy } 1837b5926430SAlexey Kardashevskiy 1838f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 18390bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 184000547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 184100547193SAlexey Kardashevskiy { 184200547193SAlexey Kardashevskiy unsigned long bytes = 0; 184300547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 184400547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 184500547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 184600547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 184700547193SAlexey Kardashevskiy unsigned long direct_table_size; 184800547193SAlexey Kardashevskiy 184900547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 185000547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 185100547193SAlexey Kardashevskiy return 0; 185200547193SAlexey Kardashevskiy 185300547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 185400547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 185500547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 185600547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 185700547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 185800547193SAlexey Kardashevskiy 185900547193SAlexey Kardashevskiy for ( ; levels; --levels) { 1860b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 186100547193SAlexey Kardashevskiy 186200547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 186300547193SAlexey Kardashevskiy tce_table_size <<= 3; 1864e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 1865e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 186600547193SAlexey Kardashevskiy } 186700547193SAlexey Kardashevskiy 1868090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 1869090bad39SAlexey Kardashevskiy } 1870090bad39SAlexey Kardashevskiy 1871090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 1872090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 1873090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1874090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 1875090bad39SAlexey Kardashevskiy { 187611f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 1877090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 187811f5acceSAlexey Kardashevskiy 187911f5acceSAlexey Kardashevskiy if (!ret) 188011f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 188111f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 188211f5acceSAlexey Kardashevskiy return ret; 188300547193SAlexey Kardashevskiy } 188400547193SAlexey Kardashevskiy 1885e3417faeSOliver O'Halloran static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 1886e3417faeSOliver O'Halloran { 1887e3417faeSOliver O'Halloran struct pci_dev *dev; 1888e3417faeSOliver O'Halloran 1889e3417faeSOliver O'Halloran list_for_each_entry(dev, &bus->devices, bus_list) { 1890e3417faeSOliver O'Halloran set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1891e3417faeSOliver O'Halloran dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1892e3417faeSOliver O'Halloran 1893e3417faeSOliver O'Halloran if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1894e3417faeSOliver O'Halloran pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1895e3417faeSOliver O'Halloran } 1896e3417faeSOliver O'Halloran } 1897e3417faeSOliver O'Halloran 1898f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 1899cd15b048SBenjamin Herrenschmidt { 1900f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1901f87a8864SAlexey Kardashevskiy table_group); 190246d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 190346d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 1904cd15b048SBenjamin Herrenschmidt 1905f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 190646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1907db08e1d5SAlexey Kardashevskiy if (pe->pbus) 19085eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 19095636427dSAlexey Kardashevskiy else if (pe->pdev) 19105636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 1911e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1912cd15b048SBenjamin Herrenschmidt } 1913cd15b048SBenjamin Herrenschmidt 1914f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 1915f87a8864SAlexey Kardashevskiy { 1916f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1917f87a8864SAlexey Kardashevskiy table_group); 1918f87a8864SAlexey Kardashevskiy 191946d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 1920db08e1d5SAlexey Kardashevskiy if (pe->pbus) 19215eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 1922f87a8864SAlexey Kardashevskiy } 1923f87a8864SAlexey Kardashevskiy 1924f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 192500547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 1926090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 19274793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 19284793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 1929f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 1930f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 1931f87a8864SAlexey Kardashevskiy }; 1932f87a8864SAlexey Kardashevskiy #endif 1933f87a8864SAlexey Kardashevskiy 193437b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1935373f5657SGavin Shan struct pnv_ioda_pe *pe) 1936373f5657SGavin Shan { 1937373f5657SGavin Shan int64_t rc; 1938373f5657SGavin Shan 1939f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 1940f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 1941f87a8864SAlexey Kardashevskiy 1942373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1943373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1944aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 1945373f5657SGavin Shan 1946e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 19474793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 19484793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 19494793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 19504793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 19514793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 19527ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 1953e5aad1e6SAlexey Kardashevskiy 195446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 1955801846d1SGavin Shan if (rc) 195646d3e1e1SAlexey Kardashevskiy return; 195746d3e1e1SAlexey Kardashevskiy 19589b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 19599b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 19609b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 19619b9408c5SOliver O'Halloran pe->pe_number); 19629b9408c5SOliver O'Halloran #endif 196301e12629SOliver O'Halloran pe->dma_setup_done = true; 1964373f5657SGavin Shan } 1965373f5657SGavin Shan 19664ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 1967137436c9SGavin Shan { 1968137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 1969137436c9SGavin Shan ioda.irq_chip); 1970137436c9SGavin Shan 19714ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 19724ee11c1aSSuresh Warrier } 19734ee11c1aSSuresh Warrier 19744ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 19754ee11c1aSSuresh Warrier { 19764ee11c1aSSuresh Warrier int64_t rc; 19774ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 19784ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 19794ee11c1aSSuresh Warrier 19804ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 1981137436c9SGavin Shan WARN_ON_ONCE(rc); 1982137436c9SGavin Shan 1983137436c9SGavin Shan icp_native_eoi(d); 1984137436c9SGavin Shan } 1985137436c9SGavin Shan 1986fd9a1c26SIan Munsie 1987f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 1988fd9a1c26SIan Munsie { 1989fd9a1c26SIan Munsie struct irq_data *idata; 1990fd9a1c26SIan Munsie struct irq_chip *ichip; 1991fd9a1c26SIan Munsie 1992fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 1993fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 1994fd9a1c26SIan Munsie return; 1995fd9a1c26SIan Munsie 1996fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 1997fd9a1c26SIan Munsie /* 1998fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 1999fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2000fd9a1c26SIan Munsie */ 2001fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2002fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2003fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2004fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2005fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2006fd9a1c26SIan Munsie } 2007fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2008fd9a1c26SIan Munsie } 2009fd9a1c26SIan Munsie 20104ee11c1aSSuresh Warrier /* 20114ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 20124ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 20134ee11c1aSSuresh Warrier */ 20144ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 20154ee11c1aSSuresh Warrier { 20164ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 20174ee11c1aSSuresh Warrier } 20184ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 20194ee11c1aSSuresh Warrier 20202c50d7e9SCédric Le Goater static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 20212c50d7e9SCédric Le Goater unsigned int xive_num, 2022137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2023184cd4a3SBenjamin Herrenschmidt { 2024184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 20253a1a4661SBenjamin Herrenschmidt __be32 data; 2026184cd4a3SBenjamin Herrenschmidt int rc; 2027184cd4a3SBenjamin Herrenschmidt 20282c50d7e9SCédric Le Goater dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__, 20292c50d7e9SCédric Le Goater is_64 ? "64" : "32", xive_num); 20302c50d7e9SCédric Le Goater 2031184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2032184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2033184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2034184cd4a3SBenjamin Herrenschmidt 2035184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2036184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2037184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2038184cd4a3SBenjamin Herrenschmidt 2039b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 204036074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2041b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2042b72c1f65SBenjamin Herrenschmidt 2043184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2044184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2045184cd4a3SBenjamin Herrenschmidt if (rc) { 2046184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2047184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2048184cd4a3SBenjamin Herrenschmidt return -EIO; 2049184cd4a3SBenjamin Herrenschmidt } 2050184cd4a3SBenjamin Herrenschmidt 2051184cd4a3SBenjamin Herrenschmidt if (is_64) { 20523a1a4661SBenjamin Herrenschmidt __be64 addr64; 20533a1a4661SBenjamin Herrenschmidt 2054184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2055184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2056184cd4a3SBenjamin Herrenschmidt if (rc) { 2057184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2058184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2059184cd4a3SBenjamin Herrenschmidt return -EIO; 2060184cd4a3SBenjamin Herrenschmidt } 20613a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 20623a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2063184cd4a3SBenjamin Herrenschmidt } else { 20643a1a4661SBenjamin Herrenschmidt __be32 addr32; 20653a1a4661SBenjamin Herrenschmidt 2066184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2067184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2068184cd4a3SBenjamin Herrenschmidt if (rc) { 2069184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2070184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2071184cd4a3SBenjamin Herrenschmidt return -EIO; 2072184cd4a3SBenjamin Herrenschmidt } 2073184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 20743a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2075184cd4a3SBenjamin Herrenschmidt } 20763a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2077184cd4a3SBenjamin Herrenschmidt 20782c50d7e9SCédric Le Goater return 0; 20792c50d7e9SCédric Le Goater } 20802c50d7e9SCédric Le Goater 20812c50d7e9SCédric Le Goater static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 20822c50d7e9SCédric Le Goater unsigned int hwirq, unsigned int virq, 20832c50d7e9SCédric Le Goater unsigned int is_64, struct msi_msg *msg) 20842c50d7e9SCédric Le Goater { 20852c50d7e9SCédric Le Goater struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 20862c50d7e9SCédric Le Goater unsigned int xive_num = hwirq - phb->msi_base; 20872c50d7e9SCédric Le Goater int rc; 20882c50d7e9SCédric Le Goater 20892c50d7e9SCédric Le Goater rc = __pnv_pci_ioda_msi_setup(phb, dev, xive_num, is_64, msg); 20902c50d7e9SCédric Le Goater if (rc) 20912c50d7e9SCédric Le Goater return rc; 20922c50d7e9SCédric Le Goater 20932c50d7e9SCédric Le Goater /* P8 only */ 2094f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2095137436c9SGavin Shan 2096184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 20971f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2098184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 20992c50d7e9SCédric Le Goater msg->address_hi, msg->address_lo, msg->data, pe->pe_number); 2100184cd4a3SBenjamin Herrenschmidt 2101184cd4a3SBenjamin Herrenschmidt return 0; 2102184cd4a3SBenjamin Herrenschmidt } 2103184cd4a3SBenjamin Herrenschmidt 2104*0fcfe224SCédric Le Goater /* 2105*0fcfe224SCédric Le Goater * The msi_free() op is called before irq_domain_free_irqs_top() when 2106*0fcfe224SCédric Le Goater * the handler data is still available. Use that to clear the XIVE 2107*0fcfe224SCédric Le Goater * controller. 2108*0fcfe224SCédric Le Goater */ 2109*0fcfe224SCédric Le Goater static void pnv_msi_ops_msi_free(struct irq_domain *domain, 2110*0fcfe224SCédric Le Goater struct msi_domain_info *info, 2111*0fcfe224SCédric Le Goater unsigned int irq) 2112*0fcfe224SCédric Le Goater { 2113*0fcfe224SCédric Le Goater if (xive_enabled()) 2114*0fcfe224SCédric Le Goater xive_irq_free_data(irq); 2115*0fcfe224SCédric Le Goater } 2116*0fcfe224SCédric Le Goater 2117*0fcfe224SCédric Le Goater static struct msi_domain_ops pnv_pci_msi_domain_ops = { 2118*0fcfe224SCédric Le Goater .msi_free = pnv_msi_ops_msi_free, 2119*0fcfe224SCédric Le Goater }; 2120*0fcfe224SCédric Le Goater 2121*0fcfe224SCédric Le Goater static void pnv_msi_shutdown(struct irq_data *d) 2122*0fcfe224SCédric Le Goater { 2123*0fcfe224SCédric Le Goater d = d->parent_data; 2124*0fcfe224SCédric Le Goater if (d->chip->irq_shutdown) 2125*0fcfe224SCédric Le Goater d->chip->irq_shutdown(d); 2126*0fcfe224SCédric Le Goater } 2127*0fcfe224SCédric Le Goater 2128*0fcfe224SCédric Le Goater static void pnv_msi_mask(struct irq_data *d) 2129*0fcfe224SCédric Le Goater { 2130*0fcfe224SCédric Le Goater pci_msi_mask_irq(d); 2131*0fcfe224SCédric Le Goater irq_chip_mask_parent(d); 2132*0fcfe224SCédric Le Goater } 2133*0fcfe224SCédric Le Goater 2134*0fcfe224SCédric Le Goater static void pnv_msi_unmask(struct irq_data *d) 2135*0fcfe224SCédric Le Goater { 2136*0fcfe224SCédric Le Goater pci_msi_unmask_irq(d); 2137*0fcfe224SCédric Le Goater irq_chip_unmask_parent(d); 2138*0fcfe224SCédric Le Goater } 2139*0fcfe224SCédric Le Goater 2140*0fcfe224SCédric Le Goater static struct irq_chip pnv_pci_msi_irq_chip = { 2141*0fcfe224SCédric Le Goater .name = "PNV-PCI-MSI", 2142*0fcfe224SCédric Le Goater .irq_shutdown = pnv_msi_shutdown, 2143*0fcfe224SCédric Le Goater .irq_mask = pnv_msi_mask, 2144*0fcfe224SCédric Le Goater .irq_unmask = pnv_msi_unmask, 2145*0fcfe224SCédric Le Goater .irq_eoi = irq_chip_eoi_parent, 2146*0fcfe224SCédric Le Goater }; 2147*0fcfe224SCédric Le Goater 2148*0fcfe224SCédric Le Goater static struct msi_domain_info pnv_msi_domain_info = { 2149*0fcfe224SCédric Le Goater .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 2150*0fcfe224SCédric Le Goater MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), 2151*0fcfe224SCédric Le Goater .ops = &pnv_pci_msi_domain_ops, 2152*0fcfe224SCédric Le Goater .chip = &pnv_pci_msi_irq_chip, 2153*0fcfe224SCédric Le Goater }; 2154*0fcfe224SCédric Le Goater 2155*0fcfe224SCédric Le Goater static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg) 2156*0fcfe224SCédric Le Goater { 2157*0fcfe224SCédric Le Goater struct msi_desc *entry = irq_data_get_msi_desc(d); 2158*0fcfe224SCédric Le Goater struct pci_dev *pdev = msi_desc_to_pci_dev(entry); 2159*0fcfe224SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2160*0fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 2161*0fcfe224SCédric Le Goater int rc; 2162*0fcfe224SCédric Le Goater 2163*0fcfe224SCédric Le Goater rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq, 2164*0fcfe224SCédric Le Goater entry->msi_attrib.is_64, msg); 2165*0fcfe224SCédric Le Goater if (rc) 2166*0fcfe224SCédric Le Goater dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n", 2167*0fcfe224SCédric Le Goater entry->msi_attrib.is_64 ? "64" : "32", d->hwirq, rc); 2168*0fcfe224SCédric Le Goater } 2169*0fcfe224SCédric Le Goater 2170*0fcfe224SCédric Le Goater static struct irq_chip pnv_msi_irq_chip = { 2171*0fcfe224SCédric Le Goater .name = "PNV-MSI", 2172*0fcfe224SCédric Le Goater .irq_shutdown = pnv_msi_shutdown, 2173*0fcfe224SCédric Le Goater .irq_mask = irq_chip_mask_parent, 2174*0fcfe224SCédric Le Goater .irq_unmask = irq_chip_unmask_parent, 2175*0fcfe224SCédric Le Goater .irq_eoi = irq_chip_eoi_parent, 2176*0fcfe224SCédric Le Goater .irq_set_affinity = irq_chip_set_affinity_parent, 2177*0fcfe224SCédric Le Goater .irq_compose_msi_msg = pnv_msi_compose_msg, 2178*0fcfe224SCédric Le Goater }; 2179*0fcfe224SCédric Le Goater 2180*0fcfe224SCédric Le Goater static int pnv_irq_parent_domain_alloc(struct irq_domain *domain, 2181*0fcfe224SCédric Le Goater unsigned int virq, int hwirq) 2182*0fcfe224SCédric Le Goater { 2183*0fcfe224SCédric Le Goater struct irq_fwspec parent_fwspec; 2184*0fcfe224SCédric Le Goater int ret; 2185*0fcfe224SCédric Le Goater 2186*0fcfe224SCédric Le Goater parent_fwspec.fwnode = domain->parent->fwnode; 2187*0fcfe224SCédric Le Goater parent_fwspec.param_count = 2; 2188*0fcfe224SCédric Le Goater parent_fwspec.param[0] = hwirq; 2189*0fcfe224SCédric Le Goater parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING; 2190*0fcfe224SCédric Le Goater 2191*0fcfe224SCédric Le Goater ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); 2192*0fcfe224SCédric Le Goater if (ret) 2193*0fcfe224SCédric Le Goater return ret; 2194*0fcfe224SCédric Le Goater 2195*0fcfe224SCédric Le Goater return 0; 2196*0fcfe224SCédric Le Goater } 2197*0fcfe224SCédric Le Goater 2198*0fcfe224SCédric Le Goater static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 2199*0fcfe224SCédric Le Goater unsigned int nr_irqs, void *arg) 2200*0fcfe224SCédric Le Goater { 2201*0fcfe224SCédric Le Goater struct pci_controller *hose = domain->host_data; 2202*0fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 2203*0fcfe224SCédric Le Goater msi_alloc_info_t *info = arg; 2204*0fcfe224SCédric Le Goater struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc); 2205*0fcfe224SCédric Le Goater int hwirq; 2206*0fcfe224SCédric Le Goater int i, ret; 2207*0fcfe224SCédric Le Goater 2208*0fcfe224SCédric Le Goater hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs); 2209*0fcfe224SCédric Le Goater if (hwirq < 0) { 2210*0fcfe224SCédric Le Goater dev_warn(&pdev->dev, "failed to find a free MSI\n"); 2211*0fcfe224SCédric Le Goater return -ENOSPC; 2212*0fcfe224SCédric Le Goater } 2213*0fcfe224SCédric Le Goater 2214*0fcfe224SCédric Le Goater dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__, 2215*0fcfe224SCédric Le Goater hose->dn, virq, hwirq, nr_irqs); 2216*0fcfe224SCédric Le Goater 2217*0fcfe224SCédric Le Goater for (i = 0; i < nr_irqs; i++) { 2218*0fcfe224SCédric Le Goater ret = pnv_irq_parent_domain_alloc(domain, virq + i, 2219*0fcfe224SCédric Le Goater phb->msi_base + hwirq + i); 2220*0fcfe224SCédric Le Goater if (ret) 2221*0fcfe224SCédric Le Goater goto out; 2222*0fcfe224SCédric Le Goater 2223*0fcfe224SCédric Le Goater irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 2224*0fcfe224SCédric Le Goater &pnv_msi_irq_chip, hose); 2225*0fcfe224SCédric Le Goater } 2226*0fcfe224SCédric Le Goater 2227*0fcfe224SCédric Le Goater return 0; 2228*0fcfe224SCédric Le Goater 2229*0fcfe224SCédric Le Goater out: 2230*0fcfe224SCédric Le Goater irq_domain_free_irqs_parent(domain, virq, i - 1); 2231*0fcfe224SCédric Le Goater msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs); 2232*0fcfe224SCédric Le Goater return ret; 2233*0fcfe224SCédric Le Goater } 2234*0fcfe224SCédric Le Goater 2235*0fcfe224SCédric Le Goater static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq, 2236*0fcfe224SCédric Le Goater unsigned int nr_irqs) 2237*0fcfe224SCédric Le Goater { 2238*0fcfe224SCédric Le Goater struct irq_data *d = irq_domain_get_irq_data(domain, virq); 2239*0fcfe224SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2240*0fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 2241*0fcfe224SCédric Le Goater 2242*0fcfe224SCédric Le Goater pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn, 2243*0fcfe224SCédric Le Goater virq, d->hwirq, nr_irqs); 2244*0fcfe224SCédric Le Goater 2245*0fcfe224SCédric Le Goater msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs); 2246*0fcfe224SCédric Le Goater /* XIVE domain is cleared through ->msi_free() */ 2247*0fcfe224SCédric Le Goater } 2248*0fcfe224SCédric Le Goater 2249*0fcfe224SCédric Le Goater static const struct irq_domain_ops pnv_irq_domain_ops = { 2250*0fcfe224SCédric Le Goater .alloc = pnv_irq_domain_alloc, 2251*0fcfe224SCédric Le Goater .free = pnv_irq_domain_free, 2252*0fcfe224SCédric Le Goater }; 2253*0fcfe224SCédric Le Goater 2254*0fcfe224SCédric Le Goater static int pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count) 2255*0fcfe224SCédric Le Goater { 2256*0fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 2257*0fcfe224SCédric Le Goater struct irq_domain *parent = irq_get_default_host(); 2258*0fcfe224SCédric Le Goater 2259*0fcfe224SCédric Le Goater hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id); 2260*0fcfe224SCédric Le Goater if (!hose->fwnode) 2261*0fcfe224SCédric Le Goater return -ENOMEM; 2262*0fcfe224SCédric Le Goater 2263*0fcfe224SCédric Le Goater hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count, 2264*0fcfe224SCédric Le Goater hose->fwnode, 2265*0fcfe224SCédric Le Goater &pnv_irq_domain_ops, hose); 2266*0fcfe224SCédric Le Goater if (!hose->dev_domain) { 2267*0fcfe224SCédric Le Goater pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n", 2268*0fcfe224SCédric Le Goater hose->dn, hose->global_number); 2269*0fcfe224SCédric Le Goater irq_domain_free_fwnode(hose->fwnode); 2270*0fcfe224SCédric Le Goater return -ENOMEM; 2271*0fcfe224SCédric Le Goater } 2272*0fcfe224SCédric Le Goater 2273*0fcfe224SCédric Le Goater hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn), 2274*0fcfe224SCédric Le Goater &pnv_msi_domain_info, 2275*0fcfe224SCédric Le Goater hose->dev_domain); 2276*0fcfe224SCédric Le Goater if (!hose->msi_domain) { 2277*0fcfe224SCédric Le Goater pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n", 2278*0fcfe224SCédric Le Goater hose->dn, hose->global_number); 2279*0fcfe224SCédric Le Goater irq_domain_free_fwnode(hose->fwnode); 2280*0fcfe224SCédric Le Goater irq_domain_remove(hose->dev_domain); 2281*0fcfe224SCédric Le Goater return -ENOMEM; 2282*0fcfe224SCédric Le Goater } 2283*0fcfe224SCédric Le Goater 2284*0fcfe224SCédric Le Goater return 0; 2285*0fcfe224SCédric Le Goater } 2286*0fcfe224SCédric Le Goater 2287184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2288184cd4a3SBenjamin Herrenschmidt { 2289fb1b55d6SGavin Shan unsigned int count; 2290184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2291184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2292184cd4a3SBenjamin Herrenschmidt if (!prop) { 2293184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2294184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2295184cd4a3SBenjamin Herrenschmidt } 2296184cd4a3SBenjamin Herrenschmidt if (!prop) 2297184cd4a3SBenjamin Herrenschmidt return; 2298184cd4a3SBenjamin Herrenschmidt 2299184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2300fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2301fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2302184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2303184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2304184cd4a3SBenjamin Herrenschmidt return; 2305184cd4a3SBenjamin Herrenschmidt } 2306fb1b55d6SGavin Shan 2307184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2308184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2309184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2310fb1b55d6SGavin Shan count, phb->msi_base); 2311*0fcfe224SCédric Le Goater 2312*0fcfe224SCédric Le Goater /* Only supported by the XIVE driver */ 2313*0fcfe224SCédric Le Goater if (xive_enabled()) 2314*0fcfe224SCédric Le Goater pnv_msi_allocate_domains(phb->hose, count); 2315184cd4a3SBenjamin Herrenschmidt } 2316184cd4a3SBenjamin Herrenschmidt 231723e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 231823e79425SGavin Shan struct resource *res) 231911685becSGavin Shan { 232023e79425SGavin Shan struct pnv_phb *phb = pe->phb; 232111685becSGavin Shan struct pci_bus_region region; 232223e79425SGavin Shan int index; 232323e79425SGavin Shan int64_t rc; 232411685becSGavin Shan 232523e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 232623e79425SGavin Shan return; 232711685becSGavin Shan 232811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 232911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 233011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 233111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 233211685becSGavin Shan 233392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 233411685becSGavin Shan region.start <= region.end) { 233511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 233611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 233711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 233811685becSGavin Shan if (rc != OPAL_SUCCESS) { 23391f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 234011685becSGavin Shan __func__, rc, index, pe->pe_number); 234111685becSGavin Shan break; 234211685becSGavin Shan } 234311685becSGavin Shan 234411685becSGavin Shan region.start += phb->ioda.io_segsize; 234511685becSGavin Shan index++; 234611685becSGavin Shan } 2347027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 23485958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 234911685becSGavin Shan region.start = res->start - 235023e79425SGavin Shan phb->hose->mem_offset[0] - 235111685becSGavin Shan phb->ioda.m32_pci_base; 235211685becSGavin Shan region.end = res->end - 235323e79425SGavin Shan phb->hose->mem_offset[0] - 235411685becSGavin Shan phb->ioda.m32_pci_base; 235511685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 235611685becSGavin Shan 235792b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 235811685becSGavin Shan region.start <= region.end) { 235911685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 236011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 236111685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 236211685becSGavin Shan if (rc != OPAL_SUCCESS) { 23631f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 236411685becSGavin Shan __func__, rc, index, pe->pe_number); 236511685becSGavin Shan break; 236611685becSGavin Shan } 236711685becSGavin Shan 236811685becSGavin Shan region.start += phb->ioda.m32_segsize; 236911685becSGavin Shan index++; 237011685becSGavin Shan } 237111685becSGavin Shan } 237211685becSGavin Shan } 237323e79425SGavin Shan 237423e79425SGavin Shan /* 237523e79425SGavin Shan * This function is supposed to be called on basis of PE from top 237623e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 237703671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 237823e79425SGavin Shan */ 237923e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 238023e79425SGavin Shan { 238169d733e7SGavin Shan struct pci_dev *pdev; 238223e79425SGavin Shan int i; 238323e79425SGavin Shan 238423e79425SGavin Shan /* 238523e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 238623e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 238723e79425SGavin Shan * be figured out later. 238823e79425SGavin Shan */ 238923e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 239023e79425SGavin Shan 239169d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 239269d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 239369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 239469d733e7SGavin Shan 239569d733e7SGavin Shan /* 239669d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 239769d733e7SGavin Shan * windows of the child bridges should be mapped to 239869d733e7SGavin Shan * the PE as well. 239969d733e7SGavin Shan */ 240069d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 240169d733e7SGavin Shan continue; 240269d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 240369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 240469d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 240569d733e7SGavin Shan } 240611685becSGavin Shan } 240711685becSGavin Shan 240898b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 240998b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 241098b665daSRussell Currey { 241122ba7289SOliver O'Halloran struct pnv_phb *phb = data; 241298b665daSRussell Currey s64 ret; 241398b665daSRussell Currey 241498b665daSRussell Currey /* Retrieve the diag data from firmware */ 24155cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 24165cb1f8fdSRussell Currey phb->diag_data_size); 241798b665daSRussell Currey if (ret != OPAL_SUCCESS) 241898b665daSRussell Currey return -EIO; 241998b665daSRussell Currey 242098b665daSRussell Currey /* Print the diag data to the kernel log */ 24215cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 242298b665daSRussell Currey return 0; 242398b665daSRussell Currey } 242498b665daSRussell Currey 2425bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2426bfa2325eSYueHaibing "%llu\n"); 242798b665daSRussell Currey 242818697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 242918697d2bSOliver O'Halloran { 243018697d2bSOliver O'Halloran struct pnv_phb *phb = data; 243118697d2bSOliver O'Halloran int pe_num; 243218697d2bSOliver O'Halloran 243318697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 243418697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 243518697d2bSOliver O'Halloran 243618697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 243718697d2bSOliver O'Halloran continue; 243818697d2bSOliver O'Halloran 243918697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 244018697d2bSOliver O'Halloran pe->rid, pe->device_count, 244118697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 244218697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 244318697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 244418697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 244518697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 244618697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 244718697d2bSOliver O'Halloran } 244818697d2bSOliver O'Halloran 244918697d2bSOliver O'Halloran return 0; 245018697d2bSOliver O'Halloran } 245118697d2bSOliver O'Halloran 245218697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 245318697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 245418697d2bSOliver O'Halloran 245598b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 245698b665daSRussell Currey 245737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 245837c367f2SGavin Shan { 245937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 246037c367f2SGavin Shan struct pci_controller *hose, *tmp; 246137c367f2SGavin Shan struct pnv_phb *phb; 246237c367f2SGavin Shan char name[16]; 246337c367f2SGavin Shan 246437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 246537c367f2SGavin Shan phb = hose->private_data; 246637c367f2SGavin Shan 246737c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 246837c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 246998b665daSRussell Currey 2470bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 247122ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 247218697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 247318697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 247437c367f2SGavin Shan } 247537c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 247637c367f2SGavin Shan } 247737c367f2SGavin Shan 2478db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 2479db217319SBenjamin Herrenschmidt { 2480db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 2481db217319SBenjamin Herrenschmidt struct pci_bus *child; 2482db217319SBenjamin Herrenschmidt 2483db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 2484db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 2485db217319SBenjamin Herrenschmidt return; 2486db217319SBenjamin Herrenschmidt 2487db217319SBenjamin Herrenschmidt /* 2488db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 2489db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 2490db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 2491db217319SBenjamin Herrenschmidt * fixed. 2492db217319SBenjamin Herrenschmidt */ 2493db217319SBenjamin Herrenschmidt if (dev) { 2494db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 2495db217319SBenjamin Herrenschmidt if (rc) 2496db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 2497db217319SBenjamin Herrenschmidt pci_set_master(dev); 2498db217319SBenjamin Herrenschmidt } 2499db217319SBenjamin Herrenschmidt 2500db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 2501db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 2502db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 2503db217319SBenjamin Herrenschmidt } 2504db217319SBenjamin Herrenschmidt 2505db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 2506db217319SBenjamin Herrenschmidt { 2507db217319SBenjamin Herrenschmidt struct pci_controller *hose; 2508db217319SBenjamin Herrenschmidt 2509db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 2510db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 2511db217319SBenjamin Herrenschmidt } 2512db217319SBenjamin Herrenschmidt 2513cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2514fb446ad0SGavin Shan { 251537c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 251637c367f2SGavin Shan 2517db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 2518db217319SBenjamin Herrenschmidt 2519e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2520b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 2521e9cc17d4SGavin Shan #endif 2522fb446ad0SGavin Shan } 2523fb446ad0SGavin Shan 2524271fd03aSGavin Shan /* 2525271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2526271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2527271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2528271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2529271fd03aSGavin Shan * 1MiB for memory) will be returned. 2530271fd03aSGavin Shan * 2531271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2532271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2533271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2534271fd03aSGavin Shan * resources. 2535271fd03aSGavin Shan */ 2536271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2537271fd03aSGavin Shan unsigned long type) 2538271fd03aSGavin Shan { 25395609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2540271fd03aSGavin Shan int num_pci_bridges = 0; 25415609ffddSOliver O'Halloran struct pci_dev *bridge; 2542271fd03aSGavin Shan 2543271fd03aSGavin Shan bridge = bus->self; 2544271fd03aSGavin Shan while (bridge) { 2545271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2546271fd03aSGavin Shan num_pci_bridges++; 2547271fd03aSGavin Shan if (num_pci_bridges >= 2) 2548271fd03aSGavin Shan return 1; 2549271fd03aSGavin Shan } 2550271fd03aSGavin Shan 2551271fd03aSGavin Shan bridge = bridge->bus->self; 2552271fd03aSGavin Shan } 2553271fd03aSGavin Shan 25545958d19aSBenjamin Herrenschmidt /* 25555958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 25565958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 25575958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 25585958d19aSBenjamin Herrenschmidt */ 2559b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 2560262af557SGuo Chao return phb->ioda.m64_segsize; 2561271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2562271fd03aSGavin Shan return phb->ioda.m32_segsize; 2563271fd03aSGavin Shan 2564271fd03aSGavin Shan return phb->ioda.io_segsize; 2565271fd03aSGavin Shan } 2566271fd03aSGavin Shan 256740e2a47eSGavin Shan /* 256840e2a47eSGavin Shan * We are updating root port or the upstream port of the 256940e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 257040e2a47eSGavin Shan * to accommodate the changes on required resources during 257140e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 257240e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 257340e2a47eSGavin Shan * root port. 257440e2a47eSGavin Shan */ 257540e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 257640e2a47eSGavin Shan unsigned long type) 257740e2a47eSGavin Shan { 257840e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 257940e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 258040e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 258140e2a47eSGavin Shan struct resource *r, *w; 258240e2a47eSGavin Shan bool msi_region = false; 258340e2a47eSGavin Shan int i; 258440e2a47eSGavin Shan 258540e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 258640e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 258740e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 258840e2a47eSGavin Shan return; 258940e2a47eSGavin Shan 259040e2a47eSGavin Shan /* Fixup the resources */ 259140e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 259240e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 259340e2a47eSGavin Shan if (!r->flags || !r->parent) 259440e2a47eSGavin Shan continue; 259540e2a47eSGavin Shan 259640e2a47eSGavin Shan w = NULL; 259740e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 259840e2a47eSGavin Shan w = &hose->io_resource; 25995958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 260040e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 260140e2a47eSGavin Shan phb->ioda.m64_segsize) 260240e2a47eSGavin Shan w = &hose->mem_resources[1]; 260340e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 260440e2a47eSGavin Shan w = &hose->mem_resources[0]; 260540e2a47eSGavin Shan msi_region = true; 260640e2a47eSGavin Shan } 260740e2a47eSGavin Shan 260840e2a47eSGavin Shan r->start = w->start; 260940e2a47eSGavin Shan r->end = w->end; 261040e2a47eSGavin Shan 261140e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 261240e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 261340e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 261440e2a47eSGavin Shan * 261540e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 261640e2a47eSGavin Shan * 32-bits bridge window. 261740e2a47eSGavin Shan */ 261840e2a47eSGavin Shan if (msi_region) { 261940e2a47eSGavin Shan r->end += 0x10000; 262040e2a47eSGavin Shan r->end -= 0x100000; 262140e2a47eSGavin Shan } 262240e2a47eSGavin Shan } 262340e2a47eSGavin Shan } 262440e2a47eSGavin Shan 2625dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus) 2626ccd1c191SGavin Shan { 2627ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 2628ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 2629dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 2630ccd1c191SGavin Shan 2631dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n"); 263240e2a47eSGavin Shan 2633ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 26346ae8aedfSOliver O'Halloran if (WARN_ON(list_empty(&bus->devices))) 2635ccd1c191SGavin Shan return; 2636ccd1c191SGavin Shan 2637ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 2638a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 2639ccd1c191SGavin Shan 2640ccd1c191SGavin Shan /* 2641ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 2642ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 2643ccd1c191SGavin Shan * not allocate resources again. 2644ccd1c191SGavin Shan */ 2645ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 2646ccd1c191SGavin Shan if (!pe) 2647ccd1c191SGavin Shan return; 2648ccd1c191SGavin Shan 2649ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 2650ccd1c191SGavin Shan } 2651ccd1c191SGavin Shan 265238274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 265338274637SYongji Xie { 265438274637SYongji Xie return PAGE_SIZE; 265538274637SYongji Xie } 265638274637SYongji Xie 2657184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 2658184cd4a3SBenjamin Herrenschmidt * assign a PE 2659184cd4a3SBenjamin Herrenschmidt */ 26608bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2661184cd4a3SBenjamin Herrenschmidt { 2662db1266c8SGavin Shan struct pci_dn *pdn; 2663184cd4a3SBenjamin Herrenschmidt 2664b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 26656c58b1b4SOliver O'Halloran if (!pdn || pdn->pe_number == IODA_INVALID_PE) { 26666c58b1b4SOliver O'Halloran pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); 2667c88c2a18SDaniel Axtens return false; 26686c58b1b4SOliver O'Halloran } 2669db1266c8SGavin Shan 2670c88c2a18SDaniel Axtens return true; 2671184cd4a3SBenjamin Herrenschmidt } 2672184cd4a3SBenjamin Herrenschmidt 2673c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 2674c1a2feadSFrederic Barrat { 2675c1a2feadSFrederic Barrat struct pci_dn *pdn; 2676c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 2677c1a2feadSFrederic Barrat 2678c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 2679c1a2feadSFrederic Barrat if (!pdn) 2680c1a2feadSFrederic Barrat return false; 2681c1a2feadSFrederic Barrat 2682c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 2683c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 2684c1a2feadSFrederic Barrat if (!pe) 2685c1a2feadSFrederic Barrat return false; 2686c1a2feadSFrederic Barrat } 2687c1a2feadSFrederic Barrat return true; 2688c1a2feadSFrederic Barrat } 2689c1a2feadSFrederic Barrat 2690c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 2691c5f7700bSGavin Shan int num) 2692c5f7700bSGavin Shan { 2693c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 2694c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 2695c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2696c5f7700bSGavin Shan unsigned int idx; 2697c5f7700bSGavin Shan long rc; 2698c5f7700bSGavin Shan 2699c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 2700c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 2701c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 2702c5f7700bSGavin Shan continue; 2703c5f7700bSGavin Shan 2704c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2705c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 2706c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 2707c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 2708c5f7700bSGavin Shan rc, idx); 2709c5f7700bSGavin Shan return rc; 2710c5f7700bSGavin Shan } 2711c5f7700bSGavin Shan 2712c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 2713c5f7700bSGavin Shan } 2714c5f7700bSGavin Shan 2715c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2716c5f7700bSGavin Shan return OPAL_SUCCESS; 2717c5f7700bSGavin Shan } 2718c5f7700bSGavin Shan 2719c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 2720c5f7700bSGavin Shan { 2721c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2722c5f7700bSGavin Shan int64_t rc; 2723c5f7700bSGavin Shan 272401e12629SOliver O'Halloran if (!pe->dma_setup_done) 2725c5f7700bSGavin Shan return; 2726c5f7700bSGavin Shan 2727c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 2728c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 2729c5f7700bSGavin Shan return; 2730c5f7700bSGavin Shan 2731a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 2732c5f7700bSGavin Shan if (pe->table_group.group) { 2733c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2734c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2735c5f7700bSGavin Shan } 2736c5f7700bSGavin Shan 2737c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 2738e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2739c5f7700bSGavin Shan } 2740c5f7700bSGavin Shan 274137b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 2742c5f7700bSGavin Shan { 2743c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2744c5f7700bSGavin Shan int64_t rc; 2745c5f7700bSGavin Shan 2746e17a7c0eSFrederic Barrat if (!pe->dma_setup_done) 2747c5f7700bSGavin Shan return; 2748c5f7700bSGavin Shan 2749c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2750c5f7700bSGavin Shan if (rc) 27511e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 2752c5f7700bSGavin Shan 2753c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 2754c5f7700bSGavin Shan if (pe->table_group.group) { 2755c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2756c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2757c5f7700bSGavin Shan } 2758c5f7700bSGavin Shan 2759e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2760c5f7700bSGavin Shan } 2761c5f7700bSGavin Shan 2762c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 2763c5f7700bSGavin Shan unsigned short win, 2764c5f7700bSGavin Shan unsigned int *map) 2765c5f7700bSGavin Shan { 2766c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2767c5f7700bSGavin Shan int idx; 2768c5f7700bSGavin Shan int64_t rc; 2769c5f7700bSGavin Shan 2770c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 2771c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 2772c5f7700bSGavin Shan continue; 2773c5f7700bSGavin Shan 2774c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2775c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 2776c5f7700bSGavin Shan 2777c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 27781e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 2779c5f7700bSGavin Shan rc, win, idx); 2780c5f7700bSGavin Shan 2781c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 2782c5f7700bSGavin Shan } 2783c5f7700bSGavin Shan } 2784c5f7700bSGavin Shan 2785c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 2786c5f7700bSGavin Shan { 2787c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2788c5f7700bSGavin Shan 2789c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2790c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 2791c5f7700bSGavin Shan phb->ioda.io_segmap); 2792c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2793c5f7700bSGavin Shan phb->ioda.m32_segmap); 279436963365SOliver O'Halloran /* M64 is pre-configured by pnv_ioda1_init_m64() */ 2795c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 2796c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2797c5f7700bSGavin Shan phb->ioda.m32_segmap); 2798c5f7700bSGavin Shan } 2799c5f7700bSGavin Shan } 2800c5f7700bSGavin Shan 2801c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 2802c5f7700bSGavin Shan { 2803c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2804c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 2805c5f7700bSGavin Shan 2806e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n"); 2807e5500ab6SOliver O'Halloran 280880f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 2809c5f7700bSGavin Shan list_del(&pe->list); 281080f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 281180f1ff83SFrederic Barrat 2812c5f7700bSGavin Shan switch (phb->type) { 2813c5f7700bSGavin Shan case PNV_PHB_IODA1: 2814c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 2815c5f7700bSGavin Shan break; 2816c5f7700bSGavin Shan case PNV_PHB_IODA2: 2817c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 2818c5f7700bSGavin Shan break; 2819f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 2820f724385fSFrederic Barrat break; 2821c5f7700bSGavin Shan default: 2822c5f7700bSGavin Shan WARN_ON(1); 2823c5f7700bSGavin Shan } 2824c5f7700bSGavin Shan 2825c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 2826c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 2827b314427aSGavin Shan 2828b314427aSGavin Shan /* Release slave PEs in the compound PE */ 2829b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 2830b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 2831b314427aSGavin Shan list_del(&slave->list); 2832b314427aSGavin Shan pnv_ioda_free_pe(slave); 2833b314427aSGavin Shan } 2834b314427aSGavin Shan } 2835b314427aSGavin Shan 28366eaed166SGavin Shan /* 28376eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 28386eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 28396eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 28406eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 28416eaed166SGavin Shan */ 2842718d249aSOliver O'Halloran if (phb->ioda.root_pe_idx == pe->pe_number) 2843718d249aSOliver O'Halloran return; 2844718d249aSOliver O'Halloran 2845c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 2846c5f7700bSGavin Shan } 2847c5f7700bSGavin Shan 2848c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 2849c5f7700bSGavin Shan { 28505609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2851c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 2852c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 2853c5f7700bSGavin Shan 285437b59ef0SOliver O'Halloran /* The VF PE state is torn down when sriov_disable() is called */ 2855c5f7700bSGavin Shan if (pdev->is_virtfn) 2856c5f7700bSGavin Shan return; 2857c5f7700bSGavin Shan 2858c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2859c5f7700bSGavin Shan return; 2860c5f7700bSGavin Shan 286137b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV 286237b59ef0SOliver O'Halloran /* 286337b59ef0SOliver O'Halloran * FIXME: Try move this to sriov_disable(). It's here since we allocate 286437b59ef0SOliver O'Halloran * the iov state at probe time since we need to fiddle with the IOV 286537b59ef0SOliver O'Halloran * resources. 286637b59ef0SOliver O'Halloran */ 286737b59ef0SOliver O'Halloran if (pdev->is_physfn) 286837b59ef0SOliver O'Halloran kfree(pdev->dev.archdata.iov_data); 286937b59ef0SOliver O'Halloran #endif 287037b59ef0SOliver O'Halloran 287129bf282dSGavin Shan /* 287229bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 287329bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 287429bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 287529bf282dSGavin Shan * device count is decreased on removing devices while failing to 287629bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 287729bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 287829bf282dSGavin Shan */ 2879c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 288029bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 288129bf282dSGavin Shan 2882c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 2883c5f7700bSGavin Shan if (pe->device_count == 0) 2884c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 2885c5f7700bSGavin Shan } 2886c5f7700bSGavin Shan 28877a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 288873ed148aSBenjamin Herrenschmidt { 28897a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 28907a8e6bbfSMichael Neuling 2891d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 289273ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 289373ed148aSBenjamin Herrenschmidt } 289473ed148aSBenjamin Herrenschmidt 2895946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 2896946743d0SOliver O'Halloran { 28975609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2898946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 2899946743d0SOliver O'Halloran 2900946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2901946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 2902946743d0SOliver O'Halloran continue; 2903946743d0SOliver O'Halloran 2904946743d0SOliver O'Halloran if (!pe->pbus) 2905946743d0SOliver O'Halloran continue; 2906946743d0SOliver O'Halloran 2907946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 2908946743d0SOliver O'Halloran pe->pbus = bus; 2909946743d0SOliver O'Halloran break; 2910946743d0SOliver O'Halloran } 2911946743d0SOliver O'Halloran } 2912946743d0SOliver O'Halloran } 2913946743d0SOliver O'Halloran 291492ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 29150a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 2916946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 29172d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 291892ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 291992ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 292092ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 2921c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 292292ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 2923dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources, 292492ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 29257a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 292692ae0353SDaniel Axtens }; 292792ae0353SDaniel Axtens 29287f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 2929c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 2930f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 29317f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 29327f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 29337f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 29347f2c39e9SFrederic Barrat }; 29357f2c39e9SFrederic Barrat 2936e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2937e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 2938184cd4a3SBenjamin Herrenschmidt { 2939184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 2940184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 29412b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 29422b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 2943718d249aSOliver O'Halloran struct pnv_ioda_pe *root_pe; 2944fd141d1aSBenjamin Herrenschmidt struct resource r; 2945c681b93cSAlistair Popple const __be64 *prop64; 29463a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 2947f1b7cc3eSGavin Shan int len; 29483fa23ff8SGavin Shan unsigned int segno; 2949184cd4a3SBenjamin Herrenschmidt u64 phb_id; 2950184cd4a3SBenjamin Herrenschmidt void *aux; 2951184cd4a3SBenjamin Herrenschmidt long rc; 2952184cd4a3SBenjamin Herrenschmidt 295308a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 295408a45b32SBenjamin Herrenschmidt return; 295508a45b32SBenjamin Herrenschmidt 2956b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 2957184cd4a3SBenjamin Herrenschmidt 2958184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2959184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2960184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2961184cd4a3SBenjamin Herrenschmidt return; 2962184cd4a3SBenjamin Herrenschmidt } 2963184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 2964184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2965184cd4a3SBenjamin Herrenschmidt 2966dea6f4c6SMichael Ellerman phb = kzalloc(sizeof(*phb), GFP_KERNEL); 29678a7f97b9SMike Rapoport if (!phb) 29688a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 29698a7f97b9SMike Rapoport sizeof(*phb)); 297058d714ecSGavin Shan 297158d714ecSGavin Shan /* Allocate PCI controller */ 2972184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 297358d714ecSGavin Shan if (!phb->hose) { 2974b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 2975b7c670d6SRob Herring np); 2976e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 2977184cd4a3SBenjamin Herrenschmidt return; 2978184cd4a3SBenjamin Herrenschmidt } 2979184cd4a3SBenjamin Herrenschmidt 2980184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 2981f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 2982f1b7cc3eSGavin Shan if (prop32 && len == 8) { 29833a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 29843a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 2985f1b7cc3eSGavin Shan } else { 2986b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 2987184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 2988184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 2989f1b7cc3eSGavin Shan } 2990184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 2991e9cc17d4SGavin Shan phb->hub_id = hub_id; 2992184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 2993aa0c033fSGavin Shan phb->type = ioda_type; 2994781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 2995184cd4a3SBenjamin Herrenschmidt 2996cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 2997cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 2998cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 2999f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3000aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 3001cee72d5bSBenjamin Herrenschmidt else 3002cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3003cee72d5bSBenjamin Herrenschmidt 30045cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 30055cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 30065cb1f8fdSRussell Currey if (prop32) 30075cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 30085cb1f8fdSRussell Currey else 30095cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 30105cb1f8fdSRussell Currey 3011dea6f4c6SMichael Ellerman phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL); 30128a7f97b9SMike Rapoport if (!phb->diag_data) 30138a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 30148a7f97b9SMike Rapoport phb->diag_data_size); 30155cb1f8fdSRussell Currey 3016aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 30172f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3018184cd4a3SBenjamin Herrenschmidt 3019aa0c033fSGavin Shan /* Get registers */ 3020fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3021fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3022fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3023184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3024184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3025fd141d1aSBenjamin Herrenschmidt } 3026577c8c88SGavin Shan 3027184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 302892b8f137SGavin Shan phb->ioda.total_pe_num = 1; 302936954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 303036954dc7SGavin Shan if (prop32) 303192b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 303236954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 303336954dc7SGavin Shan if (prop32) 303492b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3035262af557SGuo Chao 3036c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3037c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3038c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3039c127562aSGavin Shan 3040262af557SGuo Chao /* Parse 64-bit MMIO range */ 3041262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3042262af557SGuo Chao 3043184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3044aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3045184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3046184cd4a3SBenjamin Herrenschmidt 304792b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 30483fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3049184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 305092b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3051184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3052184cd4a3SBenjamin Herrenschmidt 30532b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 30542b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 30552b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 30562b923ed1SGavin Shan 3057c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3058b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 305992a86756SAlexey Kardashevskiy sizeof(unsigned long)); 306093289d8cSGavin Shan m64map_off = size; 306193289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3062184cd4a3SBenjamin Herrenschmidt m32map_off = size; 306392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3064c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3065c35d2a8cSGavin Shan iomap_off = size; 306692b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 30672b923ed1SGavin Shan dma32map_off = size; 30682b923ed1SGavin Shan size += phb->ioda.dma32_count * 30692b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3070c35d2a8cSGavin Shan } 3071184cd4a3SBenjamin Herrenschmidt pemap_off = size; 307292b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3073dea6f4c6SMichael Ellerman aux = kzalloc(size, GFP_KERNEL); 30748a7f97b9SMike Rapoport if (!aux) 30758a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3076fbbefb32SOliver O'Halloran 3077184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 307893289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3079184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 308093289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 308193289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 30823fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 308393289d8cSGavin Shan } 30843fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3085184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 30863fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 30873fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 30882b923ed1SGavin Shan 30892b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 30902b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 30912b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 30923fa23ff8SGavin Shan } 3093184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 309463803c39SGavin Shan 309563803c39SGavin Shan /* 309663803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 309763803c39SGavin Shan * M64 resources consumed by its child devices. To pick 309863803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 309963803c39SGavin Shan */ 310063803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 310163803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 310263803c39SGavin Shan phb->ioda.root_pe_idx = 1; 310363803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 310463803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 310563803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 310663803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 310763803c39SGavin Shan } else { 3108718d249aSOliver O'Halloran /* otherwise just allocate one */ 3109a4bc676eSOliver O'Halloran root_pe = pnv_ioda_alloc_pe(phb, 1); 3110718d249aSOliver O'Halloran phb->ioda.root_pe_idx = root_pe->pe_number; 311163803c39SGavin Shan } 3112184cd4a3SBenjamin Herrenschmidt 3113184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3114781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3115184cd4a3SBenjamin Herrenschmidt 3116184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 31172b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3118acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3119184cd4a3SBenjamin Herrenschmidt 3120aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3121184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3122184cd4a3SBenjamin Herrenschmidt window_type, 3123184cd4a3SBenjamin Herrenschmidt window_num, 3124184cd4a3SBenjamin Herrenschmidt starting_real_address, 3125184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3126184cd4a3SBenjamin Herrenschmidt segment_size); 3127184cd4a3SBenjamin Herrenschmidt #endif 3128184cd4a3SBenjamin Herrenschmidt 3129262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 313092b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3131262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3132262af557SGuo Chao if (phb->ioda.m64_size) 3133262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3134262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3135262af557SGuo Chao if (phb->ioda.io_size) 3136262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3137184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3138184cd4a3SBenjamin Herrenschmidt 3139262af557SGuo Chao 3140184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 314149dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 314249dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 314349dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3144184cd4a3SBenjamin Herrenschmidt 3145184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3146184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3147184cd4a3SBenjamin Herrenschmidt 3148c40a4210SGavin Shan /* 3149c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3150c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3151c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3152c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3153c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3154184cd4a3SBenjamin Herrenschmidt */ 3155fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 31565d2aa710SAlistair Popple 31577f2c39e9SFrederic Barrat switch (phb->type) { 31587f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 31597f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 31607f2c39e9SFrederic Barrat break; 31617f2c39e9SFrederic Barrat default: 316292ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3163f9f83456SAlexey Kardashevskiy } 3164ad30cb99SMichael Ellerman 316538274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 316638274637SYongji Xie 31676e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 3168965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 31695350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3170988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3171988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3172ad30cb99SMichael Ellerman #endif 3173ad30cb99SMichael Ellerman 3174c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3175184cd4a3SBenjamin Herrenschmidt 3176184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3177d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3178184cd4a3SBenjamin Herrenschmidt if (rc) 3179f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3180361f2a2aSGavin Shan 31816060e9eaSAndrew Donnellan /* 31826060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3183361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3184361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 318545baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3186b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3187b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3188b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3189b174b4fbSOliver O'Halloran * boot. 3190361f2a2aSGavin Shan */ 3191b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3192361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3193cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3194cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3195361f2a2aSGavin Shan } 3196262af557SGuo Chao 31979e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 31989e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3199262af557SGuo Chao hose->mem_resources[1].flags = 0; 3200fbbefb32SOliver O'Halloran 3201fbbefb32SOliver O'Halloran /* create pci_dn's for DT nodes under this PHB */ 3202fbbefb32SOliver O'Halloran pci_devs_phb_init_dynamic(hose); 3203184cd4a3SBenjamin Herrenschmidt } 3204184cd4a3SBenjamin Herrenschmidt 320567975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3206aa0c033fSGavin Shan { 3207e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3208aa0c033fSGavin Shan } 3209aa0c033fSGavin Shan 32107f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 32117f2c39e9SFrederic Barrat { 32127f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 32135d2aa710SAlistair Popple } 32145d2aa710SAlistair Popple 3215228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3216228c2f41SAndrew Donnellan { 32175609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3218228c2f41SAndrew Donnellan 3219228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3220228c2f41SAndrew Donnellan return; 3221228c2f41SAndrew Donnellan 3222228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3223228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3224228c2f41SAndrew Donnellan } 3225228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3226228c2f41SAndrew Donnellan 3227184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3228184cd4a3SBenjamin Herrenschmidt { 3229184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3230c681b93cSAlistair Popple const __be64 *prop64; 3231184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3232184cd4a3SBenjamin Herrenschmidt 3233b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3234184cd4a3SBenjamin Herrenschmidt 3235184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3236184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3237184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3238184cd4a3SBenjamin Herrenschmidt return; 3239184cd4a3SBenjamin Herrenschmidt } 3240184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3241184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3242184cd4a3SBenjamin Herrenschmidt 3243184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3244184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3245184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3246184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3247e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3248184cd4a3SBenjamin Herrenschmidt } 3249184cd4a3SBenjamin Herrenschmidt } 3250