1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 51781a868fSWei Yang /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 52781a868fSWei Yang #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 53781a868fSWei Yang 54bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 56bbb845c4SAlexey Kardashevskiy 57aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 58aca6913fSAlexey Kardashevskiy 596d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 606d31c2faSJoe Perches const char *fmt, ...) 616d31c2faSJoe Perches { 626d31c2faSJoe Perches struct va_format vaf; 636d31c2faSJoe Perches va_list args; 646d31c2faSJoe Perches char pfix[32]; 65184cd4a3SBenjamin Herrenschmidt 666d31c2faSJoe Perches va_start(args, fmt); 676d31c2faSJoe Perches 686d31c2faSJoe Perches vaf.fmt = fmt; 696d31c2faSJoe Perches vaf.va = &args; 706d31c2faSJoe Perches 71781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 726d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 73781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 746d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 756d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 76781a868fSWei Yang #ifdef CONFIG_PCI_IOV 77781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 78781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 79781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 80781a868fSWei Yang (pe->rid & 0xff00) >> 8, 81781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 82781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 836d31c2faSJoe Perches 846d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 856d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 866d31c2faSJoe Perches 876d31c2faSJoe Perches va_end(args); 886d31c2faSJoe Perches } 896d31c2faSJoe Perches 906d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 916d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 926d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 936d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 946d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 956d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 96184cd4a3SBenjamin Herrenschmidt 974e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 984e287840SThadeu Lima de Souza Cascardo 994e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 1004e287840SThadeu Lima de Souza Cascardo { 1014e287840SThadeu Lima de Souza Cascardo if (!str) 1024e287840SThadeu Lima de Souza Cascardo return -EINVAL; 1034e287840SThadeu Lima de Souza Cascardo 1044e287840SThadeu Lima de Souza Cascardo while (*str) { 1054e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1064e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1074e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1084e287840SThadeu Lima de Souza Cascardo break; 1094e287840SThadeu Lima de Souza Cascardo } 1104e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1114e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1124e287840SThadeu Lima de Souza Cascardo str++; 1134e287840SThadeu Lima de Souza Cascardo } 1144e287840SThadeu Lima de Souza Cascardo 1154e287840SThadeu Lima de Souza Cascardo return 0; 1164e287840SThadeu Lima de Souza Cascardo } 1174e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1184e287840SThadeu Lima de Souza Cascardo 1198e0a1611SAlexey Kardashevskiy /* 1208e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 1218e0a1611SAlexey Kardashevskiy * the architecture spec 1228e0a1611SAlexey Kardashevskiy */ 1238e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 1248e0a1611SAlexey Kardashevskiy { 1258e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 1268e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 1278e0a1611SAlexey Kardashevskiy } 1288e0a1611SAlexey Kardashevskiy 129262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 130262af557SGuo Chao { 131262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 132262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 133262af557SGuo Chao } 134262af557SGuo Chao 1354b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1364b82ab18SGavin Shan { 1374b82ab18SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { 1384b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1394b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1404b82ab18SGavin Shan return; 1414b82ab18SGavin Shan } 1424b82ab18SGavin Shan 1434b82ab18SGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) { 1444b82ab18SGavin Shan pr_warn("%s: PE %d was assigned on PHB#%x\n", 1454b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1464b82ab18SGavin Shan return; 1474b82ab18SGavin Shan } 1484b82ab18SGavin Shan 1494b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1504b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1514b82ab18SGavin Shan } 1524b82ab18SGavin Shan 153cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 154184cd4a3SBenjamin Herrenschmidt { 155184cd4a3SBenjamin Herrenschmidt unsigned long pe; 156184cd4a3SBenjamin Herrenschmidt 157184cd4a3SBenjamin Herrenschmidt do { 158184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 159184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 160184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 161184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 162184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 163184cd4a3SBenjamin Herrenschmidt 1644cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 165184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 166184cd4a3SBenjamin Herrenschmidt return pe; 167184cd4a3SBenjamin Herrenschmidt } 168184cd4a3SBenjamin Herrenschmidt 169cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 170184cd4a3SBenjamin Herrenschmidt { 171184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 172184cd4a3SBenjamin Herrenschmidt 173184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 174184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 175184cd4a3SBenjamin Herrenschmidt } 176184cd4a3SBenjamin Herrenschmidt 177262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 178262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 179262af557SGuo Chao { 180262af557SGuo Chao const char *desc; 181262af557SGuo Chao struct resource *r; 182262af557SGuo Chao s64 rc; 183262af557SGuo Chao 184262af557SGuo Chao /* Configure the default M64 BAR */ 185262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 186262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 187262af557SGuo Chao phb->ioda.m64_bar_idx, 188262af557SGuo Chao phb->ioda.m64_base, 189262af557SGuo Chao 0, /* unused */ 190262af557SGuo Chao phb->ioda.m64_size); 191262af557SGuo Chao if (rc != OPAL_SUCCESS) { 192262af557SGuo Chao desc = "configuring"; 193262af557SGuo Chao goto fail; 194262af557SGuo Chao } 195262af557SGuo Chao 196262af557SGuo Chao /* Enable the default M64 BAR */ 197262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 198262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 199262af557SGuo Chao phb->ioda.m64_bar_idx, 200262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 201262af557SGuo Chao if (rc != OPAL_SUCCESS) { 202262af557SGuo Chao desc = "enabling"; 203262af557SGuo Chao goto fail; 204262af557SGuo Chao } 205262af557SGuo Chao 206262af557SGuo Chao /* Mark the M64 BAR assigned */ 207262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 208262af557SGuo Chao 209262af557SGuo Chao /* 210262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 211262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 212262af557SGuo Chao */ 213262af557SGuo Chao r = &phb->hose->mem_resources[1]; 214262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 215262af557SGuo Chao r->start += phb->ioda.m64_segsize; 216262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 217262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 218262af557SGuo Chao else 219262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 220262af557SGuo Chao phb->ioda.reserved_pe); 221262af557SGuo Chao 222262af557SGuo Chao return 0; 223262af557SGuo Chao 224262af557SGuo Chao fail: 225262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 226262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 227262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 228262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 229262af557SGuo Chao phb->ioda.m64_bar_idx, 230262af557SGuo Chao OPAL_DISABLE_M64); 231262af557SGuo Chao return -EIO; 232262af557SGuo Chao } 233262af557SGuo Chao 2345ef73567SGavin Shan static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) 235262af557SGuo Chao { 236262af557SGuo Chao resource_size_t sgsz = phb->ioda.m64_segsize; 237262af557SGuo Chao struct pci_dev *pdev; 238262af557SGuo Chao struct resource *r; 239262af557SGuo Chao int base, step, i; 240262af557SGuo Chao 241262af557SGuo Chao /* 242262af557SGuo Chao * Root bus always has full M64 range and root port has 243262af557SGuo Chao * M64 range used in reality. So we're checking root port 244262af557SGuo Chao * instead of root bus. 245262af557SGuo Chao */ 246262af557SGuo Chao list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { 2474b82ab18SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 2484b82ab18SGavin Shan r = &pdev->resource[PCI_BRIDGE_RESOURCES + i]; 249262af557SGuo Chao if (!r->parent || 250262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 251262af557SGuo Chao continue; 252262af557SGuo Chao 253262af557SGuo Chao base = (r->start - phb->ioda.m64_base) / sgsz; 254262af557SGuo Chao for (step = 0; step < resource_size(r) / sgsz; step++) 2554b82ab18SGavin Shan pnv_ioda_reserve_pe(phb, base + step); 256262af557SGuo Chao } 257262af557SGuo Chao } 258262af557SGuo Chao } 259262af557SGuo Chao 260262af557SGuo Chao static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 261262af557SGuo Chao struct pci_bus *bus, int all) 262262af557SGuo Chao { 263262af557SGuo Chao resource_size_t segsz = phb->ioda.m64_segsize; 264262af557SGuo Chao struct pci_dev *pdev; 265262af557SGuo Chao struct resource *r; 266262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 267262af557SGuo Chao unsigned long size, *pe_alloc; 268262af557SGuo Chao bool found; 269262af557SGuo Chao int start, i, j; 270262af557SGuo Chao 271262af557SGuo Chao /* Root bus shouldn't use M64 */ 272262af557SGuo Chao if (pci_is_root_bus(bus)) 273262af557SGuo Chao return IODA_INVALID_PE; 274262af557SGuo Chao 275262af557SGuo Chao /* We support only one M64 window on each bus */ 276262af557SGuo Chao found = false; 277262af557SGuo Chao pci_bus_for_each_resource(bus, r, i) { 278262af557SGuo Chao if (r && r->parent && 279262af557SGuo Chao pnv_pci_is_mem_pref_64(r->flags)) { 280262af557SGuo Chao found = true; 281262af557SGuo Chao break; 282262af557SGuo Chao } 283262af557SGuo Chao } 284262af557SGuo Chao 285262af557SGuo Chao /* No M64 window found ? */ 286262af557SGuo Chao if (!found) 287262af557SGuo Chao return IODA_INVALID_PE; 288262af557SGuo Chao 289262af557SGuo Chao /* Allocate bitmap */ 290262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 291262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 292262af557SGuo Chao if (!pe_alloc) { 293262af557SGuo Chao pr_warn("%s: Out of memory !\n", 294262af557SGuo Chao __func__); 295262af557SGuo Chao return IODA_INVALID_PE; 296262af557SGuo Chao } 297262af557SGuo Chao 298262af557SGuo Chao /* 299262af557SGuo Chao * Figure out reserved PE numbers by the PE 300262af557SGuo Chao * the its child PEs. 301262af557SGuo Chao */ 302262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 303262af557SGuo Chao for (i = 0; i < resource_size(r) / segsz; i++) 304262af557SGuo Chao set_bit(start + i, pe_alloc); 305262af557SGuo Chao 306262af557SGuo Chao if (all) 307262af557SGuo Chao goto done; 308262af557SGuo Chao 309262af557SGuo Chao /* 310262af557SGuo Chao * If the PE doesn't cover all subordinate buses, 311262af557SGuo Chao * we need subtract from reserved PEs for children. 312262af557SGuo Chao */ 313262af557SGuo Chao list_for_each_entry(pdev, &bus->devices, bus_list) { 314262af557SGuo Chao if (!pdev->subordinate) 315262af557SGuo Chao continue; 316262af557SGuo Chao 317262af557SGuo Chao pci_bus_for_each_resource(pdev->subordinate, r, i) { 318262af557SGuo Chao if (!r || !r->parent || 319262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 320262af557SGuo Chao continue; 321262af557SGuo Chao 322262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 323262af557SGuo Chao for (j = 0; j < resource_size(r) / segsz ; j++) 324262af557SGuo Chao clear_bit(start + j, pe_alloc); 325262af557SGuo Chao } 326262af557SGuo Chao } 327262af557SGuo Chao 328262af557SGuo Chao /* 329262af557SGuo Chao * the current bus might not own M64 window and that's all 330262af557SGuo Chao * contributed by its child buses. For the case, we needn't 331262af557SGuo Chao * pick M64 dependent PE#. 332262af557SGuo Chao */ 333262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 334262af557SGuo Chao kfree(pe_alloc); 335262af557SGuo Chao return IODA_INVALID_PE; 336262af557SGuo Chao } 337262af557SGuo Chao 338262af557SGuo Chao /* 339262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 340262af557SGuo Chao * PE's list to form compound PE. 341262af557SGuo Chao */ 342262af557SGuo Chao done: 343262af557SGuo Chao master_pe = NULL; 344262af557SGuo Chao i = -1; 345262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 346262af557SGuo Chao phb->ioda.total_pe) { 347262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 348262af557SGuo Chao 349262af557SGuo Chao if (!master_pe) { 350262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 351262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 352262af557SGuo Chao master_pe = pe; 353262af557SGuo Chao } else { 354262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 355262af557SGuo Chao pe->master = master_pe; 356262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 357262af557SGuo Chao } 358262af557SGuo Chao } 359262af557SGuo Chao 360262af557SGuo Chao kfree(pe_alloc); 361262af557SGuo Chao return master_pe->pe_number; 362262af557SGuo Chao } 363262af557SGuo Chao 364262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 365262af557SGuo Chao { 366262af557SGuo Chao struct pci_controller *hose = phb->hose; 367262af557SGuo Chao struct device_node *dn = hose->dn; 368262af557SGuo Chao struct resource *res; 369262af557SGuo Chao const u32 *r; 370262af557SGuo Chao u64 pci_addr; 371262af557SGuo Chao 3721665c4a8SGavin Shan /* FIXME: Support M64 for P7IOC */ 3731665c4a8SGavin Shan if (phb->type != PNV_PHB_IODA2) { 3741665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3751665c4a8SGavin Shan return; 3761665c4a8SGavin Shan } 3771665c4a8SGavin Shan 378262af557SGuo Chao if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 379262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 380262af557SGuo Chao return; 381262af557SGuo Chao } 382262af557SGuo Chao 383262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 384262af557SGuo Chao if (!r) { 385262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 386262af557SGuo Chao dn->full_name); 387262af557SGuo Chao return; 388262af557SGuo Chao } 389262af557SGuo Chao 390262af557SGuo Chao res = &hose->mem_resources[1]; 391262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 392262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 393262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 394262af557SGuo Chao pci_addr = of_read_number(r, 2); 395262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 396262af557SGuo Chao 397262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 398262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 399262af557SGuo Chao phb->ioda.m64_base = pci_addr; 400262af557SGuo Chao 401e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 402e9863e68SWei Yang res->start, res->end, pci_addr); 403e9863e68SWei Yang 404262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 405262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 406262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 4075ef73567SGavin Shan phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 408262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 409262af557SGuo Chao } 410262af557SGuo Chao 41149dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 41249dec922SGavin Shan { 41349dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 41449dec922SGavin Shan struct pnv_ioda_pe *slave; 41549dec922SGavin Shan s64 rc; 41649dec922SGavin Shan 41749dec922SGavin Shan /* Fetch master PE */ 41849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 41949dec922SGavin Shan pe = pe->master; 420ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 421ec8e4e9dSGavin Shan return; 422ec8e4e9dSGavin Shan 42349dec922SGavin Shan pe_no = pe->pe_number; 42449dec922SGavin Shan } 42549dec922SGavin Shan 42649dec922SGavin Shan /* Freeze master PE */ 42749dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 42849dec922SGavin Shan pe_no, 42949dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 43049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 43149dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 43249dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 43349dec922SGavin Shan return; 43449dec922SGavin Shan } 43549dec922SGavin Shan 43649dec922SGavin Shan /* Freeze slave PEs */ 43749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 43849dec922SGavin Shan return; 43949dec922SGavin Shan 44049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 44149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 44249dec922SGavin Shan slave->pe_number, 44349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 44449dec922SGavin Shan if (rc != OPAL_SUCCESS) 44549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 44649dec922SGavin Shan __func__, rc, phb->hose->global_number, 44749dec922SGavin Shan slave->pe_number); 44849dec922SGavin Shan } 44949dec922SGavin Shan } 45049dec922SGavin Shan 451e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 45249dec922SGavin Shan { 45349dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 45449dec922SGavin Shan s64 rc; 45549dec922SGavin Shan 45649dec922SGavin Shan /* Find master PE */ 45749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 45849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 45949dec922SGavin Shan pe = pe->master; 46049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 46149dec922SGavin Shan pe_no = pe->pe_number; 46249dec922SGavin Shan } 46349dec922SGavin Shan 46449dec922SGavin Shan /* Clear frozen state for master PE */ 46549dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 46649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 46749dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 46849dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 46949dec922SGavin Shan return -EIO; 47049dec922SGavin Shan } 47149dec922SGavin Shan 47249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 47349dec922SGavin Shan return 0; 47449dec922SGavin Shan 47549dec922SGavin Shan /* Clear frozen state for slave PEs */ 47649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 47749dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 47849dec922SGavin Shan slave->pe_number, 47949dec922SGavin Shan opt); 48049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 48149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 48249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 48349dec922SGavin Shan slave->pe_number); 48449dec922SGavin Shan return -EIO; 48549dec922SGavin Shan } 48649dec922SGavin Shan } 48749dec922SGavin Shan 48849dec922SGavin Shan return 0; 48949dec922SGavin Shan } 49049dec922SGavin Shan 49149dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 49249dec922SGavin Shan { 49349dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 49449dec922SGavin Shan u8 fstate, state; 49549dec922SGavin Shan __be16 pcierr; 49649dec922SGavin Shan s64 rc; 49749dec922SGavin Shan 49849dec922SGavin Shan /* Sanity check on PE number */ 49949dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 50049dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 50149dec922SGavin Shan 50249dec922SGavin Shan /* 50349dec922SGavin Shan * Fetch the master PE and the PE instance might be 50449dec922SGavin Shan * not initialized yet. 50549dec922SGavin Shan */ 50649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 50749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 50849dec922SGavin Shan pe = pe->master; 50949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 51049dec922SGavin Shan pe_no = pe->pe_number; 51149dec922SGavin Shan } 51249dec922SGavin Shan 51349dec922SGavin Shan /* Check the master PE */ 51449dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 51549dec922SGavin Shan &state, &pcierr, NULL); 51649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 51749dec922SGavin Shan pr_warn("%s: Failure %lld getting " 51849dec922SGavin Shan "PHB#%x-PE#%x state\n", 51949dec922SGavin Shan __func__, rc, 52049dec922SGavin Shan phb->hose->global_number, pe_no); 52149dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 52249dec922SGavin Shan } 52349dec922SGavin Shan 52449dec922SGavin Shan /* Check the slave PE */ 52549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 52649dec922SGavin Shan return state; 52749dec922SGavin Shan 52849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 52949dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 53049dec922SGavin Shan slave->pe_number, 53149dec922SGavin Shan &fstate, 53249dec922SGavin Shan &pcierr, 53349dec922SGavin Shan NULL); 53449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 53549dec922SGavin Shan pr_warn("%s: Failure %lld getting " 53649dec922SGavin Shan "PHB#%x-PE#%x state\n", 53749dec922SGavin Shan __func__, rc, 53849dec922SGavin Shan phb->hose->global_number, slave->pe_number); 53949dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 54049dec922SGavin Shan } 54149dec922SGavin Shan 54249dec922SGavin Shan /* 54349dec922SGavin Shan * Override the result based on the ascending 54449dec922SGavin Shan * priority. 54549dec922SGavin Shan */ 54649dec922SGavin Shan if (fstate > state) 54749dec922SGavin Shan state = fstate; 54849dec922SGavin Shan } 54949dec922SGavin Shan 55049dec922SGavin Shan return state; 55149dec922SGavin Shan } 55249dec922SGavin Shan 553184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 554184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 555184cd4a3SBenjamin Herrenschmidt */ 556184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 557cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 558184cd4a3SBenjamin Herrenschmidt { 559184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 560184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 561b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 562184cd4a3SBenjamin Herrenschmidt 563184cd4a3SBenjamin Herrenschmidt if (!pdn) 564184cd4a3SBenjamin Herrenschmidt return NULL; 565184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 566184cd4a3SBenjamin Herrenschmidt return NULL; 567184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 568184cd4a3SBenjamin Herrenschmidt } 569184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 570184cd4a3SBenjamin Herrenschmidt 571b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 572b131a842SGavin Shan struct pnv_ioda_pe *parent, 573b131a842SGavin Shan struct pnv_ioda_pe *child, 574b131a842SGavin Shan bool is_add) 575b131a842SGavin Shan { 576b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 577b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 578b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 579b131a842SGavin Shan struct pnv_ioda_pe *slave; 580b131a842SGavin Shan long rc; 581b131a842SGavin Shan 582b131a842SGavin Shan /* Parent PE affects child PE */ 583b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 584b131a842SGavin Shan child->pe_number, op); 585b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 586b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 587b131a842SGavin Shan rc, desc); 588b131a842SGavin Shan return -ENXIO; 589b131a842SGavin Shan } 590b131a842SGavin Shan 591b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 592b131a842SGavin Shan return 0; 593b131a842SGavin Shan 594b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 595b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 596b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 597b131a842SGavin Shan slave->pe_number, op); 598b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 599b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 600b131a842SGavin Shan rc, desc); 601b131a842SGavin Shan return -ENXIO; 602b131a842SGavin Shan } 603b131a842SGavin Shan } 604b131a842SGavin Shan 605b131a842SGavin Shan return 0; 606b131a842SGavin Shan } 607b131a842SGavin Shan 608b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 609b131a842SGavin Shan struct pnv_ioda_pe *pe, 610b131a842SGavin Shan bool is_add) 611b131a842SGavin Shan { 612b131a842SGavin Shan struct pnv_ioda_pe *slave; 613781a868fSWei Yang struct pci_dev *pdev = NULL; 614b131a842SGavin Shan int ret; 615b131a842SGavin Shan 616b131a842SGavin Shan /* 617b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 618b131a842SGavin Shan * clear slave PE frozen state as well. 619b131a842SGavin Shan */ 620b131a842SGavin Shan if (is_add) { 621b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 622b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 623b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 624b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 625b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 626b131a842SGavin Shan slave->pe_number, 627b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 628b131a842SGavin Shan } 629b131a842SGavin Shan } 630b131a842SGavin Shan 631b131a842SGavin Shan /* 632b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 633b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 634b131a842SGavin Shan * originated from the PE might contribute to other 635b131a842SGavin Shan * PEs. 636b131a842SGavin Shan */ 637b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 638b131a842SGavin Shan if (ret) 639b131a842SGavin Shan return ret; 640b131a842SGavin Shan 641b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 642b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 643b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 644b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 645b131a842SGavin Shan if (ret) 646b131a842SGavin Shan return ret; 647b131a842SGavin Shan } 648b131a842SGavin Shan } 649b131a842SGavin Shan 650b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 651b131a842SGavin Shan pdev = pe->pbus->self; 652781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 653b131a842SGavin Shan pdev = pe->pdev->bus->self; 654781a868fSWei Yang #ifdef CONFIG_PCI_IOV 655781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 656781a868fSWei Yang pdev = pe->parent_dev->bus->self; 657781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 658b131a842SGavin Shan while (pdev) { 659b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 660b131a842SGavin Shan struct pnv_ioda_pe *parent; 661b131a842SGavin Shan 662b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 663b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 664b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 665b131a842SGavin Shan if (ret) 666b131a842SGavin Shan return ret; 667b131a842SGavin Shan } 668b131a842SGavin Shan 669b131a842SGavin Shan pdev = pdev->bus->self; 670b131a842SGavin Shan } 671b131a842SGavin Shan 672b131a842SGavin Shan return 0; 673b131a842SGavin Shan } 674b131a842SGavin Shan 675781a868fSWei Yang #ifdef CONFIG_PCI_IOV 676781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 677781a868fSWei Yang { 678781a868fSWei Yang struct pci_dev *parent; 679781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 680781a868fSWei Yang int64_t rc; 681781a868fSWei Yang long rid_end, rid; 682781a868fSWei Yang 683781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 684781a868fSWei Yang if (pe->pbus) { 685781a868fSWei Yang int count; 686781a868fSWei Yang 687781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 688781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 689781a868fSWei Yang parent = pe->pbus->self; 690781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 691781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 692781a868fSWei Yang else 693781a868fSWei Yang count = 1; 694781a868fSWei Yang 695781a868fSWei Yang switch(count) { 696781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 697781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 698781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 699781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 700781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 701781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 702781a868fSWei Yang default: 703781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 704781a868fSWei Yang count); 705781a868fSWei Yang /* Do an exact match only */ 706781a868fSWei Yang bcomp = OpalPciBusAll; 707781a868fSWei Yang } 708781a868fSWei Yang rid_end = pe->rid + (count << 8); 709781a868fSWei Yang } else { 710781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 711781a868fSWei Yang parent = pe->parent_dev; 712781a868fSWei Yang else 713781a868fSWei Yang parent = pe->pdev->bus->self; 714781a868fSWei Yang bcomp = OpalPciBusAll; 715781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 716781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 717781a868fSWei Yang rid_end = pe->rid + 1; 718781a868fSWei Yang } 719781a868fSWei Yang 720781a868fSWei Yang /* Clear the reverse map */ 721781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 722781a868fSWei Yang phb->ioda.pe_rmap[rid] = 0; 723781a868fSWei Yang 724781a868fSWei Yang /* Release from all parents PELT-V */ 725781a868fSWei Yang while (parent) { 726781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 727781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 728781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 729781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 730781a868fSWei Yang /* XXX What to do in case of error ? */ 731781a868fSWei Yang } 732781a868fSWei Yang parent = parent->bus->self; 733781a868fSWei Yang } 734781a868fSWei Yang 735781a868fSWei Yang opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number, 736781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 737781a868fSWei Yang 738781a868fSWei Yang /* Disassociate PE in PELT */ 739781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 740781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 741781a868fSWei Yang if (rc) 742781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 743781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 744781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 745781a868fSWei Yang if (rc) 746781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 747781a868fSWei Yang 748781a868fSWei Yang pe->pbus = NULL; 749781a868fSWei Yang pe->pdev = NULL; 750781a868fSWei Yang pe->parent_dev = NULL; 751781a868fSWei Yang 752781a868fSWei Yang return 0; 753781a868fSWei Yang } 754781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 755781a868fSWei Yang 756cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 757184cd4a3SBenjamin Herrenschmidt { 758184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 759184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 760184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 761184cd4a3SBenjamin Herrenschmidt 762184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 763184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 764184cd4a3SBenjamin Herrenschmidt int count; 765184cd4a3SBenjamin Herrenschmidt 766184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 767184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 768184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 769fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 770b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 771fb446ad0SGavin Shan else 772fb446ad0SGavin Shan count = 1; 773fb446ad0SGavin Shan 774184cd4a3SBenjamin Herrenschmidt switch(count) { 775184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 776184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 777184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 778184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 779184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 780184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 781184cd4a3SBenjamin Herrenschmidt default: 782781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 783781a868fSWei Yang count); 784184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 785184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 786184cd4a3SBenjamin Herrenschmidt } 787184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 788184cd4a3SBenjamin Herrenschmidt } else { 789781a868fSWei Yang #ifdef CONFIG_PCI_IOV 790781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 791781a868fSWei Yang parent = pe->parent_dev; 792781a868fSWei Yang else 793781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 794184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 795184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 796184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 797184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 798184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 799184cd4a3SBenjamin Herrenschmidt } 800184cd4a3SBenjamin Herrenschmidt 801631ad691SGavin Shan /* 802631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 803631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 804631ad691SGavin Shan * originated from the PE might contribute to other 805631ad691SGavin Shan * PEs. 806631ad691SGavin Shan */ 807184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 808184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 809184cd4a3SBenjamin Herrenschmidt if (rc) { 810184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 811184cd4a3SBenjamin Herrenschmidt return -ENXIO; 812184cd4a3SBenjamin Herrenschmidt } 813631ad691SGavin Shan 814b131a842SGavin Shan /* Configure PELTV */ 815b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 816184cd4a3SBenjamin Herrenschmidt 817184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 818184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 819184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 820184cd4a3SBenjamin Herrenschmidt 821184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8224773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8234773f76bSGavin Shan pe->mve_number = 0; 8244773f76bSGavin Shan goto out; 8254773f76bSGavin Shan } 8264773f76bSGavin Shan 827184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8284773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8294773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 830184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 831184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 832184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 833184cd4a3SBenjamin Herrenschmidt } else { 834184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 835cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 836184cd4a3SBenjamin Herrenschmidt if (rc) { 837184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 838184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 839184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 840184cd4a3SBenjamin Herrenschmidt } 841184cd4a3SBenjamin Herrenschmidt } 842184cd4a3SBenjamin Herrenschmidt 8434773f76bSGavin Shan out: 844184cd4a3SBenjamin Herrenschmidt return 0; 845184cd4a3SBenjamin Herrenschmidt } 846184cd4a3SBenjamin Herrenschmidt 847cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 848184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 849184cd4a3SBenjamin Herrenschmidt { 850184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 851184cd4a3SBenjamin Herrenschmidt 8527ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 853184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 8547ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 855184cd4a3SBenjamin Herrenschmidt return; 856184cd4a3SBenjamin Herrenschmidt } 857184cd4a3SBenjamin Herrenschmidt } 8587ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 859184cd4a3SBenjamin Herrenschmidt } 860184cd4a3SBenjamin Herrenschmidt 861184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 862184cd4a3SBenjamin Herrenschmidt { 863184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 864184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 865184cd4a3SBenjamin Herrenschmidt */ 866184cd4a3SBenjamin Herrenschmidt 867184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 868184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 869184cd4a3SBenjamin Herrenschmidt return 0; 870184cd4a3SBenjamin Herrenschmidt 871184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 872184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 873184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 874184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 875184cd4a3SBenjamin Herrenschmidt return 3; 876184cd4a3SBenjamin Herrenschmidt 877184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 878184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 879184cd4a3SBenjamin Herrenschmidt return 15; 880184cd4a3SBenjamin Herrenschmidt 881184cd4a3SBenjamin Herrenschmidt /* Default */ 882184cd4a3SBenjamin Herrenschmidt return 10; 883184cd4a3SBenjamin Herrenschmidt } 884184cd4a3SBenjamin Herrenschmidt 885781a868fSWei Yang #ifdef CONFIG_PCI_IOV 886781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 887781a868fSWei Yang { 888781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 889781a868fSWei Yang int i; 890781a868fSWei Yang struct resource *res, res2; 891781a868fSWei Yang resource_size_t size; 892781a868fSWei Yang u16 num_vfs; 893781a868fSWei Yang 894781a868fSWei Yang if (!dev->is_physfn) 895781a868fSWei Yang return -EINVAL; 896781a868fSWei Yang 897781a868fSWei Yang /* 898781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 899781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 900781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 901781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 902781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 903781a868fSWei Yang * range of PEs the VFs are in. 904781a868fSWei Yang */ 905781a868fSWei Yang num_vfs = pdn->num_vfs; 906781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 907781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 908781a868fSWei Yang if (!res->flags || !res->parent) 909781a868fSWei Yang continue; 910781a868fSWei Yang 911781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 912781a868fSWei Yang continue; 913781a868fSWei Yang 914781a868fSWei Yang /* 915781a868fSWei Yang * The actual IOV BAR range is determined by the start address 916781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 917781a868fSWei Yang * make sure that after shifting, the range will not overlap 918781a868fSWei Yang * with another device. 919781a868fSWei Yang */ 920781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 921781a868fSWei Yang res2.flags = res->flags; 922781a868fSWei Yang res2.start = res->start + (size * offset); 923781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 924781a868fSWei Yang 925781a868fSWei Yang if (res2.end > res->end) { 926781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 927781a868fSWei Yang i, &res2, res, num_vfs, offset); 928781a868fSWei Yang return -EBUSY; 929781a868fSWei Yang } 930781a868fSWei Yang } 931781a868fSWei Yang 932781a868fSWei Yang /* 933781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 934781a868fSWei Yang * offset is a positive value. It looks like the device return some 935781a868fSWei Yang * mmio back to the system, which actually no one could use it. 936781a868fSWei Yang */ 937781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 938781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 939781a868fSWei Yang if (!res->flags || !res->parent) 940781a868fSWei Yang continue; 941781a868fSWei Yang 942781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 943781a868fSWei Yang continue; 944781a868fSWei Yang 945781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 946781a868fSWei Yang res2 = *res; 947781a868fSWei Yang res->start += size * offset; 948781a868fSWei Yang 949781a868fSWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n", 950781a868fSWei Yang i, &res2, res, num_vfs, offset); 951781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 952781a868fSWei Yang } 953781a868fSWei Yang return 0; 954781a868fSWei Yang } 955781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 956781a868fSWei Yang 957fb446ad0SGavin Shan #if 0 958cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 959184cd4a3SBenjamin Herrenschmidt { 960184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 961184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 962b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 963184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 964184cd4a3SBenjamin Herrenschmidt int pe_num; 965184cd4a3SBenjamin Herrenschmidt 966184cd4a3SBenjamin Herrenschmidt if (!pdn) { 967184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 968184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 969184cd4a3SBenjamin Herrenschmidt return NULL; 970184cd4a3SBenjamin Herrenschmidt } 971184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 972184cd4a3SBenjamin Herrenschmidt return NULL; 973184cd4a3SBenjamin Herrenschmidt 974184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 975184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 976184cd4a3SBenjamin Herrenschmidt pe_num = 0; 977184cd4a3SBenjamin Herrenschmidt else 978184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 979184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 980184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 981184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 982184cd4a3SBenjamin Herrenschmidt return NULL; 983184cd4a3SBenjamin Herrenschmidt } 984184cd4a3SBenjamin Herrenschmidt 985184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 986184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 987184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 988184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 989184cd4a3SBenjamin Herrenschmidt * 990184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 991184cd4a3SBenjamin Herrenschmidt */ 992184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 993184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 994184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 995184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 996184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 997184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 998184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 999184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1000184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1001184cd4a3SBenjamin Herrenschmidt 1002184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1003184cd4a3SBenjamin Herrenschmidt 1004184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1005184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1006184cd4a3SBenjamin Herrenschmidt if (pe_num) 1007184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1008184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1009184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1010184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1011184cd4a3SBenjamin Herrenschmidt return NULL; 1012184cd4a3SBenjamin Herrenschmidt } 1013184cd4a3SBenjamin Herrenschmidt 1014184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 1015184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 1016184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1017184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1018184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1019184cd4a3SBenjamin Herrenschmidt } 1020184cd4a3SBenjamin Herrenschmidt 1021184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1022184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1023184cd4a3SBenjamin Herrenschmidt 1024184cd4a3SBenjamin Herrenschmidt return pe; 1025184cd4a3SBenjamin Herrenschmidt } 1026fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 1027184cd4a3SBenjamin Herrenschmidt 1028184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1029184cd4a3SBenjamin Herrenschmidt { 1030184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1031184cd4a3SBenjamin Herrenschmidt 1032184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1033b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1034184cd4a3SBenjamin Herrenschmidt 1035184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1036184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1037184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1038184cd4a3SBenjamin Herrenschmidt continue; 1039184cd4a3SBenjamin Herrenschmidt } 1040184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1041184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 1042fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1043184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1044184cd4a3SBenjamin Herrenschmidt } 1045184cd4a3SBenjamin Herrenschmidt } 1046184cd4a3SBenjamin Herrenschmidt 1047fb446ad0SGavin Shan /* 1048fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1049fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1050fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1051fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1052fb446ad0SGavin Shan */ 1053cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 1054184cd4a3SBenjamin Herrenschmidt { 1055fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1056184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1057184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1058262af557SGuo Chao int pe_num = IODA_INVALID_PE; 1059184cd4a3SBenjamin Herrenschmidt 1060262af557SGuo Chao /* Check if PE is determined by M64 */ 1061262af557SGuo Chao if (phb->pick_m64_pe) 1062262af557SGuo Chao pe_num = phb->pick_m64_pe(phb, bus, all); 1063262af557SGuo Chao 1064262af557SGuo Chao /* The PE number isn't pinned by M64 */ 1065262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 1066184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 1067262af557SGuo Chao 1068184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 1069fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1070fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 1071184cd4a3SBenjamin Herrenschmidt return; 1072184cd4a3SBenjamin Herrenschmidt } 1073184cd4a3SBenjamin Herrenschmidt 1074184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1075262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1076184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1077184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1078184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1079184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1080b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1081184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 1082184cd4a3SBenjamin Herrenschmidt 1083fb446ad0SGavin Shan if (all) 1084fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1085fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 1086fb446ad0SGavin Shan else 1087fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1088fb446ad0SGavin Shan bus->busn_res.start, pe_num); 1089184cd4a3SBenjamin Herrenschmidt 1090184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1091184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1092184cd4a3SBenjamin Herrenschmidt if (pe_num) 1093184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1094184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1095184cd4a3SBenjamin Herrenschmidt return; 1096184cd4a3SBenjamin Herrenschmidt } 1097184cd4a3SBenjamin Herrenschmidt 1098184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1099184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1100184cd4a3SBenjamin Herrenschmidt 11017ebdf956SGavin Shan /* Put PE to the list */ 11027ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11037ebdf956SGavin Shan 1104184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 1105184cd4a3SBenjamin Herrenschmidt * below the bridge 1106184cd4a3SBenjamin Herrenschmidt */ 1107184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1108184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1109184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1110184cd4a3SBenjamin Herrenschmidt } 1111184cd4a3SBenjamin Herrenschmidt 1112184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1113184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1114184cd4a3SBenjamin Herrenschmidt } 1115184cd4a3SBenjamin Herrenschmidt 1116cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1117184cd4a3SBenjamin Herrenschmidt { 1118184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1119fb446ad0SGavin Shan 1120fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 1121184cd4a3SBenjamin Herrenschmidt 1122184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1123fb446ad0SGavin Shan if (dev->subordinate) { 112462f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1125fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 1126fb446ad0SGavin Shan else 1127184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 1128184cd4a3SBenjamin Herrenschmidt } 1129184cd4a3SBenjamin Herrenschmidt } 1130fb446ad0SGavin Shan } 1131fb446ad0SGavin Shan 1132fb446ad0SGavin Shan /* 1133fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 1134fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 1135fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 1136fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 1137fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 1138fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 1139fb446ad0SGavin Shan */ 1140cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1141fb446ad0SGavin Shan { 1142fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1143262af557SGuo Chao struct pnv_phb *phb; 1144fb446ad0SGavin Shan 1145fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1146262af557SGuo Chao phb = hose->private_data; 1147262af557SGuo Chao 1148262af557SGuo Chao /* M64 layout might affect PE allocation */ 11495ef73567SGavin Shan if (phb->reserve_m64_pe) 11505ef73567SGavin Shan phb->reserve_m64_pe(phb); 1151262af557SGuo Chao 1152fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 1153fb446ad0SGavin Shan } 1154fb446ad0SGavin Shan } 1155184cd4a3SBenjamin Herrenschmidt 1156a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1157781a868fSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev) 1158781a868fSWei Yang { 1159781a868fSWei Yang struct pci_bus *bus; 1160781a868fSWei Yang struct pci_controller *hose; 1161781a868fSWei Yang struct pnv_phb *phb; 1162781a868fSWei Yang struct pci_dn *pdn; 116302639b0eSWei Yang int i, j; 1164781a868fSWei Yang 1165781a868fSWei Yang bus = pdev->bus; 1166781a868fSWei Yang hose = pci_bus_to_host(bus); 1167781a868fSWei Yang phb = hose->private_data; 1168781a868fSWei Yang pdn = pci_get_pdn(pdev); 1169781a868fSWei Yang 117002639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 117102639b0eSWei Yang for (j = 0; j < M64_PER_IOV; j++) { 117202639b0eSWei Yang if (pdn->m64_wins[i][j] == IODA_INVALID_M64) 1173781a868fSWei Yang continue; 1174781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 117502639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0); 117602639b0eSWei Yang clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc); 117702639b0eSWei Yang pdn->m64_wins[i][j] = IODA_INVALID_M64; 1178781a868fSWei Yang } 1179781a868fSWei Yang 1180781a868fSWei Yang return 0; 1181781a868fSWei Yang } 1182781a868fSWei Yang 118302639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1184781a868fSWei Yang { 1185781a868fSWei Yang struct pci_bus *bus; 1186781a868fSWei Yang struct pci_controller *hose; 1187781a868fSWei Yang struct pnv_phb *phb; 1188781a868fSWei Yang struct pci_dn *pdn; 1189781a868fSWei Yang unsigned int win; 1190781a868fSWei Yang struct resource *res; 119102639b0eSWei Yang int i, j; 1192781a868fSWei Yang int64_t rc; 119302639b0eSWei Yang int total_vfs; 119402639b0eSWei Yang resource_size_t size, start; 119502639b0eSWei Yang int pe_num; 119602639b0eSWei Yang int vf_groups; 119702639b0eSWei Yang int vf_per_group; 1198781a868fSWei Yang 1199781a868fSWei Yang bus = pdev->bus; 1200781a868fSWei Yang hose = pci_bus_to_host(bus); 1201781a868fSWei Yang phb = hose->private_data; 1202781a868fSWei Yang pdn = pci_get_pdn(pdev); 120302639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1204781a868fSWei Yang 1205781a868fSWei Yang /* Initialize the m64_wins to IODA_INVALID_M64 */ 1206781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 120702639b0eSWei Yang for (j = 0; j < M64_PER_IOV; j++) 120802639b0eSWei Yang pdn->m64_wins[i][j] = IODA_INVALID_M64; 120902639b0eSWei Yang 121002639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 121102639b0eSWei Yang vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV; 121202639b0eSWei Yang vf_per_group = (num_vfs <= M64_PER_IOV)? 1: 121302639b0eSWei Yang roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 121402639b0eSWei Yang } else { 121502639b0eSWei Yang vf_groups = 1; 121602639b0eSWei Yang vf_per_group = 1; 121702639b0eSWei Yang } 1218781a868fSWei Yang 1219781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1220781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1221781a868fSWei Yang if (!res->flags || !res->parent) 1222781a868fSWei Yang continue; 1223781a868fSWei Yang 1224781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 1225781a868fSWei Yang continue; 1226781a868fSWei Yang 122702639b0eSWei Yang for (j = 0; j < vf_groups; j++) { 1228781a868fSWei Yang do { 1229781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1230781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1231781a868fSWei Yang 1232781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1233781a868fSWei Yang goto m64_failed; 1234781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1235781a868fSWei Yang 123602639b0eSWei Yang pdn->m64_wins[i][j] = win; 123702639b0eSWei Yang 123802639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 123902639b0eSWei Yang size = pci_iov_resource_size(pdev, 124002639b0eSWei Yang PCI_IOV_RESOURCES + i); 124102639b0eSWei Yang size = size * vf_per_group; 124202639b0eSWei Yang start = res->start + size * j; 124302639b0eSWei Yang } else { 124402639b0eSWei Yang size = resource_size(res); 124502639b0eSWei Yang start = res->start; 124602639b0eSWei Yang } 1247781a868fSWei Yang 1248781a868fSWei Yang /* Map the M64 here */ 124902639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 125002639b0eSWei Yang pe_num = pdn->offset + j; 125102639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 125202639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 125302639b0eSWei Yang pdn->m64_wins[i][j], 0); 125402639b0eSWei Yang } 125502639b0eSWei Yang 1256781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1257781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 125802639b0eSWei Yang pdn->m64_wins[i][j], 125902639b0eSWei Yang start, 1260781a868fSWei Yang 0, /* unused */ 126102639b0eSWei Yang size); 126202639b0eSWei Yang 126302639b0eSWei Yang 1264781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1265781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1266781a868fSWei Yang win, rc); 1267781a868fSWei Yang goto m64_failed; 1268781a868fSWei Yang } 1269781a868fSWei Yang 127002639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) 1271781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 127202639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2); 127302639b0eSWei Yang else 127402639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 127502639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1); 127602639b0eSWei Yang 1277781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1278781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1279781a868fSWei Yang win, rc); 1280781a868fSWei Yang goto m64_failed; 1281781a868fSWei Yang } 1282781a868fSWei Yang } 128302639b0eSWei Yang } 1284781a868fSWei Yang return 0; 1285781a868fSWei Yang 1286781a868fSWei Yang m64_failed: 1287781a868fSWei Yang pnv_pci_vf_release_m64(pdev); 1288781a868fSWei Yang return -EBUSY; 1289781a868fSWei Yang } 1290781a868fSWei Yang 1291c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1292c035e37bSAlexey Kardashevskiy int num); 1293c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1294c035e37bSAlexey Kardashevskiy 1295781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1296781a868fSWei Yang { 1297781a868fSWei Yang struct iommu_table *tbl; 1298781a868fSWei Yang int64_t rc; 1299781a868fSWei Yang 1300b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1301c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1302781a868fSWei Yang if (rc) 1303781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1304781a868fSWei Yang 1305c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 13060eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 13070eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 13080eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1309ac9a5889SAlexey Kardashevskiy } 1310aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1311781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1312781a868fSWei Yang } 1313781a868fSWei Yang 131402639b0eSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1315781a868fSWei Yang { 1316781a868fSWei Yang struct pci_bus *bus; 1317781a868fSWei Yang struct pci_controller *hose; 1318781a868fSWei Yang struct pnv_phb *phb; 1319781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1320781a868fSWei Yang struct pci_dn *pdn; 132102639b0eSWei Yang u16 vf_index; 132202639b0eSWei Yang int64_t rc; 1323781a868fSWei Yang 1324781a868fSWei Yang bus = pdev->bus; 1325781a868fSWei Yang hose = pci_bus_to_host(bus); 1326781a868fSWei Yang phb = hose->private_data; 132702639b0eSWei Yang pdn = pci_get_pdn(pdev); 1328781a868fSWei Yang 1329781a868fSWei Yang if (!pdev->is_physfn) 1330781a868fSWei Yang return; 1331781a868fSWei Yang 133202639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 133302639b0eSWei Yang int vf_group; 133402639b0eSWei Yang int vf_per_group; 133502639b0eSWei Yang int vf_index1; 133602639b0eSWei Yang 133702639b0eSWei Yang vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 133802639b0eSWei Yang 133902639b0eSWei Yang for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) 134002639b0eSWei Yang for (vf_index = vf_group * vf_per_group; 134102639b0eSWei Yang vf_index < (vf_group + 1) * vf_per_group && 134202639b0eSWei Yang vf_index < num_vfs; 134302639b0eSWei Yang vf_index++) 134402639b0eSWei Yang for (vf_index1 = vf_group * vf_per_group; 134502639b0eSWei Yang vf_index1 < (vf_group + 1) * vf_per_group && 134602639b0eSWei Yang vf_index1 < num_vfs; 134702639b0eSWei Yang vf_index1++){ 134802639b0eSWei Yang 134902639b0eSWei Yang rc = opal_pci_set_peltv(phb->opal_id, 135002639b0eSWei Yang pdn->offset + vf_index, 135102639b0eSWei Yang pdn->offset + vf_index1, 135202639b0eSWei Yang OPAL_REMOVE_PE_FROM_DOMAIN); 135302639b0eSWei Yang 135402639b0eSWei Yang if (rc) 135502639b0eSWei Yang dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n", 135602639b0eSWei Yang __func__, 135702639b0eSWei Yang pdn->offset + vf_index1, rc); 135802639b0eSWei Yang } 135902639b0eSWei Yang } 136002639b0eSWei Yang 1361781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1362781a868fSWei Yang if (pe->parent_dev != pdev) 1363781a868fSWei Yang continue; 1364781a868fSWei Yang 1365781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1366781a868fSWei Yang 1367781a868fSWei Yang /* Remove from list */ 1368781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1369781a868fSWei Yang list_del(&pe->list); 1370781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1371781a868fSWei Yang 1372781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1373781a868fSWei Yang 1374781a868fSWei Yang pnv_ioda_free_pe(phb, pe->pe_number); 1375781a868fSWei Yang } 1376781a868fSWei Yang } 1377781a868fSWei Yang 1378781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1379781a868fSWei Yang { 1380781a868fSWei Yang struct pci_bus *bus; 1381781a868fSWei Yang struct pci_controller *hose; 1382781a868fSWei Yang struct pnv_phb *phb; 1383781a868fSWei Yang struct pci_dn *pdn; 1384781a868fSWei Yang struct pci_sriov *iov; 1385781a868fSWei Yang u16 num_vfs; 1386781a868fSWei Yang 1387781a868fSWei Yang bus = pdev->bus; 1388781a868fSWei Yang hose = pci_bus_to_host(bus); 1389781a868fSWei Yang phb = hose->private_data; 1390781a868fSWei Yang pdn = pci_get_pdn(pdev); 1391781a868fSWei Yang iov = pdev->sriov; 1392781a868fSWei Yang num_vfs = pdn->num_vfs; 1393781a868fSWei Yang 1394781a868fSWei Yang /* Release VF PEs */ 139502639b0eSWei Yang pnv_ioda_release_vf_PE(pdev, num_vfs); 1396781a868fSWei Yang 1397781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 139802639b0eSWei Yang if (pdn->m64_per_iov == 1) 1399781a868fSWei Yang pnv_pci_vf_resource_shift(pdev, -pdn->offset); 1400781a868fSWei Yang 1401781a868fSWei Yang /* Release M64 windows */ 1402781a868fSWei Yang pnv_pci_vf_release_m64(pdev); 1403781a868fSWei Yang 1404781a868fSWei Yang /* Release PE numbers */ 1405781a868fSWei Yang bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1406781a868fSWei Yang pdn->offset = 0; 1407781a868fSWei Yang } 1408781a868fSWei Yang } 1409781a868fSWei Yang 1410781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1411781a868fSWei Yang struct pnv_ioda_pe *pe); 1412781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1413781a868fSWei Yang { 1414781a868fSWei Yang struct pci_bus *bus; 1415781a868fSWei Yang struct pci_controller *hose; 1416781a868fSWei Yang struct pnv_phb *phb; 1417781a868fSWei Yang struct pnv_ioda_pe *pe; 1418781a868fSWei Yang int pe_num; 1419781a868fSWei Yang u16 vf_index; 1420781a868fSWei Yang struct pci_dn *pdn; 142102639b0eSWei Yang int64_t rc; 1422781a868fSWei Yang 1423781a868fSWei Yang bus = pdev->bus; 1424781a868fSWei Yang hose = pci_bus_to_host(bus); 1425781a868fSWei Yang phb = hose->private_data; 1426781a868fSWei Yang pdn = pci_get_pdn(pdev); 1427781a868fSWei Yang 1428781a868fSWei Yang if (!pdev->is_physfn) 1429781a868fSWei Yang return; 1430781a868fSWei Yang 1431781a868fSWei Yang /* Reserve PE for each VF */ 1432781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1433781a868fSWei Yang pe_num = pdn->offset + vf_index; 1434781a868fSWei Yang 1435781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1436781a868fSWei Yang pe->pe_number = pe_num; 1437781a868fSWei Yang pe->phb = phb; 1438781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1439781a868fSWei Yang pe->pbus = NULL; 1440781a868fSWei Yang pe->parent_dev = pdev; 1441781a868fSWei Yang pe->tce32_seg = -1; 1442781a868fSWei Yang pe->mve_number = -1; 1443781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1444781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1445781a868fSWei Yang 1446781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1447781a868fSWei Yang hose->global_number, pdev->bus->number, 1448781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1449781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1450781a868fSWei Yang 1451781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1452781a868fSWei Yang /* XXX What do we do here ? */ 1453781a868fSWei Yang if (pe_num) 1454781a868fSWei Yang pnv_ioda_free_pe(phb, pe_num); 1455781a868fSWei Yang pe->pdev = NULL; 1456781a868fSWei Yang continue; 1457781a868fSWei Yang } 1458781a868fSWei Yang 1459781a868fSWei Yang /* Put PE to the list */ 1460781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1461781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1462781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1463781a868fSWei Yang 1464781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1465781a868fSWei Yang } 146602639b0eSWei Yang 146702639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 146802639b0eSWei Yang int vf_group; 146902639b0eSWei Yang int vf_per_group; 147002639b0eSWei Yang int vf_index1; 147102639b0eSWei Yang 147202639b0eSWei Yang vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 147302639b0eSWei Yang 147402639b0eSWei Yang for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) { 147502639b0eSWei Yang for (vf_index = vf_group * vf_per_group; 147602639b0eSWei Yang vf_index < (vf_group + 1) * vf_per_group && 147702639b0eSWei Yang vf_index < num_vfs; 147802639b0eSWei Yang vf_index++) { 147902639b0eSWei Yang for (vf_index1 = vf_group * vf_per_group; 148002639b0eSWei Yang vf_index1 < (vf_group + 1) * vf_per_group && 148102639b0eSWei Yang vf_index1 < num_vfs; 148202639b0eSWei Yang vf_index1++) { 148302639b0eSWei Yang 148402639b0eSWei Yang rc = opal_pci_set_peltv(phb->opal_id, 148502639b0eSWei Yang pdn->offset + vf_index, 148602639b0eSWei Yang pdn->offset + vf_index1, 148702639b0eSWei Yang OPAL_ADD_PE_TO_DOMAIN); 148802639b0eSWei Yang 148902639b0eSWei Yang if (rc) 149002639b0eSWei Yang dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n", 149102639b0eSWei Yang __func__, 149202639b0eSWei Yang pdn->offset + vf_index1, rc); 149302639b0eSWei Yang } 149402639b0eSWei Yang } 149502639b0eSWei Yang } 149602639b0eSWei Yang } 1497781a868fSWei Yang } 1498781a868fSWei Yang 1499781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1500781a868fSWei Yang { 1501781a868fSWei Yang struct pci_bus *bus; 1502781a868fSWei Yang struct pci_controller *hose; 1503781a868fSWei Yang struct pnv_phb *phb; 1504781a868fSWei Yang struct pci_dn *pdn; 1505781a868fSWei Yang int ret; 1506781a868fSWei Yang 1507781a868fSWei Yang bus = pdev->bus; 1508781a868fSWei Yang hose = pci_bus_to_host(bus); 1509781a868fSWei Yang phb = hose->private_data; 1510781a868fSWei Yang pdn = pci_get_pdn(pdev); 1511781a868fSWei Yang 1512781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1513781a868fSWei Yang /* Calculate available PE for required VFs */ 1514781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1515781a868fSWei Yang pdn->offset = bitmap_find_next_zero_area( 1516781a868fSWei Yang phb->ioda.pe_alloc, phb->ioda.total_pe, 1517781a868fSWei Yang 0, num_vfs, 0); 1518781a868fSWei Yang if (pdn->offset >= phb->ioda.total_pe) { 1519781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1520781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1521781a868fSWei Yang pdn->offset = 0; 1522781a868fSWei Yang return -EBUSY; 1523781a868fSWei Yang } 1524781a868fSWei Yang bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1525781a868fSWei Yang pdn->num_vfs = num_vfs; 1526781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1527781a868fSWei Yang 1528781a868fSWei Yang /* Assign M64 window accordingly */ 152902639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1530781a868fSWei Yang if (ret) { 1531781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1532781a868fSWei Yang goto m64_failed; 1533781a868fSWei Yang } 1534781a868fSWei Yang 1535781a868fSWei Yang /* 1536781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1537781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1538781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1539781a868fSWei Yang */ 154002639b0eSWei Yang if (pdn->m64_per_iov == 1) { 1541781a868fSWei Yang ret = pnv_pci_vf_resource_shift(pdev, pdn->offset); 1542781a868fSWei Yang if (ret) 1543781a868fSWei Yang goto m64_failed; 1544781a868fSWei Yang } 154502639b0eSWei Yang } 1546781a868fSWei Yang 1547781a868fSWei Yang /* Setup VF PEs */ 1548781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1549781a868fSWei Yang 1550781a868fSWei Yang return 0; 1551781a868fSWei Yang 1552781a868fSWei Yang m64_failed: 1553781a868fSWei Yang bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1554781a868fSWei Yang pdn->offset = 0; 1555781a868fSWei Yang 1556781a868fSWei Yang return ret; 1557781a868fSWei Yang } 1558781a868fSWei Yang 1559a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1560a8b2f828SGavin Shan { 1561781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1562781a868fSWei Yang 1563a8b2f828SGavin Shan /* Release PCI data */ 1564a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1565a8b2f828SGavin Shan return 0; 1566a8b2f828SGavin Shan } 1567a8b2f828SGavin Shan 1568a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1569a8b2f828SGavin Shan { 1570a8b2f828SGavin Shan /* Allocate PCI data */ 1571a8b2f828SGavin Shan add_dev_pci_data(pdev); 1572781a868fSWei Yang 1573781a868fSWei Yang pnv_pci_sriov_enable(pdev, num_vfs); 1574a8b2f828SGavin Shan return 0; 1575a8b2f828SGavin Shan } 1576a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1577a8b2f828SGavin Shan 1578959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1579184cd4a3SBenjamin Herrenschmidt { 1580b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1581959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1582184cd4a3SBenjamin Herrenschmidt 1583959c9bddSGavin Shan /* 1584959c9bddSGavin Shan * The function can be called while the PE# 1585959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1586959c9bddSGavin Shan * case. 1587959c9bddSGavin Shan */ 1588959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1589959c9bddSGavin Shan return; 1590184cd4a3SBenjamin Herrenschmidt 1591959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1592cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1593b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 15944617082eSAlexey Kardashevskiy /* 15954617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 15964617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 15974617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 15984617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 15994617082eSAlexey Kardashevskiy */ 1600184cd4a3SBenjamin Herrenschmidt } 1601184cd4a3SBenjamin Herrenschmidt 1602763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1603cd15b048SBenjamin Herrenschmidt { 1604763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1605763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1606cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1607cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1608cd15b048SBenjamin Herrenschmidt uint64_t top; 1609cd15b048SBenjamin Herrenschmidt bool bypass = false; 1610cd15b048SBenjamin Herrenschmidt 1611cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1612cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1613cd15b048SBenjamin Herrenschmidt 1614cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1615cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1616cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1617cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1618cd15b048SBenjamin Herrenschmidt } 1619cd15b048SBenjamin Herrenschmidt 1620cd15b048SBenjamin Herrenschmidt if (bypass) { 1621cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1622cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1623cd15b048SBenjamin Herrenschmidt set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1624cd15b048SBenjamin Herrenschmidt } else { 1625cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1626cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1627b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1628cd15b048SBenjamin Herrenschmidt } 1629a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 1630cd15b048SBenjamin Herrenschmidt return 0; 1631cd15b048SBenjamin Herrenschmidt } 1632cd15b048SBenjamin Herrenschmidt 1633fe7e85c6SGavin Shan static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, 1634fe7e85c6SGavin Shan struct pci_dev *pdev) 1635fe7e85c6SGavin Shan { 1636fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1637fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1638fe7e85c6SGavin Shan u64 end, mask; 1639fe7e85c6SGavin Shan 1640fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1641fe7e85c6SGavin Shan return 0; 1642fe7e85c6SGavin Shan 1643fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1644fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1645fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1646fe7e85c6SGavin Shan 1647fe7e85c6SGavin Shan 1648fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1649fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1650fe7e85c6SGavin Shan mask += mask - 1; 1651fe7e85c6SGavin Shan 1652fe7e85c6SGavin Shan return mask; 1653fe7e85c6SGavin Shan } 1654fe7e85c6SGavin Shan 1655dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1656ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 165774251fe2SBenjamin Herrenschmidt { 165874251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 165974251fe2SBenjamin Herrenschmidt 166074251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1661b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 16624617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1663dff4a39eSGavin Shan 166474251fe2SBenjamin Herrenschmidt if (dev->subordinate) 1665ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 166674251fe2SBenjamin Herrenschmidt } 166774251fe2SBenjamin Herrenschmidt } 166874251fe2SBenjamin Herrenschmidt 1669decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1670decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 16714cce9550SGavin Shan { 16720eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 16730eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 16740eaf4defSAlexey Kardashevskiy next); 16750eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1676b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 16773ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 16785780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 16795780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 16804cce9550SGavin Shan unsigned long start, end, inc; 1681b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 16824cce9550SGavin Shan 1683decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1684decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1685decbda25SAlexey Kardashevskiy npages - 1); 16864cce9550SGavin Shan 16874cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 16884cce9550SGavin Shan if (tbl->it_busno) { 1689b0376c9bSAlexey Kardashevskiy start <<= shift; 1690b0376c9bSAlexey Kardashevskiy end <<= shift; 1691b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 16924cce9550SGavin Shan start |= tbl->it_busno; 16934cce9550SGavin Shan end |= tbl->it_busno; 16944cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 16954cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 16964cce9550SGavin Shan start |= (1ull << 63); 16974cce9550SGavin Shan end |= (1ull << 63); 16984cce9550SGavin Shan inc = 16; 16994cce9550SGavin Shan } else { 17004cce9550SGavin Shan /* Default (older HW) */ 17014cce9550SGavin Shan inc = 128; 17024cce9550SGavin Shan } 17034cce9550SGavin Shan 17044cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17054cce9550SGavin Shan 17064cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17074cce9550SGavin Shan while (start <= end) { 17088e0a1611SAlexey Kardashevskiy if (rm) 17093ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17108e0a1611SAlexey Kardashevskiy else 17113a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17124cce9550SGavin Shan start += inc; 17134cce9550SGavin Shan } 17144cce9550SGavin Shan 17154cce9550SGavin Shan /* 17164cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 17174cce9550SGavin Shan * and we don't care on free() 17184cce9550SGavin Shan */ 17194cce9550SGavin Shan } 17204cce9550SGavin Shan 1721decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1722decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1723decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1724decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1725decbda25SAlexey Kardashevskiy { 1726decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1727decbda25SAlexey Kardashevskiy attrs); 1728decbda25SAlexey Kardashevskiy 1729decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1730decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1731decbda25SAlexey Kardashevskiy 1732decbda25SAlexey Kardashevskiy return ret; 1733decbda25SAlexey Kardashevskiy } 1734decbda25SAlexey Kardashevskiy 173505c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 173605c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 173705c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 173805c6cfb9SAlexey Kardashevskiy { 173905c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 174005c6cfb9SAlexey Kardashevskiy 174105c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 174205c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 174305c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 174405c6cfb9SAlexey Kardashevskiy 174505c6cfb9SAlexey Kardashevskiy return ret; 174605c6cfb9SAlexey Kardashevskiy } 174705c6cfb9SAlexey Kardashevskiy #endif 174805c6cfb9SAlexey Kardashevskiy 1749decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1750decbda25SAlexey Kardashevskiy long npages) 1751decbda25SAlexey Kardashevskiy { 1752decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1753decbda25SAlexey Kardashevskiy 1754decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1755decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1756decbda25SAlexey Kardashevskiy } 1757decbda25SAlexey Kardashevskiy 1758da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1759decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 176005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 176105c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 176205c6cfb9SAlexey Kardashevskiy #endif 1763decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1764da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1765da004c36SAlexey Kardashevskiy }; 1766da004c36SAlexey Kardashevskiy 17675780fb04SAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 17685780fb04SAlexey Kardashevskiy { 17695780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 17705780fb04SAlexey Kardashevskiy unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 17715780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 17725780fb04SAlexey Kardashevskiy 17735780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 17745780fb04SAlexey Kardashevskiy return; 17755780fb04SAlexey Kardashevskiy 17765780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 17775780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 17785780fb04SAlexey Kardashevskiy } 17795780fb04SAlexey Kardashevskiy 1780e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1781e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1782e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 17834cce9550SGavin Shan { 17844cce9550SGavin Shan unsigned long start, end, inc; 17854cce9550SGavin Shan 17864cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1787b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 1788e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 17894cce9550SGavin Shan end = start; 17904cce9550SGavin Shan 17914cce9550SGavin Shan /* Figure out the start, end and step */ 1792decbda25SAlexey Kardashevskiy start |= (index << shift); 1793decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1794b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 17954cce9550SGavin Shan mb(); 17964cce9550SGavin Shan 17974cce9550SGavin Shan while (start <= end) { 17988e0a1611SAlexey Kardashevskiy if (rm) 17993ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18008e0a1611SAlexey Kardashevskiy else 18013a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18024cce9550SGavin Shan start += inc; 18034cce9550SGavin Shan } 18044cce9550SGavin Shan } 18054cce9550SGavin Shan 1806e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1807e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1808e57080f1SAlexey Kardashevskiy { 1809e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1810e57080f1SAlexey Kardashevskiy 1811e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1812e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1813e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1814e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1815e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1816e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 1817e57080f1SAlexey Kardashevskiy 1818e57080f1SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1819e57080f1SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 1820e57080f1SAlexey Kardashevskiy index, npages); 1821e57080f1SAlexey Kardashevskiy } 1822e57080f1SAlexey Kardashevskiy } 1823e57080f1SAlexey Kardashevskiy 1824decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1825decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1826decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1827decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 18284cce9550SGavin Shan { 1829decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1830decbda25SAlexey Kardashevskiy attrs); 18314cce9550SGavin Shan 1832decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1833decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1834decbda25SAlexey Kardashevskiy 1835decbda25SAlexey Kardashevskiy return ret; 1836decbda25SAlexey Kardashevskiy } 1837decbda25SAlexey Kardashevskiy 183805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 183905c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 184005c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 184105c6cfb9SAlexey Kardashevskiy { 184205c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 184305c6cfb9SAlexey Kardashevskiy 184405c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 184505c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 184605c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 184705c6cfb9SAlexey Kardashevskiy 184805c6cfb9SAlexey Kardashevskiy return ret; 184905c6cfb9SAlexey Kardashevskiy } 185005c6cfb9SAlexey Kardashevskiy #endif 185105c6cfb9SAlexey Kardashevskiy 1852decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1853decbda25SAlexey Kardashevskiy long npages) 1854decbda25SAlexey Kardashevskiy { 1855decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1856decbda25SAlexey Kardashevskiy 1857decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1858decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 18594cce9550SGavin Shan } 18604cce9550SGavin Shan 18614793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 18624793d65dSAlexey Kardashevskiy { 18634793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 18644793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 18654793d65dSAlexey Kardashevskiy } 18664793d65dSAlexey Kardashevskiy 1867da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1868decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 186905c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 187005c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 187105c6cfb9SAlexey Kardashevskiy #endif 1872decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1873da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 18744793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 1875da004c36SAlexey Kardashevskiy }; 1876da004c36SAlexey Kardashevskiy 1877cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1878cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1879184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1880184cd4a3SBenjamin Herrenschmidt { 1881184cd4a3SBenjamin Herrenschmidt 1882184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1883184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1884184cd4a3SBenjamin Herrenschmidt unsigned int i; 1885184cd4a3SBenjamin Herrenschmidt int64_t rc; 1886184cd4a3SBenjamin Herrenschmidt void *addr; 1887184cd4a3SBenjamin Herrenschmidt 1888184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1889184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1890184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1891184cd4a3SBenjamin Herrenschmidt 1892184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1893184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1894184cd4a3SBenjamin Herrenschmidt return; 1895184cd4a3SBenjamin Herrenschmidt 18960eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 1897b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1898b348aa65SAlexey Kardashevskiy pe->pe_number); 18990eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1900c5773822SAlexey Kardashevskiy 1901184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1902184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1903184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1904184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1905184cd4a3SBenjamin Herrenschmidt 1906184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1907184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1908184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1909184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1910184cd4a3SBenjamin Herrenschmidt */ 1911184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1912184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1913184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1914184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1915184cd4a3SBenjamin Herrenschmidt goto fail; 1916184cd4a3SBenjamin Herrenschmidt } 1917184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1918184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1919184cd4a3SBenjamin Herrenschmidt 1920184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1921184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1922184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1923184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1924184cd4a3SBenjamin Herrenschmidt base + i, 1, 1925184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1926184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1927184cd4a3SBenjamin Herrenschmidt if (rc) { 1928184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1929184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1930184cd4a3SBenjamin Herrenschmidt goto fail; 1931184cd4a3SBenjamin Herrenschmidt } 1932184cd4a3SBenjamin Herrenschmidt } 1933184cd4a3SBenjamin Herrenschmidt 1934184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1935184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 19368fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1937184cd4a3SBenjamin Herrenschmidt 1938184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 19395780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 194065fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 194165fd766bSGavin Shan TCE_PCI_SWINV_FREE | 194265fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 19435780fb04SAlexey Kardashevskiy 1944da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 19454793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 19464793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1947184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1948184cd4a3SBenjamin Herrenschmidt 1949781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 19504617082eSAlexey Kardashevskiy /* 19514617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 19524617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 19534617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 19544617082eSAlexey Kardashevskiy */ 19554617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 19564617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 1957c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 1958ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 195974251fe2SBenjamin Herrenschmidt 1960184cd4a3SBenjamin Herrenschmidt return; 1961184cd4a3SBenjamin Herrenschmidt fail: 1962184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1963184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1964184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1965184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1966184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 19670eaf4defSAlexey Kardashevskiy if (tbl) { 19680eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 19690eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19700eaf4defSAlexey Kardashevskiy } 1971184cd4a3SBenjamin Herrenschmidt } 1972184cd4a3SBenjamin Herrenschmidt 197343cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 197443cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 197543cb60abSAlexey Kardashevskiy { 197643cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 197743cb60abSAlexey Kardashevskiy table_group); 197843cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 197943cb60abSAlexey Kardashevskiy int64_t rc; 1980bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1981bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 198243cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 198343cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 198443cb60abSAlexey Kardashevskiy 19854793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 198643cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 198743cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 198843cb60abSAlexey Kardashevskiy 198943cb60abSAlexey Kardashevskiy /* 199043cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 199143cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 199243cb60abSAlexey Kardashevskiy */ 199343cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 199443cb60abSAlexey Kardashevskiy pe->pe_number, 19954793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 1996bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 199743cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 1998bbb845c4SAlexey Kardashevskiy size << 3, 199943cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 200043cb60abSAlexey Kardashevskiy if (rc) { 200143cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 200243cb60abSAlexey Kardashevskiy return rc; 200343cb60abSAlexey Kardashevskiy } 200443cb60abSAlexey Kardashevskiy 200543cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 200643cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 200743cb60abSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 200843cb60abSAlexey Kardashevskiy 200943cb60abSAlexey Kardashevskiy return 0; 201043cb60abSAlexey Kardashevskiy } 201143cb60abSAlexey Kardashevskiy 2012f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2013cd15b048SBenjamin Herrenschmidt { 2014cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2015cd15b048SBenjamin Herrenschmidt int64_t rc; 2016cd15b048SBenjamin Herrenschmidt 2017cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2018cd15b048SBenjamin Herrenschmidt if (enable) { 2019cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2020cd15b048SBenjamin Herrenschmidt 2021cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2022cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2023cd15b048SBenjamin Herrenschmidt pe->pe_number, 2024cd15b048SBenjamin Herrenschmidt window_id, 2025cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2026cd15b048SBenjamin Herrenschmidt top); 2027cd15b048SBenjamin Herrenschmidt } else { 2028cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2029cd15b048SBenjamin Herrenschmidt pe->pe_number, 2030cd15b048SBenjamin Herrenschmidt window_id, 2031cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2032cd15b048SBenjamin Herrenschmidt 0); 2033cd15b048SBenjamin Herrenschmidt } 2034cd15b048SBenjamin Herrenschmidt if (rc) 2035cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2036cd15b048SBenjamin Herrenschmidt else 2037cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2038cd15b048SBenjamin Herrenschmidt } 2039cd15b048SBenjamin Herrenschmidt 20404793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 20414793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 20424793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 20434793d65dSAlexey Kardashevskiy 20444793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 20454793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 20464793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 20474793d65dSAlexey Kardashevskiy { 20484793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 20494793d65dSAlexey Kardashevskiy table_group); 20504793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 20514793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 20524793d65dSAlexey Kardashevskiy long ret; 20534793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 20544793d65dSAlexey Kardashevskiy 20554793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 20564793d65dSAlexey Kardashevskiy if (!tbl) 20574793d65dSAlexey Kardashevskiy return -ENOMEM; 20584793d65dSAlexey Kardashevskiy 20594793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 20604793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 20614793d65dSAlexey Kardashevskiy levels, tbl); 20624793d65dSAlexey Kardashevskiy if (ret) { 20634793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 20644793d65dSAlexey Kardashevskiy return ret; 20654793d65dSAlexey Kardashevskiy } 20664793d65dSAlexey Kardashevskiy 20674793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 20684793d65dSAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 20694793d65dSAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 20704793d65dSAlexey Kardashevskiy 20714793d65dSAlexey Kardashevskiy *ptbl = tbl; 20724793d65dSAlexey Kardashevskiy 20734793d65dSAlexey Kardashevskiy return 0; 20744793d65dSAlexey Kardashevskiy } 20754793d65dSAlexey Kardashevskiy 2076f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 207700547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 207800547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 207900547193SAlexey Kardashevskiy { 208000547193SAlexey Kardashevskiy unsigned long bytes = 0; 208100547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 208200547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 208300547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 208400547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 208500547193SAlexey Kardashevskiy unsigned long direct_table_size; 208600547193SAlexey Kardashevskiy 208700547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 208800547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 208900547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 209000547193SAlexey Kardashevskiy return 0; 209100547193SAlexey Kardashevskiy 209200547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 209300547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 209400547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 209500547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 209600547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 209700547193SAlexey Kardashevskiy 209800547193SAlexey Kardashevskiy for ( ; levels; --levels) { 209900547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 210000547193SAlexey Kardashevskiy 210100547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 210200547193SAlexey Kardashevskiy tce_table_size <<= 3; 210300547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 210400547193SAlexey Kardashevskiy } 210500547193SAlexey Kardashevskiy 210600547193SAlexey Kardashevskiy return bytes; 210700547193SAlexey Kardashevskiy } 210800547193SAlexey Kardashevskiy 21094793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 21104793d65dSAlexey Kardashevskiy int num) 21114793d65dSAlexey Kardashevskiy { 21124793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 21134793d65dSAlexey Kardashevskiy table_group); 21144793d65dSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 21154793d65dSAlexey Kardashevskiy long ret; 21164793d65dSAlexey Kardashevskiy 21174793d65dSAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 21184793d65dSAlexey Kardashevskiy 21194793d65dSAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 21204793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 21214793d65dSAlexey Kardashevskiy 0/* levels */, 0/* table address */, 21224793d65dSAlexey Kardashevskiy 0/* table size */, 0/* page size */); 21234793d65dSAlexey Kardashevskiy if (ret) 21244793d65dSAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 21254793d65dSAlexey Kardashevskiy else 21264793d65dSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 21274793d65dSAlexey Kardashevskiy 21284793d65dSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 21294793d65dSAlexey Kardashevskiy 21304793d65dSAlexey Kardashevskiy return ret; 21314793d65dSAlexey Kardashevskiy } 21324793d65dSAlexey Kardashevskiy 2133f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2134cd15b048SBenjamin Herrenschmidt { 2135f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2136f87a8864SAlexey Kardashevskiy table_group); 2137cd15b048SBenjamin Herrenschmidt 2138f87a8864SAlexey Kardashevskiy iommu_take_ownership(table_group->tables[0]); 2139f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 2140cd15b048SBenjamin Herrenschmidt } 2141cd15b048SBenjamin Herrenschmidt 2142f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2143f87a8864SAlexey Kardashevskiy { 2144f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2145f87a8864SAlexey Kardashevskiy table_group); 2146f87a8864SAlexey Kardashevskiy 2147f87a8864SAlexey Kardashevskiy iommu_release_ownership(table_group->tables[0]); 2148f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 2149f87a8864SAlexey Kardashevskiy } 2150f87a8864SAlexey Kardashevskiy 2151f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 215200547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 21534793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 21544793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 21554793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2156f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2157f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2158f87a8864SAlexey Kardashevskiy }; 2159f87a8864SAlexey Kardashevskiy #endif 2160f87a8864SAlexey Kardashevskiy 21615780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 21625780fb04SAlexey Kardashevskiy { 21635780fb04SAlexey Kardashevskiy const __be64 *swinvp; 21645780fb04SAlexey Kardashevskiy 21655780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 21665780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 21675780fb04SAlexey Kardashevskiy if (!swinvp) 21685780fb04SAlexey Kardashevskiy return; 21695780fb04SAlexey Kardashevskiy 21705780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 21715780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 21725780fb04SAlexey Kardashevskiy } 21735780fb04SAlexey Kardashevskiy 2174bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2175bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 2176bbb845c4SAlexey Kardashevskiy unsigned long *current_offset) 2177aca6913fSAlexey Kardashevskiy { 2178aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2179bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2180aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2181bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2182bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2183bbb845c4SAlexey Kardashevskiy long i; 2184aca6913fSAlexey Kardashevskiy 2185aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2186aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2187aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2188aca6913fSAlexey Kardashevskiy return NULL; 2189aca6913fSAlexey Kardashevskiy } 2190aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2191bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 2192bbb845c4SAlexey Kardashevskiy 2193bbb845c4SAlexey Kardashevskiy --levels; 2194bbb845c4SAlexey Kardashevskiy if (!levels) { 2195bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2196bbb845c4SAlexey Kardashevskiy return addr; 2197bbb845c4SAlexey Kardashevskiy } 2198bbb845c4SAlexey Kardashevskiy 2199bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2200bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2201bbb845c4SAlexey Kardashevskiy levels, limit, current_offset); 2202bbb845c4SAlexey Kardashevskiy if (!tmp) 2203bbb845c4SAlexey Kardashevskiy break; 2204bbb845c4SAlexey Kardashevskiy 2205bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2206bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2207bbb845c4SAlexey Kardashevskiy 2208bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2209bbb845c4SAlexey Kardashevskiy break; 2210bbb845c4SAlexey Kardashevskiy } 2211aca6913fSAlexey Kardashevskiy 2212aca6913fSAlexey Kardashevskiy return addr; 2213aca6913fSAlexey Kardashevskiy } 2214aca6913fSAlexey Kardashevskiy 2215bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2216bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2217bbb845c4SAlexey Kardashevskiy 2218aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2219bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2220bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2221aca6913fSAlexey Kardashevskiy { 2222aca6913fSAlexey Kardashevskiy void *addr; 2223bbb845c4SAlexey Kardashevskiy unsigned long offset = 0, level_shift; 2224aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2225aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2226aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2227aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2228aca6913fSAlexey Kardashevskiy 2229bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2230bbb845c4SAlexey Kardashevskiy return -EINVAL; 2231bbb845c4SAlexey Kardashevskiy 2232aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2233aca6913fSAlexey Kardashevskiy return -EINVAL; 2234aca6913fSAlexey Kardashevskiy 2235bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2236bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2237bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2238bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2239bbb845c4SAlexey Kardashevskiy 2240aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2241bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2242bbb845c4SAlexey Kardashevskiy levels, tce_table_size, &offset); 2243bbb845c4SAlexey Kardashevskiy 2244bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2245aca6913fSAlexey Kardashevskiy if (!addr) 2246aca6913fSAlexey Kardashevskiy return -ENOMEM; 2247aca6913fSAlexey Kardashevskiy 2248bbb845c4SAlexey Kardashevskiy /* 2249bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2250bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2251bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2252bbb845c4SAlexey Kardashevskiy */ 2253bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2254bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2255bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2256bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2257bbb845c4SAlexey Kardashevskiy } 2258bbb845c4SAlexey Kardashevskiy 2259aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2260aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2261aca6913fSAlexey Kardashevskiy page_shift); 2262bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2263bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 226400547193SAlexey Kardashevskiy tbl->it_allocated_size = offset; 2265aca6913fSAlexey Kardashevskiy 2266aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2267aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2268aca6913fSAlexey Kardashevskiy 2269aca6913fSAlexey Kardashevskiy return 0; 2270aca6913fSAlexey Kardashevskiy } 2271aca6913fSAlexey Kardashevskiy 2272bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2273bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2274bbb845c4SAlexey Kardashevskiy { 2275bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2276bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2277bbb845c4SAlexey Kardashevskiy 2278bbb845c4SAlexey Kardashevskiy if (level) { 2279bbb845c4SAlexey Kardashevskiy long i; 2280bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2281bbb845c4SAlexey Kardashevskiy 2282bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2283bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2284bbb845c4SAlexey Kardashevskiy 2285bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2286bbb845c4SAlexey Kardashevskiy continue; 2287bbb845c4SAlexey Kardashevskiy 2288bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2289bbb845c4SAlexey Kardashevskiy level - 1); 2290bbb845c4SAlexey Kardashevskiy } 2291bbb845c4SAlexey Kardashevskiy } 2292bbb845c4SAlexey Kardashevskiy 2293bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2294bbb845c4SAlexey Kardashevskiy } 2295bbb845c4SAlexey Kardashevskiy 2296aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2297aca6913fSAlexey Kardashevskiy { 2298bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2299bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2300bbb845c4SAlexey Kardashevskiy 2301aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2302aca6913fSAlexey Kardashevskiy return; 2303aca6913fSAlexey Kardashevskiy 2304bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2305bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2306aca6913fSAlexey Kardashevskiy } 2307aca6913fSAlexey Kardashevskiy 2308373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2309373f5657SGavin Shan struct pnv_ioda_pe *pe) 2310373f5657SGavin Shan { 23114793d65dSAlexey Kardashevskiy struct iommu_table *tbl = NULL; 2312373f5657SGavin Shan int64_t rc; 2313373f5657SGavin Shan 2314373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 2315373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 2316373f5657SGavin Shan return; 2317373f5657SGavin Shan 2318f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2319f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2320f87a8864SAlexey Kardashevskiy 2321b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2322b348aa65SAlexey Kardashevskiy pe->pe_number); 2323c5773822SAlexey Kardashevskiy 2324373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2325373f5657SGavin Shan pe->tce32_seg = 0; 2326373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2327aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2328373f5657SGavin Shan 2329e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 23304793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 23314793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 23324793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 23334793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 23344793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 23354793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 23364793d65dSAlexey Kardashevskiy 23374793d65dSAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 23384793d65dSAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 23394793d65dSAlexey Kardashevskiy pe->table_group.tce32_size, 23404793d65dSAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2341aca6913fSAlexey Kardashevskiy if (rc) { 2342aca6913fSAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", rc); 2343aca6913fSAlexey Kardashevskiy goto fail; 2344aca6913fSAlexey Kardashevskiy } 23454793d65dSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2346e5aad1e6SAlexey Kardashevskiy 2347e5aad1e6SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 2348e5aad1e6SAlexey Kardashevskiy iommu_init_table(tbl, phb->hose->node); 2349e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2350e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2351e5aad1e6SAlexey Kardashevskiy #endif 2352e5aad1e6SAlexey Kardashevskiy 235343cb60abSAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2354373f5657SGavin Shan if (rc) { 2355373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 2356373f5657SGavin Shan " err %ld\n", rc); 2357373f5657SGavin Shan goto fail; 2358373f5657SGavin Shan } 2359373f5657SGavin Shan 2360373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 23615780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 236265fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 23635780fb04SAlexey Kardashevskiy 2364781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 23654617082eSAlexey Kardashevskiy /* 23664617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 23674617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 23684617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 23694617082eSAlexey Kardashevskiy */ 23704617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 23714617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2372c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2373ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 237474251fe2SBenjamin Herrenschmidt 2375cd15b048SBenjamin Herrenschmidt /* Also create a bypass window */ 23764e287840SThadeu Lima de Souza Cascardo if (!pnv_iommu_bypass_disabled) 2377f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 23784e287840SThadeu Lima de Souza Cascardo 2379373f5657SGavin Shan return; 2380373f5657SGavin Shan fail: 2381373f5657SGavin Shan if (pe->tce32_seg >= 0) 2382373f5657SGavin Shan pe->tce32_seg = -1; 23830eaf4defSAlexey Kardashevskiy if (tbl) { 2384aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 23850eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 23860eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 23870eaf4defSAlexey Kardashevskiy } 2388373f5657SGavin Shan } 2389373f5657SGavin Shan 2390cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2391184cd4a3SBenjamin Herrenschmidt { 2392184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 2393184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 2394184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 2395184cd4a3SBenjamin Herrenschmidt 2396184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 2397184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 2398184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 2399184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 2400184cd4a3SBenjamin Herrenschmidt */ 2401184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 2402184cd4a3SBenjamin Herrenschmidt residual = 0; 2403184cd4a3SBenjamin Herrenschmidt else 2404184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 2405184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 2406184cd4a3SBenjamin Herrenschmidt 2407184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 2408184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 2409184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 2410184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 2411184cd4a3SBenjamin Herrenschmidt 24125780fb04SAlexey Kardashevskiy pnv_pci_ioda_setup_opal_tce_kill(phb); 24135780fb04SAlexey Kardashevskiy 2414184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 2415184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 2416184cd4a3SBenjamin Herrenschmidt * weight 2417184cd4a3SBenjamin Herrenschmidt */ 2418184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 2419184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 2420184cd4a3SBenjamin Herrenschmidt base = 0; 24217ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 2422184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 2423184cd4a3SBenjamin Herrenschmidt continue; 2424184cd4a3SBenjamin Herrenschmidt if (!remaining) { 2425184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 2426184cd4a3SBenjamin Herrenschmidt continue; 2427184cd4a3SBenjamin Herrenschmidt } 2428184cd4a3SBenjamin Herrenschmidt segs = 1; 2429184cd4a3SBenjamin Herrenschmidt if (residual) { 2430184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 2431184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 2432184cd4a3SBenjamin Herrenschmidt segs = remaining; 2433184cd4a3SBenjamin Herrenschmidt } 2434373f5657SGavin Shan 2435373f5657SGavin Shan /* 2436373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 2437373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 2438373f5657SGavin Shan * the specific PE. 2439373f5657SGavin Shan */ 2440373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 2441184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 2442184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 2443184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 2444373f5657SGavin Shan } else { 2445373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 2446373f5657SGavin Shan segs = 0; 2447373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 2448373f5657SGavin Shan } 2449373f5657SGavin Shan 2450184cd4a3SBenjamin Herrenschmidt remaining -= segs; 2451184cd4a3SBenjamin Herrenschmidt base += segs; 2452184cd4a3SBenjamin Herrenschmidt } 2453184cd4a3SBenjamin Herrenschmidt } 2454184cd4a3SBenjamin Herrenschmidt 2455184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2456137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2457137436c9SGavin Shan { 2458137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2459137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2460137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2461137436c9SGavin Shan ioda.irq_chip); 2462137436c9SGavin Shan int64_t rc; 2463137436c9SGavin Shan 2464137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2465137436c9SGavin Shan WARN_ON_ONCE(rc); 2466137436c9SGavin Shan 2467137436c9SGavin Shan icp_native_eoi(d); 2468137436c9SGavin Shan } 2469137436c9SGavin Shan 2470fd9a1c26SIan Munsie 2471fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2472fd9a1c26SIan Munsie { 2473fd9a1c26SIan Munsie struct irq_data *idata; 2474fd9a1c26SIan Munsie struct irq_chip *ichip; 2475fd9a1c26SIan Munsie 2476fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2477fd9a1c26SIan Munsie return; 2478fd9a1c26SIan Munsie 2479fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2480fd9a1c26SIan Munsie /* 2481fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2482fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2483fd9a1c26SIan Munsie */ 2484fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2485fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2486fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2487fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2488fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2489fd9a1c26SIan Munsie } 2490fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2491fd9a1c26SIan Munsie } 2492fd9a1c26SIan Munsie 249380c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 249480c49c7eSIan Munsie 24956f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 249680c49c7eSIan Munsie { 249780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 249880c49c7eSIan Munsie 24996f963ec2SRyan Grimm return of_node_get(hose->dn); 250080c49c7eSIan Munsie } 25016f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 250280c49c7eSIan Munsie 25031212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 250480c49c7eSIan Munsie { 250580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 250680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 250780c49c7eSIan Munsie struct pnv_ioda_pe *pe; 250880c49c7eSIan Munsie int rc; 250980c49c7eSIan Munsie 251080c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 251180c49c7eSIan Munsie if (!pe) 251280c49c7eSIan Munsie return -ENODEV; 251380c49c7eSIan Munsie 251480c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 251580c49c7eSIan Munsie 25161212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 251780c49c7eSIan Munsie if (rc) 251880c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 251980c49c7eSIan Munsie 252080c49c7eSIan Munsie return rc; 252180c49c7eSIan Munsie } 25221212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 252380c49c7eSIan Munsie 252480c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 252580c49c7eSIan Munsie * Returns the absolute hardware IRQ number 252680c49c7eSIan Munsie */ 252780c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 252880c49c7eSIan Munsie { 252980c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 253080c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 253180c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 253280c49c7eSIan Munsie 253380c49c7eSIan Munsie if (hwirq < 0) { 253480c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 253580c49c7eSIan Munsie return -ENOSPC; 253680c49c7eSIan Munsie } 253780c49c7eSIan Munsie 253880c49c7eSIan Munsie return phb->msi_base + hwirq; 253980c49c7eSIan Munsie } 254080c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 254180c49c7eSIan Munsie 254280c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 254380c49c7eSIan Munsie { 254480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 254580c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 254680c49c7eSIan Munsie 254780c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 254880c49c7eSIan Munsie } 254980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 255080c49c7eSIan Munsie 255180c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 255280c49c7eSIan Munsie struct pci_dev *dev) 255380c49c7eSIan Munsie { 255480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 255580c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 255680c49c7eSIan Munsie int i, hwirq; 255780c49c7eSIan Munsie 255880c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 255980c49c7eSIan Munsie if (!irqs->range[i]) 256080c49c7eSIan Munsie continue; 256180c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 256280c49c7eSIan Munsie i, irqs->offset[i], 256380c49c7eSIan Munsie irqs->range[i]); 256480c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 256580c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 256680c49c7eSIan Munsie irqs->range[i]); 256780c49c7eSIan Munsie } 256880c49c7eSIan Munsie } 256980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 257080c49c7eSIan Munsie 257180c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 257280c49c7eSIan Munsie struct pci_dev *dev, int num) 257380c49c7eSIan Munsie { 257480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 257580c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 257680c49c7eSIan Munsie int i, hwirq, try; 257780c49c7eSIan Munsie 257880c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 257980c49c7eSIan Munsie 258080c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 258180c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 258280c49c7eSIan Munsie try = num; 258380c49c7eSIan Munsie while (try) { 258480c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 258580c49c7eSIan Munsie if (hwirq >= 0) 258680c49c7eSIan Munsie break; 258780c49c7eSIan Munsie try /= 2; 258880c49c7eSIan Munsie } 258980c49c7eSIan Munsie if (!try) 259080c49c7eSIan Munsie goto fail; 259180c49c7eSIan Munsie 259280c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 259380c49c7eSIan Munsie irqs->range[i] = try; 259480c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 259580c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 259680c49c7eSIan Munsie num -= try; 259780c49c7eSIan Munsie } 259880c49c7eSIan Munsie if (num) 259980c49c7eSIan Munsie goto fail; 260080c49c7eSIan Munsie 260180c49c7eSIan Munsie return 0; 260280c49c7eSIan Munsie fail: 260380c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 260480c49c7eSIan Munsie return -ENOSPC; 260580c49c7eSIan Munsie } 260680c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 260780c49c7eSIan Munsie 260880c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 260980c49c7eSIan Munsie { 261080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 261180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 261280c49c7eSIan Munsie 261380c49c7eSIan Munsie return phb->msi_bmp.irq_count; 261480c49c7eSIan Munsie } 261580c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 261680c49c7eSIan Munsie 261780c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 261880c49c7eSIan Munsie unsigned int virq) 261980c49c7eSIan Munsie { 262080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 262180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 262280c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 262380c49c7eSIan Munsie struct pnv_ioda_pe *pe; 262480c49c7eSIan Munsie int rc; 262580c49c7eSIan Munsie 262680c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 262780c49c7eSIan Munsie return -ENODEV; 262880c49c7eSIan Munsie 262980c49c7eSIan Munsie /* Assign XIVE to PE */ 263080c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 263180c49c7eSIan Munsie if (rc) { 263280c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 263380c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 263480c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 263580c49c7eSIan Munsie return -EIO; 263680c49c7eSIan Munsie } 263780c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 263880c49c7eSIan Munsie 263980c49c7eSIan Munsie return 0; 264080c49c7eSIan Munsie } 264180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 264280c49c7eSIan Munsie #endif 264380c49c7eSIan Munsie 2644184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2645137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2646137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2647184cd4a3SBenjamin Herrenschmidt { 2648184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2649184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 26503a1a4661SBenjamin Herrenschmidt __be32 data; 2651184cd4a3SBenjamin Herrenschmidt int rc; 2652184cd4a3SBenjamin Herrenschmidt 2653184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2654184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2655184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2656184cd4a3SBenjamin Herrenschmidt 2657184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2658184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2659184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2660184cd4a3SBenjamin Herrenschmidt 2661b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 266236074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2663b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2664b72c1f65SBenjamin Herrenschmidt 2665184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2666184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2667184cd4a3SBenjamin Herrenschmidt if (rc) { 2668184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2669184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2670184cd4a3SBenjamin Herrenschmidt return -EIO; 2671184cd4a3SBenjamin Herrenschmidt } 2672184cd4a3SBenjamin Herrenschmidt 2673184cd4a3SBenjamin Herrenschmidt if (is_64) { 26743a1a4661SBenjamin Herrenschmidt __be64 addr64; 26753a1a4661SBenjamin Herrenschmidt 2676184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2677184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2678184cd4a3SBenjamin Herrenschmidt if (rc) { 2679184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2680184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2681184cd4a3SBenjamin Herrenschmidt return -EIO; 2682184cd4a3SBenjamin Herrenschmidt } 26833a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 26843a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2685184cd4a3SBenjamin Herrenschmidt } else { 26863a1a4661SBenjamin Herrenschmidt __be32 addr32; 26873a1a4661SBenjamin Herrenschmidt 2688184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2689184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2690184cd4a3SBenjamin Herrenschmidt if (rc) { 2691184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2692184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2693184cd4a3SBenjamin Herrenschmidt return -EIO; 2694184cd4a3SBenjamin Herrenschmidt } 2695184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 26963a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2697184cd4a3SBenjamin Herrenschmidt } 26983a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2699184cd4a3SBenjamin Herrenschmidt 2700fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2701137436c9SGavin Shan 2702184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2703184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2704184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2705184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2706184cd4a3SBenjamin Herrenschmidt 2707184cd4a3SBenjamin Herrenschmidt return 0; 2708184cd4a3SBenjamin Herrenschmidt } 2709184cd4a3SBenjamin Herrenschmidt 2710184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2711184cd4a3SBenjamin Herrenschmidt { 2712fb1b55d6SGavin Shan unsigned int count; 2713184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2714184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2715184cd4a3SBenjamin Herrenschmidt if (!prop) { 2716184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2717184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2718184cd4a3SBenjamin Herrenschmidt } 2719184cd4a3SBenjamin Herrenschmidt if (!prop) 2720184cd4a3SBenjamin Herrenschmidt return; 2721184cd4a3SBenjamin Herrenschmidt 2722184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2723fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2724fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2725184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2726184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2727184cd4a3SBenjamin Herrenschmidt return; 2728184cd4a3SBenjamin Herrenschmidt } 2729fb1b55d6SGavin Shan 2730184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2731184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2732184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2733fb1b55d6SGavin Shan count, phb->msi_base); 2734184cd4a3SBenjamin Herrenschmidt } 2735184cd4a3SBenjamin Herrenschmidt #else 2736184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2737184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2738184cd4a3SBenjamin Herrenschmidt 27396e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 27406e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 27416e628c7dSWei Yang { 27426e628c7dSWei Yang struct pci_controller *hose; 27436e628c7dSWei Yang struct pnv_phb *phb; 27446e628c7dSWei Yang struct resource *res; 27456e628c7dSWei Yang int i; 27466e628c7dSWei Yang resource_size_t size; 27476e628c7dSWei Yang struct pci_dn *pdn; 27485b88ec22SWei Yang int mul, total_vfs; 27496e628c7dSWei Yang 27506e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 27516e628c7dSWei Yang return; 27526e628c7dSWei Yang 27536e628c7dSWei Yang hose = pci_bus_to_host(pdev->bus); 27546e628c7dSWei Yang phb = hose->private_data; 27556e628c7dSWei Yang 27566e628c7dSWei Yang pdn = pci_get_pdn(pdev); 27576e628c7dSWei Yang pdn->vfs_expanded = 0; 27586e628c7dSWei Yang 27595b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 27605b88ec22SWei Yang pdn->m64_per_iov = 1; 27615b88ec22SWei Yang mul = phb->ioda.total_pe; 27625b88ec22SWei Yang 27635b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27645b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 27655b88ec22SWei Yang if (!res->flags || res->parent) 27665b88ec22SWei Yang continue; 27675b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 27685b88ec22SWei Yang dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n", 27695b88ec22SWei Yang i, res); 27705b88ec22SWei Yang continue; 27715b88ec22SWei Yang } 27725b88ec22SWei Yang 27735b88ec22SWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 27745b88ec22SWei Yang 27755b88ec22SWei Yang /* bigger than 64M */ 27765b88ec22SWei Yang if (size > (1 << 26)) { 27775b88ec22SWei Yang dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n", 27785b88ec22SWei Yang i, res); 27795b88ec22SWei Yang pdn->m64_per_iov = M64_PER_IOV; 27805b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 27815b88ec22SWei Yang break; 27825b88ec22SWei Yang } 27835b88ec22SWei Yang } 27845b88ec22SWei Yang 27856e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27866e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 27876e628c7dSWei Yang if (!res->flags || res->parent) 27886e628c7dSWei Yang continue; 27896e628c7dSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 27906e628c7dSWei Yang dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n", 27916e628c7dSWei Yang i, res); 27926e628c7dSWei Yang continue; 27936e628c7dSWei Yang } 27946e628c7dSWei Yang 27956e628c7dSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 27966e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 27975b88ec22SWei Yang res->end = res->start + size * mul - 1; 27986e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 27996e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 28005b88ec22SWei Yang i, res, mul); 28016e628c7dSWei Yang } 28025b88ec22SWei Yang pdn->vfs_expanded = mul; 28036e628c7dSWei Yang } 28046e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 28056e628c7dSWei Yang 280611685becSGavin Shan /* 280711685becSGavin Shan * This function is supposed to be called on basis of PE from top 280811685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 280911685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 281011685becSGavin Shan */ 2811cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 281211685becSGavin Shan struct pnv_ioda_pe *pe) 281311685becSGavin Shan { 281411685becSGavin Shan struct pnv_phb *phb = hose->private_data; 281511685becSGavin Shan struct pci_bus_region region; 281611685becSGavin Shan struct resource *res; 281711685becSGavin Shan int i, index; 281811685becSGavin Shan int rc; 281911685becSGavin Shan 282011685becSGavin Shan /* 282111685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 282211685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 282311685becSGavin Shan * be figured out later. 282411685becSGavin Shan */ 282511685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 282611685becSGavin Shan 282711685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 282811685becSGavin Shan if (!res || !res->flags || 282911685becSGavin Shan res->start > res->end) 283011685becSGavin Shan continue; 283111685becSGavin Shan 283211685becSGavin Shan if (res->flags & IORESOURCE_IO) { 283311685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 283411685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 283511685becSGavin Shan index = region.start / phb->ioda.io_segsize; 283611685becSGavin Shan 283711685becSGavin Shan while (index < phb->ioda.total_pe && 283811685becSGavin Shan region.start <= region.end) { 283911685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 284011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 284111685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 284211685becSGavin Shan if (rc != OPAL_SUCCESS) { 284311685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 284411685becSGavin Shan "segment #%d to PE#%d\n", 284511685becSGavin Shan __func__, rc, index, pe->pe_number); 284611685becSGavin Shan break; 284711685becSGavin Shan } 284811685becSGavin Shan 284911685becSGavin Shan region.start += phb->ioda.io_segsize; 285011685becSGavin Shan index++; 285111685becSGavin Shan } 2852027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 2853027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 285411685becSGavin Shan region.start = res->start - 28553fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 285611685becSGavin Shan phb->ioda.m32_pci_base; 285711685becSGavin Shan region.end = res->end - 28583fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 285911685becSGavin Shan phb->ioda.m32_pci_base; 286011685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 286111685becSGavin Shan 286211685becSGavin Shan while (index < phb->ioda.total_pe && 286311685becSGavin Shan region.start <= region.end) { 286411685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 286511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 286611685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 286711685becSGavin Shan if (rc != OPAL_SUCCESS) { 286811685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 286911685becSGavin Shan "segment#%d to PE#%d", 287011685becSGavin Shan __func__, rc, index, pe->pe_number); 287111685becSGavin Shan break; 287211685becSGavin Shan } 287311685becSGavin Shan 287411685becSGavin Shan region.start += phb->ioda.m32_segsize; 287511685becSGavin Shan index++; 287611685becSGavin Shan } 287711685becSGavin Shan } 287811685becSGavin Shan } 287911685becSGavin Shan } 288011685becSGavin Shan 2881cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 288211685becSGavin Shan { 288311685becSGavin Shan struct pci_controller *tmp, *hose; 288411685becSGavin Shan struct pnv_phb *phb; 288511685becSGavin Shan struct pnv_ioda_pe *pe; 288611685becSGavin Shan 288711685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 288811685becSGavin Shan phb = hose->private_data; 288911685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 289011685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 289111685becSGavin Shan } 289211685becSGavin Shan } 289311685becSGavin Shan } 289411685becSGavin Shan 2895cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 289613395c48SGavin Shan { 289713395c48SGavin Shan struct pci_controller *hose, *tmp; 2898db1266c8SGavin Shan struct pnv_phb *phb; 289913395c48SGavin Shan 290013395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 290113395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 2902db1266c8SGavin Shan 2903db1266c8SGavin Shan /* Mark the PHB initialization done */ 2904db1266c8SGavin Shan phb = hose->private_data; 2905db1266c8SGavin Shan phb->initialized = 1; 290613395c48SGavin Shan } 290713395c48SGavin Shan } 290813395c48SGavin Shan 290937c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 291037c367f2SGavin Shan { 291137c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 291237c367f2SGavin Shan struct pci_controller *hose, *tmp; 291337c367f2SGavin Shan struct pnv_phb *phb; 291437c367f2SGavin Shan char name[16]; 291537c367f2SGavin Shan 291637c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 291737c367f2SGavin Shan phb = hose->private_data; 291837c367f2SGavin Shan 291937c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 292037c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 292137c367f2SGavin Shan if (!phb->dbgfs) 292237c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 292337c367f2SGavin Shan __func__, hose->global_number); 292437c367f2SGavin Shan } 292537c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 292637c367f2SGavin Shan } 292737c367f2SGavin Shan 2928cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2929fb446ad0SGavin Shan { 2930fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 293111685becSGavin Shan pnv_pci_ioda_setup_seg(); 293213395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 2933e9cc17d4SGavin Shan 293437c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 293537c367f2SGavin Shan 2936e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2937e9cc17d4SGavin Shan eeh_init(); 2938dadcd6d6SMike Qiu eeh_addr_cache_build(); 2939e9cc17d4SGavin Shan #endif 2940fb446ad0SGavin Shan } 2941fb446ad0SGavin Shan 2942271fd03aSGavin Shan /* 2943271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2944271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2945271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2946271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2947271fd03aSGavin Shan * 1MiB for memory) will be returned. 2948271fd03aSGavin Shan * 2949271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2950271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2951271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2952271fd03aSGavin Shan * resources. 2953271fd03aSGavin Shan */ 2954271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2955271fd03aSGavin Shan unsigned long type) 2956271fd03aSGavin Shan { 2957271fd03aSGavin Shan struct pci_dev *bridge; 2958271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 2959271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 2960271fd03aSGavin Shan int num_pci_bridges = 0; 2961271fd03aSGavin Shan 2962271fd03aSGavin Shan bridge = bus->self; 2963271fd03aSGavin Shan while (bridge) { 2964271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2965271fd03aSGavin Shan num_pci_bridges++; 2966271fd03aSGavin Shan if (num_pci_bridges >= 2) 2967271fd03aSGavin Shan return 1; 2968271fd03aSGavin Shan } 2969271fd03aSGavin Shan 2970271fd03aSGavin Shan bridge = bridge->bus->self; 2971271fd03aSGavin Shan } 2972271fd03aSGavin Shan 2973262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 2974262af557SGuo Chao if (phb->ioda.m64_segsize && 2975262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 2976262af557SGuo Chao return phb->ioda.m64_segsize; 2977271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2978271fd03aSGavin Shan return phb->ioda.m32_segsize; 2979271fd03aSGavin Shan 2980271fd03aSGavin Shan return phb->ioda.io_segsize; 2981271fd03aSGavin Shan } 2982271fd03aSGavin Shan 29835350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 29845350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 29855350ab3fSWei Yang int resno) 29865350ab3fSWei Yang { 29875350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 29885350ab3fSWei Yang resource_size_t align, iov_align; 29895350ab3fSWei Yang 29905350ab3fSWei Yang iov_align = resource_size(&pdev->resource[resno]); 29915350ab3fSWei Yang if (iov_align) 29925350ab3fSWei Yang return iov_align; 29935350ab3fSWei Yang 29945350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 29955350ab3fSWei Yang if (pdn->vfs_expanded) 29965350ab3fSWei Yang return pdn->vfs_expanded * align; 29975350ab3fSWei Yang 29985350ab3fSWei Yang return align; 29995350ab3fSWei Yang } 30005350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 30015350ab3fSWei Yang 3002184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3003184cd4a3SBenjamin Herrenschmidt * assign a PE 3004184cd4a3SBenjamin Herrenschmidt */ 3005c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3006184cd4a3SBenjamin Herrenschmidt { 3007db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3008db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3009db1266c8SGavin Shan struct pci_dn *pdn; 3010184cd4a3SBenjamin Herrenschmidt 3011db1266c8SGavin Shan /* The function is probably called while the PEs have 3012db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3013db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3014db1266c8SGavin Shan * PEs isn't ready. 3015db1266c8SGavin Shan */ 3016db1266c8SGavin Shan if (!phb->initialized) 3017c88c2a18SDaniel Axtens return true; 3018db1266c8SGavin Shan 3019b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3020184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3021c88c2a18SDaniel Axtens return false; 3022db1266c8SGavin Shan 3023c88c2a18SDaniel Axtens return true; 3024184cd4a3SBenjamin Herrenschmidt } 3025184cd4a3SBenjamin Herrenschmidt 3026184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 3027184cd4a3SBenjamin Herrenschmidt u32 devfn) 3028184cd4a3SBenjamin Herrenschmidt { 3029184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 3030184cd4a3SBenjamin Herrenschmidt } 3031184cd4a3SBenjamin Herrenschmidt 30327a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 303373ed148aSBenjamin Herrenschmidt { 30347a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 30357a8e6bbfSMichael Neuling 3036d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 303773ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 303873ed148aSBenjamin Herrenschmidt } 303973ed148aSBenjamin Herrenschmidt 304092ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 304192ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 304292ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 304392ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 304492ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 304592ae0353SDaniel Axtens #endif 304692ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 304792ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 304892ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3049763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 30507a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 305192ae0353SDaniel Axtens }; 305292ae0353SDaniel Axtens 3053e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3054e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3055184cd4a3SBenjamin Herrenschmidt { 3056184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3057184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 30588184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 3059c681b93cSAlistair Popple const __be64 *prop64; 30603a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3061f1b7cc3eSGavin Shan int len; 3062184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3063184cd4a3SBenjamin Herrenschmidt void *aux; 3064184cd4a3SBenjamin Herrenschmidt long rc; 3065184cd4a3SBenjamin Herrenschmidt 3066aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3067184cd4a3SBenjamin Herrenschmidt 3068184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3069184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3070184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3071184cd4a3SBenjamin Herrenschmidt return; 3072184cd4a3SBenjamin Herrenschmidt } 3073184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3074184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3075184cd4a3SBenjamin Herrenschmidt 3076e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 307758d714ecSGavin Shan 307858d714ecSGavin Shan /* Allocate PCI controller */ 3079184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 308058d714ecSGavin Shan if (!phb->hose) { 308158d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3082184cd4a3SBenjamin Herrenschmidt np->full_name); 3083e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3084184cd4a3SBenjamin Herrenschmidt return; 3085184cd4a3SBenjamin Herrenschmidt } 3086184cd4a3SBenjamin Herrenschmidt 3087184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3088f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3089f1b7cc3eSGavin Shan if (prop32 && len == 8) { 30903a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 30913a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3092f1b7cc3eSGavin Shan } else { 3093f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3094184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3095184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3096f1b7cc3eSGavin Shan } 3097184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3098e9cc17d4SGavin Shan phb->hub_id = hub_id; 3099184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3100aa0c033fSGavin Shan phb->type = ioda_type; 3101781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3102184cd4a3SBenjamin Herrenschmidt 3103cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3104cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3105cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3106f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3107aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 3108cee72d5bSBenjamin Herrenschmidt else 3109cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3110cee72d5bSBenjamin Herrenschmidt 3111aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 31122f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3113184cd4a3SBenjamin Herrenschmidt 3114aa0c033fSGavin Shan /* Get registers */ 3115184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 3116184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3117184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3118184cd4a3SBenjamin Herrenschmidt 3119184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 3120aa0c033fSGavin Shan phb->ioda.total_pe = 1; 312136954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 312236954dc7SGavin Shan if (prop32) 31233a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 312436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 312536954dc7SGavin Shan if (prop32) 312636954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 3127262af557SGuo Chao 3128262af557SGuo Chao /* Parse 64-bit MMIO range */ 3129262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3130262af557SGuo Chao 3131184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3132aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3133184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3134184cd4a3SBenjamin Herrenschmidt 3135184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 31363fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3137184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 3138184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 3139184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3140184cd4a3SBenjamin Herrenschmidt 3141c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3142184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 3143184cd4a3SBenjamin Herrenschmidt m32map_off = size; 3144e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 3145c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3146c35d2a8cSGavin Shan iomap_off = size; 3147e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 3148c35d2a8cSGavin Shan } 3149184cd4a3SBenjamin Herrenschmidt pemap_off = size; 3150184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 3151e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3152184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 3153184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 3154c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 3155184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 3156184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 315736954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 3158184cd4a3SBenjamin Herrenschmidt 31597ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 3160184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3161781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3162184cd4a3SBenjamin Herrenschmidt 3163184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 3164184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 3165184cd4a3SBenjamin Herrenschmidt 3166aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3167184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3168184cd4a3SBenjamin Herrenschmidt window_type, 3169184cd4a3SBenjamin Herrenschmidt window_num, 3170184cd4a3SBenjamin Herrenschmidt starting_real_address, 3171184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3172184cd4a3SBenjamin Herrenschmidt segment_size); 3173184cd4a3SBenjamin Herrenschmidt #endif 3174184cd4a3SBenjamin Herrenschmidt 3175262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3176262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 3177262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3178262af557SGuo Chao if (phb->ioda.m64_size) 3179262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3180262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3181262af557SGuo Chao if (phb->ioda.io_size) 3182262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3183184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3184184cd4a3SBenjamin Herrenschmidt 3185262af557SGuo Chao 3186184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 318749dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 318849dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 318949dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3190184cd4a3SBenjamin Herrenschmidt 3191184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 3192184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 3193184cd4a3SBenjamin Herrenschmidt 3194184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 3195184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3196fe7e85c6SGavin Shan phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; 3197184cd4a3SBenjamin Herrenschmidt 3198184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3199184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3200184cd4a3SBenjamin Herrenschmidt 3201c40a4210SGavin Shan /* 3202c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3203c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3204c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3205c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3206c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3207184cd4a3SBenjamin Herrenschmidt */ 3208fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 320992ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3210ad30cb99SMichael Ellerman 32116e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 32126e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 32135350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3214ad30cb99SMichael Ellerman #endif 3215ad30cb99SMichael Ellerman 3216c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3217184cd4a3SBenjamin Herrenschmidt 3218184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3219d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3220184cd4a3SBenjamin Herrenschmidt if (rc) 3221f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3222361f2a2aSGavin Shan 3223361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3224361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3225361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3226361f2a2aSGavin Shan * transactions from previous kerenl. 3227361f2a2aSGavin Shan */ 3228361f2a2aSGavin Shan if (is_kdump_kernel()) { 3229361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3230cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3231cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3232361f2a2aSGavin Shan } 3233262af557SGuo Chao 32349e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 32359e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3236262af557SGuo Chao hose->mem_resources[1].flags = 0; 3237184cd4a3SBenjamin Herrenschmidt } 3238184cd4a3SBenjamin Herrenschmidt 323967975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3240aa0c033fSGavin Shan { 3241e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3242aa0c033fSGavin Shan } 3243aa0c033fSGavin Shan 3244184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3245184cd4a3SBenjamin Herrenschmidt { 3246184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3247c681b93cSAlistair Popple const __be64 *prop64; 3248184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3249184cd4a3SBenjamin Herrenschmidt 3250184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3251184cd4a3SBenjamin Herrenschmidt 3252184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3253184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3254184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3255184cd4a3SBenjamin Herrenschmidt return; 3256184cd4a3SBenjamin Herrenschmidt } 3257184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3258184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3259184cd4a3SBenjamin Herrenschmidt 3260184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3261184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3262184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3263184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3264e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3265184cd4a3SBenjamin Herrenschmidt } 3266184cd4a3SBenjamin Herrenschmidt } 3267