16f52b16cSGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2c3617f72SDavid Howells #ifndef _ASM_POWERPC_AUXVEC_H 3c3617f72SDavid Howells #define _ASM_POWERPC_AUXVEC_H 4c3617f72SDavid Howells 5c3617f72SDavid Howells /* 6c3617f72SDavid Howells * We need to put in some extra aux table entries to tell glibc what 7c3617f72SDavid Howells * the cache block size is, so it can use the dcbz instruction safely. 8c3617f72SDavid Howells */ 9c3617f72SDavid Howells #define AT_DCACHEBSIZE 19 10c3617f72SDavid Howells #define AT_ICACHEBSIZE 20 11c3617f72SDavid Howells #define AT_UCACHEBSIZE 21 12c3617f72SDavid Howells /* A special ignored type value for PPC, for glibc compatibility. */ 13c3617f72SDavid Howells #define AT_IGNOREPPC 22 14c3617f72SDavid Howells 15c3617f72SDavid Howells /* The vDSO location. We have to use the same value as x86 for glibc's 16c3617f72SDavid Howells * sake :-) 17c3617f72SDavid Howells */ 18c3617f72SDavid Howells #define AT_SYSINFO_EHDR 33 19c3617f72SDavid Howells 2098a5f361SBenjamin Herrenschmidt /* 2198a5f361SBenjamin Herrenschmidt * AT_*CACHEBSIZE above represent the cache *block* size which is 2298a5f361SBenjamin Herrenschmidt * the size that is affected by the cache management instructions. 2398a5f361SBenjamin Herrenschmidt * 2498a5f361SBenjamin Herrenschmidt * It doesn't nececssarily matches the cache *line* size which is 2598a5f361SBenjamin Herrenschmidt * more of a performance tuning hint. Additionally the latter can 2698a5f361SBenjamin Herrenschmidt * be different for the different cache levels. 2798a5f361SBenjamin Herrenschmidt * 2898a5f361SBenjamin Herrenschmidt * The set of entries below represent more extensive information 2998a5f361SBenjamin Herrenschmidt * about the caches, in the form of two entry per cache type, 3098a5f361SBenjamin Herrenschmidt * one entry containing the cache size in bytes, and the other 3198a5f361SBenjamin Herrenschmidt * containing the cache line size in bytes in the bottom 16 bits 3298a5f361SBenjamin Herrenschmidt * and the cache associativity in the next 16 bits. 3398a5f361SBenjamin Herrenschmidt * 3498a5f361SBenjamin Herrenschmidt * The associativity is such that if N is the 16-bit value, the 3598a5f361SBenjamin Herrenschmidt * cache is N way set associative. A value if 0xffff means fully 3698a5f361SBenjamin Herrenschmidt * associative, a value of 1 means directly mapped. 3798a5f361SBenjamin Herrenschmidt * 3898a5f361SBenjamin Herrenschmidt * For all these fields, a value of 0 means that the information 3998a5f361SBenjamin Herrenschmidt * is not known. 4098a5f361SBenjamin Herrenschmidt */ 4198a5f361SBenjamin Herrenschmidt 4298a5f361SBenjamin Herrenschmidt #define AT_L1I_CACHESIZE 40 4398a5f361SBenjamin Herrenschmidt #define AT_L1I_CACHEGEOMETRY 41 4498a5f361SBenjamin Herrenschmidt #define AT_L1D_CACHESIZE 42 4598a5f361SBenjamin Herrenschmidt #define AT_L1D_CACHEGEOMETRY 43 4698a5f361SBenjamin Herrenschmidt #define AT_L2_CACHESIZE 44 4798a5f361SBenjamin Herrenschmidt #define AT_L2_CACHEGEOMETRY 45 4898a5f361SBenjamin Herrenschmidt #define AT_L3_CACHESIZE 46 4998a5f361SBenjamin Herrenschmidt #define AT_L3_CACHEGEOMETRY 47 5098a5f361SBenjamin Herrenschmidt 51*2896b2dfSNicholas Piggin #define AT_MINSIGSTKSZ 51 /* stack needed for signal delivery */ 52*2896b2dfSNicholas Piggin 53*2896b2dfSNicholas Piggin #define AT_VECTOR_SIZE_ARCH 15 /* entries in ARCH_DLINFO */ 54c3617f72SDavid Howells 55c3617f72SDavid Howells #endif 56