1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 #ifndef _ASM_POWERPC_AUXVEC_H
3 #define _ASM_POWERPC_AUXVEC_H
4 
5 /*
6  * We need to put in some extra aux table entries to tell glibc what
7  * the cache block size is, so it can use the dcbz instruction safely.
8  */
9 #define AT_DCACHEBSIZE		19
10 #define AT_ICACHEBSIZE		20
11 #define AT_UCACHEBSIZE		21
12 /* A special ignored type value for PPC, for glibc compatibility.  */
13 #define AT_IGNOREPPC		22
14 
15 /* The vDSO location. We have to use the same value as x86 for glibc's
16  * sake :-)
17  */
18 #define AT_SYSINFO_EHDR		33
19 
20 /*
21  * AT_*CACHEBSIZE above represent the cache *block* size which is
22  * the size that is affected by the cache management instructions.
23  *
24  * It doesn't nececssarily matches the cache *line* size which is
25  * more of a performance tuning hint. Additionally the latter can
26  * be different for the different cache levels.
27  *
28  * The set of entries below represent more extensive information
29  * about the caches, in the form of two entry per cache type,
30  * one entry containing the cache size in bytes, and the other
31  * containing the cache line size in bytes in the bottom 16 bits
32  * and the cache associativity in the next 16 bits.
33  *
34  * The associativity is such that if N is the 16-bit value, the
35  * cache is N way set associative. A value if 0xffff means fully
36  * associative, a value of 1 means directly mapped.
37  *
38  * For all these fields, a value of 0 means that the information
39  * is not known.
40  */
41 
42 #define AT_L1I_CACHESIZE	40
43 #define AT_L1I_CACHEGEOMETRY	41
44 #define AT_L1D_CACHESIZE	42
45 #define AT_L1D_CACHEGEOMETRY	43
46 #define AT_L2_CACHESIZE		44
47 #define AT_L2_CACHEGEOMETRY	45
48 #define AT_L3_CACHESIZE		46
49 #define AT_L3_CACHEGEOMETRY	47
50 
51 #define AT_MINSIGSTKSZ		51      /* stack needed for signal delivery */
52 
53 #define AT_VECTOR_SIZE_ARCH	15 /* entries in ARCH_DLINFO */
54 
55 #endif
56