1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_32_PTE_8xx_H
3 #define _ASM_POWERPC_NOHASH_32_PTE_8xx_H
4 #ifdef __KERNEL__
5 
6 /*
7  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
8  * We also use the two level tables, but we can put the real bits in them
9  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
10  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
11  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
12  * based upon user/super access.  The TLB does not have accessed nor write
13  * protect.  We assume that if the TLB get loaded with an entry it is
14  * accessed, and overload the changed bit for write protect.  We use
15  * two bits in the software pte that are supposed to be set to zero in
16  * the TLB entry (24 and 25) for these indicators.  Although the level 1
17  * descriptor contains the guarded and writethrough/copyback bits, we can
18  * set these at the page level since they get copied from the Mx_TWC
19  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
20  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
21  * These will get masked from the level 2 descriptor at TLB load time, and
22  * copied to the MD_TWC before it gets loaded.
23  * Large page sizes added.  We currently support two sizes, 4K and 8M.
24  * This also allows a TLB hander optimization because we can directly
25  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
26  * mapping of well known areas.  The PMD (PGD) entries contain control
27  * flags in addition to the address, so care must be taken that the
28  * software no longer assumes these are only pointers.
29  */
30 
31 /* Definitions for 8xx embedded chips. */
32 #define _PAGE_PRESENT	0x0001	/* Page is valid */
33 #define _PAGE_NO_CACHE	0x0002	/* I: cache inhibit */
34 #define _PAGE_PRIVILEGED	0x0004	/* No ASID (context) compare */
35 #define _PAGE_HUGE	0x0008	/* SPS: Small Page Size (1 if 16k, 512k or 8M)*/
36 #define _PAGE_DIRTY	0x0100	/* C: page changed */
37 
38 /* These 4 software bits must be masked out when the L2 entry is loaded
39  * into the TLB.
40  */
41 #define _PAGE_GUARDED	0x0010	/* Copied to L1 G entry in DTLB */
42 #define _PAGE_SPECIAL	0x0020	/* SW entry */
43 #define _PAGE_EXEC	0x0040	/* Copied to PP (bit 21) in ITLB */
44 #define _PAGE_ACCESSED	0x0080	/* software: page referenced */
45 
46 #define _PAGE_NA	0x0200	/* Supervisor NA, User no access */
47 #define _PAGE_RO	0x0600	/* Supervisor RO, User no access */
48 
49 #define _PMD_PRESENT	0x0001
50 #define _PMD_BAD	0x0fd0
51 #define _PMD_PAGE_MASK	0x000c
52 #define _PMD_PAGE_8M	0x000c
53 #define _PMD_PAGE_512K	0x0004
54 #define _PMD_USER	0x0020	/* APG 1 */
55 
56 /* Until my rework is finished, 8xx still needs atomic PTE updates */
57 #define PTE_ATOMIC_UPDATES	1
58 
59 #ifdef CONFIG_PPC_16K_PAGES
60 #define _PAGE_PSIZE	_PAGE_HUGE
61 #endif
62 
63 #endif /* __KERNEL__ */
64 #endif /*  _ASM_POWERPC_NOHASH_32_PTE_8xx_H */
65