1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 39 /* PACA save area offsets (exgen, exmc, etc) */ 40 #define EX_R9 0 41 #define EX_R10 8 42 #define EX_R11 16 43 #define EX_R12 24 44 #define EX_R13 32 45 #define EX_DAR 40 46 #define EX_DSISR 48 47 #define EX_CCR 52 48 #define EX_CFAR 56 49 #define EX_PPR 64 50 #if defined(CONFIG_RELOCATABLE) 51 #define EX_CTR 72 52 #define EX_SIZE 10 /* size in u64 units */ 53 #else 54 #define EX_SIZE 9 /* size in u64 units */ 55 #endif 56 57 /* 58 * maximum recursive depth of MCE exceptions 59 */ 60 #define MAX_MCE_DEPTH 4 61 62 /* 63 * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR 64 * EX_CCR similarly with DSISR, but being 4 byte registers there is a hole 65 * in the save area so it's not necessary to overlap them. Could be used 66 * for future savings though if another 4 byte register was to be saved. 67 */ 68 #define EX_LR EX_DAR 69 70 /* 71 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 72 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 73 * with EX_DAR. 74 */ 75 #define EX_R3 EX_DAR 76 77 #ifdef CONFIG_RELOCATABLE 78 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 79 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 80 LOAD_HANDLER(r12,label); \ 81 mtctr r12; \ 82 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 83 li r10,MSR_RI; \ 84 mtmsrd r10,1; /* Set RI (EE=0) */ \ 85 bctr; 86 #else 87 /* If not relocatable, we can jump directly -- and save messing with LR */ 88 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 89 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 90 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 91 li r10,MSR_RI; \ 92 mtmsrd r10,1; /* Set RI (EE=0) */ \ 93 b label; 94 #endif 95 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 96 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 97 98 /* 99 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 100 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 101 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 102 */ 103 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 104 EXCEPTION_PROLOG_0(area); \ 105 EXCEPTION_PROLOG_1(area, extra, vec); \ 106 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 107 108 /* 109 * We're short on space and time in the exception prolog, so we can't 110 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 111 * Instead we get the base of the kernel from paca->kernelbase and or in the low 112 * part of label. This requires that the label be within 64KB of kernelbase, and 113 * that kernelbase be 64K aligned. 114 */ 115 #define LOAD_HANDLER(reg, label) \ 116 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 117 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label); 118 119 #define __LOAD_HANDLER(reg, label) \ 120 ld reg,PACAKBASE(r13); \ 121 ori reg,reg,(ABS_ADDR(label))@l; 122 123 /* 124 * Branches from unrelocated code (e.g., interrupts) to labels outside 125 * head-y require >64K offsets. 126 */ 127 #define __LOAD_FAR_HANDLER(reg, label) \ 128 ld reg,PACAKBASE(r13); \ 129 ori reg,reg,(ABS_ADDR(label))@l; \ 130 addis reg,reg,(ABS_ADDR(label))@h; 131 132 /* Exception register prefixes */ 133 #define EXC_HV H 134 #define EXC_STD 135 136 #if defined(CONFIG_RELOCATABLE) 137 /* 138 * If we support interrupts with relocation on AND we're a relocatable kernel, 139 * we need to use CTR to get to the 2nd level handler. So, save/restore it 140 * when required. 141 */ 142 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 143 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 144 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 145 #else 146 /* ...else CTR is unused and in register. */ 147 #define SAVE_CTR(reg, area) 148 #define GET_CTR(reg, area) mfctr reg 149 #define RESTORE_CTR(reg, area) 150 #endif 151 152 /* 153 * PPR save/restore macros used in exceptions_64s.S 154 * Used for P7 or later processors 155 */ 156 #define SAVE_PPR(area, ra, rb) \ 157 BEGIN_FTR_SECTION_NESTED(940) \ 158 ld ra,PACACURRENT(r13); \ 159 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 160 std rb,TASKTHREADPPR(ra); \ 161 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 162 163 #define RESTORE_PPR_PACA(area, ra) \ 164 BEGIN_FTR_SECTION_NESTED(941) \ 165 ld ra,area+EX_PPR(r13); \ 166 mtspr SPRN_PPR,ra; \ 167 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 168 169 /* 170 * Get an SPR into a register if the CPU has the given feature 171 */ 172 #define OPT_GET_SPR(ra, spr, ftr) \ 173 BEGIN_FTR_SECTION_NESTED(943) \ 174 mfspr ra,spr; \ 175 END_FTR_SECTION_NESTED(ftr,ftr,943) 176 177 /* 178 * Set an SPR from a register if the CPU has the given feature 179 */ 180 #define OPT_SET_SPR(ra, spr, ftr) \ 181 BEGIN_FTR_SECTION_NESTED(943) \ 182 mtspr spr,ra; \ 183 END_FTR_SECTION_NESTED(ftr,ftr,943) 184 185 /* 186 * Save a register to the PACA if the CPU has the given feature 187 */ 188 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 189 BEGIN_FTR_SECTION_NESTED(943) \ 190 std ra,offset(r13); \ 191 END_FTR_SECTION_NESTED(ftr,ftr,943) 192 193 #define EXCEPTION_PROLOG_0(area) \ 194 GET_PACA(r13); \ 195 std r9,area+EX_R9(r13); /* save r9 */ \ 196 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 197 HMT_MEDIUM; \ 198 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 199 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 200 201 #define __EXCEPTION_PROLOG_1_PRE(area) \ 202 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 203 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 204 SAVE_CTR(r10, area); \ 205 mfcr r9; 206 207 #define __EXCEPTION_PROLOG_1_POST(area) \ 208 std r11,area+EX_R11(r13); \ 209 std r12,area+EX_R12(r13); \ 210 GET_SCRATCH0(r10); \ 211 std r10,area+EX_R13(r13) 212 213 /* 214 * This version of the EXCEPTION_PROLOG_1 will carry 215 * addition parameter called "bitmask" to support 216 * checking of the interrupt maskable level in the SOFTEN_TEST. 217 * Intended to be used in MASKABLE_EXCPETION_* macros. 218 */ 219 #define MASKABLE_EXCEPTION_PROLOG_1(area, extra, vec, bitmask) \ 220 __EXCEPTION_PROLOG_1_PRE(area); \ 221 extra(vec, bitmask); \ 222 __EXCEPTION_PROLOG_1_POST(area); 223 224 /* 225 * This version of the EXCEPTION_PROLOG_1 is intended 226 * to be used in STD_EXCEPTION* macros 227 */ 228 #define _EXCEPTION_PROLOG_1(area, extra, vec) \ 229 __EXCEPTION_PROLOG_1_PRE(area); \ 230 extra(vec); \ 231 __EXCEPTION_PROLOG_1_POST(area); 232 233 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 234 _EXCEPTION_PROLOG_1(area, extra, vec) 235 236 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ 237 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 238 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 239 LOAD_HANDLER(r12,label) \ 240 mtspr SPRN_##h##SRR0,r12; \ 241 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 242 mtspr SPRN_##h##SRR1,r10; \ 243 h##rfid; \ 244 b . /* prevent speculative execution */ 245 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ 246 __EXCEPTION_PROLOG_PSERIES_1(label, h) 247 248 /* _NORI variant keeps MSR_RI clear */ 249 #define __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 250 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 251 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \ 252 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 253 LOAD_HANDLER(r12,label) \ 254 mtspr SPRN_##h##SRR0,r12; \ 255 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 256 mtspr SPRN_##h##SRR1,r10; \ 257 h##rfid; \ 258 b . /* prevent speculative execution */ 259 260 #define EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 261 __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) 262 263 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 264 EXCEPTION_PROLOG_0(area); \ 265 EXCEPTION_PROLOG_1(area, extra, vec); \ 266 EXCEPTION_PROLOG_PSERIES_1(label, h); 267 268 #define __KVMTEST(h, n) \ 269 lbz r10,HSTATE_IN_GUEST(r13); \ 270 cmpwi r10,0; \ 271 bne do_kvm_##h##n 272 273 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 274 /* 275 * If hv is possible, interrupts come into to the hv version 276 * of the kvmppc_interrupt code, which then jumps to the PR handler, 277 * kvmppc_interrupt_pr, if the guest is a PR guest. 278 */ 279 #define kvmppc_interrupt kvmppc_interrupt_hv 280 #else 281 #define kvmppc_interrupt kvmppc_interrupt_pr 282 #endif 283 284 /* 285 * Branch to label using its 0xC000 address. This results in instruction 286 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 287 * on using mtmsr rather than rfid. 288 * 289 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 290 * load KBASE for a slight optimisation. 291 */ 292 #define BRANCH_TO_C000(reg, label) \ 293 __LOAD_HANDLER(reg, label); \ 294 mtctr reg; \ 295 bctr 296 297 #ifdef CONFIG_RELOCATABLE 298 #define BRANCH_TO_COMMON(reg, label) \ 299 __LOAD_HANDLER(reg, label); \ 300 mtctr reg; \ 301 bctr 302 303 #define BRANCH_LINK_TO_FAR(label) \ 304 __LOAD_FAR_HANDLER(r12, label); \ 305 mtctr r12; \ 306 bctrl 307 308 /* 309 * KVM requires __LOAD_FAR_HANDLER. 310 * 311 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 312 * explicitly use r9 then reload it from PACA before branching. Hence 313 * the double-underscore. 314 */ 315 #define __BRANCH_TO_KVM_EXIT(area, label) \ 316 mfctr r9; \ 317 std r9,HSTATE_SCRATCH1(r13); \ 318 __LOAD_FAR_HANDLER(r9, label); \ 319 mtctr r9; \ 320 ld r9,area+EX_R9(r13); \ 321 bctr 322 323 #else 324 #define BRANCH_TO_COMMON(reg, label) \ 325 b label 326 327 #define BRANCH_LINK_TO_FAR(label) \ 328 bl label 329 330 #define __BRANCH_TO_KVM_EXIT(area, label) \ 331 ld r9,area+EX_R9(r13); \ 332 b label 333 334 #endif 335 336 /* Do not enable RI */ 337 #define EXCEPTION_PROLOG_PSERIES_NORI(area, label, h, extra, vec) \ 338 EXCEPTION_PROLOG_0(area); \ 339 EXCEPTION_PROLOG_1(area, extra, vec); \ 340 EXCEPTION_PROLOG_PSERIES_1_NORI(label, h); 341 342 343 #define __KVM_HANDLER(area, h, n) \ 344 BEGIN_FTR_SECTION_NESTED(947) \ 345 ld r10,area+EX_CFAR(r13); \ 346 std r10,HSTATE_CFAR(r13); \ 347 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 348 BEGIN_FTR_SECTION_NESTED(948) \ 349 ld r10,area+EX_PPR(r13); \ 350 std r10,HSTATE_PPR(r13); \ 351 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 352 ld r10,area+EX_R10(r13); \ 353 std r12,HSTATE_SCRATCH0(r13); \ 354 sldi r12,r9,32; \ 355 ori r12,r12,(n); \ 356 /* This reloads r9 before branching to kvmppc_interrupt */ \ 357 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt) 358 359 #define __KVM_HANDLER_SKIP(area, h, n) \ 360 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 361 beq 89f; \ 362 BEGIN_FTR_SECTION_NESTED(948) \ 363 ld r10,area+EX_PPR(r13); \ 364 std r10,HSTATE_PPR(r13); \ 365 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 366 ld r10,area+EX_R10(r13); \ 367 std r12,HSTATE_SCRATCH0(r13); \ 368 sldi r12,r9,32; \ 369 ori r12,r12,(n); \ 370 /* This reloads r9 before branching to kvmppc_interrupt */ \ 371 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \ 372 89: mtocrf 0x80,r9; \ 373 ld r9,area+EX_R9(r13); \ 374 ld r10,area+EX_R10(r13); \ 375 b kvmppc_skip_##h##interrupt 376 377 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 378 #define KVMTEST(h, n) __KVMTEST(h, n) 379 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 380 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 381 382 #else 383 #define KVMTEST(h, n) 384 #define KVM_HANDLER(area, h, n) 385 #define KVM_HANDLER_SKIP(area, h, n) 386 #endif 387 388 #define NOTEST(n) 389 390 #define EXCEPTION_PROLOG_COMMON_1() \ 391 std r9,_CCR(r1); /* save CR in stackframe */ \ 392 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 393 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 394 std r10,0(r1); /* make stack chain pointer */ \ 395 std r0,GPR0(r1); /* save r0 in stackframe */ \ 396 std r10,GPR1(r1); /* save r1 in stackframe */ \ 397 398 399 /* 400 * The common exception prolog is used for all except a few exceptions 401 * such as a segment miss on a kernel address. We have to be prepared 402 * to take another exception from the point where we first touch the 403 * kernel stack onwards. 404 * 405 * On entry r13 points to the paca, r9-r13 are saved in the paca, 406 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 407 * SRR1, and relocation is on. 408 */ 409 #define EXCEPTION_PROLOG_COMMON(n, area) \ 410 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 411 mr r10,r1; /* Save r1 */ \ 412 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 413 beq- 1f; \ 414 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 415 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 416 blt+ cr1,3f; /* abort if it is */ \ 417 li r1,(n); /* will be reloaded later */ \ 418 sth r1,PACA_TRAP_SAVE(r13); \ 419 std r3,area+EX_R3(r13); \ 420 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 421 RESTORE_CTR(r1, area); \ 422 b bad_stack; \ 423 3: EXCEPTION_PROLOG_COMMON_1(); \ 424 beq 4f; /* if from kernel mode */ \ 425 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 426 SAVE_PPR(area, r9, r10); \ 427 4: EXCEPTION_PROLOG_COMMON_2(area) \ 428 EXCEPTION_PROLOG_COMMON_3(n) \ 429 ACCOUNT_STOLEN_TIME 430 431 /* Save original regs values from save area to stack frame. */ 432 #define EXCEPTION_PROLOG_COMMON_2(area) \ 433 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 434 ld r10,area+EX_R10(r13); \ 435 std r9,GPR9(r1); \ 436 std r10,GPR10(r1); \ 437 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 438 ld r10,area+EX_R12(r13); \ 439 ld r11,area+EX_R13(r13); \ 440 std r9,GPR11(r1); \ 441 std r10,GPR12(r1); \ 442 std r11,GPR13(r1); \ 443 BEGIN_FTR_SECTION_NESTED(66); \ 444 ld r10,area+EX_CFAR(r13); \ 445 std r10,ORIG_GPR3(r1); \ 446 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 447 GET_CTR(r10, area); \ 448 std r10,_CTR(r1); 449 450 #define EXCEPTION_PROLOG_COMMON_3(n) \ 451 std r2,GPR2(r1); /* save r2 in stackframe */ \ 452 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 453 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 454 mflr r9; /* Get LR, later save to stack */ \ 455 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 456 std r9,_LINK(r1); \ 457 lbz r10,PACAIRQSOFTMASK(r13); \ 458 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 459 std r10,SOFTE(r1); \ 460 std r11,_XER(r1); \ 461 li r9,(n)+1; \ 462 std r9,_TRAP(r1); /* set trap number */ \ 463 li r10,0; \ 464 ld r11,exception_marker@toc(r2); \ 465 std r10,RESULT(r1); /* clear regs->result */ \ 466 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 467 468 /* 469 * Exception vectors. 470 */ 471 #define STD_EXCEPTION_PSERIES(vec, label) \ 472 SET_SCRATCH0(r13); /* save r13 */ \ 473 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 474 EXC_STD, KVMTEST_PR, vec); \ 475 476 /* Version of above for when we have to branch out-of-line */ 477 #define __OOL_EXCEPTION(vec, label, hdlr) \ 478 SET_SCRATCH0(r13) \ 479 EXCEPTION_PROLOG_0(PACA_EXGEN) \ 480 b hdlr; 481 482 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \ 483 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 484 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 485 486 #define STD_EXCEPTION_HV(loc, vec, label) \ 487 SET_SCRATCH0(r13); /* save r13 */ \ 488 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 489 EXC_HV, KVMTEST_HV, vec); 490 491 #define STD_EXCEPTION_HV_OOL(vec, label) \ 492 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 493 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 494 495 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 496 /* No guest interrupts come through here */ \ 497 SET_SCRATCH0(r13); /* save r13 */ \ 498 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec); 499 500 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \ 501 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 502 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_STD) 503 504 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 505 SET_SCRATCH0(r13); /* save r13 */ \ 506 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, \ 507 EXC_HV, KVMTEST_HV, vec); 508 509 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 510 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 511 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 512 513 /* This associate vector numbers with bits in paca->irq_happened */ 514 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 515 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 516 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC 517 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 518 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 519 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 520 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 521 522 #define __SOFTEN_TEST(h, vec, bitmask) \ 523 lbz r10,PACAIRQSOFTMASK(r13); \ 524 andi. r10,r10,bitmask; \ 525 li r10,SOFTEN_VALUE_##vec; \ 526 bne masked_##h##interrupt 527 528 #define _SOFTEN_TEST(h, vec, bitmask) __SOFTEN_TEST(h, vec, bitmask) 529 530 #define SOFTEN_TEST_PR(vec, bitmask) \ 531 KVMTEST(EXC_STD, vec); \ 532 _SOFTEN_TEST(EXC_STD, vec, bitmask) 533 534 #define SOFTEN_TEST_HV(vec, bitmask) \ 535 KVMTEST(EXC_HV, vec); \ 536 _SOFTEN_TEST(EXC_HV, vec, bitmask) 537 538 #define KVMTEST_PR(vec) \ 539 KVMTEST(EXC_STD, vec) 540 541 #define KVMTEST_HV(vec) \ 542 KVMTEST(EXC_HV, vec) 543 544 #define SOFTEN_NOTEST_PR(vec, bitmask) _SOFTEN_TEST(EXC_STD, vec, bitmask) 545 #define SOFTEN_NOTEST_HV(vec, bitmask) _SOFTEN_TEST(EXC_HV, vec, bitmask) 546 547 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 548 SET_SCRATCH0(r13); /* save r13 */ \ 549 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 550 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 551 EXCEPTION_PROLOG_PSERIES_1(label, h); 552 553 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 554 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) 555 556 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label, bitmask) \ 557 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 558 EXC_STD, SOFTEN_TEST_PR, bitmask) 559 560 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label, bitmask) \ 561 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec, bitmask);\ 562 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 563 564 #define MASKABLE_EXCEPTION_HV(loc, vec, label, bitmask) \ 565 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 566 EXC_HV, SOFTEN_TEST_HV, bitmask) 567 568 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \ 569 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 570 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 571 572 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 573 SET_SCRATCH0(r13); /* save r13 */ \ 574 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 575 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 576 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 577 578 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask)\ 579 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) 580 581 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label, bitmask) \ 582 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 583 EXC_STD, SOFTEN_NOTEST_PR, bitmask) 584 585 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label, bitmask) \ 586 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 587 EXC_HV, SOFTEN_TEST_HV, bitmask) 588 589 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \ 590 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_HV, vec, bitmask);\ 591 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 592 593 /* 594 * Our exception common code can be passed various "additions" 595 * to specify the behaviour of interrupts, whether to kick the 596 * runlatch, etc... 597 */ 598 599 /* 600 * This addition reconciles our actual IRQ state with the various software 601 * flags that track it. This may call C code. 602 */ 603 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 604 605 #define ADD_NVGPRS \ 606 bl save_nvgprs 607 608 #define RUNLATCH_ON \ 609 BEGIN_FTR_SECTION \ 610 CURRENT_THREAD_INFO(r3, r1); \ 611 ld r4,TI_LOCAL_FLAGS(r3); \ 612 andi. r0,r4,_TLF_RUNLATCH; \ 613 beql ppc64_runlatch_on_trampoline; \ 614 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 615 616 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 617 EXCEPTION_PROLOG_COMMON(trap, area); \ 618 /* Volatile regs are potentially clobbered here */ \ 619 additions; \ 620 addi r3,r1,STACK_FRAME_OVERHEAD; \ 621 bl hdlr; \ 622 b ret 623 624 /* 625 * Exception where stack is already set in r1, r1 is saved in r10, and it 626 * continues rather than returns. 627 */ 628 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 629 EXCEPTION_PROLOG_COMMON_1(); \ 630 EXCEPTION_PROLOG_COMMON_2(area); \ 631 EXCEPTION_PROLOG_COMMON_3(trap); \ 632 /* Volatile regs are potentially clobbered here */ \ 633 additions; \ 634 addi r3,r1,STACK_FRAME_OVERHEAD; \ 635 bl hdlr 636 637 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 638 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 639 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 640 641 /* 642 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 643 * in the idle task and therefore need the special idle handling 644 * (finish nap and runlatch) 645 */ 646 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 647 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 648 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 649 650 /* 651 * When the idle code in power4_idle puts the CPU into NAP mode, 652 * it has to do so in a loop, and relies on the external interrupt 653 * and decrementer interrupt entry code to get it out of the loop. 654 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 655 * to signal that it is in the loop and needs help to get out. 656 */ 657 #ifdef CONFIG_PPC_970_NAP 658 #define FINISH_NAP \ 659 BEGIN_FTR_SECTION \ 660 CURRENT_THREAD_INFO(r11, r1); \ 661 ld r9,TI_LOCAL_FLAGS(r11); \ 662 andi. r10,r9,_TLF_NAPPING; \ 663 bnel power4_fixup_nap; \ 664 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 665 #else 666 #define FINISH_NAP 667 #endif 668 669 #endif /* _ASM_POWERPC_EXCEPTION_H */ 670