1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 39 /* PACA save area offsets (exgen, exmc, etc) */ 40 #define EX_R9 0 41 #define EX_R10 8 42 #define EX_R11 16 43 #define EX_R12 24 44 #define EX_R13 32 45 #define EX_DAR 40 46 #define EX_DSISR 48 47 #define EX_CCR 52 48 #define EX_R3 56 49 #define EX_CFAR 64 50 #define EX_PPR 72 51 #define EX_CTR 80 52 53 #define EX_SIZE 11 /* size in u64 units */ 54 55 /* 56 * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR 57 * EX_CCR similarly with DSISR, but being 4 byte registers there is a hole 58 * in the save area so it's not necessary to overlap them. Could be used 59 * for future savings though if another 4 byte register was to be saved. 60 */ 61 #define EX_LR EX_DAR 62 63 #ifdef CONFIG_RELOCATABLE 64 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 65 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 66 LOAD_HANDLER(r12,label); \ 67 mtctr r12; \ 68 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 69 li r10,MSR_RI; \ 70 mtmsrd r10,1; /* Set RI (EE=0) */ \ 71 bctr; 72 #else 73 /* If not relocatable, we can jump directly -- and save messing with LR */ 74 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 75 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 76 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 77 li r10,MSR_RI; \ 78 mtmsrd r10,1; /* Set RI (EE=0) */ \ 79 b label; 80 #endif 81 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 82 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 83 84 /* 85 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 86 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 87 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 88 */ 89 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 90 EXCEPTION_PROLOG_0(area); \ 91 EXCEPTION_PROLOG_1(area, extra, vec); \ 92 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 93 94 /* 95 * We're short on space and time in the exception prolog, so we can't 96 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 97 * Instead we get the base of the kernel from paca->kernelbase and or in the low 98 * part of label. This requires that the label be within 64KB of kernelbase, and 99 * that kernelbase be 64K aligned. 100 */ 101 #define LOAD_HANDLER(reg, label) \ 102 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 103 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label); 104 105 #define __LOAD_HANDLER(reg, label) \ 106 ld reg,PACAKBASE(r13); \ 107 ori reg,reg,(ABS_ADDR(label))@l; 108 109 /* 110 * Branches from unrelocated code (e.g., interrupts) to labels outside 111 * head-y require >64K offsets. 112 */ 113 #define __LOAD_FAR_HANDLER(reg, label) \ 114 ld reg,PACAKBASE(r13); \ 115 ori reg,reg,(ABS_ADDR(label))@l; \ 116 addis reg,reg,(ABS_ADDR(label))@h; 117 118 /* Exception register prefixes */ 119 #define EXC_HV H 120 #define EXC_STD 121 122 #if defined(CONFIG_RELOCATABLE) 123 /* 124 * If we support interrupts with relocation on AND we're a relocatable kernel, 125 * we need to use CTR to get to the 2nd level handler. So, save/restore it 126 * when required. 127 */ 128 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 129 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 130 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 131 #else 132 /* ...else CTR is unused and in register. */ 133 #define SAVE_CTR(reg, area) 134 #define GET_CTR(reg, area) mfctr reg 135 #define RESTORE_CTR(reg, area) 136 #endif 137 138 /* 139 * PPR save/restore macros used in exceptions_64s.S 140 * Used for P7 or later processors 141 */ 142 #define SAVE_PPR(area, ra, rb) \ 143 BEGIN_FTR_SECTION_NESTED(940) \ 144 ld ra,PACACURRENT(r13); \ 145 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 146 std rb,TASKTHREADPPR(ra); \ 147 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 148 149 #define RESTORE_PPR_PACA(area, ra) \ 150 BEGIN_FTR_SECTION_NESTED(941) \ 151 ld ra,area+EX_PPR(r13); \ 152 mtspr SPRN_PPR,ra; \ 153 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 154 155 /* 156 * Get an SPR into a register if the CPU has the given feature 157 */ 158 #define OPT_GET_SPR(ra, spr, ftr) \ 159 BEGIN_FTR_SECTION_NESTED(943) \ 160 mfspr ra,spr; \ 161 END_FTR_SECTION_NESTED(ftr,ftr,943) 162 163 /* 164 * Set an SPR from a register if the CPU has the given feature 165 */ 166 #define OPT_SET_SPR(ra, spr, ftr) \ 167 BEGIN_FTR_SECTION_NESTED(943) \ 168 mtspr spr,ra; \ 169 END_FTR_SECTION_NESTED(ftr,ftr,943) 170 171 /* 172 * Save a register to the PACA if the CPU has the given feature 173 */ 174 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 175 BEGIN_FTR_SECTION_NESTED(943) \ 176 std ra,offset(r13); \ 177 END_FTR_SECTION_NESTED(ftr,ftr,943) 178 179 #define EXCEPTION_PROLOG_0(area) \ 180 GET_PACA(r13); \ 181 std r9,area+EX_R9(r13); /* save r9 */ \ 182 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 183 HMT_MEDIUM; \ 184 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 185 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 186 187 #define __EXCEPTION_PROLOG_1(area, extra, vec) \ 188 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 189 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 190 SAVE_CTR(r10, area); \ 191 mfcr r9; \ 192 extra(vec); \ 193 std r11,area+EX_R11(r13); \ 194 std r12,area+EX_R12(r13); \ 195 GET_SCRATCH0(r10); \ 196 std r10,area+EX_R13(r13) 197 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 198 __EXCEPTION_PROLOG_1(area, extra, vec) 199 200 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ 201 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 202 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 203 LOAD_HANDLER(r12,label) \ 204 mtspr SPRN_##h##SRR0,r12; \ 205 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 206 mtspr SPRN_##h##SRR1,r10; \ 207 h##rfid; \ 208 b . /* prevent speculative execution */ 209 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ 210 __EXCEPTION_PROLOG_PSERIES_1(label, h) 211 212 /* _NORI variant keeps MSR_RI clear */ 213 #define __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 214 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 215 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \ 216 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 217 LOAD_HANDLER(r12,label) \ 218 mtspr SPRN_##h##SRR0,r12; \ 219 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 220 mtspr SPRN_##h##SRR1,r10; \ 221 h##rfid; \ 222 b . /* prevent speculative execution */ 223 224 #define EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 225 __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) 226 227 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 228 EXCEPTION_PROLOG_0(area); \ 229 EXCEPTION_PROLOG_1(area, extra, vec); \ 230 EXCEPTION_PROLOG_PSERIES_1(label, h); 231 232 #define __KVMTEST(h, n) \ 233 lbz r10,HSTATE_IN_GUEST(r13); \ 234 cmpwi r10,0; \ 235 bne do_kvm_##h##n 236 237 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 238 /* 239 * If hv is possible, interrupts come into to the hv version 240 * of the kvmppc_interrupt code, which then jumps to the PR handler, 241 * kvmppc_interrupt_pr, if the guest is a PR guest. 242 */ 243 #define kvmppc_interrupt kvmppc_interrupt_hv 244 #else 245 #define kvmppc_interrupt kvmppc_interrupt_pr 246 #endif 247 248 /* 249 * Branch to label using its 0xC000 address. This results in instruction 250 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 251 * on using mtmsr rather than rfid. 252 * 253 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 254 * load KBASE for a slight optimisation. 255 */ 256 #define BRANCH_TO_C000(reg, label) \ 257 __LOAD_HANDLER(reg, label); \ 258 mtctr reg; \ 259 bctr 260 261 #ifdef CONFIG_RELOCATABLE 262 #define BRANCH_TO_COMMON(reg, label) \ 263 __LOAD_HANDLER(reg, label); \ 264 mtctr reg; \ 265 bctr 266 267 #define BRANCH_LINK_TO_FAR(label) \ 268 __LOAD_FAR_HANDLER(r12, label); \ 269 mtctr r12; \ 270 bctrl 271 272 /* 273 * KVM requires __LOAD_FAR_HANDLER. 274 * 275 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 276 * explicitly use r9 then reload it from PACA before branching. Hence 277 * the double-underscore. 278 */ 279 #define __BRANCH_TO_KVM_EXIT(area, label) \ 280 mfctr r9; \ 281 std r9,HSTATE_SCRATCH1(r13); \ 282 __LOAD_FAR_HANDLER(r9, label); \ 283 mtctr r9; \ 284 ld r9,area+EX_R9(r13); \ 285 bctr 286 287 #else 288 #define BRANCH_TO_COMMON(reg, label) \ 289 b label 290 291 #define BRANCH_LINK_TO_FAR(label) \ 292 bl label 293 294 #define __BRANCH_TO_KVM_EXIT(area, label) \ 295 ld r9,area+EX_R9(r13); \ 296 b label 297 298 #endif 299 300 /* Do not enable RI */ 301 #define EXCEPTION_PROLOG_PSERIES_NORI(area, label, h, extra, vec) \ 302 EXCEPTION_PROLOG_0(area); \ 303 EXCEPTION_PROLOG_1(area, extra, vec); \ 304 EXCEPTION_PROLOG_PSERIES_1_NORI(label, h); 305 306 307 #define __KVM_HANDLER(area, h, n) \ 308 BEGIN_FTR_SECTION_NESTED(947) \ 309 ld r10,area+EX_CFAR(r13); \ 310 std r10,HSTATE_CFAR(r13); \ 311 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 312 BEGIN_FTR_SECTION_NESTED(948) \ 313 ld r10,area+EX_PPR(r13); \ 314 std r10,HSTATE_PPR(r13); \ 315 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 316 ld r10,area+EX_R10(r13); \ 317 std r12,HSTATE_SCRATCH0(r13); \ 318 sldi r12,r9,32; \ 319 ori r12,r12,(n); \ 320 /* This reloads r9 before branching to kvmppc_interrupt */ \ 321 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt) 322 323 #define __KVM_HANDLER_SKIP(area, h, n) \ 324 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 325 beq 89f; \ 326 BEGIN_FTR_SECTION_NESTED(948) \ 327 ld r10,area+EX_PPR(r13); \ 328 std r10,HSTATE_PPR(r13); \ 329 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 330 ld r10,area+EX_R10(r13); \ 331 std r12,HSTATE_SCRATCH0(r13); \ 332 sldi r12,r9,32; \ 333 ori r12,r12,(n); \ 334 /* This reloads r9 before branching to kvmppc_interrupt */ \ 335 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \ 336 89: mtocrf 0x80,r9; \ 337 ld r9,area+EX_R9(r13); \ 338 ld r10,area+EX_R10(r13); \ 339 b kvmppc_skip_##h##interrupt 340 341 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 342 #define KVMTEST(h, n) __KVMTEST(h, n) 343 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 344 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 345 346 #else 347 #define KVMTEST(h, n) 348 #define KVM_HANDLER(area, h, n) 349 #define KVM_HANDLER_SKIP(area, h, n) 350 #endif 351 352 #define NOTEST(n) 353 354 #define EXCEPTION_PROLOG_COMMON_1() \ 355 std r9,_CCR(r1); /* save CR in stackframe */ \ 356 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 357 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 358 std r10,0(r1); /* make stack chain pointer */ \ 359 std r0,GPR0(r1); /* save r0 in stackframe */ \ 360 std r10,GPR1(r1); /* save r1 in stackframe */ \ 361 362 363 /* 364 * The common exception prolog is used for all except a few exceptions 365 * such as a segment miss on a kernel address. We have to be prepared 366 * to take another exception from the point where we first touch the 367 * kernel stack onwards. 368 * 369 * On entry r13 points to the paca, r9-r13 are saved in the paca, 370 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 371 * SRR1, and relocation is on. 372 */ 373 #define EXCEPTION_PROLOG_COMMON(n, area) \ 374 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 375 mr r10,r1; /* Save r1 */ \ 376 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 377 beq- 1f; \ 378 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 379 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 380 blt+ cr1,3f; /* abort if it is */ \ 381 li r1,(n); /* will be reloaded later */ \ 382 sth r1,PACA_TRAP_SAVE(r13); \ 383 std r3,area+EX_R3(r13); \ 384 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 385 RESTORE_CTR(r1, area); \ 386 b bad_stack; \ 387 3: EXCEPTION_PROLOG_COMMON_1(); \ 388 beq 4f; /* if from kernel mode */ \ 389 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 390 SAVE_PPR(area, r9, r10); \ 391 4: EXCEPTION_PROLOG_COMMON_2(area) \ 392 EXCEPTION_PROLOG_COMMON_3(n) \ 393 ACCOUNT_STOLEN_TIME 394 395 /* Save original regs values from save area to stack frame. */ 396 #define EXCEPTION_PROLOG_COMMON_2(area) \ 397 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 398 ld r10,area+EX_R10(r13); \ 399 std r9,GPR9(r1); \ 400 std r10,GPR10(r1); \ 401 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 402 ld r10,area+EX_R12(r13); \ 403 ld r11,area+EX_R13(r13); \ 404 std r9,GPR11(r1); \ 405 std r10,GPR12(r1); \ 406 std r11,GPR13(r1); \ 407 BEGIN_FTR_SECTION_NESTED(66); \ 408 ld r10,area+EX_CFAR(r13); \ 409 std r10,ORIG_GPR3(r1); \ 410 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 411 GET_CTR(r10, area); \ 412 std r10,_CTR(r1); 413 414 #define EXCEPTION_PROLOG_COMMON_3(n) \ 415 std r2,GPR2(r1); /* save r2 in stackframe */ \ 416 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 417 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 418 mflr r9; /* Get LR, later save to stack */ \ 419 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 420 std r9,_LINK(r1); \ 421 lbz r10,PACASOFTIRQEN(r13); \ 422 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 423 std r10,SOFTE(r1); \ 424 std r11,_XER(r1); \ 425 li r9,(n)+1; \ 426 std r9,_TRAP(r1); /* set trap number */ \ 427 li r10,0; \ 428 ld r11,exception_marker@toc(r2); \ 429 std r10,RESULT(r1); /* clear regs->result */ \ 430 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 431 432 /* 433 * Exception vectors. 434 */ 435 #define STD_EXCEPTION_PSERIES(vec, label) \ 436 SET_SCRATCH0(r13); /* save r13 */ \ 437 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 438 EXC_STD, KVMTEST_PR, vec); \ 439 440 /* Version of above for when we have to branch out-of-line */ 441 #define __OOL_EXCEPTION(vec, label, hdlr) \ 442 SET_SCRATCH0(r13) \ 443 EXCEPTION_PROLOG_0(PACA_EXGEN) \ 444 b hdlr; 445 446 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \ 447 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 448 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 449 450 #define STD_EXCEPTION_HV(loc, vec, label) \ 451 SET_SCRATCH0(r13); /* save r13 */ \ 452 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 453 EXC_HV, KVMTEST_HV, vec); 454 455 #define STD_EXCEPTION_HV_OOL(vec, label) \ 456 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 457 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 458 459 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 460 /* No guest interrupts come through here */ \ 461 SET_SCRATCH0(r13); /* save r13 */ \ 462 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec); 463 464 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \ 465 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 466 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_STD) 467 468 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 469 SET_SCRATCH0(r13); /* save r13 */ \ 470 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, \ 471 EXC_HV, KVMTEST_HV, vec); 472 473 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 474 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 475 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 476 477 /* This associate vector numbers with bits in paca->irq_happened */ 478 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 479 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 480 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC 481 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 482 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 483 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 484 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 485 486 #define __SOFTEN_TEST(h, vec) \ 487 lbz r10,PACASOFTIRQEN(r13); \ 488 cmpwi r10,0; \ 489 li r10,SOFTEN_VALUE_##vec; \ 490 beq masked_##h##interrupt 491 492 #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec) 493 494 #define SOFTEN_TEST_PR(vec) \ 495 KVMTEST(EXC_STD, vec); \ 496 _SOFTEN_TEST(EXC_STD, vec) 497 498 #define SOFTEN_TEST_HV(vec) \ 499 KVMTEST(EXC_HV, vec); \ 500 _SOFTEN_TEST(EXC_HV, vec) 501 502 #define KVMTEST_PR(vec) \ 503 KVMTEST(EXC_STD, vec) 504 505 #define KVMTEST_HV(vec) \ 506 KVMTEST(EXC_HV, vec) 507 508 #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec) 509 #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) 510 511 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 512 SET_SCRATCH0(r13); /* save r13 */ \ 513 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 514 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 515 EXCEPTION_PROLOG_PSERIES_1(label, h); 516 517 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 518 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) 519 520 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \ 521 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 522 EXC_STD, SOFTEN_TEST_PR) 523 524 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label) \ 525 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec); \ 526 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 527 528 #define MASKABLE_EXCEPTION_HV(loc, vec, label) \ 529 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 530 EXC_HV, SOFTEN_TEST_HV) 531 532 #define MASKABLE_EXCEPTION_HV_OOL(vec, label) \ 533 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ 534 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 535 536 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 537 SET_SCRATCH0(r13); /* save r13 */ \ 538 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 539 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 540 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 541 542 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 543 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) 544 545 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 546 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 547 EXC_STD, SOFTEN_NOTEST_PR) 548 549 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \ 550 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 551 EXC_HV, SOFTEN_TEST_HV) 552 553 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \ 554 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ 555 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 556 557 /* 558 * Our exception common code can be passed various "additions" 559 * to specify the behaviour of interrupts, whether to kick the 560 * runlatch, etc... 561 */ 562 563 /* 564 * This addition reconciles our actual IRQ state with the various software 565 * flags that track it. This may call C code. 566 */ 567 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 568 569 #define ADD_NVGPRS \ 570 bl save_nvgprs 571 572 #define RUNLATCH_ON \ 573 BEGIN_FTR_SECTION \ 574 CURRENT_THREAD_INFO(r3, r1); \ 575 ld r4,TI_LOCAL_FLAGS(r3); \ 576 andi. r0,r4,_TLF_RUNLATCH; \ 577 beql ppc64_runlatch_on_trampoline; \ 578 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 579 580 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 581 EXCEPTION_PROLOG_COMMON(trap, area); \ 582 /* Volatile regs are potentially clobbered here */ \ 583 additions; \ 584 addi r3,r1,STACK_FRAME_OVERHEAD; \ 585 bl hdlr; \ 586 b ret 587 588 /* 589 * Exception where stack is already set in r1, r1 is saved in r10, and it 590 * continues rather than returns. 591 */ 592 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 593 EXCEPTION_PROLOG_COMMON_1(); \ 594 EXCEPTION_PROLOG_COMMON_2(area); \ 595 EXCEPTION_PROLOG_COMMON_3(trap); \ 596 /* Volatile regs are potentially clobbered here */ \ 597 additions; \ 598 addi r3,r1,STACK_FRAME_OVERHEAD; \ 599 bl hdlr 600 601 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 602 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 603 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 604 605 /* 606 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 607 * in the idle task and therefore need the special idle handling 608 * (finish nap and runlatch) 609 */ 610 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 611 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 612 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 613 614 /* 615 * When the idle code in power4_idle puts the CPU into NAP mode, 616 * it has to do so in a loop, and relies on the external interrupt 617 * and decrementer interrupt entry code to get it out of the loop. 618 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 619 * to signal that it is in the loop and needs help to get out. 620 */ 621 #ifdef CONFIG_PPC_970_NAP 622 #define FINISH_NAP \ 623 BEGIN_FTR_SECTION \ 624 CURRENT_THREAD_INFO(r11, r1); \ 625 ld r9,TI_LOCAL_FLAGS(r11); \ 626 andi. r10,r9,_TLF_NAPPING; \ 627 bnel power4_fixup_nap; \ 628 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 629 #else 630 #define FINISH_NAP 631 #endif 632 633 #endif /* _ASM_POWERPC_EXCEPTION_H */ 634