1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 38 #define EX_R9 0 39 #define EX_R10 8 40 #define EX_R11 16 41 #define EX_R12 24 42 #define EX_R13 32 43 #define EX_SRR0 40 44 #define EX_DAR 48 45 #define EX_DSISR 56 46 #define EX_CCR 60 47 #define EX_R3 64 48 #define EX_LR 72 49 #define EX_CFAR 80 50 #define EX_PPR 88 /* SMT thread status register (priority) */ 51 #define EX_CTR 96 52 53 #ifdef CONFIG_RELOCATABLE 54 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 55 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 56 LOAD_HANDLER(r12,label); \ 57 mtctr r12; \ 58 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 59 li r10,MSR_RI; \ 60 mtmsrd r10,1; /* Set RI (EE=0) */ \ 61 bctr; 62 #else 63 /* If not relocatable, we can jump directly -- and save messing with LR */ 64 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 65 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 66 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 67 li r10,MSR_RI; \ 68 mtmsrd r10,1; /* Set RI (EE=0) */ \ 69 b label; 70 #endif 71 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 72 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 73 74 /* 75 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 76 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 77 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 78 */ 79 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 80 EXCEPTION_PROLOG_0(area); \ 81 EXCEPTION_PROLOG_1(area, extra, vec); \ 82 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 83 84 /* 85 * We're short on space and time in the exception prolog, so we can't 86 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 87 * Instead we get the base of the kernel from paca->kernelbase and or in the low 88 * part of label. This requires that the label be within 64KB of kernelbase, and 89 * that kernelbase be 64K aligned. 90 */ 91 #define LOAD_HANDLER(reg, label) \ 92 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 93 ori reg,reg,(label)-_stext; /* virt addr of handler ... */ 94 95 /* Exception register prefixes */ 96 #define EXC_HV H 97 #define EXC_STD 98 99 #if defined(CONFIG_RELOCATABLE) 100 /* 101 * If we support interrupts with relocation on AND we're a relocatable kernel, 102 * we need to use CTR to get to the 2nd level handler. So, save/restore it 103 * when required. 104 */ 105 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 106 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 107 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 108 #else 109 /* ...else CTR is unused and in register. */ 110 #define SAVE_CTR(reg, area) 111 #define GET_CTR(reg, area) mfctr reg 112 #define RESTORE_CTR(reg, area) 113 #endif 114 115 /* 116 * PPR save/restore macros used in exceptions_64s.S 117 * Used for P7 or later processors 118 */ 119 #define SAVE_PPR(area, ra, rb) \ 120 BEGIN_FTR_SECTION_NESTED(940) \ 121 ld ra,PACACURRENT(r13); \ 122 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 123 std rb,TASKTHREADPPR(ra); \ 124 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 125 126 #define RESTORE_PPR_PACA(area, ra) \ 127 BEGIN_FTR_SECTION_NESTED(941) \ 128 ld ra,area+EX_PPR(r13); \ 129 mtspr SPRN_PPR,ra; \ 130 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 131 132 /* 133 * Get an SPR into a register if the CPU has the given feature 134 */ 135 #define OPT_GET_SPR(ra, spr, ftr) \ 136 BEGIN_FTR_SECTION_NESTED(943) \ 137 mfspr ra,spr; \ 138 END_FTR_SECTION_NESTED(ftr,ftr,943) 139 140 /* 141 * Set an SPR from a register if the CPU has the given feature 142 */ 143 #define OPT_SET_SPR(ra, spr, ftr) \ 144 BEGIN_FTR_SECTION_NESTED(943) \ 145 mtspr spr,ra; \ 146 END_FTR_SECTION_NESTED(ftr,ftr,943) 147 148 /* 149 * Save a register to the PACA if the CPU has the given feature 150 */ 151 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 152 BEGIN_FTR_SECTION_NESTED(943) \ 153 std ra,offset(r13); \ 154 END_FTR_SECTION_NESTED(ftr,ftr,943) 155 156 #define EXCEPTION_PROLOG_0(area) \ 157 GET_PACA(r13); \ 158 std r9,area+EX_R9(r13); /* save r9 */ \ 159 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 160 HMT_MEDIUM; \ 161 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 162 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 163 164 #define __EXCEPTION_PROLOG_1(area, extra, vec) \ 165 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 166 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 167 SAVE_CTR(r10, area); \ 168 mfcr r9; \ 169 extra(vec); \ 170 std r11,area+EX_R11(r13); \ 171 std r12,area+EX_R12(r13); \ 172 GET_SCRATCH0(r10); \ 173 std r10,area+EX_R13(r13) 174 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 175 __EXCEPTION_PROLOG_1(area, extra, vec) 176 177 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ 178 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 179 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 180 LOAD_HANDLER(r12,label) \ 181 mtspr SPRN_##h##SRR0,r12; \ 182 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 183 mtspr SPRN_##h##SRR1,r10; \ 184 h##rfid; \ 185 b . /* prevent speculative execution */ 186 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ 187 __EXCEPTION_PROLOG_PSERIES_1(label, h) 188 189 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 190 EXCEPTION_PROLOG_0(area); \ 191 EXCEPTION_PROLOG_1(area, extra, vec); \ 192 EXCEPTION_PROLOG_PSERIES_1(label, h); 193 194 #define __KVMTEST(n) \ 195 lbz r10,HSTATE_IN_GUEST(r13); \ 196 cmpwi r10,0; \ 197 bne do_kvm_##n 198 199 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 200 /* 201 * If hv is possible, interrupts come into to the hv version 202 * of the kvmppc_interrupt code, which then jumps to the PR handler, 203 * kvmppc_interrupt_pr, if the guest is a PR guest. 204 */ 205 #define kvmppc_interrupt kvmppc_interrupt_hv 206 #else 207 #define kvmppc_interrupt kvmppc_interrupt_pr 208 #endif 209 210 #define __KVM_HANDLER(area, h, n) \ 211 do_kvm_##n: \ 212 BEGIN_FTR_SECTION_NESTED(947) \ 213 ld r10,area+EX_CFAR(r13); \ 214 std r10,HSTATE_CFAR(r13); \ 215 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 216 BEGIN_FTR_SECTION_NESTED(948) \ 217 ld r10,area+EX_PPR(r13); \ 218 std r10,HSTATE_PPR(r13); \ 219 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 220 ld r10,area+EX_R10(r13); \ 221 stw r9,HSTATE_SCRATCH1(r13); \ 222 ld r9,area+EX_R9(r13); \ 223 std r12,HSTATE_SCRATCH0(r13); \ 224 li r12,n; \ 225 b kvmppc_interrupt 226 227 #define __KVM_HANDLER_SKIP(area, h, n) \ 228 do_kvm_##n: \ 229 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 230 ld r10,area+EX_R10(r13); \ 231 beq 89f; \ 232 stw r9,HSTATE_SCRATCH1(r13); \ 233 BEGIN_FTR_SECTION_NESTED(948) \ 234 ld r9,area+EX_PPR(r13); \ 235 std r9,HSTATE_PPR(r13); \ 236 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 237 ld r9,area+EX_R9(r13); \ 238 std r12,HSTATE_SCRATCH0(r13); \ 239 li r12,n; \ 240 b kvmppc_interrupt; \ 241 89: mtocrf 0x80,r9; \ 242 ld r9,area+EX_R9(r13); \ 243 b kvmppc_skip_##h##interrupt 244 245 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 246 #define KVMTEST(n) __KVMTEST(n) 247 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 248 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 249 250 #else 251 #define KVMTEST(n) 252 #define KVM_HANDLER(area, h, n) 253 #define KVM_HANDLER_SKIP(area, h, n) 254 #endif 255 256 #define NOTEST(n) 257 258 /* 259 * The common exception prolog is used for all except a few exceptions 260 * such as a segment miss on a kernel address. We have to be prepared 261 * to take another exception from the point where we first touch the 262 * kernel stack onwards. 263 * 264 * On entry r13 points to the paca, r9-r13 are saved in the paca, 265 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 266 * SRR1, and relocation is on. 267 */ 268 #define EXCEPTION_PROLOG_COMMON(n, area) \ 269 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 270 mr r10,r1; /* Save r1 */ \ 271 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 272 beq- 1f; \ 273 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 274 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 275 blt+ cr1,3f; /* abort if it is */ \ 276 li r1,(n); /* will be reloaded later */ \ 277 sth r1,PACA_TRAP_SAVE(r13); \ 278 std r3,area+EX_R3(r13); \ 279 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 280 RESTORE_CTR(r1, area); \ 281 b bad_stack; \ 282 3: std r9,_CCR(r1); /* save CR in stackframe */ \ 283 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 284 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 285 std r10,0(r1); /* make stack chain pointer */ \ 286 std r0,GPR0(r1); /* save r0 in stackframe */ \ 287 std r10,GPR1(r1); /* save r1 in stackframe */ \ 288 beq 4f; /* if from kernel mode */ \ 289 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 290 SAVE_PPR(area, r9, r10); \ 291 4: EXCEPTION_PROLOG_COMMON_2(area) \ 292 EXCEPTION_PROLOG_COMMON_3(n) \ 293 ACCOUNT_STOLEN_TIME 294 295 /* Save original regs values from save area to stack frame. */ 296 #define EXCEPTION_PROLOG_COMMON_2(area) \ 297 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 298 ld r10,area+EX_R10(r13); \ 299 std r9,GPR9(r1); \ 300 std r10,GPR10(r1); \ 301 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 302 ld r10,area+EX_R12(r13); \ 303 ld r11,area+EX_R13(r13); \ 304 std r9,GPR11(r1); \ 305 std r10,GPR12(r1); \ 306 std r11,GPR13(r1); \ 307 BEGIN_FTR_SECTION_NESTED(66); \ 308 ld r10,area+EX_CFAR(r13); \ 309 std r10,ORIG_GPR3(r1); \ 310 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 311 GET_CTR(r10, area); \ 312 std r10,_CTR(r1); 313 314 #define EXCEPTION_PROLOG_COMMON_3(n) \ 315 std r2,GPR2(r1); /* save r2 in stackframe */ \ 316 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 317 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 318 mflr r9; /* Get LR, later save to stack */ \ 319 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 320 std r9,_LINK(r1); \ 321 lbz r10,PACASOFTIRQEN(r13); \ 322 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 323 std r10,SOFTE(r1); \ 324 std r11,_XER(r1); \ 325 li r9,(n)+1; \ 326 std r9,_TRAP(r1); /* set trap number */ \ 327 li r10,0; \ 328 ld r11,exception_marker@toc(r2); \ 329 std r10,RESULT(r1); /* clear regs->result */ \ 330 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 331 332 /* 333 * Exception vectors. 334 */ 335 #define STD_EXCEPTION_PSERIES(vec, label) \ 336 . = vec; \ 337 .globl label##_pSeries; \ 338 label##_pSeries: \ 339 SET_SCRATCH0(r13); /* save r13 */ \ 340 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 341 EXC_STD, KVMTEST, vec) 342 343 /* Version of above for when we have to branch out-of-line */ 344 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \ 345 .globl label##_pSeries; \ 346 label##_pSeries: \ 347 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST, vec); \ 348 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_STD) 349 350 #define STD_EXCEPTION_HV(loc, vec, label) \ 351 . = loc; \ 352 .globl label##_hv; \ 353 label##_hv: \ 354 SET_SCRATCH0(r13); /* save r13 */ \ 355 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 356 EXC_HV, KVMTEST, vec) 357 358 /* Version of above for when we have to branch out-of-line */ 359 #define STD_EXCEPTION_HV_OOL(vec, label) \ 360 .globl label##_hv; \ 361 label##_hv: \ 362 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST, vec); \ 363 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV) 364 365 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 366 . = loc; \ 367 .globl label##_relon_pSeries; \ 368 label##_relon_pSeries: \ 369 /* No guest interrupts come through here */ \ 370 SET_SCRATCH0(r13); /* save r13 */ \ 371 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 372 EXC_STD, NOTEST, vec) 373 374 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \ 375 .globl label##_relon_pSeries; \ 376 label##_relon_pSeries: \ 377 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 378 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_STD) 379 380 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 381 . = loc; \ 382 .globl label##_relon_hv; \ 383 label##_relon_hv: \ 384 /* No guest interrupts come through here */ \ 385 SET_SCRATCH0(r13); /* save r13 */ \ 386 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 387 EXC_HV, NOTEST, vec) 388 389 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 390 .globl label##_relon_hv; \ 391 label##_relon_hv: \ 392 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 393 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_HV) 394 395 /* This associate vector numbers with bits in paca->irq_happened */ 396 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 397 #define SOFTEN_VALUE_0x502 PACA_IRQ_EE 398 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 399 #define SOFTEN_VALUE_0x982 PACA_IRQ_DEC 400 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 401 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 402 #define SOFTEN_VALUE_0xe82 PACA_IRQ_DBELL 403 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 404 #define SOFTEN_VALUE_0xe62 PACA_IRQ_HMI 405 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 406 #define SOFTEN_VALUE_0xea2 PACA_IRQ_EE 407 408 #define __SOFTEN_TEST(h, vec) \ 409 lbz r10,PACASOFTIRQEN(r13); \ 410 cmpwi r10,0; \ 411 li r10,SOFTEN_VALUE_##vec; \ 412 beq masked_##h##interrupt 413 #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec) 414 415 #define SOFTEN_TEST_PR(vec) \ 416 KVMTEST(vec); \ 417 _SOFTEN_TEST(EXC_STD, vec) 418 419 #define SOFTEN_TEST_HV(vec) \ 420 KVMTEST(vec); \ 421 _SOFTEN_TEST(EXC_HV, vec) 422 423 #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec) 424 #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) 425 426 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 427 SET_SCRATCH0(r13); /* save r13 */ \ 428 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 429 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 430 EXCEPTION_PROLOG_PSERIES_1(label##_common, h); 431 432 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 433 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) 434 435 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \ 436 . = loc; \ 437 .globl label##_pSeries; \ 438 label##_pSeries: \ 439 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 440 EXC_STD, SOFTEN_TEST_PR) 441 442 #define MASKABLE_EXCEPTION_HV(loc, vec, label) \ 443 . = loc; \ 444 .globl label##_hv; \ 445 label##_hv: \ 446 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 447 EXC_HV, SOFTEN_TEST_HV) 448 449 #define MASKABLE_EXCEPTION_HV_OOL(vec, label) \ 450 .globl label##_hv; \ 451 label##_hv: \ 452 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ 453 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV); 454 455 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 456 SET_SCRATCH0(r13); /* save r13 */ \ 457 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 458 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 459 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, h); 460 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 461 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) 462 463 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 464 . = loc; \ 465 .globl label##_relon_pSeries; \ 466 label##_relon_pSeries: \ 467 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 468 EXC_STD, SOFTEN_NOTEST_PR) 469 470 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \ 471 . = loc; \ 472 .globl label##_relon_hv; \ 473 label##_relon_hv: \ 474 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 475 EXC_HV, SOFTEN_NOTEST_HV) 476 477 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \ 478 .globl label##_relon_hv; \ 479 label##_relon_hv: \ 480 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_HV, vec); \ 481 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV); 482 483 /* 484 * Our exception common code can be passed various "additions" 485 * to specify the behaviour of interrupts, whether to kick the 486 * runlatch, etc... 487 */ 488 489 /* 490 * This addition reconciles our actual IRQ state with the various software 491 * flags that track it. This may call C code. 492 */ 493 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 494 495 #define ADD_NVGPRS \ 496 bl save_nvgprs 497 498 #define RUNLATCH_ON \ 499 BEGIN_FTR_SECTION \ 500 CURRENT_THREAD_INFO(r3, r1); \ 501 ld r4,TI_LOCAL_FLAGS(r3); \ 502 andi. r0,r4,_TLF_RUNLATCH; \ 503 beql ppc64_runlatch_on_trampoline; \ 504 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 505 506 #define EXCEPTION_COMMON(trap, label, hdlr, ret, additions) \ 507 .align 7; \ 508 .globl label##_common; \ 509 label##_common: \ 510 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 511 /* Volatile regs are potentially clobbered here */ \ 512 additions; \ 513 addi r3,r1,STACK_FRAME_OVERHEAD; \ 514 bl hdlr; \ 515 b ret 516 517 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 518 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except, \ 519 ADD_NVGPRS;ADD_RECONCILE) 520 521 /* 522 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 523 * in the idle task and therefore need the special idle handling 524 * (finish nap and runlatch) 525 */ 526 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 527 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \ 528 FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 529 530 /* 531 * When the idle code in power4_idle puts the CPU into NAP mode, 532 * it has to do so in a loop, and relies on the external interrupt 533 * and decrementer interrupt entry code to get it out of the loop. 534 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 535 * to signal that it is in the loop and needs help to get out. 536 */ 537 #ifdef CONFIG_PPC_970_NAP 538 #define FINISH_NAP \ 539 BEGIN_FTR_SECTION \ 540 CURRENT_THREAD_INFO(r11, r1); \ 541 ld r9,TI_LOCAL_FLAGS(r11); \ 542 andi. r10,r9,_TLF_NAPPING; \ 543 bnel power4_fixup_nap; \ 544 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 545 #else 546 #define FINISH_NAP 547 #endif 548 549 #endif /* _ASM_POWERPC_EXCEPTION_H */ 550