1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 #include <asm/feature-fixups.h> 39 40 /* PACA save area offsets (exgen, exmc, etc) */ 41 #define EX_R9 0 42 #define EX_R10 8 43 #define EX_R11 16 44 #define EX_R12 24 45 #define EX_R13 32 46 #define EX_DAR 40 47 #define EX_DSISR 48 48 #define EX_CCR 52 49 #define EX_CFAR 56 50 #define EX_PPR 64 51 #if defined(CONFIG_RELOCATABLE) 52 #define EX_CTR 72 53 #define EX_SIZE 10 /* size in u64 units */ 54 #else 55 #define EX_SIZE 9 /* size in u64 units */ 56 #endif 57 58 /* 59 * maximum recursive depth of MCE exceptions 60 */ 61 #define MAX_MCE_DEPTH 4 62 63 /* 64 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 65 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 66 * with EX_DAR. 67 */ 68 #define EX_R3 EX_DAR 69 70 #ifdef __ASSEMBLY__ 71 72 #define STF_ENTRY_BARRIER_SLOT \ 73 STF_ENTRY_BARRIER_FIXUP_SECTION; \ 74 nop; \ 75 nop; \ 76 nop 77 78 #define STF_EXIT_BARRIER_SLOT \ 79 STF_EXIT_BARRIER_FIXUP_SECTION; \ 80 nop; \ 81 nop; \ 82 nop; \ 83 nop; \ 84 nop; \ 85 nop 86 87 /* 88 * r10 must be free to use, r13 must be paca 89 */ 90 #define INTERRUPT_TO_KERNEL \ 91 STF_ENTRY_BARRIER_SLOT 92 93 /* 94 * Macros for annotating the expected destination of (h)rfid 95 * 96 * The nop instructions allow us to insert one or more instructions to flush the 97 * L1-D cache when returning to userspace or a guest. 98 */ 99 #define RFI_FLUSH_SLOT \ 100 RFI_FLUSH_FIXUP_SECTION; \ 101 nop; \ 102 nop; \ 103 nop 104 105 #define RFI_TO_KERNEL \ 106 rfid 107 108 #define RFI_TO_USER \ 109 STF_EXIT_BARRIER_SLOT; \ 110 RFI_FLUSH_SLOT; \ 111 rfid; \ 112 b rfi_flush_fallback 113 114 #define RFI_TO_USER_OR_KERNEL \ 115 STF_EXIT_BARRIER_SLOT; \ 116 RFI_FLUSH_SLOT; \ 117 rfid; \ 118 b rfi_flush_fallback 119 120 #define RFI_TO_GUEST \ 121 STF_EXIT_BARRIER_SLOT; \ 122 RFI_FLUSH_SLOT; \ 123 rfid; \ 124 b rfi_flush_fallback 125 126 #define HRFI_TO_KERNEL \ 127 hrfid 128 129 #define HRFI_TO_USER \ 130 STF_EXIT_BARRIER_SLOT; \ 131 RFI_FLUSH_SLOT; \ 132 hrfid; \ 133 b hrfi_flush_fallback 134 135 #define HRFI_TO_USER_OR_KERNEL \ 136 STF_EXIT_BARRIER_SLOT; \ 137 RFI_FLUSH_SLOT; \ 138 hrfid; \ 139 b hrfi_flush_fallback 140 141 #define HRFI_TO_GUEST \ 142 STF_EXIT_BARRIER_SLOT; \ 143 RFI_FLUSH_SLOT; \ 144 hrfid; \ 145 b hrfi_flush_fallback 146 147 #define HRFI_TO_UNKNOWN \ 148 STF_EXIT_BARRIER_SLOT; \ 149 RFI_FLUSH_SLOT; \ 150 hrfid; \ 151 b hrfi_flush_fallback 152 153 /* 154 * We're short on space and time in the exception prolog, so we can't 155 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 156 * Instead we get the base of the kernel from paca->kernelbase and or in the low 157 * part of label. This requires that the label be within 64KB of kernelbase, and 158 * that kernelbase be 64K aligned. 159 */ 160 #define LOAD_HANDLER(reg, label) \ 161 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 162 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) 163 164 #define __LOAD_HANDLER(reg, label) \ 165 ld reg,PACAKBASE(r13); \ 166 ori reg,reg,(ABS_ADDR(label))@l 167 168 /* 169 * Branches from unrelocated code (e.g., interrupts) to labels outside 170 * head-y require >64K offsets. 171 */ 172 #define __LOAD_FAR_HANDLER(reg, label) \ 173 ld reg,PACAKBASE(r13); \ 174 ori reg,reg,(ABS_ADDR(label))@l; \ 175 addis reg,reg,(ABS_ADDR(label))@h 176 177 .macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri 178 ld r10,PACAKMSR(r13) /* get MSR value for kernel */ 179 .if ! \set_ri 180 xori r10,r10,MSR_RI /* Clear MSR_RI */ 181 .endif 182 .if \hsrr 183 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 184 .else 185 mfspr r11,SPRN_SRR0 /* save SRR0 */ 186 .endif 187 LOAD_HANDLER(r12, \label\()) 188 .if \hsrr 189 mtspr SPRN_HSRR0,r12 190 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 191 mtspr SPRN_HSRR1,r10 192 HRFI_TO_KERNEL 193 .else 194 mtspr SPRN_SRR0,r12 195 mfspr r12,SPRN_SRR1 /* and SRR1 */ 196 mtspr SPRN_SRR1,r10 197 RFI_TO_KERNEL 198 .endif 199 b . /* prevent speculative execution */ 200 .endm 201 202 .macro EXCEPTION_PROLOG_2_VIRT label, hsrr 203 #ifdef CONFIG_RELOCATABLE 204 .if \hsrr 205 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 206 .else 207 mfspr r11,SPRN_SRR0 /* save SRR0 */ 208 .endif 209 LOAD_HANDLER(r12, \label\()) 210 mtctr r12 211 .if \hsrr 212 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 213 .else 214 mfspr r12,SPRN_SRR1 /* and HSRR1 */ 215 .endif 216 li r10,MSR_RI 217 mtmsrd r10,1 /* Set RI (EE=0) */ 218 bctr 219 #else 220 .if \hsrr 221 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 222 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 223 .else 224 mfspr r11,SPRN_SRR0 /* save SRR0 */ 225 mfspr r12,SPRN_SRR1 /* and SRR1 */ 226 .endif 227 li r10,MSR_RI 228 mtmsrd r10,1 /* Set RI (EE=0) */ 229 b \label 230 #endif 231 .endm 232 233 /* 234 * As EXCEPTION_PROLOG(), except we've already got relocation on so no need to 235 * rfid. Save CTR in case we're CONFIG_RELOCATABLE, in which case 236 * EXCEPTION_PROLOG_2_VIRT will be using CTR. 237 */ 238 #define EXCEPTION_RELON_PROLOG(area, label, hsrr, kvm, vec) \ 239 SET_SCRATCH0(r13); /* save r13 */ \ 240 EXCEPTION_PROLOG_0 area ; \ 241 EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \ 242 EXCEPTION_PROLOG_2_VIRT label, hsrr 243 244 /* Exception register prefixes */ 245 #define EXC_HV 1 246 #define EXC_STD 0 247 248 #if defined(CONFIG_RELOCATABLE) 249 /* 250 * If we support interrupts with relocation on AND we're a relocatable kernel, 251 * we need to use CTR to get to the 2nd level handler. So, save/restore it 252 * when required. 253 */ 254 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 255 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 256 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 257 #else 258 /* ...else CTR is unused and in register. */ 259 #define SAVE_CTR(reg, area) 260 #define GET_CTR(reg, area) mfctr reg 261 #define RESTORE_CTR(reg, area) 262 #endif 263 264 /* 265 * PPR save/restore macros used in exceptions_64s.S 266 * Used for P7 or later processors 267 */ 268 #define SAVE_PPR(area, ra) \ 269 BEGIN_FTR_SECTION_NESTED(940) \ 270 ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ 271 std ra,_PPR(r1); \ 272 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 273 274 #define RESTORE_PPR_PACA(area, ra) \ 275 BEGIN_FTR_SECTION_NESTED(941) \ 276 ld ra,area+EX_PPR(r13); \ 277 mtspr SPRN_PPR,ra; \ 278 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 279 280 /* 281 * Get an SPR into a register if the CPU has the given feature 282 */ 283 #define OPT_GET_SPR(ra, spr, ftr) \ 284 BEGIN_FTR_SECTION_NESTED(943) \ 285 mfspr ra,spr; \ 286 END_FTR_SECTION_NESTED(ftr,ftr,943) 287 288 /* 289 * Set an SPR from a register if the CPU has the given feature 290 */ 291 #define OPT_SET_SPR(ra, spr, ftr) \ 292 BEGIN_FTR_SECTION_NESTED(943) \ 293 mtspr spr,ra; \ 294 END_FTR_SECTION_NESTED(ftr,ftr,943) 295 296 /* 297 * Save a register to the PACA if the CPU has the given feature 298 */ 299 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 300 BEGIN_FTR_SECTION_NESTED(943) \ 301 std ra,offset(r13); \ 302 END_FTR_SECTION_NESTED(ftr,ftr,943) 303 304 .macro EXCEPTION_PROLOG_0 area 305 GET_PACA(r13) 306 std r9,\area\()+EX_R9(r13) /* save r9 */ 307 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR) 308 HMT_MEDIUM 309 std r10,\area\()+EX_R10(r13) /* save r10 - r12 */ 310 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 311 .endm 312 313 .macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask 314 OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR) 315 OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR) 316 INTERRUPT_TO_KERNEL 317 SAVE_CTR(r10, \area\()) 318 mfcr r9 319 .if \kvm 320 KVMTEST \hsrr \vec 321 .endif 322 323 .if \bitmask 324 lbz r10,PACAIRQSOFTMASK(r13) 325 andi. r10,r10,\bitmask 326 /* Associate vector numbers with bits in paca->irq_happened */ 327 .if \vec == 0x500 || \vec == 0xea0 328 li r10,PACA_IRQ_EE 329 .elseif \vec == 0x900 330 li r10,PACA_IRQ_DEC 331 .elseif \vec == 0xa00 || \vec == 0xe80 332 li r10,PACA_IRQ_DBELL 333 .elseif \vec == 0xe60 334 li r10,PACA_IRQ_HMI 335 .elseif \vec == 0xf00 336 li r10,PACA_IRQ_PMI 337 .else 338 .abort "Bad maskable vector" 339 .endif 340 341 .if \hsrr 342 bne masked_Hinterrupt 343 .else 344 bne masked_interrupt 345 .endif 346 .endif 347 348 std r11,\area\()+EX_R11(r13) 349 std r12,\area\()+EX_R12(r13) 350 GET_SCRATCH0(r10) 351 std r10,\area\()+EX_R13(r13) 352 .endm 353 354 #define EXCEPTION_PROLOG(area, label, hsrr, kvm, vec) \ 355 SET_SCRATCH0(r13); /* save r13 */ \ 356 EXCEPTION_PROLOG_0 area ; \ 357 EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \ 358 EXCEPTION_PROLOG_2_REAL label, hsrr, 1 359 360 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 361 /* 362 * If hv is possible, interrupts come into to the hv version 363 * of the kvmppc_interrupt code, which then jumps to the PR handler, 364 * kvmppc_interrupt_pr, if the guest is a PR guest. 365 */ 366 #define kvmppc_interrupt kvmppc_interrupt_hv 367 #else 368 #define kvmppc_interrupt kvmppc_interrupt_pr 369 #endif 370 371 /* 372 * Branch to label using its 0xC000 address. This results in instruction 373 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 374 * on using mtmsr rather than rfid. 375 * 376 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 377 * load KBASE for a slight optimisation. 378 */ 379 #define BRANCH_TO_C000(reg, label) \ 380 __LOAD_HANDLER(reg, label); \ 381 mtctr reg; \ 382 bctr 383 384 #ifdef CONFIG_RELOCATABLE 385 #define BRANCH_TO_COMMON(reg, label) \ 386 __LOAD_HANDLER(reg, label); \ 387 mtctr reg; \ 388 bctr 389 390 #define BRANCH_LINK_TO_FAR(label) \ 391 __LOAD_FAR_HANDLER(r12, label); \ 392 mtctr r12; \ 393 bctrl 394 395 /* 396 * KVM requires __LOAD_FAR_HANDLER. 397 * 398 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 399 * explicitly use r9 then reload it from PACA before branching. Hence 400 * the double-underscore. 401 */ 402 #define __BRANCH_TO_KVM_EXIT(area, label) \ 403 mfctr r9; \ 404 std r9,HSTATE_SCRATCH1(r13); \ 405 __LOAD_FAR_HANDLER(r9, label); \ 406 mtctr r9; \ 407 ld r9,area+EX_R9(r13); \ 408 bctr 409 410 #else 411 #define BRANCH_TO_COMMON(reg, label) \ 412 b label 413 414 #define BRANCH_LINK_TO_FAR(label) \ 415 bl label 416 417 #define __BRANCH_TO_KVM_EXIT(area, label) \ 418 ld r9,area+EX_R9(r13); \ 419 b label 420 421 #endif 422 423 /* Do not enable RI */ 424 #define EXCEPTION_PROLOG_NORI(area, label, hsrr, kvm, vec) \ 425 EXCEPTION_PROLOG_0 area ; \ 426 EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \ 427 EXCEPTION_PROLOG_2_REAL label, hsrr, 0 428 429 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 430 .macro KVMTEST hsrr, n 431 lbz r10,HSTATE_IN_GUEST(r13) 432 cmpwi r10,0 433 .if \hsrr 434 bne do_kvm_H\n 435 .else 436 bne do_kvm_\n 437 .endif 438 .endm 439 440 .macro KVM_HANDLER area, hsrr, n, skip 441 .if \skip 442 cmpwi r10,KVM_GUEST_MODE_SKIP 443 beq 89f 444 .else 445 BEGIN_FTR_SECTION_NESTED(947) 446 ld r10,\area+EX_CFAR(r13) 447 std r10,HSTATE_CFAR(r13) 448 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947) 449 .endif 450 451 BEGIN_FTR_SECTION_NESTED(948) 452 ld r10,\area+EX_PPR(r13) 453 std r10,HSTATE_PPR(r13) 454 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) 455 ld r10,\area+EX_R10(r13) 456 std r12,HSTATE_SCRATCH0(r13) 457 sldi r12,r9,32 458 /* HSRR variants have the 0x2 bit added to their trap number */ 459 .if \hsrr 460 ori r12,r12,(\n + 0x2) 461 .else 462 ori r12,r12,(\n) 463 .endif 464 /* This reloads r9 before branching to kvmppc_interrupt */ 465 __BRANCH_TO_KVM_EXIT(\area, kvmppc_interrupt) 466 467 .if \skip 468 89: mtocrf 0x80,r9 469 ld r9,\area+EX_R9(r13) 470 ld r10,\area+EX_R10(r13) 471 .if \hsrr 472 b kvmppc_skip_Hinterrupt 473 .else 474 b kvmppc_skip_interrupt 475 .endif 476 .endif 477 .endm 478 479 #else 480 .macro KVMTEST hsrr, n 481 .endm 482 .macro KVM_HANDLER area, hsrr, n, skip 483 .endm 484 #endif 485 486 #define EXCEPTION_PROLOG_COMMON_1() \ 487 std r9,_CCR(r1); /* save CR in stackframe */ \ 488 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 489 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 490 std r10,0(r1); /* make stack chain pointer */ \ 491 std r0,GPR0(r1); /* save r0 in stackframe */ \ 492 std r10,GPR1(r1); /* save r1 in stackframe */ \ 493 494 495 /* 496 * The common exception prolog is used for all except a few exceptions 497 * such as a segment miss on a kernel address. We have to be prepared 498 * to take another exception from the point where we first touch the 499 * kernel stack onwards. 500 * 501 * On entry r13 points to the paca, r9-r13 are saved in the paca, 502 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 503 * SRR1, and relocation is on. 504 */ 505 #define EXCEPTION_PROLOG_COMMON(n, area) \ 506 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 507 mr r10,r1; /* Save r1 */ \ 508 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 509 beq- 1f; \ 510 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 511 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 512 blt+ cr1,3f; /* abort if it is */ \ 513 li r1,(n); /* will be reloaded later */ \ 514 sth r1,PACA_TRAP_SAVE(r13); \ 515 std r3,area+EX_R3(r13); \ 516 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 517 RESTORE_CTR(r1, area); \ 518 b bad_stack; \ 519 3: EXCEPTION_PROLOG_COMMON_1(); \ 520 kuap_save_amr_and_lock r9, r10, cr1, cr0; \ 521 beq 4f; /* if from kernel mode */ \ 522 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 523 SAVE_PPR(area, r9); \ 524 4: EXCEPTION_PROLOG_COMMON_2(area) \ 525 EXCEPTION_PROLOG_COMMON_3(n) \ 526 ACCOUNT_STOLEN_TIME 527 528 /* Save original regs values from save area to stack frame. */ 529 #define EXCEPTION_PROLOG_COMMON_2(area) \ 530 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 531 ld r10,area+EX_R10(r13); \ 532 std r9,GPR9(r1); \ 533 std r10,GPR10(r1); \ 534 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 535 ld r10,area+EX_R12(r13); \ 536 ld r11,area+EX_R13(r13); \ 537 std r9,GPR11(r1); \ 538 std r10,GPR12(r1); \ 539 std r11,GPR13(r1); \ 540 BEGIN_FTR_SECTION_NESTED(66); \ 541 ld r10,area+EX_CFAR(r13); \ 542 std r10,ORIG_GPR3(r1); \ 543 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 544 GET_CTR(r10, area); \ 545 std r10,_CTR(r1); 546 547 #define EXCEPTION_PROLOG_COMMON_3(n) \ 548 std r2,GPR2(r1); /* save r2 in stackframe */ \ 549 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 550 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 551 mflr r9; /* Get LR, later save to stack */ \ 552 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 553 std r9,_LINK(r1); \ 554 lbz r10,PACAIRQSOFTMASK(r13); \ 555 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 556 std r10,SOFTE(r1); \ 557 std r11,_XER(r1); \ 558 li r9,(n)+1; \ 559 std r9,_TRAP(r1); /* set trap number */ \ 560 li r10,0; \ 561 ld r11,exception_marker@toc(r2); \ 562 std r10,RESULT(r1); /* clear regs->result */ \ 563 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 564 565 /* 566 * Exception vectors. 567 */ 568 #define STD_EXCEPTION(vec, label) \ 569 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_STD, 1, vec); 570 571 /* Version of above for when we have to branch out-of-line */ 572 #define __OOL_EXCEPTION(vec, label, hdlr) \ 573 SET_SCRATCH0(r13); \ 574 EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 575 b hdlr 576 577 #define STD_EXCEPTION_OOL(vec, label) \ 578 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ; \ 579 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1 580 581 #define STD_EXCEPTION_HV(loc, vec, label) \ 582 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_HV, 1, vec) 583 584 #define STD_EXCEPTION_HV_OOL(vec, label) \ 585 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \ 586 EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1 587 588 #define STD_RELON_EXCEPTION(loc, vec, label) \ 589 /* No guest interrupts come through here */ \ 590 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_STD, 0, vec) 591 592 #define STD_RELON_EXCEPTION_OOL(vec, label) \ 593 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ; \ 594 EXCEPTION_PROLOG_2_VIRT label, EXC_STD 595 596 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 597 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_HV, 1, vec) 598 599 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 600 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \ 601 EXCEPTION_PROLOG_2_VIRT label, EXC_HV 602 603 #define __MASKABLE_EXCEPTION(vec, label, hsrr, kvm, bitmask) \ 604 SET_SCRATCH0(r13); /* save r13 */ \ 605 EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 606 EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \ 607 EXCEPTION_PROLOG_2_REAL label, hsrr, 1 608 609 #define MASKABLE_EXCEPTION(vec, label, bitmask) \ 610 __MASKABLE_EXCEPTION(vec, label, EXC_STD, 1, bitmask) 611 612 #define MASKABLE_EXCEPTION_OOL(vec, label, bitmask) \ 613 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \ 614 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1 615 616 #define MASKABLE_EXCEPTION_HV(vec, label, bitmask) \ 617 __MASKABLE_EXCEPTION(vec, label, EXC_HV, 1, bitmask) 618 619 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \ 620 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \ 621 EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1 622 623 #define __MASKABLE_RELON_EXCEPTION(vec, label, hsrr, kvm, bitmask) \ 624 SET_SCRATCH0(r13); /* save r13 */ \ 625 EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 626 EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \ 627 EXCEPTION_PROLOG_2_VIRT label, hsrr 628 629 #define MASKABLE_RELON_EXCEPTION(vec, label, bitmask) \ 630 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_STD, 0, bitmask) 631 632 #define MASKABLE_RELON_EXCEPTION_OOL(vec, label, bitmask) \ 633 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, bitmask ; \ 634 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1 635 636 #define MASKABLE_RELON_EXCEPTION_HV(vec, label, bitmask) \ 637 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_HV, 1, bitmask) 638 639 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \ 640 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \ 641 EXCEPTION_PROLOG_2_VIRT label, EXC_HV 642 643 /* 644 * Our exception common code can be passed various "additions" 645 * to specify the behaviour of interrupts, whether to kick the 646 * runlatch, etc... 647 */ 648 649 /* 650 * This addition reconciles our actual IRQ state with the various software 651 * flags that track it. This may call C code. 652 */ 653 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 654 655 #define ADD_NVGPRS \ 656 bl save_nvgprs 657 658 #define RUNLATCH_ON \ 659 BEGIN_FTR_SECTION \ 660 ld r3, PACA_THREAD_INFO(r13); \ 661 ld r4,TI_LOCAL_FLAGS(r3); \ 662 andi. r0,r4,_TLF_RUNLATCH; \ 663 beql ppc64_runlatch_on_trampoline; \ 664 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 665 666 #define EXCEPTION_COMMON(area, trap, label, additions) \ 667 EXCEPTION_PROLOG_COMMON(trap, area); \ 668 /* Volatile regs are potentially clobbered here */ \ 669 additions 670 671 /* 672 * Exception where stack is already set in r1, r1 is saved in r10, and it 673 * continues rather than returns. 674 */ 675 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, additions) \ 676 EXCEPTION_PROLOG_COMMON_1(); \ 677 kuap_save_amr_and_lock r9, r10, cr1; \ 678 EXCEPTION_PROLOG_COMMON_2(area); \ 679 EXCEPTION_PROLOG_COMMON_3(trap); \ 680 /* Volatile regs are potentially clobbered here */ \ 681 additions 682 683 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 684 EXCEPTION_COMMON(PACA_EXGEN, trap, label, ADD_NVGPRS;ADD_RECONCILE); \ 685 addi r3,r1,STACK_FRAME_OVERHEAD; \ 686 bl hdlr; \ 687 b ret_from_except 688 689 /* 690 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 691 * in the idle task and therefore need the special idle handling 692 * (finish nap and runlatch) 693 */ 694 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 695 EXCEPTION_COMMON(PACA_EXGEN, trap, label, \ 696 FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON); \ 697 addi r3,r1,STACK_FRAME_OVERHEAD; \ 698 bl hdlr; \ 699 b ret_from_except_lite 700 701 /* 702 * When the idle code in power4_idle puts the CPU into NAP mode, 703 * it has to do so in a loop, and relies on the external interrupt 704 * and decrementer interrupt entry code to get it out of the loop. 705 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 706 * to signal that it is in the loop and needs help to get out. 707 */ 708 #ifdef CONFIG_PPC_970_NAP 709 #define FINISH_NAP \ 710 BEGIN_FTR_SECTION \ 711 ld r11, PACA_THREAD_INFO(r13); \ 712 ld r9,TI_LOCAL_FLAGS(r11); \ 713 andi. r10,r9,_TLF_NAPPING; \ 714 bnel power4_fixup_nap; \ 715 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 716 #else 717 #define FINISH_NAP 718 #endif 719 720 #endif /* __ASSEMBLY__ */ 721 722 #endif /* _ASM_POWERPC_EXCEPTION_H */ 723