1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 38 #define EX_R9 0 39 #define EX_R10 8 40 #define EX_R11 16 41 #define EX_R12 24 42 #define EX_R13 32 43 #define EX_SRR0 40 44 #define EX_DAR 48 45 #define EX_DSISR 56 46 #define EX_CCR 60 47 #define EX_R3 64 48 #define EX_LR 72 49 50 /* 51 * We're short on space and time in the exception prolog, so we can't 52 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the 53 * low halfword of the address, but for Kdump we need the whole low 54 * word. 55 */ 56 #define LOAD_HANDLER(reg, label) \ 57 addi reg,reg,(label)-_stext; /* virt addr of handler ... */ 58 59 #define EXCEPTION_PROLOG_1(area) \ 60 mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \ 61 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 62 std r10,area+EX_R10(r13); \ 63 std r11,area+EX_R11(r13); \ 64 std r12,area+EX_R12(r13); \ 65 mfspr r9,SPRN_SPRG_SCRATCH0; \ 66 std r9,area+EX_R13(r13); \ 67 mfcr r9 68 69 #define EXCEPTION_PROLOG_PSERIES_1(label) \ 70 ld r12,PACAKBASE(r13); /* get high part of &label */ \ 71 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 72 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 73 LOAD_HANDLER(r12,label) \ 74 mtspr SPRN_SRR0,r12; \ 75 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 76 mtspr SPRN_SRR1,r10; \ 77 rfid; \ 78 b . /* prevent speculative execution */ 79 80 #define EXCEPTION_PROLOG_PSERIES(area, label) \ 81 EXCEPTION_PROLOG_1(area); \ 82 EXCEPTION_PROLOG_PSERIES_1(label); 83 84 /* 85 * The common exception prolog is used for all except a few exceptions 86 * such as a segment miss on a kernel address. We have to be prepared 87 * to take another exception from the point where we first touch the 88 * kernel stack onwards. 89 * 90 * On entry r13 points to the paca, r9-r13 are saved in the paca, 91 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 92 * SRR1, and relocation is on. 93 */ 94 #define EXCEPTION_PROLOG_COMMON(n, area) \ 95 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 96 mr r10,r1; /* Save r1 */ \ 97 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 98 beq- 1f; \ 99 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 100 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 101 bge- cr1,2f; /* abort if it is */ \ 102 b 3f; \ 103 2: li r1,(n); /* will be reloaded later */ \ 104 sth r1,PACA_TRAP_SAVE(r13); \ 105 b bad_stack; \ 106 3: std r9,_CCR(r1); /* save CR in stackframe */ \ 107 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 108 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 109 std r10,0(r1); /* make stack chain pointer */ \ 110 std r0,GPR0(r1); /* save r0 in stackframe */ \ 111 std r10,GPR1(r1); /* save r1 in stackframe */ \ 112 ACCOUNT_CPU_USER_ENTRY(r9, r10); \ 113 std r2,GPR2(r1); /* save r2 in stackframe */ \ 114 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 115 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 116 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 117 ld r10,area+EX_R10(r13); \ 118 std r9,GPR9(r1); \ 119 std r10,GPR10(r1); \ 120 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 121 ld r10,area+EX_R12(r13); \ 122 ld r11,area+EX_R13(r13); \ 123 std r9,GPR11(r1); \ 124 std r10,GPR12(r1); \ 125 std r11,GPR13(r1); \ 126 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 127 mflr r9; /* save LR in stackframe */ \ 128 std r9,_LINK(r1); \ 129 mfctr r10; /* save CTR in stackframe */ \ 130 std r10,_CTR(r1); \ 131 lbz r10,PACASOFTIRQEN(r13); \ 132 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 133 std r10,SOFTE(r1); \ 134 std r11,_XER(r1); \ 135 li r9,(n)+1; \ 136 std r9,_TRAP(r1); /* set trap number */ \ 137 li r10,0; \ 138 ld r11,exception_marker@toc(r2); \ 139 std r10,RESULT(r1); /* clear regs->result */ \ 140 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 141 142 /* 143 * Exception vectors. 144 */ 145 #define STD_EXCEPTION_PSERIES(n, label) \ 146 . = n; \ 147 .globl label##_pSeries; \ 148 label##_pSeries: \ 149 HMT_MEDIUM; \ 150 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \ 151 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 152 153 #define HSTD_EXCEPTION_PSERIES(n, label) \ 154 . = n; \ 155 .globl label##_pSeries; \ 156 label##_pSeries: \ 157 HMT_MEDIUM; \ 158 mtspr SPRN_SPRG_SCRATCH0,r20; /* save r20 */ \ 159 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ 160 mtspr SPRN_SRR0,r20; \ 161 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \ 162 mtspr SPRN_SRR1,r20; \ 163 mfspr r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \ 164 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \ 165 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 166 167 168 #define MASKABLE_EXCEPTION_PSERIES(n, label) \ 169 . = n; \ 170 .globl label##_pSeries; \ 171 label##_pSeries: \ 172 HMT_MEDIUM; \ 173 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \ 174 mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \ 175 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ 176 std r10,PACA_EXGEN+EX_R10(r13); \ 177 lbz r10,PACASOFTIRQEN(r13); \ 178 mfcr r9; \ 179 cmpwi r10,0; \ 180 beq masked_interrupt; \ 181 mfspr r10,SPRN_SPRG_SCRATCH0; \ 182 std r10,PACA_EXGEN+EX_R13(r13); \ 183 std r11,PACA_EXGEN+EX_R11(r13); \ 184 std r12,PACA_EXGEN+EX_R12(r13); \ 185 ld r12,PACAKBASE(r13); /* get high part of &label */ \ 186 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 187 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 188 LOAD_HANDLER(r12,label##_common) \ 189 mtspr SPRN_SRR0,r12; \ 190 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 191 mtspr SPRN_SRR1,r10; \ 192 rfid; \ 193 b . /* prevent speculative execution */ 194 195 #ifdef CONFIG_PPC_ISERIES 196 #define DISABLE_INTS \ 197 li r11,0; \ 198 stb r11,PACASOFTIRQEN(r13); \ 199 BEGIN_FW_FTR_SECTION; \ 200 stb r11,PACAHARDIRQEN(r13); \ 201 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ 202 TRACE_DISABLE_INTS; \ 203 BEGIN_FW_FTR_SECTION; \ 204 mfmsr r10; \ 205 ori r10,r10,MSR_EE; \ 206 mtmsrd r10,1; \ 207 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 208 #else 209 #define DISABLE_INTS \ 210 li r11,0; \ 211 stb r11,PACASOFTIRQEN(r13); \ 212 stb r11,PACAHARDIRQEN(r13); \ 213 TRACE_DISABLE_INTS 214 #endif /* CONFIG_PPC_ISERIES */ 215 216 #define ENABLE_INTS \ 217 ld r12,_MSR(r1); \ 218 mfmsr r11; \ 219 rlwimi r11,r12,0,MSR_EE; \ 220 mtmsrd r11,1 221 222 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 223 .align 7; \ 224 .globl label##_common; \ 225 label##_common: \ 226 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 227 DISABLE_INTS; \ 228 bl .save_nvgprs; \ 229 addi r3,r1,STACK_FRAME_OVERHEAD; \ 230 bl hdlr; \ 231 b .ret_from_except 232 233 /* 234 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 235 * in the idle task and therefore need the special idle handling. 236 */ 237 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \ 238 .align 7; \ 239 .globl label##_common; \ 240 label##_common: \ 241 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 242 FINISH_NAP; \ 243 DISABLE_INTS; \ 244 bl .save_nvgprs; \ 245 addi r3,r1,STACK_FRAME_OVERHEAD; \ 246 bl hdlr; \ 247 b .ret_from_except 248 249 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ 250 .align 7; \ 251 .globl label##_common; \ 252 label##_common: \ 253 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 254 FINISH_NAP; \ 255 DISABLE_INTS; \ 256 BEGIN_FTR_SECTION \ 257 bl .ppc64_runlatch_on; \ 258 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) \ 259 addi r3,r1,STACK_FRAME_OVERHEAD; \ 260 bl hdlr; \ 261 b .ret_from_except_lite 262 263 /* 264 * When the idle code in power4_idle puts the CPU into NAP mode, 265 * it has to do so in a loop, and relies on the external interrupt 266 * and decrementer interrupt entry code to get it out of the loop. 267 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 268 * to signal that it is in the loop and needs help to get out. 269 */ 270 #ifdef CONFIG_PPC_970_NAP 271 #define FINISH_NAP \ 272 BEGIN_FTR_SECTION \ 273 clrrdi r11,r1,THREAD_SHIFT; \ 274 ld r9,TI_LOCAL_FLAGS(r11); \ 275 andi. r10,r9,_TLF_NAPPING; \ 276 bnel power4_fixup_nap; \ 277 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 278 #else 279 #define FINISH_NAP 280 #endif 281 282 #endif /* _ASM_POWERPC_EXCEPTION_H */ 283