1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 #include <asm/feature-fixups.h> 39 40 /* PACA save area offsets (exgen, exmc, etc) */ 41 #define EX_R9 0 42 #define EX_R10 8 43 #define EX_R11 16 44 #define EX_R12 24 45 #define EX_R13 32 46 #define EX_DAR 40 47 #define EX_DSISR 48 48 #define EX_CCR 52 49 #define EX_CFAR 56 50 #define EX_PPR 64 51 #if defined(CONFIG_RELOCATABLE) 52 #define EX_CTR 72 53 #define EX_SIZE 10 /* size in u64 units */ 54 #else 55 #define EX_SIZE 9 /* size in u64 units */ 56 #endif 57 58 /* 59 * maximum recursive depth of MCE exceptions 60 */ 61 #define MAX_MCE_DEPTH 4 62 63 /* 64 * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR 65 * EX_CCR similarly with DSISR, but being 4 byte registers there is a hole 66 * in the save area so it's not necessary to overlap them. Could be used 67 * for future savings though if another 4 byte register was to be saved. 68 */ 69 #define EX_LR EX_DAR 70 71 /* 72 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 73 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 74 * with EX_DAR. 75 */ 76 #define EX_R3 EX_DAR 77 78 #define STF_ENTRY_BARRIER_SLOT \ 79 STF_ENTRY_BARRIER_FIXUP_SECTION; \ 80 nop; \ 81 nop; \ 82 nop 83 84 #define STF_EXIT_BARRIER_SLOT \ 85 STF_EXIT_BARRIER_FIXUP_SECTION; \ 86 nop; \ 87 nop; \ 88 nop; \ 89 nop; \ 90 nop; \ 91 nop 92 93 /* 94 * r10 must be free to use, r13 must be paca 95 */ 96 #define INTERRUPT_TO_KERNEL \ 97 STF_ENTRY_BARRIER_SLOT 98 99 /* 100 * Macros for annotating the expected destination of (h)rfid 101 * 102 * The nop instructions allow us to insert one or more instructions to flush the 103 * L1-D cache when returning to userspace or a guest. 104 */ 105 #define RFI_FLUSH_SLOT \ 106 RFI_FLUSH_FIXUP_SECTION; \ 107 nop; \ 108 nop; \ 109 nop 110 111 #define RFI_TO_KERNEL \ 112 rfid 113 114 #define RFI_TO_USER \ 115 STF_EXIT_BARRIER_SLOT; \ 116 RFI_FLUSH_SLOT; \ 117 rfid; \ 118 b rfi_flush_fallback 119 120 #define RFI_TO_USER_OR_KERNEL \ 121 STF_EXIT_BARRIER_SLOT; \ 122 RFI_FLUSH_SLOT; \ 123 rfid; \ 124 b rfi_flush_fallback 125 126 #define RFI_TO_GUEST \ 127 STF_EXIT_BARRIER_SLOT; \ 128 RFI_FLUSH_SLOT; \ 129 rfid; \ 130 b rfi_flush_fallback 131 132 #define HRFI_TO_KERNEL \ 133 hrfid 134 135 #define HRFI_TO_USER \ 136 STF_EXIT_BARRIER_SLOT; \ 137 RFI_FLUSH_SLOT; \ 138 hrfid; \ 139 b hrfi_flush_fallback 140 141 #define HRFI_TO_USER_OR_KERNEL \ 142 STF_EXIT_BARRIER_SLOT; \ 143 RFI_FLUSH_SLOT; \ 144 hrfid; \ 145 b hrfi_flush_fallback 146 147 #define HRFI_TO_GUEST \ 148 STF_EXIT_BARRIER_SLOT; \ 149 RFI_FLUSH_SLOT; \ 150 hrfid; \ 151 b hrfi_flush_fallback 152 153 #define HRFI_TO_UNKNOWN \ 154 STF_EXIT_BARRIER_SLOT; \ 155 RFI_FLUSH_SLOT; \ 156 hrfid; \ 157 b hrfi_flush_fallback 158 159 #ifdef CONFIG_RELOCATABLE 160 #define __EXCEPTION_PROLOG_2_RELON(label, h) \ 161 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 162 LOAD_HANDLER(r12,label); \ 163 mtctr r12; \ 164 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 165 li r10,MSR_RI; \ 166 mtmsrd r10,1; /* Set RI (EE=0) */ \ 167 bctr; 168 #else 169 /* If not relocatable, we can jump directly -- and save messing with LR */ 170 #define __EXCEPTION_PROLOG_2_RELON(label, h) \ 171 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 172 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 173 li r10,MSR_RI; \ 174 mtmsrd r10,1; /* Set RI (EE=0) */ \ 175 b label; 176 #endif 177 #define EXCEPTION_PROLOG_2_RELON(label, h) \ 178 __EXCEPTION_PROLOG_2_RELON(label, h) 179 180 /* 181 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 182 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 183 * case EXCEPTION_PROLOG_2_RELON will be using LR. 184 */ 185 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 186 SET_SCRATCH0(r13); /* save r13 */ \ 187 EXCEPTION_PROLOG_0(area); \ 188 EXCEPTION_PROLOG_1(area, extra, vec); \ 189 EXCEPTION_PROLOG_2_RELON(label, h) 190 191 /* 192 * We're short on space and time in the exception prolog, so we can't 193 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 194 * Instead we get the base of the kernel from paca->kernelbase and or in the low 195 * part of label. This requires that the label be within 64KB of kernelbase, and 196 * that kernelbase be 64K aligned. 197 */ 198 #define LOAD_HANDLER(reg, label) \ 199 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 200 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label); 201 202 #define __LOAD_HANDLER(reg, label) \ 203 ld reg,PACAKBASE(r13); \ 204 ori reg,reg,(ABS_ADDR(label))@l; 205 206 /* 207 * Branches from unrelocated code (e.g., interrupts) to labels outside 208 * head-y require >64K offsets. 209 */ 210 #define __LOAD_FAR_HANDLER(reg, label) \ 211 ld reg,PACAKBASE(r13); \ 212 ori reg,reg,(ABS_ADDR(label))@l; \ 213 addis reg,reg,(ABS_ADDR(label))@h; 214 215 /* Exception register prefixes */ 216 #define EXC_HV H 217 #define EXC_STD 218 219 #if defined(CONFIG_RELOCATABLE) 220 /* 221 * If we support interrupts with relocation on AND we're a relocatable kernel, 222 * we need to use CTR to get to the 2nd level handler. So, save/restore it 223 * when required. 224 */ 225 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 226 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 227 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 228 #else 229 /* ...else CTR is unused and in register. */ 230 #define SAVE_CTR(reg, area) 231 #define GET_CTR(reg, area) mfctr reg 232 #define RESTORE_CTR(reg, area) 233 #endif 234 235 /* 236 * PPR save/restore macros used in exceptions_64s.S 237 * Used for P7 or later processors 238 */ 239 #define SAVE_PPR(area, ra, rb) \ 240 BEGIN_FTR_SECTION_NESTED(940) \ 241 ld ra,PACACURRENT(r13); \ 242 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 243 std rb,TASKTHREADPPR(ra); \ 244 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 245 246 #define RESTORE_PPR_PACA(area, ra) \ 247 BEGIN_FTR_SECTION_NESTED(941) \ 248 ld ra,area+EX_PPR(r13); \ 249 mtspr SPRN_PPR,ra; \ 250 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 251 252 /* 253 * Get an SPR into a register if the CPU has the given feature 254 */ 255 #define OPT_GET_SPR(ra, spr, ftr) \ 256 BEGIN_FTR_SECTION_NESTED(943) \ 257 mfspr ra,spr; \ 258 END_FTR_SECTION_NESTED(ftr,ftr,943) 259 260 /* 261 * Set an SPR from a register if the CPU has the given feature 262 */ 263 #define OPT_SET_SPR(ra, spr, ftr) \ 264 BEGIN_FTR_SECTION_NESTED(943) \ 265 mtspr spr,ra; \ 266 END_FTR_SECTION_NESTED(ftr,ftr,943) 267 268 /* 269 * Save a register to the PACA if the CPU has the given feature 270 */ 271 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 272 BEGIN_FTR_SECTION_NESTED(943) \ 273 std ra,offset(r13); \ 274 END_FTR_SECTION_NESTED(ftr,ftr,943) 275 276 #define EXCEPTION_PROLOG_0(area) \ 277 GET_PACA(r13); \ 278 std r9,area+EX_R9(r13); /* save r9 */ \ 279 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 280 HMT_MEDIUM; \ 281 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 282 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 283 284 #define __EXCEPTION_PROLOG_1_PRE(area) \ 285 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 286 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 287 INTERRUPT_TO_KERNEL; \ 288 SAVE_CTR(r10, area); \ 289 mfcr r9; 290 291 #define __EXCEPTION_PROLOG_1_POST(area) \ 292 std r11,area+EX_R11(r13); \ 293 std r12,area+EX_R12(r13); \ 294 GET_SCRATCH0(r10); \ 295 std r10,area+EX_R13(r13) 296 297 /* 298 * This version of the EXCEPTION_PROLOG_1 will carry 299 * addition parameter called "bitmask" to support 300 * checking of the interrupt maskable level in the SOFTEN_TEST. 301 * Intended to be used in MASKABLE_EXCPETION_* macros. 302 */ 303 #define MASKABLE_EXCEPTION_PROLOG_1(area, extra, vec, bitmask) \ 304 __EXCEPTION_PROLOG_1_PRE(area); \ 305 extra(vec, bitmask); \ 306 __EXCEPTION_PROLOG_1_POST(area); 307 308 /* 309 * This version of the EXCEPTION_PROLOG_1 is intended 310 * to be used in STD_EXCEPTION* macros 311 */ 312 #define _EXCEPTION_PROLOG_1(area, extra, vec) \ 313 __EXCEPTION_PROLOG_1_PRE(area); \ 314 extra(vec); \ 315 __EXCEPTION_PROLOG_1_POST(area); 316 317 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 318 _EXCEPTION_PROLOG_1(area, extra, vec) 319 320 #define __EXCEPTION_PROLOG_2(label, h) \ 321 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 322 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 323 LOAD_HANDLER(r12,label) \ 324 mtspr SPRN_##h##SRR0,r12; \ 325 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 326 mtspr SPRN_##h##SRR1,r10; \ 327 h##RFI_TO_KERNEL; \ 328 b . /* prevent speculative execution */ 329 #define EXCEPTION_PROLOG_2(label, h) \ 330 __EXCEPTION_PROLOG_2(label, h) 331 332 /* _NORI variant keeps MSR_RI clear */ 333 #define __EXCEPTION_PROLOG_2_NORI(label, h) \ 334 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 335 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \ 336 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 337 LOAD_HANDLER(r12,label) \ 338 mtspr SPRN_##h##SRR0,r12; \ 339 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 340 mtspr SPRN_##h##SRR1,r10; \ 341 h##RFI_TO_KERNEL; \ 342 b . /* prevent speculative execution */ 343 344 #define EXCEPTION_PROLOG_2_NORI(label, h) \ 345 __EXCEPTION_PROLOG_2_NORI(label, h) 346 347 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 348 SET_SCRATCH0(r13); /* save r13 */ \ 349 EXCEPTION_PROLOG_0(area); \ 350 EXCEPTION_PROLOG_1(area, extra, vec); \ 351 EXCEPTION_PROLOG_2(label, h); 352 353 #define __KVMTEST(h, n) \ 354 lbz r10,HSTATE_IN_GUEST(r13); \ 355 cmpwi r10,0; \ 356 bne do_kvm_##h##n 357 358 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 359 /* 360 * If hv is possible, interrupts come into to the hv version 361 * of the kvmppc_interrupt code, which then jumps to the PR handler, 362 * kvmppc_interrupt_pr, if the guest is a PR guest. 363 */ 364 #define kvmppc_interrupt kvmppc_interrupt_hv 365 #else 366 #define kvmppc_interrupt kvmppc_interrupt_pr 367 #endif 368 369 /* 370 * Branch to label using its 0xC000 address. This results in instruction 371 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 372 * on using mtmsr rather than rfid. 373 * 374 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 375 * load KBASE for a slight optimisation. 376 */ 377 #define BRANCH_TO_C000(reg, label) \ 378 __LOAD_HANDLER(reg, label); \ 379 mtctr reg; \ 380 bctr 381 382 #ifdef CONFIG_RELOCATABLE 383 #define BRANCH_TO_COMMON(reg, label) \ 384 __LOAD_HANDLER(reg, label); \ 385 mtctr reg; \ 386 bctr 387 388 #define BRANCH_LINK_TO_FAR(label) \ 389 __LOAD_FAR_HANDLER(r12, label); \ 390 mtctr r12; \ 391 bctrl 392 393 /* 394 * KVM requires __LOAD_FAR_HANDLER. 395 * 396 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 397 * explicitly use r9 then reload it from PACA before branching. Hence 398 * the double-underscore. 399 */ 400 #define __BRANCH_TO_KVM_EXIT(area, label) \ 401 mfctr r9; \ 402 std r9,HSTATE_SCRATCH1(r13); \ 403 __LOAD_FAR_HANDLER(r9, label); \ 404 mtctr r9; \ 405 ld r9,area+EX_R9(r13); \ 406 bctr 407 408 #else 409 #define BRANCH_TO_COMMON(reg, label) \ 410 b label 411 412 #define BRANCH_LINK_TO_FAR(label) \ 413 bl label 414 415 #define __BRANCH_TO_KVM_EXIT(area, label) \ 416 ld r9,area+EX_R9(r13); \ 417 b label 418 419 #endif 420 421 /* Do not enable RI */ 422 #define EXCEPTION_PROLOG_NORI(area, label, h, extra, vec) \ 423 EXCEPTION_PROLOG_0(area); \ 424 EXCEPTION_PROLOG_1(area, extra, vec); \ 425 EXCEPTION_PROLOG_2_NORI(label, h); 426 427 428 #define __KVM_HANDLER(area, h, n) \ 429 BEGIN_FTR_SECTION_NESTED(947) \ 430 ld r10,area+EX_CFAR(r13); \ 431 std r10,HSTATE_CFAR(r13); \ 432 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 433 BEGIN_FTR_SECTION_NESTED(948) \ 434 ld r10,area+EX_PPR(r13); \ 435 std r10,HSTATE_PPR(r13); \ 436 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 437 ld r10,area+EX_R10(r13); \ 438 std r12,HSTATE_SCRATCH0(r13); \ 439 sldi r12,r9,32; \ 440 ori r12,r12,(n); \ 441 /* This reloads r9 before branching to kvmppc_interrupt */ \ 442 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt) 443 444 #define __KVM_HANDLER_SKIP(area, h, n) \ 445 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 446 beq 89f; \ 447 BEGIN_FTR_SECTION_NESTED(948) \ 448 ld r10,area+EX_PPR(r13); \ 449 std r10,HSTATE_PPR(r13); \ 450 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 451 ld r10,area+EX_R10(r13); \ 452 std r12,HSTATE_SCRATCH0(r13); \ 453 sldi r12,r9,32; \ 454 ori r12,r12,(n); \ 455 /* This reloads r9 before branching to kvmppc_interrupt */ \ 456 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \ 457 89: mtocrf 0x80,r9; \ 458 ld r9,area+EX_R9(r13); \ 459 ld r10,area+EX_R10(r13); \ 460 b kvmppc_skip_##h##interrupt 461 462 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 463 #define KVMTEST(h, n) __KVMTEST(h, n) 464 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 465 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 466 467 #else 468 #define KVMTEST(h, n) 469 #define KVM_HANDLER(area, h, n) 470 #define KVM_HANDLER_SKIP(area, h, n) 471 #endif 472 473 #define NOTEST(n) 474 475 #define EXCEPTION_PROLOG_COMMON_1() \ 476 std r9,_CCR(r1); /* save CR in stackframe */ \ 477 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 478 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 479 std r10,0(r1); /* make stack chain pointer */ \ 480 std r0,GPR0(r1); /* save r0 in stackframe */ \ 481 std r10,GPR1(r1); /* save r1 in stackframe */ \ 482 483 484 /* 485 * The common exception prolog is used for all except a few exceptions 486 * such as a segment miss on a kernel address. We have to be prepared 487 * to take another exception from the point where we first touch the 488 * kernel stack onwards. 489 * 490 * On entry r13 points to the paca, r9-r13 are saved in the paca, 491 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 492 * SRR1, and relocation is on. 493 */ 494 #define EXCEPTION_PROLOG_COMMON(n, area) \ 495 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 496 mr r10,r1; /* Save r1 */ \ 497 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 498 beq- 1f; \ 499 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 500 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 501 blt+ cr1,3f; /* abort if it is */ \ 502 li r1,(n); /* will be reloaded later */ \ 503 sth r1,PACA_TRAP_SAVE(r13); \ 504 std r3,area+EX_R3(r13); \ 505 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 506 RESTORE_CTR(r1, area); \ 507 b bad_stack; \ 508 3: EXCEPTION_PROLOG_COMMON_1(); \ 509 beq 4f; /* if from kernel mode */ \ 510 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 511 SAVE_PPR(area, r9, r10); \ 512 4: EXCEPTION_PROLOG_COMMON_2(area) \ 513 EXCEPTION_PROLOG_COMMON_3(n) \ 514 ACCOUNT_STOLEN_TIME 515 516 /* Save original regs values from save area to stack frame. */ 517 #define EXCEPTION_PROLOG_COMMON_2(area) \ 518 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 519 ld r10,area+EX_R10(r13); \ 520 std r9,GPR9(r1); \ 521 std r10,GPR10(r1); \ 522 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 523 ld r10,area+EX_R12(r13); \ 524 ld r11,area+EX_R13(r13); \ 525 std r9,GPR11(r1); \ 526 std r10,GPR12(r1); \ 527 std r11,GPR13(r1); \ 528 BEGIN_FTR_SECTION_NESTED(66); \ 529 ld r10,area+EX_CFAR(r13); \ 530 std r10,ORIG_GPR3(r1); \ 531 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 532 GET_CTR(r10, area); \ 533 std r10,_CTR(r1); 534 535 #define EXCEPTION_PROLOG_COMMON_3(n) \ 536 std r2,GPR2(r1); /* save r2 in stackframe */ \ 537 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 538 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 539 mflr r9; /* Get LR, later save to stack */ \ 540 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 541 std r9,_LINK(r1); \ 542 lbz r10,PACAIRQSOFTMASK(r13); \ 543 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 544 std r10,SOFTE(r1); \ 545 std r11,_XER(r1); \ 546 li r9,(n)+1; \ 547 std r9,_TRAP(r1); /* set trap number */ \ 548 li r10,0; \ 549 ld r11,exception_marker@toc(r2); \ 550 std r10,RESULT(r1); /* clear regs->result */ \ 551 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 552 553 /* 554 * Exception vectors. 555 */ 556 #define STD_EXCEPTION(vec, label) \ 557 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 558 EXC_STD, KVMTEST_PR, vec); \ 559 560 /* Version of above for when we have to branch out-of-line */ 561 #define __OOL_EXCEPTION(vec, label, hdlr) \ 562 SET_SCRATCH0(r13) \ 563 EXCEPTION_PROLOG_0(PACA_EXGEN) \ 564 b hdlr; 565 566 #define STD_EXCEPTION_OOL(vec, label) \ 567 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 568 EXCEPTION_PROLOG_2(label, EXC_STD) 569 570 #define STD_EXCEPTION_HV(loc, vec, label) \ 571 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 572 EXC_HV, KVMTEST_HV, vec); 573 574 #define STD_EXCEPTION_HV_OOL(vec, label) \ 575 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 576 EXCEPTION_PROLOG_2(label, EXC_HV) 577 578 #define STD_RELON_EXCEPTION(loc, vec, label) \ 579 /* No guest interrupts come through here */ \ 580 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec); 581 582 #define STD_RELON_EXCEPTION_OOL(vec, label) \ 583 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 584 EXCEPTION_PROLOG_2_RELON(label, EXC_STD) 585 586 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 587 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, \ 588 EXC_HV, KVMTEST_HV, vec); 589 590 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 591 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 592 EXCEPTION_PROLOG_2_RELON(label, EXC_HV) 593 594 /* This associate vector numbers with bits in paca->irq_happened */ 595 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 596 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 597 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC 598 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 599 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 600 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 601 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 602 #define SOFTEN_VALUE_0xf00 PACA_IRQ_PMI 603 604 #define __SOFTEN_TEST(h, vec, bitmask) \ 605 lbz r10,PACAIRQSOFTMASK(r13); \ 606 andi. r10,r10,bitmask; \ 607 li r10,SOFTEN_VALUE_##vec; \ 608 bne masked_##h##interrupt 609 610 #define _SOFTEN_TEST(h, vec, bitmask) __SOFTEN_TEST(h, vec, bitmask) 611 612 #define SOFTEN_TEST_PR(vec, bitmask) \ 613 KVMTEST(EXC_STD, vec); \ 614 _SOFTEN_TEST(EXC_STD, vec, bitmask) 615 616 #define SOFTEN_TEST_HV(vec, bitmask) \ 617 KVMTEST(EXC_HV, vec); \ 618 _SOFTEN_TEST(EXC_HV, vec, bitmask) 619 620 #define KVMTEST_PR(vec) \ 621 KVMTEST(EXC_STD, vec) 622 623 #define KVMTEST_HV(vec) \ 624 KVMTEST(EXC_HV, vec) 625 626 #define SOFTEN_NOTEST_PR(vec, bitmask) _SOFTEN_TEST(EXC_STD, vec, bitmask) 627 #define SOFTEN_NOTEST_HV(vec, bitmask) _SOFTEN_TEST(EXC_HV, vec, bitmask) 628 629 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 630 SET_SCRATCH0(r13); /* save r13 */ \ 631 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 632 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 633 EXCEPTION_PROLOG_2(label, h); 634 635 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 636 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) 637 638 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label, bitmask) \ 639 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 640 EXC_STD, SOFTEN_TEST_PR, bitmask) 641 642 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label, bitmask) \ 643 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec, bitmask);\ 644 EXCEPTION_PROLOG_2(label, EXC_STD) 645 646 #define MASKABLE_EXCEPTION_HV(loc, vec, label, bitmask) \ 647 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 648 EXC_HV, SOFTEN_TEST_HV, bitmask) 649 650 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \ 651 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 652 EXCEPTION_PROLOG_2(label, EXC_HV) 653 654 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 655 SET_SCRATCH0(r13); /* save r13 */ \ 656 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 657 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 658 EXCEPTION_PROLOG_2_RELON(label, h) 659 660 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask)\ 661 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) 662 663 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label, bitmask) \ 664 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 665 EXC_STD, SOFTEN_NOTEST_PR, bitmask) 666 667 #define MASKABLE_RELON_EXCEPTION_PSERIES_OOL(vec, label, bitmask) \ 668 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_PR, vec, bitmask);\ 669 EXCEPTION_PROLOG_2(label, EXC_STD); 670 671 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label, bitmask) \ 672 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 673 EXC_HV, SOFTEN_TEST_HV, bitmask) 674 675 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \ 676 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 677 EXCEPTION_PROLOG_2_RELON(label, EXC_HV) 678 679 /* 680 * Our exception common code can be passed various "additions" 681 * to specify the behaviour of interrupts, whether to kick the 682 * runlatch, etc... 683 */ 684 685 /* 686 * This addition reconciles our actual IRQ state with the various software 687 * flags that track it. This may call C code. 688 */ 689 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 690 691 #define ADD_NVGPRS \ 692 bl save_nvgprs 693 694 #define RUNLATCH_ON \ 695 BEGIN_FTR_SECTION \ 696 CURRENT_THREAD_INFO(r3, r1); \ 697 ld r4,TI_LOCAL_FLAGS(r3); \ 698 andi. r0,r4,_TLF_RUNLATCH; \ 699 beql ppc64_runlatch_on_trampoline; \ 700 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 701 702 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 703 EXCEPTION_PROLOG_COMMON(trap, area); \ 704 /* Volatile regs are potentially clobbered here */ \ 705 additions; \ 706 addi r3,r1,STACK_FRAME_OVERHEAD; \ 707 bl hdlr; \ 708 b ret 709 710 /* 711 * Exception where stack is already set in r1, r1 is saved in r10, and it 712 * continues rather than returns. 713 */ 714 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 715 EXCEPTION_PROLOG_COMMON_1(); \ 716 EXCEPTION_PROLOG_COMMON_2(area); \ 717 EXCEPTION_PROLOG_COMMON_3(trap); \ 718 /* Volatile regs are potentially clobbered here */ \ 719 additions; \ 720 addi r3,r1,STACK_FRAME_OVERHEAD; \ 721 bl hdlr 722 723 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 724 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 725 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 726 727 /* 728 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 729 * in the idle task and therefore need the special idle handling 730 * (finish nap and runlatch) 731 */ 732 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 733 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 734 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 735 736 /* 737 * When the idle code in power4_idle puts the CPU into NAP mode, 738 * it has to do so in a loop, and relies on the external interrupt 739 * and decrementer interrupt entry code to get it out of the loop. 740 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 741 * to signal that it is in the loop and needs help to get out. 742 */ 743 #ifdef CONFIG_PPC_970_NAP 744 #define FINISH_NAP \ 745 BEGIN_FTR_SECTION \ 746 CURRENT_THREAD_INFO(r11, r1); \ 747 ld r9,TI_LOCAL_FLAGS(r11); \ 748 andi. r10,r9,_TLF_NAPPING; \ 749 bnel power4_fixup_nap; \ 750 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 751 #else 752 #define FINISH_NAP 753 #endif 754 755 #endif /* _ASM_POWERPC_EXCEPTION_H */ 756