1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 39 /* PACA save area offsets (exgen, exmc, etc) */ 40 #define EX_R9 0 41 #define EX_R10 8 42 #define EX_R11 16 43 #define EX_R12 24 44 #define EX_R13 32 45 #define EX_DAR 40 46 #define EX_DSISR 48 47 #define EX_CCR 52 48 #define EX_CFAR 56 49 #define EX_PPR 64 50 #if defined(CONFIG_RELOCATABLE) 51 #define EX_CTR 72 52 #define EX_SIZE 10 /* size in u64 units */ 53 #else 54 #define EX_SIZE 9 /* size in u64 units */ 55 #endif 56 57 /* 58 * maximum recursive depth of MCE exceptions 59 */ 60 #define MAX_MCE_DEPTH 4 61 62 /* 63 * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR 64 * EX_CCR similarly with DSISR, but being 4 byte registers there is a hole 65 * in the save area so it's not necessary to overlap them. Could be used 66 * for future savings though if another 4 byte register was to be saved. 67 */ 68 #define EX_LR EX_DAR 69 70 /* 71 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 72 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 73 * with EX_DAR. 74 */ 75 #define EX_R3 EX_DAR 76 77 #ifdef CONFIG_RELOCATABLE 78 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 79 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 80 LOAD_HANDLER(r12,label); \ 81 mtctr r12; \ 82 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 83 li r10,MSR_RI; \ 84 mtmsrd r10,1; /* Set RI (EE=0) */ \ 85 bctr; 86 #else 87 /* If not relocatable, we can jump directly -- and save messing with LR */ 88 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 89 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 90 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 91 li r10,MSR_RI; \ 92 mtmsrd r10,1; /* Set RI (EE=0) */ \ 93 b label; 94 #endif 95 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 96 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 97 98 /* 99 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 100 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 101 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 102 */ 103 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 104 EXCEPTION_PROLOG_0(area); \ 105 EXCEPTION_PROLOG_1(area, extra, vec); \ 106 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 107 108 /* 109 * We're short on space and time in the exception prolog, so we can't 110 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 111 * Instead we get the base of the kernel from paca->kernelbase and or in the low 112 * part of label. This requires that the label be within 64KB of kernelbase, and 113 * that kernelbase be 64K aligned. 114 */ 115 #define LOAD_HANDLER(reg, label) \ 116 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 117 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label); 118 119 #define __LOAD_HANDLER(reg, label) \ 120 ld reg,PACAKBASE(r13); \ 121 ori reg,reg,(ABS_ADDR(label))@l; 122 123 /* 124 * Branches from unrelocated code (e.g., interrupts) to labels outside 125 * head-y require >64K offsets. 126 */ 127 #define __LOAD_FAR_HANDLER(reg, label) \ 128 ld reg,PACAKBASE(r13); \ 129 ori reg,reg,(ABS_ADDR(label))@l; \ 130 addis reg,reg,(ABS_ADDR(label))@h; 131 132 /* Exception register prefixes */ 133 #define EXC_HV H 134 #define EXC_STD 135 136 #if defined(CONFIG_RELOCATABLE) 137 /* 138 * If we support interrupts with relocation on AND we're a relocatable kernel, 139 * we need to use CTR to get to the 2nd level handler. So, save/restore it 140 * when required. 141 */ 142 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 143 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 144 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 145 #else 146 /* ...else CTR is unused and in register. */ 147 #define SAVE_CTR(reg, area) 148 #define GET_CTR(reg, area) mfctr reg 149 #define RESTORE_CTR(reg, area) 150 #endif 151 152 /* 153 * PPR save/restore macros used in exceptions_64s.S 154 * Used for P7 or later processors 155 */ 156 #define SAVE_PPR(area, ra, rb) \ 157 BEGIN_FTR_SECTION_NESTED(940) \ 158 ld ra,PACACURRENT(r13); \ 159 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 160 std rb,TASKTHREADPPR(ra); \ 161 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 162 163 #define RESTORE_PPR_PACA(area, ra) \ 164 BEGIN_FTR_SECTION_NESTED(941) \ 165 ld ra,area+EX_PPR(r13); \ 166 mtspr SPRN_PPR,ra; \ 167 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 168 169 /* 170 * Get an SPR into a register if the CPU has the given feature 171 */ 172 #define OPT_GET_SPR(ra, spr, ftr) \ 173 BEGIN_FTR_SECTION_NESTED(943) \ 174 mfspr ra,spr; \ 175 END_FTR_SECTION_NESTED(ftr,ftr,943) 176 177 /* 178 * Set an SPR from a register if the CPU has the given feature 179 */ 180 #define OPT_SET_SPR(ra, spr, ftr) \ 181 BEGIN_FTR_SECTION_NESTED(943) \ 182 mtspr spr,ra; \ 183 END_FTR_SECTION_NESTED(ftr,ftr,943) 184 185 /* 186 * Save a register to the PACA if the CPU has the given feature 187 */ 188 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 189 BEGIN_FTR_SECTION_NESTED(943) \ 190 std ra,offset(r13); \ 191 END_FTR_SECTION_NESTED(ftr,ftr,943) 192 193 #define EXCEPTION_PROLOG_0(area) \ 194 GET_PACA(r13); \ 195 std r9,area+EX_R9(r13); /* save r9 */ \ 196 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 197 HMT_MEDIUM; \ 198 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 199 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 200 201 #define __EXCEPTION_PROLOG_1(area, extra, vec) \ 202 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 203 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 204 SAVE_CTR(r10, area); \ 205 mfcr r9; \ 206 extra(vec); \ 207 std r11,area+EX_R11(r13); \ 208 std r12,area+EX_R12(r13); \ 209 GET_SCRATCH0(r10); \ 210 std r10,area+EX_R13(r13) 211 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 212 __EXCEPTION_PROLOG_1(area, extra, vec) 213 214 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ 215 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 216 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 217 LOAD_HANDLER(r12,label) \ 218 mtspr SPRN_##h##SRR0,r12; \ 219 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 220 mtspr SPRN_##h##SRR1,r10; \ 221 h##rfid; \ 222 b . /* prevent speculative execution */ 223 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ 224 __EXCEPTION_PROLOG_PSERIES_1(label, h) 225 226 /* _NORI variant keeps MSR_RI clear */ 227 #define __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 228 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 229 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \ 230 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 231 LOAD_HANDLER(r12,label) \ 232 mtspr SPRN_##h##SRR0,r12; \ 233 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 234 mtspr SPRN_##h##SRR1,r10; \ 235 h##rfid; \ 236 b . /* prevent speculative execution */ 237 238 #define EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 239 __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) 240 241 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 242 EXCEPTION_PROLOG_0(area); \ 243 EXCEPTION_PROLOG_1(area, extra, vec); \ 244 EXCEPTION_PROLOG_PSERIES_1(label, h); 245 246 #define __KVMTEST(h, n) \ 247 lbz r10,HSTATE_IN_GUEST(r13); \ 248 cmpwi r10,0; \ 249 bne do_kvm_##h##n 250 251 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 252 /* 253 * If hv is possible, interrupts come into to the hv version 254 * of the kvmppc_interrupt code, which then jumps to the PR handler, 255 * kvmppc_interrupt_pr, if the guest is a PR guest. 256 */ 257 #define kvmppc_interrupt kvmppc_interrupt_hv 258 #else 259 #define kvmppc_interrupt kvmppc_interrupt_pr 260 #endif 261 262 /* 263 * Branch to label using its 0xC000 address. This results in instruction 264 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 265 * on using mtmsr rather than rfid. 266 * 267 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 268 * load KBASE for a slight optimisation. 269 */ 270 #define BRANCH_TO_C000(reg, label) \ 271 __LOAD_HANDLER(reg, label); \ 272 mtctr reg; \ 273 bctr 274 275 #ifdef CONFIG_RELOCATABLE 276 #define BRANCH_TO_COMMON(reg, label) \ 277 __LOAD_HANDLER(reg, label); \ 278 mtctr reg; \ 279 bctr 280 281 #define BRANCH_LINK_TO_FAR(label) \ 282 __LOAD_FAR_HANDLER(r12, label); \ 283 mtctr r12; \ 284 bctrl 285 286 /* 287 * KVM requires __LOAD_FAR_HANDLER. 288 * 289 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 290 * explicitly use r9 then reload it from PACA before branching. Hence 291 * the double-underscore. 292 */ 293 #define __BRANCH_TO_KVM_EXIT(area, label) \ 294 mfctr r9; \ 295 std r9,HSTATE_SCRATCH1(r13); \ 296 __LOAD_FAR_HANDLER(r9, label); \ 297 mtctr r9; \ 298 ld r9,area+EX_R9(r13); \ 299 bctr 300 301 #else 302 #define BRANCH_TO_COMMON(reg, label) \ 303 b label 304 305 #define BRANCH_LINK_TO_FAR(label) \ 306 bl label 307 308 #define __BRANCH_TO_KVM_EXIT(area, label) \ 309 ld r9,area+EX_R9(r13); \ 310 b label 311 312 #endif 313 314 /* Do not enable RI */ 315 #define EXCEPTION_PROLOG_PSERIES_NORI(area, label, h, extra, vec) \ 316 EXCEPTION_PROLOG_0(area); \ 317 EXCEPTION_PROLOG_1(area, extra, vec); \ 318 EXCEPTION_PROLOG_PSERIES_1_NORI(label, h); 319 320 321 #define __KVM_HANDLER(area, h, n) \ 322 BEGIN_FTR_SECTION_NESTED(947) \ 323 ld r10,area+EX_CFAR(r13); \ 324 std r10,HSTATE_CFAR(r13); \ 325 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 326 BEGIN_FTR_SECTION_NESTED(948) \ 327 ld r10,area+EX_PPR(r13); \ 328 std r10,HSTATE_PPR(r13); \ 329 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 330 ld r10,area+EX_R10(r13); \ 331 std r12,HSTATE_SCRATCH0(r13); \ 332 sldi r12,r9,32; \ 333 ori r12,r12,(n); \ 334 /* This reloads r9 before branching to kvmppc_interrupt */ \ 335 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt) 336 337 #define __KVM_HANDLER_SKIP(area, h, n) \ 338 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 339 beq 89f; \ 340 BEGIN_FTR_SECTION_NESTED(948) \ 341 ld r10,area+EX_PPR(r13); \ 342 std r10,HSTATE_PPR(r13); \ 343 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 344 ld r10,area+EX_R10(r13); \ 345 std r12,HSTATE_SCRATCH0(r13); \ 346 sldi r12,r9,32; \ 347 ori r12,r12,(n); \ 348 /* This reloads r9 before branching to kvmppc_interrupt */ \ 349 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \ 350 89: mtocrf 0x80,r9; \ 351 ld r9,area+EX_R9(r13); \ 352 ld r10,area+EX_R10(r13); \ 353 b kvmppc_skip_##h##interrupt 354 355 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 356 #define KVMTEST(h, n) __KVMTEST(h, n) 357 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 358 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 359 360 #else 361 #define KVMTEST(h, n) 362 #define KVM_HANDLER(area, h, n) 363 #define KVM_HANDLER_SKIP(area, h, n) 364 #endif 365 366 #define NOTEST(n) 367 368 #define EXCEPTION_PROLOG_COMMON_1() \ 369 std r9,_CCR(r1); /* save CR in stackframe */ \ 370 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 371 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 372 std r10,0(r1); /* make stack chain pointer */ \ 373 std r0,GPR0(r1); /* save r0 in stackframe */ \ 374 std r10,GPR1(r1); /* save r1 in stackframe */ \ 375 376 377 /* 378 * The common exception prolog is used for all except a few exceptions 379 * such as a segment miss on a kernel address. We have to be prepared 380 * to take another exception from the point where we first touch the 381 * kernel stack onwards. 382 * 383 * On entry r13 points to the paca, r9-r13 are saved in the paca, 384 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 385 * SRR1, and relocation is on. 386 */ 387 #define EXCEPTION_PROLOG_COMMON(n, area) \ 388 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 389 mr r10,r1; /* Save r1 */ \ 390 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 391 beq- 1f; \ 392 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 393 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 394 blt+ cr1,3f; /* abort if it is */ \ 395 li r1,(n); /* will be reloaded later */ \ 396 sth r1,PACA_TRAP_SAVE(r13); \ 397 std r3,area+EX_R3(r13); \ 398 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 399 RESTORE_CTR(r1, area); \ 400 b bad_stack; \ 401 3: EXCEPTION_PROLOG_COMMON_1(); \ 402 beq 4f; /* if from kernel mode */ \ 403 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 404 SAVE_PPR(area, r9, r10); \ 405 4: EXCEPTION_PROLOG_COMMON_2(area) \ 406 EXCEPTION_PROLOG_COMMON_3(n) \ 407 ACCOUNT_STOLEN_TIME 408 409 /* Save original regs values from save area to stack frame. */ 410 #define EXCEPTION_PROLOG_COMMON_2(area) \ 411 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 412 ld r10,area+EX_R10(r13); \ 413 std r9,GPR9(r1); \ 414 std r10,GPR10(r1); \ 415 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 416 ld r10,area+EX_R12(r13); \ 417 ld r11,area+EX_R13(r13); \ 418 std r9,GPR11(r1); \ 419 std r10,GPR12(r1); \ 420 std r11,GPR13(r1); \ 421 BEGIN_FTR_SECTION_NESTED(66); \ 422 ld r10,area+EX_CFAR(r13); \ 423 std r10,ORIG_GPR3(r1); \ 424 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 425 GET_CTR(r10, area); \ 426 std r10,_CTR(r1); 427 428 #define EXCEPTION_PROLOG_COMMON_3(n) \ 429 std r2,GPR2(r1); /* save r2 in stackframe */ \ 430 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 431 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 432 mflr r9; /* Get LR, later save to stack */ \ 433 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 434 std r9,_LINK(r1); \ 435 lbz r10,PACAIRQSOFTMASK(r13); \ 436 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 437 std r10,SOFTE(r1); \ 438 std r11,_XER(r1); \ 439 li r9,(n)+1; \ 440 std r9,_TRAP(r1); /* set trap number */ \ 441 li r10,0; \ 442 ld r11,exception_marker@toc(r2); \ 443 std r10,RESULT(r1); /* clear regs->result */ \ 444 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 445 446 /* 447 * Exception vectors. 448 */ 449 #define STD_EXCEPTION_PSERIES(vec, label) \ 450 SET_SCRATCH0(r13); /* save r13 */ \ 451 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 452 EXC_STD, KVMTEST_PR, vec); \ 453 454 /* Version of above for when we have to branch out-of-line */ 455 #define __OOL_EXCEPTION(vec, label, hdlr) \ 456 SET_SCRATCH0(r13) \ 457 EXCEPTION_PROLOG_0(PACA_EXGEN) \ 458 b hdlr; 459 460 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \ 461 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 462 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 463 464 #define STD_EXCEPTION_HV(loc, vec, label) \ 465 SET_SCRATCH0(r13); /* save r13 */ \ 466 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 467 EXC_HV, KVMTEST_HV, vec); 468 469 #define STD_EXCEPTION_HV_OOL(vec, label) \ 470 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 471 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 472 473 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 474 /* No guest interrupts come through here */ \ 475 SET_SCRATCH0(r13); /* save r13 */ \ 476 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec); 477 478 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \ 479 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 480 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_STD) 481 482 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 483 SET_SCRATCH0(r13); /* save r13 */ \ 484 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, \ 485 EXC_HV, KVMTEST_HV, vec); 486 487 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 488 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 489 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 490 491 /* This associate vector numbers with bits in paca->irq_happened */ 492 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 493 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 494 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC 495 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 496 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 497 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 498 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 499 500 #define __SOFTEN_TEST(h, vec) \ 501 lbz r10,PACAIRQSOFTMASK(r13); \ 502 andi. r10,r10,IRQS_DISABLED; \ 503 li r10,SOFTEN_VALUE_##vec; \ 504 bne masked_##h##interrupt 505 506 #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec) 507 508 #define SOFTEN_TEST_PR(vec) \ 509 KVMTEST(EXC_STD, vec); \ 510 _SOFTEN_TEST(EXC_STD, vec) 511 512 #define SOFTEN_TEST_HV(vec) \ 513 KVMTEST(EXC_HV, vec); \ 514 _SOFTEN_TEST(EXC_HV, vec) 515 516 #define KVMTEST_PR(vec) \ 517 KVMTEST(EXC_STD, vec) 518 519 #define KVMTEST_HV(vec) \ 520 KVMTEST(EXC_HV, vec) 521 522 #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec) 523 #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) 524 525 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 526 SET_SCRATCH0(r13); /* save r13 */ \ 527 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 528 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 529 EXCEPTION_PROLOG_PSERIES_1(label, h); 530 531 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 532 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) 533 534 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \ 535 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 536 EXC_STD, SOFTEN_TEST_PR) 537 538 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label) \ 539 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec); \ 540 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 541 542 #define MASKABLE_EXCEPTION_HV(loc, vec, label) \ 543 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 544 EXC_HV, SOFTEN_TEST_HV) 545 546 #define MASKABLE_EXCEPTION_HV_OOL(vec, label) \ 547 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ 548 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 549 550 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 551 SET_SCRATCH0(r13); /* save r13 */ \ 552 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 553 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 554 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 555 556 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 557 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) 558 559 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 560 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 561 EXC_STD, SOFTEN_NOTEST_PR) 562 563 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \ 564 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 565 EXC_HV, SOFTEN_TEST_HV) 566 567 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \ 568 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ 569 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 570 571 /* 572 * Our exception common code can be passed various "additions" 573 * to specify the behaviour of interrupts, whether to kick the 574 * runlatch, etc... 575 */ 576 577 /* 578 * This addition reconciles our actual IRQ state with the various software 579 * flags that track it. This may call C code. 580 */ 581 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 582 583 #define ADD_NVGPRS \ 584 bl save_nvgprs 585 586 #define RUNLATCH_ON \ 587 BEGIN_FTR_SECTION \ 588 CURRENT_THREAD_INFO(r3, r1); \ 589 ld r4,TI_LOCAL_FLAGS(r3); \ 590 andi. r0,r4,_TLF_RUNLATCH; \ 591 beql ppc64_runlatch_on_trampoline; \ 592 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 593 594 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 595 EXCEPTION_PROLOG_COMMON(trap, area); \ 596 /* Volatile regs are potentially clobbered here */ \ 597 additions; \ 598 addi r3,r1,STACK_FRAME_OVERHEAD; \ 599 bl hdlr; \ 600 b ret 601 602 /* 603 * Exception where stack is already set in r1, r1 is saved in r10, and it 604 * continues rather than returns. 605 */ 606 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 607 EXCEPTION_PROLOG_COMMON_1(); \ 608 EXCEPTION_PROLOG_COMMON_2(area); \ 609 EXCEPTION_PROLOG_COMMON_3(trap); \ 610 /* Volatile regs are potentially clobbered here */ \ 611 additions; \ 612 addi r3,r1,STACK_FRAME_OVERHEAD; \ 613 bl hdlr 614 615 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 616 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 617 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 618 619 /* 620 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 621 * in the idle task and therefore need the special idle handling 622 * (finish nap and runlatch) 623 */ 624 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 625 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 626 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 627 628 /* 629 * When the idle code in power4_idle puts the CPU into NAP mode, 630 * it has to do so in a loop, and relies on the external interrupt 631 * and decrementer interrupt entry code to get it out of the loop. 632 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 633 * to signal that it is in the loop and needs help to get out. 634 */ 635 #ifdef CONFIG_PPC_970_NAP 636 #define FINISH_NAP \ 637 BEGIN_FTR_SECTION \ 638 CURRENT_THREAD_INFO(r11, r1); \ 639 ld r9,TI_LOCAL_FLAGS(r11); \ 640 andi. r10,r9,_TLF_NAPPING; \ 641 bnel power4_fixup_nap; \ 642 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 643 #else 644 #define FINISH_NAP 645 #endif 646 647 #endif /* _ASM_POWERPC_EXCEPTION_H */ 648