1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_EXCEPTION_H
3 #define _ASM_POWERPC_EXCEPTION_H
4 /*
5  * Extracted from head_64.S
6  *
7  *  PowerPC version
8  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9  *
10  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
11  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
12  *  Adapted for Power Macintosh by Paul Mackerras.
13  *  Low-level exception handlers and MMU support
14  *  rewritten by Paul Mackerras.
15  *    Copyright (C) 1996 Paul Mackerras.
16  *
17  *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
18  *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
19  *
20  *  This file contains the low-level support and setup for the
21  *  PowerPC-64 platform, including trap and interrupt dispatch.
22  */
23 /*
24  * The following macros define the code that appears as
25  * the prologue to each of the exception handlers.  They
26  * are split into two parts to allow a single kernel binary
27  * to be used for pSeries and iSeries.
28  *
29  * We make as much of the exception code common between native
30  * exception handlers (including pSeries LPAR) and iSeries LPAR
31  * implementations as possible.
32  */
33 #include <asm/feature-fixups.h>
34 
35 /* PACA save area size in u64 units (exgen, exmc, etc) */
36 #define EX_SIZE		10
37 
38 /*
39  * maximum recursive depth of MCE exceptions
40  */
41 #define MAX_MCE_DEPTH	4
42 
43 #ifdef __ASSEMBLY__
44 
45 #define STF_ENTRY_BARRIER_SLOT						\
46 	STF_ENTRY_BARRIER_FIXUP_SECTION;				\
47 	nop;								\
48 	nop;								\
49 	nop
50 
51 #define STF_EXIT_BARRIER_SLOT						\
52 	STF_EXIT_BARRIER_FIXUP_SECTION;					\
53 	nop;								\
54 	nop;								\
55 	nop;								\
56 	nop;								\
57 	nop;								\
58 	nop
59 
60 /*
61  * r10 must be free to use, r13 must be paca
62  */
63 #define INTERRUPT_TO_KERNEL						\
64 	STF_ENTRY_BARRIER_SLOT
65 
66 /*
67  * Macros for annotating the expected destination of (h)rfid
68  *
69  * The nop instructions allow us to insert one or more instructions to flush the
70  * L1-D cache when returning to userspace or a guest.
71  *
72  * powerpc relies on return from interrupt/syscall being context synchronising
73  * (which hrfid, rfid, and rfscv are) to support ARCH_HAS_MEMBARRIER_SYNC_CORE
74  * without additional synchronisation instructions.
75  *
76  * soft-masked interrupt replay does not include a context-synchronising rfid,
77  * but those always return to kernel, the sync is only required when returning
78  * to user.
79  */
80 #define RFI_FLUSH_SLOT							\
81 	RFI_FLUSH_FIXUP_SECTION;					\
82 	nop;								\
83 	nop;								\
84 	nop
85 
86 #define RFI_TO_KERNEL							\
87 	rfid
88 
89 #define RFI_TO_USER							\
90 	STF_EXIT_BARRIER_SLOT;						\
91 	RFI_FLUSH_SLOT;							\
92 	rfid;								\
93 	b	rfi_flush_fallback
94 
95 #define RFI_TO_USER_OR_KERNEL						\
96 	STF_EXIT_BARRIER_SLOT;						\
97 	RFI_FLUSH_SLOT;							\
98 	rfid;								\
99 	b	rfi_flush_fallback
100 
101 #define RFI_TO_GUEST							\
102 	STF_EXIT_BARRIER_SLOT;						\
103 	RFI_FLUSH_SLOT;							\
104 	rfid;								\
105 	b	rfi_flush_fallback
106 
107 #define HRFI_TO_KERNEL							\
108 	hrfid
109 
110 #define HRFI_TO_USER							\
111 	STF_EXIT_BARRIER_SLOT;						\
112 	RFI_FLUSH_SLOT;							\
113 	hrfid;								\
114 	b	hrfi_flush_fallback
115 
116 #define HRFI_TO_USER_OR_KERNEL						\
117 	STF_EXIT_BARRIER_SLOT;						\
118 	RFI_FLUSH_SLOT;							\
119 	hrfid;								\
120 	b	hrfi_flush_fallback
121 
122 #define HRFI_TO_GUEST							\
123 	STF_EXIT_BARRIER_SLOT;						\
124 	RFI_FLUSH_SLOT;							\
125 	hrfid;								\
126 	b	hrfi_flush_fallback
127 
128 #define HRFI_TO_UNKNOWN							\
129 	STF_EXIT_BARRIER_SLOT;						\
130 	RFI_FLUSH_SLOT;							\
131 	hrfid;								\
132 	b	hrfi_flush_fallback
133 
134 #define RFSCV_TO_USER							\
135 	STF_EXIT_BARRIER_SLOT;						\
136 	RFI_FLUSH_SLOT;							\
137 	RFSCV;								\
138 	b	rfscv_flush_fallback
139 
140 #endif /* __ASSEMBLY__ */
141 
142 #endif	/* _ASM_POWERPC_EXCEPTION_H */
143