1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 #include <asm/feature-fixups.h> 39 40 /* PACA save area offsets (exgen, exmc, etc) */ 41 #define EX_R9 0 42 #define EX_R10 8 43 #define EX_R11 16 44 #define EX_R12 24 45 #define EX_R13 32 46 #define EX_DAR 40 47 #define EX_DSISR 48 48 #define EX_CCR 52 49 #define EX_CFAR 56 50 #define EX_PPR 64 51 #if defined(CONFIG_RELOCATABLE) 52 #define EX_CTR 72 53 #define EX_SIZE 10 /* size in u64 units */ 54 #else 55 #define EX_SIZE 9 /* size in u64 units */ 56 #endif 57 58 /* 59 * maximum recursive depth of MCE exceptions 60 */ 61 #define MAX_MCE_DEPTH 4 62 63 /* 64 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 65 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 66 * with EX_DAR. 67 */ 68 #define EX_R3 EX_DAR 69 70 #ifdef __ASSEMBLY__ 71 72 #define STF_ENTRY_BARRIER_SLOT \ 73 STF_ENTRY_BARRIER_FIXUP_SECTION; \ 74 nop; \ 75 nop; \ 76 nop 77 78 #define STF_EXIT_BARRIER_SLOT \ 79 STF_EXIT_BARRIER_FIXUP_SECTION; \ 80 nop; \ 81 nop; \ 82 nop; \ 83 nop; \ 84 nop; \ 85 nop 86 87 /* 88 * r10 must be free to use, r13 must be paca 89 */ 90 #define INTERRUPT_TO_KERNEL \ 91 STF_ENTRY_BARRIER_SLOT 92 93 /* 94 * Macros for annotating the expected destination of (h)rfid 95 * 96 * The nop instructions allow us to insert one or more instructions to flush the 97 * L1-D cache when returning to userspace or a guest. 98 */ 99 #define RFI_FLUSH_SLOT \ 100 RFI_FLUSH_FIXUP_SECTION; \ 101 nop; \ 102 nop; \ 103 nop 104 105 #define RFI_TO_KERNEL \ 106 rfid 107 108 #define RFI_TO_USER \ 109 STF_EXIT_BARRIER_SLOT; \ 110 RFI_FLUSH_SLOT; \ 111 rfid; \ 112 b rfi_flush_fallback 113 114 #define RFI_TO_USER_OR_KERNEL \ 115 STF_EXIT_BARRIER_SLOT; \ 116 RFI_FLUSH_SLOT; \ 117 rfid; \ 118 b rfi_flush_fallback 119 120 #define RFI_TO_GUEST \ 121 STF_EXIT_BARRIER_SLOT; \ 122 RFI_FLUSH_SLOT; \ 123 rfid; \ 124 b rfi_flush_fallback 125 126 #define HRFI_TO_KERNEL \ 127 hrfid 128 129 #define HRFI_TO_USER \ 130 STF_EXIT_BARRIER_SLOT; \ 131 RFI_FLUSH_SLOT; \ 132 hrfid; \ 133 b hrfi_flush_fallback 134 135 #define HRFI_TO_USER_OR_KERNEL \ 136 STF_EXIT_BARRIER_SLOT; \ 137 RFI_FLUSH_SLOT; \ 138 hrfid; \ 139 b hrfi_flush_fallback 140 141 #define HRFI_TO_GUEST \ 142 STF_EXIT_BARRIER_SLOT; \ 143 RFI_FLUSH_SLOT; \ 144 hrfid; \ 145 b hrfi_flush_fallback 146 147 #define HRFI_TO_UNKNOWN \ 148 STF_EXIT_BARRIER_SLOT; \ 149 RFI_FLUSH_SLOT; \ 150 hrfid; \ 151 b hrfi_flush_fallback 152 153 /* 154 * We're short on space and time in the exception prolog, so we can't 155 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 156 * Instead we get the base of the kernel from paca->kernelbase and or in the low 157 * part of label. This requires that the label be within 64KB of kernelbase, and 158 * that kernelbase be 64K aligned. 159 */ 160 #define LOAD_HANDLER(reg, label) \ 161 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 162 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) 163 164 #define __LOAD_HANDLER(reg, label) \ 165 ld reg,PACAKBASE(r13); \ 166 ori reg,reg,(ABS_ADDR(label))@l 167 168 /* 169 * Branches from unrelocated code (e.g., interrupts) to labels outside 170 * head-y require >64K offsets. 171 */ 172 #define __LOAD_FAR_HANDLER(reg, label) \ 173 ld reg,PACAKBASE(r13); \ 174 ori reg,reg,(ABS_ADDR(label))@l; \ 175 addis reg,reg,(ABS_ADDR(label))@h 176 177 .macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri 178 ld r10,PACAKMSR(r13) /* get MSR value for kernel */ 179 .if ! \set_ri 180 xori r10,r10,MSR_RI /* Clear MSR_RI */ 181 .endif 182 .if \hsrr 183 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 184 .else 185 mfspr r11,SPRN_SRR0 /* save SRR0 */ 186 .endif 187 LOAD_HANDLER(r12, \label\()) 188 .if \hsrr 189 mtspr SPRN_HSRR0,r12 190 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 191 mtspr SPRN_HSRR1,r10 192 HRFI_TO_KERNEL 193 .else 194 mtspr SPRN_SRR0,r12 195 mfspr r12,SPRN_SRR1 /* and SRR1 */ 196 mtspr SPRN_SRR1,r10 197 RFI_TO_KERNEL 198 .endif 199 b . /* prevent speculative execution */ 200 .endm 201 202 .macro EXCEPTION_PROLOG_2_VIRT label, hsrr 203 #ifdef CONFIG_RELOCATABLE 204 .if \hsrr 205 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 206 .else 207 mfspr r11,SPRN_SRR0 /* save SRR0 */ 208 .endif 209 LOAD_HANDLER(r12, \label\()) 210 mtctr r12 211 .if \hsrr 212 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 213 .else 214 mfspr r12,SPRN_SRR1 /* and HSRR1 */ 215 .endif 216 li r10,MSR_RI 217 mtmsrd r10,1 /* Set RI (EE=0) */ 218 bctr 219 #else 220 .if \hsrr 221 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 222 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 223 .else 224 mfspr r11,SPRN_SRR0 /* save SRR0 */ 225 mfspr r12,SPRN_SRR1 /* and SRR1 */ 226 .endif 227 li r10,MSR_RI 228 mtmsrd r10,1 /* Set RI (EE=0) */ 229 b \label 230 #endif 231 .endm 232 233 /* 234 * As EXCEPTION_PROLOG(), except we've already got relocation on so no need to 235 * rfid. Save CTR in case we're CONFIG_RELOCATABLE, in which case 236 * EXCEPTION_PROLOG_2_VIRT will be using CTR. 237 */ 238 #define EXCEPTION_RELON_PROLOG(area, label, hsrr, extra, vec) \ 239 SET_SCRATCH0(r13); /* save r13 */ \ 240 EXCEPTION_PROLOG_0(area); \ 241 EXCEPTION_PROLOG_1(area, extra, vec); \ 242 EXCEPTION_PROLOG_2_VIRT label, hsrr 243 244 /* Exception register prefixes */ 245 #define EXC_HV 1 246 #define EXC_STD 0 247 248 #if defined(CONFIG_RELOCATABLE) 249 /* 250 * If we support interrupts with relocation on AND we're a relocatable kernel, 251 * we need to use CTR to get to the 2nd level handler. So, save/restore it 252 * when required. 253 */ 254 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 255 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 256 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 257 #else 258 /* ...else CTR is unused and in register. */ 259 #define SAVE_CTR(reg, area) 260 #define GET_CTR(reg, area) mfctr reg 261 #define RESTORE_CTR(reg, area) 262 #endif 263 264 /* 265 * PPR save/restore macros used in exceptions_64s.S 266 * Used for P7 or later processors 267 */ 268 #define SAVE_PPR(area, ra) \ 269 BEGIN_FTR_SECTION_NESTED(940) \ 270 ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ 271 std ra,_PPR(r1); \ 272 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 273 274 #define RESTORE_PPR_PACA(area, ra) \ 275 BEGIN_FTR_SECTION_NESTED(941) \ 276 ld ra,area+EX_PPR(r13); \ 277 mtspr SPRN_PPR,ra; \ 278 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 279 280 /* 281 * Get an SPR into a register if the CPU has the given feature 282 */ 283 #define OPT_GET_SPR(ra, spr, ftr) \ 284 BEGIN_FTR_SECTION_NESTED(943) \ 285 mfspr ra,spr; \ 286 END_FTR_SECTION_NESTED(ftr,ftr,943) 287 288 /* 289 * Set an SPR from a register if the CPU has the given feature 290 */ 291 #define OPT_SET_SPR(ra, spr, ftr) \ 292 BEGIN_FTR_SECTION_NESTED(943) \ 293 mtspr spr,ra; \ 294 END_FTR_SECTION_NESTED(ftr,ftr,943) 295 296 /* 297 * Save a register to the PACA if the CPU has the given feature 298 */ 299 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 300 BEGIN_FTR_SECTION_NESTED(943) \ 301 std ra,offset(r13); \ 302 END_FTR_SECTION_NESTED(ftr,ftr,943) 303 304 #define EXCEPTION_PROLOG_0(area) \ 305 GET_PACA(r13); \ 306 std r9,area+EX_R9(r13); /* save r9 */ \ 307 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 308 HMT_MEDIUM; \ 309 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 310 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 311 312 #define __EXCEPTION_PROLOG_1_PRE(area) \ 313 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 314 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 315 INTERRUPT_TO_KERNEL; \ 316 SAVE_CTR(r10, area); \ 317 mfcr r9 318 319 #define __EXCEPTION_PROLOG_1_POST(area) \ 320 std r11,area+EX_R11(r13); \ 321 std r12,area+EX_R12(r13); \ 322 GET_SCRATCH0(r10); \ 323 std r10,area+EX_R13(r13) 324 325 /* 326 * This version of the EXCEPTION_PROLOG_1 will carry 327 * addition parameter called "bitmask" to support 328 * checking of the interrupt maskable level in the SOFTEN_TEST. 329 * Intended to be used in MASKABLE_EXCPETION_* macros. 330 */ 331 #define MASKABLE_EXCEPTION_PROLOG_1(area, extra, vec, bitmask) \ 332 __EXCEPTION_PROLOG_1_PRE(area); \ 333 extra(vec, bitmask); \ 334 __EXCEPTION_PROLOG_1_POST(area) 335 336 /* 337 * This version of the EXCEPTION_PROLOG_1 is intended 338 * to be used in STD_EXCEPTION* macros 339 */ 340 #define _EXCEPTION_PROLOG_1(area, extra, vec) \ 341 __EXCEPTION_PROLOG_1_PRE(area); \ 342 extra(vec); \ 343 __EXCEPTION_PROLOG_1_POST(area) 344 345 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 346 _EXCEPTION_PROLOG_1(area, extra, vec) 347 348 #define EXCEPTION_PROLOG(area, label, h, extra, vec) \ 349 SET_SCRATCH0(r13); /* save r13 */ \ 350 EXCEPTION_PROLOG_0(area); \ 351 EXCEPTION_PROLOG_1(area, extra, vec); \ 352 EXCEPTION_PROLOG_2_REAL label, h, 1 353 354 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 355 /* 356 * If hv is possible, interrupts come into to the hv version 357 * of the kvmppc_interrupt code, which then jumps to the PR handler, 358 * kvmppc_interrupt_pr, if the guest is a PR guest. 359 */ 360 #define kvmppc_interrupt kvmppc_interrupt_hv 361 #else 362 #define kvmppc_interrupt kvmppc_interrupt_pr 363 #endif 364 365 /* 366 * Branch to label using its 0xC000 address. This results in instruction 367 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 368 * on using mtmsr rather than rfid. 369 * 370 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 371 * load KBASE for a slight optimisation. 372 */ 373 #define BRANCH_TO_C000(reg, label) \ 374 __LOAD_HANDLER(reg, label); \ 375 mtctr reg; \ 376 bctr 377 378 #ifdef CONFIG_RELOCATABLE 379 #define BRANCH_TO_COMMON(reg, label) \ 380 __LOAD_HANDLER(reg, label); \ 381 mtctr reg; \ 382 bctr 383 384 #define BRANCH_LINK_TO_FAR(label) \ 385 __LOAD_FAR_HANDLER(r12, label); \ 386 mtctr r12; \ 387 bctrl 388 389 /* 390 * KVM requires __LOAD_FAR_HANDLER. 391 * 392 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 393 * explicitly use r9 then reload it from PACA before branching. Hence 394 * the double-underscore. 395 */ 396 #define __BRANCH_TO_KVM_EXIT(area, label) \ 397 mfctr r9; \ 398 std r9,HSTATE_SCRATCH1(r13); \ 399 __LOAD_FAR_HANDLER(r9, label); \ 400 mtctr r9; \ 401 ld r9,area+EX_R9(r13); \ 402 bctr 403 404 #else 405 #define BRANCH_TO_COMMON(reg, label) \ 406 b label 407 408 #define BRANCH_LINK_TO_FAR(label) \ 409 bl label 410 411 #define __BRANCH_TO_KVM_EXIT(area, label) \ 412 ld r9,area+EX_R9(r13); \ 413 b label 414 415 #endif 416 417 /* Do not enable RI */ 418 #define EXCEPTION_PROLOG_NORI(area, label, h, extra, vec) \ 419 EXCEPTION_PROLOG_0(area); \ 420 EXCEPTION_PROLOG_1(area, extra, vec); \ 421 EXCEPTION_PROLOG_2_REAL label, h, 0 422 423 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 424 .macro KVMTEST hsrr, n 425 lbz r10,HSTATE_IN_GUEST(r13) 426 cmpwi r10,0 427 .if \hsrr 428 bne do_kvm_H\n 429 .else 430 bne do_kvm_\n 431 .endif 432 .endm 433 434 .macro KVM_HANDLER area, hsrr, n 435 BEGIN_FTR_SECTION_NESTED(947) 436 ld r10,\area+EX_CFAR(r13) 437 std r10,HSTATE_CFAR(r13) 438 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947) 439 BEGIN_FTR_SECTION_NESTED(948) 440 ld r10,\area+EX_PPR(r13) 441 std r10,HSTATE_PPR(r13) 442 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) 443 ld r10,\area+EX_R10(r13) 444 std r12,HSTATE_SCRATCH0(r13) 445 sldi r12,r9,32 446 ori r12,r12,(\n) 447 /* This reloads r9 before branching to kvmppc_interrupt */ 448 __BRANCH_TO_KVM_EXIT(\area, kvmppc_interrupt) 449 .endm 450 451 .macro KVM_HANDLER_SKIP area, hsrr, n 452 cmpwi r10,KVM_GUEST_MODE_SKIP 453 beq 89f 454 BEGIN_FTR_SECTION_NESTED(948) 455 ld r10,\area+EX_PPR(r13) 456 std r10,HSTATE_PPR(r13) 457 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) 458 ld r10,\area+EX_R10(r13) 459 std r12,HSTATE_SCRATCH0(r13) 460 sldi r12,r9,32 461 ori r12,r12,(\n) 462 /* This reloads r9 before branching to kvmppc_interrupt */ 463 __BRANCH_TO_KVM_EXIT(\area, kvmppc_interrupt) 464 89: mtocrf 0x80,r9 465 ld r9,\area+EX_R9(r13) 466 ld r10,\area+EX_R10(r13) 467 .if \hsrr 468 b kvmppc_skip_Hinterrupt 469 .else 470 b kvmppc_skip_interrupt 471 .endif 472 .endm 473 474 #else 475 .macro KVMTEST hsrr, n 476 .endm 477 .macro KVM_HANDLER area, hsrr, n 478 .endm 479 .macro KVM_HANDLER_SKIP area, hsrr, n 480 .endm 481 #endif 482 483 #define NOTEST(n) 484 485 #define EXCEPTION_PROLOG_COMMON_1() \ 486 std r9,_CCR(r1); /* save CR in stackframe */ \ 487 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 488 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 489 std r10,0(r1); /* make stack chain pointer */ \ 490 std r0,GPR0(r1); /* save r0 in stackframe */ \ 491 std r10,GPR1(r1); /* save r1 in stackframe */ \ 492 493 494 /* 495 * The common exception prolog is used for all except a few exceptions 496 * such as a segment miss on a kernel address. We have to be prepared 497 * to take another exception from the point where we first touch the 498 * kernel stack onwards. 499 * 500 * On entry r13 points to the paca, r9-r13 are saved in the paca, 501 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 502 * SRR1, and relocation is on. 503 */ 504 #define EXCEPTION_PROLOG_COMMON(n, area) \ 505 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 506 mr r10,r1; /* Save r1 */ \ 507 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 508 beq- 1f; \ 509 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 510 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 511 blt+ cr1,3f; /* abort if it is */ \ 512 li r1,(n); /* will be reloaded later */ \ 513 sth r1,PACA_TRAP_SAVE(r13); \ 514 std r3,area+EX_R3(r13); \ 515 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 516 RESTORE_CTR(r1, area); \ 517 b bad_stack; \ 518 3: EXCEPTION_PROLOG_COMMON_1(); \ 519 kuap_save_amr_and_lock r9, r10, cr1, cr0; \ 520 beq 4f; /* if from kernel mode */ \ 521 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 522 SAVE_PPR(area, r9); \ 523 4: EXCEPTION_PROLOG_COMMON_2(area) \ 524 EXCEPTION_PROLOG_COMMON_3(n) \ 525 ACCOUNT_STOLEN_TIME 526 527 /* Save original regs values from save area to stack frame. */ 528 #define EXCEPTION_PROLOG_COMMON_2(area) \ 529 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 530 ld r10,area+EX_R10(r13); \ 531 std r9,GPR9(r1); \ 532 std r10,GPR10(r1); \ 533 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 534 ld r10,area+EX_R12(r13); \ 535 ld r11,area+EX_R13(r13); \ 536 std r9,GPR11(r1); \ 537 std r10,GPR12(r1); \ 538 std r11,GPR13(r1); \ 539 BEGIN_FTR_SECTION_NESTED(66); \ 540 ld r10,area+EX_CFAR(r13); \ 541 std r10,ORIG_GPR3(r1); \ 542 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 543 GET_CTR(r10, area); \ 544 std r10,_CTR(r1); 545 546 #define EXCEPTION_PROLOG_COMMON_3(n) \ 547 std r2,GPR2(r1); /* save r2 in stackframe */ \ 548 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 549 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 550 mflr r9; /* Get LR, later save to stack */ \ 551 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 552 std r9,_LINK(r1); \ 553 lbz r10,PACAIRQSOFTMASK(r13); \ 554 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 555 std r10,SOFTE(r1); \ 556 std r11,_XER(r1); \ 557 li r9,(n)+1; \ 558 std r9,_TRAP(r1); /* set trap number */ \ 559 li r10,0; \ 560 ld r11,exception_marker@toc(r2); \ 561 std r10,RESULT(r1); /* clear regs->result */ \ 562 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 563 564 /* 565 * Exception vectors. 566 */ 567 #define STD_EXCEPTION(vec, label) \ 568 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_STD, KVMTEST_PR, vec); 569 570 /* Version of above for when we have to branch out-of-line */ 571 #define __OOL_EXCEPTION(vec, label, hdlr) \ 572 SET_SCRATCH0(r13); \ 573 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 574 b hdlr 575 576 #define STD_EXCEPTION_OOL(vec, label) \ 577 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 578 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1 579 580 #define STD_EXCEPTION_HV(loc, vec, label) \ 581 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_HV, KVMTEST_HV, vec) 582 583 #define STD_EXCEPTION_HV_OOL(vec, label) \ 584 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 585 EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1 586 587 #define STD_RELON_EXCEPTION(loc, vec, label) \ 588 /* No guest interrupts come through here */ \ 589 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_STD, NOTEST, vec) 590 591 #define STD_RELON_EXCEPTION_OOL(vec, label) \ 592 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 593 EXCEPTION_PROLOG_2_VIRT label, EXC_STD 594 595 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 596 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_HV, KVMTEST_HV, vec) 597 598 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 599 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 600 EXCEPTION_PROLOG_2_VIRT label, EXC_HV 601 602 .macro SOFTEN_TEST hsrr, vec, bitmask 603 lbz r10, PACAIRQSOFTMASK(r13) 604 andi. r10, r10, \bitmask 605 /* This associates vector numbers with bits in paca->irq_happened */ 606 .if \vec == 0x500 || \vec == 0xea0 607 li r10, PACA_IRQ_EE 608 .elseif \vec == 0x900 609 li r10, PACA_IRQ_DEC 610 .elseif \vec == 0xa00 || \vec == 0xe80 611 li r10, PACA_IRQ_DBELL 612 .elseif \vec == 0xe60 613 li r10, PACA_IRQ_HMI 614 .elseif \vec == 0xf00 615 li r10, PACA_IRQ_PMI 616 .else 617 .abort "Bad maskable vector" 618 .endif 619 620 621 .if \hsrr 622 bne masked_Hinterrupt 623 .else 624 bne masked_interrupt 625 .endif 626 .endm 627 628 #define SOFTEN_TEST_PR(vec, bitmask) \ 629 KVMTEST EXC_STD, vec ; \ 630 SOFTEN_TEST EXC_STD, vec, bitmask 631 632 #define SOFTEN_TEST_HV(vec, bitmask) \ 633 KVMTEST EXC_HV, vec ; \ 634 SOFTEN_TEST EXC_HV, vec, bitmask 635 636 #define KVMTEST_PR(vec) \ 637 KVMTEST EXC_STD, vec 638 639 #define KVMTEST_HV(vec) \ 640 KVMTEST EXC_HV, vec 641 642 #define SOFTEN_NOTEST_PR(vec, bitmask) SOFTEN_TEST EXC_STD, vec, bitmask 643 #define SOFTEN_NOTEST_HV(vec, bitmask) SOFTEN_TEST EXC_HV, vec, bitmask 644 645 #define __MASKABLE_EXCEPTION(vec, label, h, extra, bitmask) \ 646 SET_SCRATCH0(r13); /* save r13 */ \ 647 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 648 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 649 EXCEPTION_PROLOG_2_REAL label, h, 1 650 651 #define MASKABLE_EXCEPTION(vec, label, bitmask) \ 652 __MASKABLE_EXCEPTION(vec, label, EXC_STD, SOFTEN_TEST_PR, bitmask) 653 654 #define MASKABLE_EXCEPTION_OOL(vec, label, bitmask) \ 655 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec, bitmask);\ 656 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1 657 658 #define MASKABLE_EXCEPTION_HV(vec, label, bitmask) \ 659 __MASKABLE_EXCEPTION(vec, label, EXC_HV, SOFTEN_TEST_HV, bitmask) 660 661 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \ 662 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 663 EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1 664 665 #define __MASKABLE_RELON_EXCEPTION(vec, label, h, extra, bitmask) \ 666 SET_SCRATCH0(r13); /* save r13 */ \ 667 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 668 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 669 EXCEPTION_PROLOG_2_VIRT label, h 670 671 #define MASKABLE_RELON_EXCEPTION(vec, label, bitmask) \ 672 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_STD, SOFTEN_NOTEST_PR, bitmask) 673 674 #define MASKABLE_RELON_EXCEPTION_OOL(vec, label, bitmask) \ 675 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_PR, vec, bitmask);\ 676 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1 677 678 #define MASKABLE_RELON_EXCEPTION_HV(vec, label, bitmask) \ 679 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_HV, SOFTEN_TEST_HV, bitmask) 680 681 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \ 682 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 683 EXCEPTION_PROLOG_2_VIRT label, EXC_HV 684 685 /* 686 * Our exception common code can be passed various "additions" 687 * to specify the behaviour of interrupts, whether to kick the 688 * runlatch, etc... 689 */ 690 691 /* 692 * This addition reconciles our actual IRQ state with the various software 693 * flags that track it. This may call C code. 694 */ 695 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 696 697 #define ADD_NVGPRS \ 698 bl save_nvgprs 699 700 #define RUNLATCH_ON \ 701 BEGIN_FTR_SECTION \ 702 ld r3, PACA_THREAD_INFO(r13); \ 703 ld r4,TI_LOCAL_FLAGS(r3); \ 704 andi. r0,r4,_TLF_RUNLATCH; \ 705 beql ppc64_runlatch_on_trampoline; \ 706 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 707 708 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 709 EXCEPTION_PROLOG_COMMON(trap, area); \ 710 /* Volatile regs are potentially clobbered here */ \ 711 additions; \ 712 addi r3,r1,STACK_FRAME_OVERHEAD; \ 713 bl hdlr; \ 714 b ret 715 716 /* 717 * Exception where stack is already set in r1, r1 is saved in r10, and it 718 * continues rather than returns. 719 */ 720 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 721 EXCEPTION_PROLOG_COMMON_1(); \ 722 kuap_save_amr_and_lock r9, r10, cr1; \ 723 EXCEPTION_PROLOG_COMMON_2(area); \ 724 EXCEPTION_PROLOG_COMMON_3(trap); \ 725 /* Volatile regs are potentially clobbered here */ \ 726 additions; \ 727 addi r3,r1,STACK_FRAME_OVERHEAD; \ 728 bl hdlr 729 730 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 731 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 732 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 733 734 /* 735 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 736 * in the idle task and therefore need the special idle handling 737 * (finish nap and runlatch) 738 */ 739 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 740 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 741 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 742 743 /* 744 * When the idle code in power4_idle puts the CPU into NAP mode, 745 * it has to do so in a loop, and relies on the external interrupt 746 * and decrementer interrupt entry code to get it out of the loop. 747 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 748 * to signal that it is in the loop and needs help to get out. 749 */ 750 #ifdef CONFIG_PPC_970_NAP 751 #define FINISH_NAP \ 752 BEGIN_FTR_SECTION \ 753 ld r11, PACA_THREAD_INFO(r13); \ 754 ld r9,TI_LOCAL_FLAGS(r11); \ 755 andi. r10,r9,_TLF_NAPPING; \ 756 bnel power4_fixup_nap; \ 757 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 758 #else 759 #define FINISH_NAP 760 #endif 761 762 #endif /* __ASSEMBLY__ */ 763 764 #endif /* _ASM_POWERPC_EXCEPTION_H */ 765