1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 39 /* PACA save area offsets (exgen, exmc, etc) */ 40 #define EX_R9 0 41 #define EX_R10 8 42 #define EX_R11 16 43 #define EX_R12 24 44 #define EX_R13 32 45 #define EX_DAR 40 46 #define EX_DSISR 48 47 #define EX_CCR 52 48 #define EX_CFAR 56 49 #define EX_PPR 64 50 #if defined(CONFIG_RELOCATABLE) 51 #define EX_CTR 72 52 #define EX_SIZE 10 /* size in u64 units */ 53 #else 54 #define EX_SIZE 9 /* size in u64 units */ 55 #endif 56 57 /* 58 * maximum recursive depth of MCE exceptions 59 */ 60 #define MAX_MCE_DEPTH 4 61 62 /* 63 * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR 64 * EX_CCR similarly with DSISR, but being 4 byte registers there is a hole 65 * in the save area so it's not necessary to overlap them. Could be used 66 * for future savings though if another 4 byte register was to be saved. 67 */ 68 #define EX_LR EX_DAR 69 70 /* 71 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 72 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 73 * with EX_DAR. 74 */ 75 #define EX_R3 EX_DAR 76 77 /* Macros for annotating the expected destination of (h)rfid */ 78 79 #define RFI_TO_KERNEL \ 80 rfid 81 82 #define RFI_TO_USER \ 83 rfid 84 85 #define RFI_TO_USER_OR_KERNEL \ 86 rfid 87 88 #define RFI_TO_GUEST \ 89 rfid 90 91 #define HRFI_TO_KERNEL \ 92 hrfid 93 94 #define HRFI_TO_USER \ 95 hrfid 96 97 #define HRFI_TO_USER_OR_KERNEL \ 98 hrfid 99 100 #define HRFI_TO_GUEST \ 101 hrfid 102 103 #define HRFI_TO_UNKNOWN \ 104 hrfid 105 106 #ifdef CONFIG_RELOCATABLE 107 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 108 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 109 LOAD_HANDLER(r12,label); \ 110 mtctr r12; \ 111 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 112 li r10,MSR_RI; \ 113 mtmsrd r10,1; /* Set RI (EE=0) */ \ 114 bctr; 115 #else 116 /* If not relocatable, we can jump directly -- and save messing with LR */ 117 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 118 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 119 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 120 li r10,MSR_RI; \ 121 mtmsrd r10,1; /* Set RI (EE=0) */ \ 122 b label; 123 #endif 124 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 125 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 126 127 /* 128 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 129 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 130 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 131 */ 132 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 133 EXCEPTION_PROLOG_0(area); \ 134 EXCEPTION_PROLOG_1(area, extra, vec); \ 135 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 136 137 /* 138 * We're short on space and time in the exception prolog, so we can't 139 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 140 * Instead we get the base of the kernel from paca->kernelbase and or in the low 141 * part of label. This requires that the label be within 64KB of kernelbase, and 142 * that kernelbase be 64K aligned. 143 */ 144 #define LOAD_HANDLER(reg, label) \ 145 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 146 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label); 147 148 #define __LOAD_HANDLER(reg, label) \ 149 ld reg,PACAKBASE(r13); \ 150 ori reg,reg,(ABS_ADDR(label))@l; 151 152 /* 153 * Branches from unrelocated code (e.g., interrupts) to labels outside 154 * head-y require >64K offsets. 155 */ 156 #define __LOAD_FAR_HANDLER(reg, label) \ 157 ld reg,PACAKBASE(r13); \ 158 ori reg,reg,(ABS_ADDR(label))@l; \ 159 addis reg,reg,(ABS_ADDR(label))@h; 160 161 /* Exception register prefixes */ 162 #define EXC_HV H 163 #define EXC_STD 164 165 #if defined(CONFIG_RELOCATABLE) 166 /* 167 * If we support interrupts with relocation on AND we're a relocatable kernel, 168 * we need to use CTR to get to the 2nd level handler. So, save/restore it 169 * when required. 170 */ 171 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 172 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 173 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 174 #else 175 /* ...else CTR is unused and in register. */ 176 #define SAVE_CTR(reg, area) 177 #define GET_CTR(reg, area) mfctr reg 178 #define RESTORE_CTR(reg, area) 179 #endif 180 181 /* 182 * PPR save/restore macros used in exceptions_64s.S 183 * Used for P7 or later processors 184 */ 185 #define SAVE_PPR(area, ra, rb) \ 186 BEGIN_FTR_SECTION_NESTED(940) \ 187 ld ra,PACACURRENT(r13); \ 188 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 189 std rb,TASKTHREADPPR(ra); \ 190 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 191 192 #define RESTORE_PPR_PACA(area, ra) \ 193 BEGIN_FTR_SECTION_NESTED(941) \ 194 ld ra,area+EX_PPR(r13); \ 195 mtspr SPRN_PPR,ra; \ 196 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 197 198 /* 199 * Get an SPR into a register if the CPU has the given feature 200 */ 201 #define OPT_GET_SPR(ra, spr, ftr) \ 202 BEGIN_FTR_SECTION_NESTED(943) \ 203 mfspr ra,spr; \ 204 END_FTR_SECTION_NESTED(ftr,ftr,943) 205 206 /* 207 * Set an SPR from a register if the CPU has the given feature 208 */ 209 #define OPT_SET_SPR(ra, spr, ftr) \ 210 BEGIN_FTR_SECTION_NESTED(943) \ 211 mtspr spr,ra; \ 212 END_FTR_SECTION_NESTED(ftr,ftr,943) 213 214 /* 215 * Save a register to the PACA if the CPU has the given feature 216 */ 217 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 218 BEGIN_FTR_SECTION_NESTED(943) \ 219 std ra,offset(r13); \ 220 END_FTR_SECTION_NESTED(ftr,ftr,943) 221 222 #define EXCEPTION_PROLOG_0(area) \ 223 GET_PACA(r13); \ 224 std r9,area+EX_R9(r13); /* save r9 */ \ 225 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 226 HMT_MEDIUM; \ 227 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 228 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 229 230 #define __EXCEPTION_PROLOG_1(area, extra, vec) \ 231 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 232 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 233 SAVE_CTR(r10, area); \ 234 mfcr r9; \ 235 extra(vec); \ 236 std r11,area+EX_R11(r13); \ 237 std r12,area+EX_R12(r13); \ 238 GET_SCRATCH0(r10); \ 239 std r10,area+EX_R13(r13) 240 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 241 __EXCEPTION_PROLOG_1(area, extra, vec) 242 243 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ 244 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 245 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 246 LOAD_HANDLER(r12,label) \ 247 mtspr SPRN_##h##SRR0,r12; \ 248 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 249 mtspr SPRN_##h##SRR1,r10; \ 250 h##RFI_TO_KERNEL; \ 251 b . /* prevent speculative execution */ 252 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ 253 __EXCEPTION_PROLOG_PSERIES_1(label, h) 254 255 /* _NORI variant keeps MSR_RI clear */ 256 #define __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 257 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 258 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \ 259 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 260 LOAD_HANDLER(r12,label) \ 261 mtspr SPRN_##h##SRR0,r12; \ 262 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 263 mtspr SPRN_##h##SRR1,r10; \ 264 h##RFI_TO_KERNEL; \ 265 b . /* prevent speculative execution */ 266 267 #define EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 268 __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) 269 270 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 271 EXCEPTION_PROLOG_0(area); \ 272 EXCEPTION_PROLOG_1(area, extra, vec); \ 273 EXCEPTION_PROLOG_PSERIES_1(label, h); 274 275 #define __KVMTEST(h, n) \ 276 lbz r10,HSTATE_IN_GUEST(r13); \ 277 cmpwi r10,0; \ 278 bne do_kvm_##h##n 279 280 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 281 /* 282 * If hv is possible, interrupts come into to the hv version 283 * of the kvmppc_interrupt code, which then jumps to the PR handler, 284 * kvmppc_interrupt_pr, if the guest is a PR guest. 285 */ 286 #define kvmppc_interrupt kvmppc_interrupt_hv 287 #else 288 #define kvmppc_interrupt kvmppc_interrupt_pr 289 #endif 290 291 /* 292 * Branch to label using its 0xC000 address. This results in instruction 293 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 294 * on using mtmsr rather than rfid. 295 * 296 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 297 * load KBASE for a slight optimisation. 298 */ 299 #define BRANCH_TO_C000(reg, label) \ 300 __LOAD_HANDLER(reg, label); \ 301 mtctr reg; \ 302 bctr 303 304 #ifdef CONFIG_RELOCATABLE 305 #define BRANCH_TO_COMMON(reg, label) \ 306 __LOAD_HANDLER(reg, label); \ 307 mtctr reg; \ 308 bctr 309 310 #define BRANCH_LINK_TO_FAR(label) \ 311 __LOAD_FAR_HANDLER(r12, label); \ 312 mtctr r12; \ 313 bctrl 314 315 /* 316 * KVM requires __LOAD_FAR_HANDLER. 317 * 318 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 319 * explicitly use r9 then reload it from PACA before branching. Hence 320 * the double-underscore. 321 */ 322 #define __BRANCH_TO_KVM_EXIT(area, label) \ 323 mfctr r9; \ 324 std r9,HSTATE_SCRATCH1(r13); \ 325 __LOAD_FAR_HANDLER(r9, label); \ 326 mtctr r9; \ 327 ld r9,area+EX_R9(r13); \ 328 bctr 329 330 #else 331 #define BRANCH_TO_COMMON(reg, label) \ 332 b label 333 334 #define BRANCH_LINK_TO_FAR(label) \ 335 bl label 336 337 #define __BRANCH_TO_KVM_EXIT(area, label) \ 338 ld r9,area+EX_R9(r13); \ 339 b label 340 341 #endif 342 343 /* Do not enable RI */ 344 #define EXCEPTION_PROLOG_PSERIES_NORI(area, label, h, extra, vec) \ 345 EXCEPTION_PROLOG_0(area); \ 346 EXCEPTION_PROLOG_1(area, extra, vec); \ 347 EXCEPTION_PROLOG_PSERIES_1_NORI(label, h); 348 349 350 #define __KVM_HANDLER(area, h, n) \ 351 BEGIN_FTR_SECTION_NESTED(947) \ 352 ld r10,area+EX_CFAR(r13); \ 353 std r10,HSTATE_CFAR(r13); \ 354 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 355 BEGIN_FTR_SECTION_NESTED(948) \ 356 ld r10,area+EX_PPR(r13); \ 357 std r10,HSTATE_PPR(r13); \ 358 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 359 ld r10,area+EX_R10(r13); \ 360 std r12,HSTATE_SCRATCH0(r13); \ 361 sldi r12,r9,32; \ 362 ori r12,r12,(n); \ 363 /* This reloads r9 before branching to kvmppc_interrupt */ \ 364 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt) 365 366 #define __KVM_HANDLER_SKIP(area, h, n) \ 367 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 368 beq 89f; \ 369 BEGIN_FTR_SECTION_NESTED(948) \ 370 ld r10,area+EX_PPR(r13); \ 371 std r10,HSTATE_PPR(r13); \ 372 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 373 ld r10,area+EX_R10(r13); \ 374 std r12,HSTATE_SCRATCH0(r13); \ 375 sldi r12,r9,32; \ 376 ori r12,r12,(n); \ 377 /* This reloads r9 before branching to kvmppc_interrupt */ \ 378 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \ 379 89: mtocrf 0x80,r9; \ 380 ld r9,area+EX_R9(r13); \ 381 ld r10,area+EX_R10(r13); \ 382 b kvmppc_skip_##h##interrupt 383 384 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 385 #define KVMTEST(h, n) __KVMTEST(h, n) 386 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 387 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 388 389 #else 390 #define KVMTEST(h, n) 391 #define KVM_HANDLER(area, h, n) 392 #define KVM_HANDLER_SKIP(area, h, n) 393 #endif 394 395 #define NOTEST(n) 396 397 #define EXCEPTION_PROLOG_COMMON_1() \ 398 std r9,_CCR(r1); /* save CR in stackframe */ \ 399 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 400 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 401 std r10,0(r1); /* make stack chain pointer */ \ 402 std r0,GPR0(r1); /* save r0 in stackframe */ \ 403 std r10,GPR1(r1); /* save r1 in stackframe */ \ 404 405 406 /* 407 * The common exception prolog is used for all except a few exceptions 408 * such as a segment miss on a kernel address. We have to be prepared 409 * to take another exception from the point where we first touch the 410 * kernel stack onwards. 411 * 412 * On entry r13 points to the paca, r9-r13 are saved in the paca, 413 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 414 * SRR1, and relocation is on. 415 */ 416 #define EXCEPTION_PROLOG_COMMON(n, area) \ 417 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 418 mr r10,r1; /* Save r1 */ \ 419 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 420 beq- 1f; \ 421 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 422 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 423 blt+ cr1,3f; /* abort if it is */ \ 424 li r1,(n); /* will be reloaded later */ \ 425 sth r1,PACA_TRAP_SAVE(r13); \ 426 std r3,area+EX_R3(r13); \ 427 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 428 RESTORE_CTR(r1, area); \ 429 b bad_stack; \ 430 3: EXCEPTION_PROLOG_COMMON_1(); \ 431 beq 4f; /* if from kernel mode */ \ 432 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 433 SAVE_PPR(area, r9, r10); \ 434 4: EXCEPTION_PROLOG_COMMON_2(area) \ 435 EXCEPTION_PROLOG_COMMON_3(n) \ 436 ACCOUNT_STOLEN_TIME 437 438 /* Save original regs values from save area to stack frame. */ 439 #define EXCEPTION_PROLOG_COMMON_2(area) \ 440 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 441 ld r10,area+EX_R10(r13); \ 442 std r9,GPR9(r1); \ 443 std r10,GPR10(r1); \ 444 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 445 ld r10,area+EX_R12(r13); \ 446 ld r11,area+EX_R13(r13); \ 447 std r9,GPR11(r1); \ 448 std r10,GPR12(r1); \ 449 std r11,GPR13(r1); \ 450 BEGIN_FTR_SECTION_NESTED(66); \ 451 ld r10,area+EX_CFAR(r13); \ 452 std r10,ORIG_GPR3(r1); \ 453 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 454 GET_CTR(r10, area); \ 455 std r10,_CTR(r1); 456 457 #define EXCEPTION_PROLOG_COMMON_3(n) \ 458 std r2,GPR2(r1); /* save r2 in stackframe */ \ 459 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 460 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 461 mflr r9; /* Get LR, later save to stack */ \ 462 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 463 std r9,_LINK(r1); \ 464 lbz r10,PACASOFTIRQEN(r13); \ 465 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 466 std r10,SOFTE(r1); \ 467 std r11,_XER(r1); \ 468 li r9,(n)+1; \ 469 std r9,_TRAP(r1); /* set trap number */ \ 470 li r10,0; \ 471 ld r11,exception_marker@toc(r2); \ 472 std r10,RESULT(r1); /* clear regs->result */ \ 473 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 474 475 /* 476 * Exception vectors. 477 */ 478 #define STD_EXCEPTION_PSERIES(vec, label) \ 479 SET_SCRATCH0(r13); /* save r13 */ \ 480 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 481 EXC_STD, KVMTEST_PR, vec); \ 482 483 /* Version of above for when we have to branch out-of-line */ 484 #define __OOL_EXCEPTION(vec, label, hdlr) \ 485 SET_SCRATCH0(r13) \ 486 EXCEPTION_PROLOG_0(PACA_EXGEN) \ 487 b hdlr; 488 489 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \ 490 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 491 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 492 493 #define STD_EXCEPTION_HV(loc, vec, label) \ 494 SET_SCRATCH0(r13); /* save r13 */ \ 495 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 496 EXC_HV, KVMTEST_HV, vec); 497 498 #define STD_EXCEPTION_HV_OOL(vec, label) \ 499 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 500 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 501 502 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 503 /* No guest interrupts come through here */ \ 504 SET_SCRATCH0(r13); /* save r13 */ \ 505 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec); 506 507 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \ 508 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 509 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_STD) 510 511 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 512 SET_SCRATCH0(r13); /* save r13 */ \ 513 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, \ 514 EXC_HV, KVMTEST_HV, vec); 515 516 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 517 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 518 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 519 520 /* This associate vector numbers with bits in paca->irq_happened */ 521 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 522 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 523 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC 524 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 525 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 526 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 527 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 528 529 #define __SOFTEN_TEST(h, vec) \ 530 lbz r10,PACASOFTIRQEN(r13); \ 531 cmpwi r10,0; \ 532 li r10,SOFTEN_VALUE_##vec; \ 533 beq masked_##h##interrupt 534 535 #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec) 536 537 #define SOFTEN_TEST_PR(vec) \ 538 KVMTEST(EXC_STD, vec); \ 539 _SOFTEN_TEST(EXC_STD, vec) 540 541 #define SOFTEN_TEST_HV(vec) \ 542 KVMTEST(EXC_HV, vec); \ 543 _SOFTEN_TEST(EXC_HV, vec) 544 545 #define KVMTEST_PR(vec) \ 546 KVMTEST(EXC_STD, vec) 547 548 #define KVMTEST_HV(vec) \ 549 KVMTEST(EXC_HV, vec) 550 551 #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec) 552 #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) 553 554 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 555 SET_SCRATCH0(r13); /* save r13 */ \ 556 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 557 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 558 EXCEPTION_PROLOG_PSERIES_1(label, h); 559 560 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 561 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) 562 563 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \ 564 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 565 EXC_STD, SOFTEN_TEST_PR) 566 567 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label) \ 568 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec); \ 569 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 570 571 #define MASKABLE_EXCEPTION_HV(loc, vec, label) \ 572 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 573 EXC_HV, SOFTEN_TEST_HV) 574 575 #define MASKABLE_EXCEPTION_HV_OOL(vec, label) \ 576 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ 577 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 578 579 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 580 SET_SCRATCH0(r13); /* save r13 */ \ 581 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 582 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 583 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 584 585 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 586 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) 587 588 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 589 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 590 EXC_STD, SOFTEN_NOTEST_PR) 591 592 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \ 593 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 594 EXC_HV, SOFTEN_TEST_HV) 595 596 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \ 597 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ 598 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 599 600 /* 601 * Our exception common code can be passed various "additions" 602 * to specify the behaviour of interrupts, whether to kick the 603 * runlatch, etc... 604 */ 605 606 /* 607 * This addition reconciles our actual IRQ state with the various software 608 * flags that track it. This may call C code. 609 */ 610 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 611 612 #define ADD_NVGPRS \ 613 bl save_nvgprs 614 615 #define RUNLATCH_ON \ 616 BEGIN_FTR_SECTION \ 617 CURRENT_THREAD_INFO(r3, r1); \ 618 ld r4,TI_LOCAL_FLAGS(r3); \ 619 andi. r0,r4,_TLF_RUNLATCH; \ 620 beql ppc64_runlatch_on_trampoline; \ 621 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 622 623 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 624 EXCEPTION_PROLOG_COMMON(trap, area); \ 625 /* Volatile regs are potentially clobbered here */ \ 626 additions; \ 627 addi r3,r1,STACK_FRAME_OVERHEAD; \ 628 bl hdlr; \ 629 b ret 630 631 /* 632 * Exception where stack is already set in r1, r1 is saved in r10, and it 633 * continues rather than returns. 634 */ 635 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 636 EXCEPTION_PROLOG_COMMON_1(); \ 637 EXCEPTION_PROLOG_COMMON_2(area); \ 638 EXCEPTION_PROLOG_COMMON_3(trap); \ 639 /* Volatile regs are potentially clobbered here */ \ 640 additions; \ 641 addi r3,r1,STACK_FRAME_OVERHEAD; \ 642 bl hdlr 643 644 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 645 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 646 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 647 648 /* 649 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 650 * in the idle task and therefore need the special idle handling 651 * (finish nap and runlatch) 652 */ 653 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 654 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 655 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 656 657 /* 658 * When the idle code in power4_idle puts the CPU into NAP mode, 659 * it has to do so in a loop, and relies on the external interrupt 660 * and decrementer interrupt entry code to get it out of the loop. 661 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 662 * to signal that it is in the loop and needs help to get out. 663 */ 664 #ifdef CONFIG_PPC_970_NAP 665 #define FINISH_NAP \ 666 BEGIN_FTR_SECTION \ 667 CURRENT_THREAD_INFO(r11, r1); \ 668 ld r9,TI_LOCAL_FLAGS(r11); \ 669 andi. r10,r9,_TLF_NAPPING; \ 670 bnel power4_fixup_nap; \ 671 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 672 #else 673 #define FINISH_NAP 674 #endif 675 676 #endif /* _ASM_POWERPC_EXCEPTION_H */ 677