1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 #include <asm/feature-fixups.h> 39 40 /* PACA save area offsets (exgen, exmc, etc) */ 41 #define EX_R9 0 42 #define EX_R10 8 43 #define EX_R11 16 44 #define EX_R12 24 45 #define EX_R13 32 46 #define EX_DAR 40 47 #define EX_DSISR 48 48 #define EX_CCR 52 49 #define EX_CFAR 56 50 #define EX_PPR 64 51 #if defined(CONFIG_RELOCATABLE) 52 #define EX_CTR 72 53 #define EX_SIZE 10 /* size in u64 units */ 54 #else 55 #define EX_SIZE 9 /* size in u64 units */ 56 #endif 57 58 /* 59 * maximum recursive depth of MCE exceptions 60 */ 61 #define MAX_MCE_DEPTH 4 62 63 /* 64 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 65 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 66 * with EX_DAR. 67 */ 68 #define EX_R3 EX_DAR 69 70 #define STF_ENTRY_BARRIER_SLOT \ 71 STF_ENTRY_BARRIER_FIXUP_SECTION; \ 72 nop; \ 73 nop; \ 74 nop 75 76 #define STF_EXIT_BARRIER_SLOT \ 77 STF_EXIT_BARRIER_FIXUP_SECTION; \ 78 nop; \ 79 nop; \ 80 nop; \ 81 nop; \ 82 nop; \ 83 nop 84 85 /* 86 * r10 must be free to use, r13 must be paca 87 */ 88 #define INTERRUPT_TO_KERNEL \ 89 STF_ENTRY_BARRIER_SLOT 90 91 /* 92 * Macros for annotating the expected destination of (h)rfid 93 * 94 * The nop instructions allow us to insert one or more instructions to flush the 95 * L1-D cache when returning to userspace or a guest. 96 */ 97 #define RFI_FLUSH_SLOT \ 98 RFI_FLUSH_FIXUP_SECTION; \ 99 nop; \ 100 nop; \ 101 nop 102 103 #define RFI_TO_KERNEL \ 104 rfid 105 106 #define RFI_TO_USER \ 107 STF_EXIT_BARRIER_SLOT; \ 108 RFI_FLUSH_SLOT; \ 109 rfid; \ 110 b rfi_flush_fallback 111 112 #define RFI_TO_USER_OR_KERNEL \ 113 STF_EXIT_BARRIER_SLOT; \ 114 RFI_FLUSH_SLOT; \ 115 rfid; \ 116 b rfi_flush_fallback 117 118 #define RFI_TO_GUEST \ 119 STF_EXIT_BARRIER_SLOT; \ 120 RFI_FLUSH_SLOT; \ 121 rfid; \ 122 b rfi_flush_fallback 123 124 #define HRFI_TO_KERNEL \ 125 hrfid 126 127 #define HRFI_TO_USER \ 128 STF_EXIT_BARRIER_SLOT; \ 129 RFI_FLUSH_SLOT; \ 130 hrfid; \ 131 b hrfi_flush_fallback 132 133 #define HRFI_TO_USER_OR_KERNEL \ 134 STF_EXIT_BARRIER_SLOT; \ 135 RFI_FLUSH_SLOT; \ 136 hrfid; \ 137 b hrfi_flush_fallback 138 139 #define HRFI_TO_GUEST \ 140 STF_EXIT_BARRIER_SLOT; \ 141 RFI_FLUSH_SLOT; \ 142 hrfid; \ 143 b hrfi_flush_fallback 144 145 #define HRFI_TO_UNKNOWN \ 146 STF_EXIT_BARRIER_SLOT; \ 147 RFI_FLUSH_SLOT; \ 148 hrfid; \ 149 b hrfi_flush_fallback 150 151 #ifdef CONFIG_RELOCATABLE 152 #define __EXCEPTION_PROLOG_2_RELON(label, h) \ 153 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 154 LOAD_HANDLER(r12,label); \ 155 mtctr r12; \ 156 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 157 li r10,MSR_RI; \ 158 mtmsrd r10,1; /* Set RI (EE=0) */ \ 159 bctr; 160 #else 161 /* If not relocatable, we can jump directly -- and save messing with LR */ 162 #define __EXCEPTION_PROLOG_2_RELON(label, h) \ 163 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 164 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 165 li r10,MSR_RI; \ 166 mtmsrd r10,1; /* Set RI (EE=0) */ \ 167 b label; 168 #endif 169 #define EXCEPTION_PROLOG_2_RELON(label, h) \ 170 __EXCEPTION_PROLOG_2_RELON(label, h) 171 172 /* 173 * As EXCEPTION_PROLOG(), except we've already got relocation on so no need to 174 * rfid. Save LR in case we're CONFIG_RELOCATABLE, in which case 175 * EXCEPTION_PROLOG_2_RELON will be using LR. 176 */ 177 #define EXCEPTION_RELON_PROLOG(area, label, h, extra, vec) \ 178 SET_SCRATCH0(r13); /* save r13 */ \ 179 EXCEPTION_PROLOG_0(area); \ 180 EXCEPTION_PROLOG_1(area, extra, vec); \ 181 EXCEPTION_PROLOG_2_RELON(label, h) 182 183 /* 184 * We're short on space and time in the exception prolog, so we can't 185 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 186 * Instead we get the base of the kernel from paca->kernelbase and or in the low 187 * part of label. This requires that the label be within 64KB of kernelbase, and 188 * that kernelbase be 64K aligned. 189 */ 190 #define LOAD_HANDLER(reg, label) \ 191 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 192 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) 193 194 #define __LOAD_HANDLER(reg, label) \ 195 ld reg,PACAKBASE(r13); \ 196 ori reg,reg,(ABS_ADDR(label))@l 197 198 /* 199 * Branches from unrelocated code (e.g., interrupts) to labels outside 200 * head-y require >64K offsets. 201 */ 202 #define __LOAD_FAR_HANDLER(reg, label) \ 203 ld reg,PACAKBASE(r13); \ 204 ori reg,reg,(ABS_ADDR(label))@l; \ 205 addis reg,reg,(ABS_ADDR(label))@h 206 207 /* Exception register prefixes */ 208 #define EXC_HV H 209 #define EXC_STD 210 211 #if defined(CONFIG_RELOCATABLE) 212 /* 213 * If we support interrupts with relocation on AND we're a relocatable kernel, 214 * we need to use CTR to get to the 2nd level handler. So, save/restore it 215 * when required. 216 */ 217 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 218 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 219 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 220 #else 221 /* ...else CTR is unused and in register. */ 222 #define SAVE_CTR(reg, area) 223 #define GET_CTR(reg, area) mfctr reg 224 #define RESTORE_CTR(reg, area) 225 #endif 226 227 /* 228 * PPR save/restore macros used in exceptions_64s.S 229 * Used for P7 or later processors 230 */ 231 #define SAVE_PPR(area, ra) \ 232 BEGIN_FTR_SECTION_NESTED(940) \ 233 ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ 234 std ra,_PPR(r1); \ 235 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 236 237 #define RESTORE_PPR_PACA(area, ra) \ 238 BEGIN_FTR_SECTION_NESTED(941) \ 239 ld ra,area+EX_PPR(r13); \ 240 mtspr SPRN_PPR,ra; \ 241 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 242 243 /* 244 * Get an SPR into a register if the CPU has the given feature 245 */ 246 #define OPT_GET_SPR(ra, spr, ftr) \ 247 BEGIN_FTR_SECTION_NESTED(943) \ 248 mfspr ra,spr; \ 249 END_FTR_SECTION_NESTED(ftr,ftr,943) 250 251 /* 252 * Set an SPR from a register if the CPU has the given feature 253 */ 254 #define OPT_SET_SPR(ra, spr, ftr) \ 255 BEGIN_FTR_SECTION_NESTED(943) \ 256 mtspr spr,ra; \ 257 END_FTR_SECTION_NESTED(ftr,ftr,943) 258 259 /* 260 * Save a register to the PACA if the CPU has the given feature 261 */ 262 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 263 BEGIN_FTR_SECTION_NESTED(943) \ 264 std ra,offset(r13); \ 265 END_FTR_SECTION_NESTED(ftr,ftr,943) 266 267 #define EXCEPTION_PROLOG_0(area) \ 268 GET_PACA(r13); \ 269 std r9,area+EX_R9(r13); /* save r9 */ \ 270 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 271 HMT_MEDIUM; \ 272 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 273 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 274 275 #define __EXCEPTION_PROLOG_1_PRE(area) \ 276 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 277 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 278 INTERRUPT_TO_KERNEL; \ 279 SAVE_CTR(r10, area); \ 280 mfcr r9 281 282 #define __EXCEPTION_PROLOG_1_POST(area) \ 283 std r11,area+EX_R11(r13); \ 284 std r12,area+EX_R12(r13); \ 285 GET_SCRATCH0(r10); \ 286 std r10,area+EX_R13(r13) 287 288 /* 289 * This version of the EXCEPTION_PROLOG_1 will carry 290 * addition parameter called "bitmask" to support 291 * checking of the interrupt maskable level in the SOFTEN_TEST. 292 * Intended to be used in MASKABLE_EXCPETION_* macros. 293 */ 294 #define MASKABLE_EXCEPTION_PROLOG_1(area, extra, vec, bitmask) \ 295 __EXCEPTION_PROLOG_1_PRE(area); \ 296 extra(vec, bitmask); \ 297 __EXCEPTION_PROLOG_1_POST(area) 298 299 /* 300 * This version of the EXCEPTION_PROLOG_1 is intended 301 * to be used in STD_EXCEPTION* macros 302 */ 303 #define _EXCEPTION_PROLOG_1(area, extra, vec) \ 304 __EXCEPTION_PROLOG_1_PRE(area); \ 305 extra(vec); \ 306 __EXCEPTION_PROLOG_1_POST(area) 307 308 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 309 _EXCEPTION_PROLOG_1(area, extra, vec) 310 311 #define __EXCEPTION_PROLOG_2(label, h) \ 312 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 313 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 314 LOAD_HANDLER(r12,label); \ 315 mtspr SPRN_##h##SRR0,r12; \ 316 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 317 mtspr SPRN_##h##SRR1,r10; \ 318 h##RFI_TO_KERNEL; \ 319 b . /* prevent speculative execution */ 320 #define EXCEPTION_PROLOG_2(label, h) \ 321 __EXCEPTION_PROLOG_2(label, h) 322 323 /* _NORI variant keeps MSR_RI clear */ 324 #define __EXCEPTION_PROLOG_2_NORI(label, h) \ 325 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 326 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \ 327 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 328 LOAD_HANDLER(r12,label); \ 329 mtspr SPRN_##h##SRR0,r12; \ 330 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 331 mtspr SPRN_##h##SRR1,r10; \ 332 h##RFI_TO_KERNEL; \ 333 b . /* prevent speculative execution */ 334 335 #define EXCEPTION_PROLOG_2_NORI(label, h) \ 336 __EXCEPTION_PROLOG_2_NORI(label, h) 337 338 #define EXCEPTION_PROLOG(area, label, h, extra, vec) \ 339 SET_SCRATCH0(r13); /* save r13 */ \ 340 EXCEPTION_PROLOG_0(area); \ 341 EXCEPTION_PROLOG_1(area, extra, vec); \ 342 EXCEPTION_PROLOG_2(label, h) 343 344 #define __KVMTEST(h, n) \ 345 lbz r10,HSTATE_IN_GUEST(r13); \ 346 cmpwi r10,0; \ 347 bne do_kvm_##h##n 348 349 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 350 /* 351 * If hv is possible, interrupts come into to the hv version 352 * of the kvmppc_interrupt code, which then jumps to the PR handler, 353 * kvmppc_interrupt_pr, if the guest is a PR guest. 354 */ 355 #define kvmppc_interrupt kvmppc_interrupt_hv 356 #else 357 #define kvmppc_interrupt kvmppc_interrupt_pr 358 #endif 359 360 /* 361 * Branch to label using its 0xC000 address. This results in instruction 362 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 363 * on using mtmsr rather than rfid. 364 * 365 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 366 * load KBASE for a slight optimisation. 367 */ 368 #define BRANCH_TO_C000(reg, label) \ 369 __LOAD_HANDLER(reg, label); \ 370 mtctr reg; \ 371 bctr 372 373 #ifdef CONFIG_RELOCATABLE 374 #define BRANCH_TO_COMMON(reg, label) \ 375 __LOAD_HANDLER(reg, label); \ 376 mtctr reg; \ 377 bctr 378 379 #define BRANCH_LINK_TO_FAR(label) \ 380 __LOAD_FAR_HANDLER(r12, label); \ 381 mtctr r12; \ 382 bctrl 383 384 /* 385 * KVM requires __LOAD_FAR_HANDLER. 386 * 387 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 388 * explicitly use r9 then reload it from PACA before branching. Hence 389 * the double-underscore. 390 */ 391 #define __BRANCH_TO_KVM_EXIT(area, label) \ 392 mfctr r9; \ 393 std r9,HSTATE_SCRATCH1(r13); \ 394 __LOAD_FAR_HANDLER(r9, label); \ 395 mtctr r9; \ 396 ld r9,area+EX_R9(r13); \ 397 bctr 398 399 #else 400 #define BRANCH_TO_COMMON(reg, label) \ 401 b label 402 403 #define BRANCH_LINK_TO_FAR(label) \ 404 bl label 405 406 #define __BRANCH_TO_KVM_EXIT(area, label) \ 407 ld r9,area+EX_R9(r13); \ 408 b label 409 410 #endif 411 412 /* Do not enable RI */ 413 #define EXCEPTION_PROLOG_NORI(area, label, h, extra, vec) \ 414 EXCEPTION_PROLOG_0(area); \ 415 EXCEPTION_PROLOG_1(area, extra, vec); \ 416 EXCEPTION_PROLOG_2_NORI(label, h) 417 418 419 #define __KVM_HANDLER(area, h, n) \ 420 BEGIN_FTR_SECTION_NESTED(947) \ 421 ld r10,area+EX_CFAR(r13); \ 422 std r10,HSTATE_CFAR(r13); \ 423 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 424 BEGIN_FTR_SECTION_NESTED(948) \ 425 ld r10,area+EX_PPR(r13); \ 426 std r10,HSTATE_PPR(r13); \ 427 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 428 ld r10,area+EX_R10(r13); \ 429 std r12,HSTATE_SCRATCH0(r13); \ 430 sldi r12,r9,32; \ 431 ori r12,r12,(n); \ 432 /* This reloads r9 before branching to kvmppc_interrupt */ \ 433 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt) 434 435 #define __KVM_HANDLER_SKIP(area, h, n) \ 436 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 437 beq 89f; \ 438 BEGIN_FTR_SECTION_NESTED(948) \ 439 ld r10,area+EX_PPR(r13); \ 440 std r10,HSTATE_PPR(r13); \ 441 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 442 ld r10,area+EX_R10(r13); \ 443 std r12,HSTATE_SCRATCH0(r13); \ 444 sldi r12,r9,32; \ 445 ori r12,r12,(n); \ 446 /* This reloads r9 before branching to kvmppc_interrupt */ \ 447 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \ 448 89: mtocrf 0x80,r9; \ 449 ld r9,area+EX_R9(r13); \ 450 ld r10,area+EX_R10(r13); \ 451 b kvmppc_skip_##h##interrupt 452 453 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 454 #define KVMTEST(h, n) __KVMTEST(h, n) 455 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 456 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 457 458 #else 459 #define KVMTEST(h, n) 460 #define KVM_HANDLER(area, h, n) 461 #define KVM_HANDLER_SKIP(area, h, n) 462 #endif 463 464 #define NOTEST(n) 465 466 #define EXCEPTION_PROLOG_COMMON_1() \ 467 std r9,_CCR(r1); /* save CR in stackframe */ \ 468 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 469 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 470 std r10,0(r1); /* make stack chain pointer */ \ 471 std r0,GPR0(r1); /* save r0 in stackframe */ \ 472 std r10,GPR1(r1); /* save r1 in stackframe */ \ 473 474 475 /* 476 * The common exception prolog is used for all except a few exceptions 477 * such as a segment miss on a kernel address. We have to be prepared 478 * to take another exception from the point where we first touch the 479 * kernel stack onwards. 480 * 481 * On entry r13 points to the paca, r9-r13 are saved in the paca, 482 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 483 * SRR1, and relocation is on. 484 */ 485 #define EXCEPTION_PROLOG_COMMON(n, area) \ 486 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 487 mr r10,r1; /* Save r1 */ \ 488 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 489 beq- 1f; \ 490 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 491 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 492 blt+ cr1,3f; /* abort if it is */ \ 493 li r1,(n); /* will be reloaded later */ \ 494 sth r1,PACA_TRAP_SAVE(r13); \ 495 std r3,area+EX_R3(r13); \ 496 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 497 RESTORE_CTR(r1, area); \ 498 b bad_stack; \ 499 3: EXCEPTION_PROLOG_COMMON_1(); \ 500 kuap_save_amr_and_lock r9, r10, cr1, cr0; \ 501 beq 4f; /* if from kernel mode */ \ 502 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 503 SAVE_PPR(area, r9); \ 504 4: EXCEPTION_PROLOG_COMMON_2(area) \ 505 EXCEPTION_PROLOG_COMMON_3(n) \ 506 ACCOUNT_STOLEN_TIME 507 508 /* Save original regs values from save area to stack frame. */ 509 #define EXCEPTION_PROLOG_COMMON_2(area) \ 510 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 511 ld r10,area+EX_R10(r13); \ 512 std r9,GPR9(r1); \ 513 std r10,GPR10(r1); \ 514 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 515 ld r10,area+EX_R12(r13); \ 516 ld r11,area+EX_R13(r13); \ 517 std r9,GPR11(r1); \ 518 std r10,GPR12(r1); \ 519 std r11,GPR13(r1); \ 520 BEGIN_FTR_SECTION_NESTED(66); \ 521 ld r10,area+EX_CFAR(r13); \ 522 std r10,ORIG_GPR3(r1); \ 523 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 524 GET_CTR(r10, area); \ 525 std r10,_CTR(r1); 526 527 #define EXCEPTION_PROLOG_COMMON_3(n) \ 528 std r2,GPR2(r1); /* save r2 in stackframe */ \ 529 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 530 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 531 mflr r9; /* Get LR, later save to stack */ \ 532 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 533 std r9,_LINK(r1); \ 534 lbz r10,PACAIRQSOFTMASK(r13); \ 535 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 536 std r10,SOFTE(r1); \ 537 std r11,_XER(r1); \ 538 li r9,(n)+1; \ 539 std r9,_TRAP(r1); /* set trap number */ \ 540 li r10,0; \ 541 ld r11,exception_marker@toc(r2); \ 542 std r10,RESULT(r1); /* clear regs->result */ \ 543 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 544 545 /* 546 * Exception vectors. 547 */ 548 #define STD_EXCEPTION(vec, label) \ 549 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_STD, KVMTEST_PR, vec); 550 551 /* Version of above for when we have to branch out-of-line */ 552 #define __OOL_EXCEPTION(vec, label, hdlr) \ 553 SET_SCRATCH0(r13); \ 554 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 555 b hdlr 556 557 #define STD_EXCEPTION_OOL(vec, label) \ 558 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 559 EXCEPTION_PROLOG_2(label, EXC_STD) 560 561 #define STD_EXCEPTION_HV(loc, vec, label) \ 562 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_HV, KVMTEST_HV, vec) 563 564 #define STD_EXCEPTION_HV_OOL(vec, label) \ 565 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 566 EXCEPTION_PROLOG_2(label, EXC_HV) 567 568 #define STD_RELON_EXCEPTION(loc, vec, label) \ 569 /* No guest interrupts come through here */ \ 570 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_STD, NOTEST, vec) 571 572 #define STD_RELON_EXCEPTION_OOL(vec, label) \ 573 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 574 EXCEPTION_PROLOG_2_RELON(label, EXC_STD) 575 576 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 577 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_HV, KVMTEST_HV, vec) 578 579 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 580 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 581 EXCEPTION_PROLOG_2_RELON(label, EXC_HV) 582 583 /* This associate vector numbers with bits in paca->irq_happened */ 584 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 585 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 586 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 587 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 588 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 589 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 590 #define SOFTEN_VALUE_0xf00 PACA_IRQ_PMI 591 592 #define __SOFTEN_TEST(h, vec, bitmask) \ 593 lbz r10,PACAIRQSOFTMASK(r13); \ 594 andi. r10,r10,bitmask; \ 595 li r10,SOFTEN_VALUE_##vec; \ 596 bne masked_##h##interrupt 597 598 #define _SOFTEN_TEST(h, vec, bitmask) __SOFTEN_TEST(h, vec, bitmask) 599 600 #define SOFTEN_TEST_PR(vec, bitmask) \ 601 KVMTEST(EXC_STD, vec); \ 602 _SOFTEN_TEST(EXC_STD, vec, bitmask) 603 604 #define SOFTEN_TEST_HV(vec, bitmask) \ 605 KVMTEST(EXC_HV, vec); \ 606 _SOFTEN_TEST(EXC_HV, vec, bitmask) 607 608 #define KVMTEST_PR(vec) \ 609 KVMTEST(EXC_STD, vec) 610 611 #define KVMTEST_HV(vec) \ 612 KVMTEST(EXC_HV, vec) 613 614 #define SOFTEN_NOTEST_PR(vec, bitmask) _SOFTEN_TEST(EXC_STD, vec, bitmask) 615 #define SOFTEN_NOTEST_HV(vec, bitmask) _SOFTEN_TEST(EXC_HV, vec, bitmask) 616 617 #define __MASKABLE_EXCEPTION(vec, label, h, extra, bitmask) \ 618 SET_SCRATCH0(r13); /* save r13 */ \ 619 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 620 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 621 EXCEPTION_PROLOG_2(label, h) 622 623 #define MASKABLE_EXCEPTION(vec, label, bitmask) \ 624 __MASKABLE_EXCEPTION(vec, label, EXC_STD, SOFTEN_TEST_PR, bitmask) 625 626 #define MASKABLE_EXCEPTION_OOL(vec, label, bitmask) \ 627 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec, bitmask);\ 628 EXCEPTION_PROLOG_2(label, EXC_STD) 629 630 #define MASKABLE_EXCEPTION_HV(vec, label, bitmask) \ 631 __MASKABLE_EXCEPTION(vec, label, EXC_HV, SOFTEN_TEST_HV, bitmask) 632 633 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \ 634 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 635 EXCEPTION_PROLOG_2(label, EXC_HV) 636 637 #define __MASKABLE_RELON_EXCEPTION(vec, label, h, extra, bitmask) \ 638 SET_SCRATCH0(r13); /* save r13 */ \ 639 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 640 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 641 EXCEPTION_PROLOG_2_RELON(label, h) 642 643 #define MASKABLE_RELON_EXCEPTION(vec, label, bitmask) \ 644 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_STD, SOFTEN_NOTEST_PR, bitmask) 645 646 #define MASKABLE_RELON_EXCEPTION_OOL(vec, label, bitmask) \ 647 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_PR, vec, bitmask);\ 648 EXCEPTION_PROLOG_2(label, EXC_STD) 649 650 #define MASKABLE_RELON_EXCEPTION_HV(vec, label, bitmask) \ 651 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_HV, SOFTEN_TEST_HV, bitmask) 652 653 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \ 654 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 655 EXCEPTION_PROLOG_2_RELON(label, EXC_HV) 656 657 /* 658 * Our exception common code can be passed various "additions" 659 * to specify the behaviour of interrupts, whether to kick the 660 * runlatch, etc... 661 */ 662 663 /* 664 * This addition reconciles our actual IRQ state with the various software 665 * flags that track it. This may call C code. 666 */ 667 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 668 669 #define ADD_NVGPRS \ 670 bl save_nvgprs 671 672 #define RUNLATCH_ON \ 673 BEGIN_FTR_SECTION \ 674 ld r3, PACA_THREAD_INFO(r13); \ 675 ld r4,TI_LOCAL_FLAGS(r3); \ 676 andi. r0,r4,_TLF_RUNLATCH; \ 677 beql ppc64_runlatch_on_trampoline; \ 678 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 679 680 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 681 EXCEPTION_PROLOG_COMMON(trap, area); \ 682 /* Volatile regs are potentially clobbered here */ \ 683 additions; \ 684 addi r3,r1,STACK_FRAME_OVERHEAD; \ 685 bl hdlr; \ 686 b ret 687 688 /* 689 * Exception where stack is already set in r1, r1 is saved in r10, and it 690 * continues rather than returns. 691 */ 692 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 693 EXCEPTION_PROLOG_COMMON_1(); \ 694 kuap_save_amr_and_lock r9, r10, cr1; \ 695 EXCEPTION_PROLOG_COMMON_2(area); \ 696 EXCEPTION_PROLOG_COMMON_3(trap); \ 697 /* Volatile regs are potentially clobbered here */ \ 698 additions; \ 699 addi r3,r1,STACK_FRAME_OVERHEAD; \ 700 bl hdlr 701 702 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 703 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 704 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 705 706 /* 707 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 708 * in the idle task and therefore need the special idle handling 709 * (finish nap and runlatch) 710 */ 711 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 712 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 713 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 714 715 /* 716 * When the idle code in power4_idle puts the CPU into NAP mode, 717 * it has to do so in a loop, and relies on the external interrupt 718 * and decrementer interrupt entry code to get it out of the loop. 719 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 720 * to signal that it is in the loop and needs help to get out. 721 */ 722 #ifdef CONFIG_PPC_970_NAP 723 #define FINISH_NAP \ 724 BEGIN_FTR_SECTION \ 725 ld r11, PACA_THREAD_INFO(r13); \ 726 ld r9,TI_LOCAL_FLAGS(r11); \ 727 andi. r10,r9,_TLF_NAPPING; \ 728 bnel power4_fixup_nap; \ 729 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 730 #else 731 #define FINISH_NAP 732 #endif 733 734 #endif /* _ASM_POWERPC_EXCEPTION_H */ 735