1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 38 #define EX_R9 0 39 #define EX_R10 8 40 #define EX_R11 16 41 #define EX_R12 24 42 #define EX_R13 32 43 #define EX_SRR0 40 44 #define EX_DAR 48 45 #define EX_DSISR 56 46 #define EX_CCR 60 47 #define EX_R3 64 48 #define EX_LR 72 49 #define EX_CFAR 80 50 #define EX_PPR 88 /* SMT thread status register (priority) */ 51 52 #ifdef CONFIG_RELOCATABLE 53 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 54 ld r12,PACAKBASE(r13); /* get high part of &label */ \ 55 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 56 LOAD_HANDLER(r12,label); \ 57 mtlr r12; \ 58 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 59 li r10,MSR_RI; \ 60 mtmsrd r10,1; /* Set RI (EE=0) */ \ 61 blr; 62 #else 63 /* If not relocatable, we can jump directly -- and save messing with LR */ 64 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 65 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 66 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 67 li r10,MSR_RI; \ 68 mtmsrd r10,1; /* Set RI (EE=0) */ \ 69 b label; 70 #endif 71 72 /* 73 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 74 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 75 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 76 */ 77 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 78 EXCEPTION_PROLOG_1(area, extra, vec); \ 79 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 80 81 /* 82 * We're short on space and time in the exception prolog, so we can't 83 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the 84 * low halfword of the address, but for Kdump we need the whole low 85 * word. 86 */ 87 #define LOAD_HANDLER(reg, label) \ 88 /* Handlers must be within 64K of kbase, which must be 64k aligned */ \ 89 ori reg,reg,(label)-_stext; /* virt addr of handler ... */ 90 91 /* Exception register prefixes */ 92 #define EXC_HV H 93 #define EXC_STD 94 95 #if defined(CONFIG_RELOCATABLE) 96 /* 97 * If we support interrupts with relocation on AND we're a relocatable 98 * kernel, we need to use LR to get to the 2nd level handler. So, save/restore 99 * it when required. 100 */ 101 #define SAVE_LR(reg, area) mflr reg ; std reg,area+EX_LR(r13) 102 #define GET_LR(reg, area) ld reg,area+EX_LR(r13) 103 #define RESTORE_LR(reg, area) ld reg,area+EX_LR(r13) ; mtlr reg 104 #else 105 /* ...else LR is unused and in register. */ 106 #define SAVE_LR(reg, area) 107 #define GET_LR(reg, area) mflr reg 108 #define RESTORE_LR(reg, area) 109 #endif 110 111 /* 112 * PPR save/restore macros used in exceptions_64s.S 113 * Used for P7 or later processors 114 */ 115 #define SAVE_PPR(area, ra, rb) \ 116 BEGIN_FTR_SECTION_NESTED(940) \ 117 ld ra,PACACURRENT(r13); \ 118 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 119 std rb,TASKTHREADPPR(ra); \ 120 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 121 122 #define RESTORE_PPR_PACA(area, ra) \ 123 BEGIN_FTR_SECTION_NESTED(941) \ 124 ld ra,area+EX_PPR(r13); \ 125 mtspr SPRN_PPR,ra; \ 126 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 127 128 /* 129 * Increase the priority on systems where PPR save/restore is not 130 * implemented/ supported. 131 */ 132 #define HMT_MEDIUM_PPR_DISCARD \ 133 BEGIN_FTR_SECTION_NESTED(942) \ 134 HMT_MEDIUM; \ 135 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,0,942) /*non P7*/ 136 137 /* 138 * Save PPR in paca whenever some register is available to use. 139 * Then increase the priority. 140 */ 141 #define HMT_MEDIUM_PPR_SAVE(area, ra) \ 142 BEGIN_FTR_SECTION_NESTED(943) \ 143 mfspr ra,SPRN_PPR; \ 144 std ra,area+EX_PPR(r13); \ 145 HMT_MEDIUM; \ 146 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,943) 147 148 #define __EXCEPTION_PROLOG_1(area, extra, vec) \ 149 GET_PACA(r13); \ 150 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 151 std r10,area+EX_R10(r13); \ 152 BEGIN_FTR_SECTION_NESTED(66); \ 153 mfspr r10,SPRN_CFAR; \ 154 std r10,area+EX_CFAR(r13); \ 155 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 156 SAVE_LR(r10, area); \ 157 mfcr r9; \ 158 extra(vec); \ 159 std r11,area+EX_R11(r13); \ 160 std r12,area+EX_R12(r13); \ 161 GET_SCRATCH0(r10); \ 162 std r10,area+EX_R13(r13) 163 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 164 __EXCEPTION_PROLOG_1(area, extra, vec) 165 166 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ 167 ld r12,PACAKBASE(r13); /* get high part of &label */ \ 168 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 169 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 170 LOAD_HANDLER(r12,label) \ 171 mtspr SPRN_##h##SRR0,r12; \ 172 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 173 mtspr SPRN_##h##SRR1,r10; \ 174 h##rfid; \ 175 b . /* prevent speculative execution */ 176 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ 177 __EXCEPTION_PROLOG_PSERIES_1(label, h) 178 179 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 180 EXCEPTION_PROLOG_1(area, extra, vec); \ 181 EXCEPTION_PROLOG_PSERIES_1(label, h); 182 183 #define __KVMTEST(n) \ 184 lbz r10,HSTATE_IN_GUEST(r13); \ 185 cmpwi r10,0; \ 186 bne do_kvm_##n 187 188 #define __KVM_HANDLER(area, h, n) \ 189 do_kvm_##n: \ 190 ld r10,area+EX_R10(r13); \ 191 stw r9,HSTATE_SCRATCH1(r13); \ 192 ld r9,area+EX_R9(r13); \ 193 std r12,HSTATE_SCRATCH0(r13); \ 194 li r12,n; \ 195 b kvmppc_interrupt 196 197 #define __KVM_HANDLER_SKIP(area, h, n) \ 198 do_kvm_##n: \ 199 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 200 ld r10,area+EX_R10(r13); \ 201 beq 89f; \ 202 stw r9,HSTATE_SCRATCH1(r13); \ 203 ld r9,area+EX_R9(r13); \ 204 std r12,HSTATE_SCRATCH0(r13); \ 205 li r12,n; \ 206 b kvmppc_interrupt; \ 207 89: mtocrf 0x80,r9; \ 208 ld r9,area+EX_R9(r13); \ 209 b kvmppc_skip_##h##interrupt 210 211 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 212 #define KVMTEST(n) __KVMTEST(n) 213 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 214 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 215 216 #else 217 #define KVMTEST(n) 218 #define KVM_HANDLER(area, h, n) 219 #define KVM_HANDLER_SKIP(area, h, n) 220 #endif 221 222 #ifdef CONFIG_KVM_BOOK3S_PR 223 #define KVMTEST_PR(n) __KVMTEST(n) 224 #define KVM_HANDLER_PR(area, h, n) __KVM_HANDLER(area, h, n) 225 #define KVM_HANDLER_PR_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 226 227 #else 228 #define KVMTEST_PR(n) 229 #define KVM_HANDLER_PR(area, h, n) 230 #define KVM_HANDLER_PR_SKIP(area, h, n) 231 #endif 232 233 #define NOTEST(n) 234 235 /* 236 * The common exception prolog is used for all except a few exceptions 237 * such as a segment miss on a kernel address. We have to be prepared 238 * to take another exception from the point where we first touch the 239 * kernel stack onwards. 240 * 241 * On entry r13 points to the paca, r9-r13 are saved in the paca, 242 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 243 * SRR1, and relocation is on. 244 */ 245 #define EXCEPTION_PROLOG_COMMON(n, area) \ 246 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 247 mr r10,r1; /* Save r1 */ \ 248 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 249 beq- 1f; \ 250 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 251 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 252 blt+ cr1,3f; /* abort if it is */ \ 253 li r1,(n); /* will be reloaded later */ \ 254 sth r1,PACA_TRAP_SAVE(r13); \ 255 std r3,area+EX_R3(r13); \ 256 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 257 RESTORE_LR(r1, area); \ 258 b bad_stack; \ 259 3: std r9,_CCR(r1); /* save CR in stackframe */ \ 260 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 261 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 262 std r10,0(r1); /* make stack chain pointer */ \ 263 std r0,GPR0(r1); /* save r0 in stackframe */ \ 264 std r10,GPR1(r1); /* save r1 in stackframe */ \ 265 beq 4f; /* if from kernel mode */ \ 266 ACCOUNT_CPU_USER_ENTRY(r9, r10); \ 267 4: std r2,GPR2(r1); /* save r2 in stackframe */ \ 268 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 269 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 270 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 271 ld r10,area+EX_R10(r13); \ 272 std r9,GPR9(r1); \ 273 std r10,GPR10(r1); \ 274 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 275 ld r10,area+EX_R12(r13); \ 276 ld r11,area+EX_R13(r13); \ 277 std r9,GPR11(r1); \ 278 std r10,GPR12(r1); \ 279 std r11,GPR13(r1); \ 280 BEGIN_FTR_SECTION_NESTED(66); \ 281 ld r10,area+EX_CFAR(r13); \ 282 std r10,ORIG_GPR3(r1); \ 283 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 284 GET_LR(r9,area); /* Get LR, later save to stack */ \ 285 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 286 std r9,_LINK(r1); \ 287 mfctr r10; /* save CTR in stackframe */ \ 288 std r10,_CTR(r1); \ 289 lbz r10,PACASOFTIRQEN(r13); \ 290 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 291 std r10,SOFTE(r1); \ 292 std r11,_XER(r1); \ 293 li r9,(n)+1; \ 294 std r9,_TRAP(r1); /* set trap number */ \ 295 li r10,0; \ 296 ld r11,exception_marker@toc(r2); \ 297 std r10,RESULT(r1); /* clear regs->result */ \ 298 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 299 ACCOUNT_STOLEN_TIME 300 301 /* 302 * Exception vectors. 303 */ 304 #define STD_EXCEPTION_PSERIES(loc, vec, label) \ 305 . = loc; \ 306 .globl label##_pSeries; \ 307 label##_pSeries: \ 308 HMT_MEDIUM; \ 309 SET_SCRATCH0(r13); /* save r13 */ \ 310 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 311 EXC_STD, KVMTEST_PR, vec) 312 313 #define STD_EXCEPTION_HV(loc, vec, label) \ 314 . = loc; \ 315 .globl label##_hv; \ 316 label##_hv: \ 317 HMT_MEDIUM; \ 318 SET_SCRATCH0(r13); /* save r13 */ \ 319 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 320 EXC_HV, KVMTEST, vec) 321 322 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 323 . = loc; \ 324 .globl label##_relon_pSeries; \ 325 label##_relon_pSeries: \ 326 HMT_MEDIUM; \ 327 /* No guest interrupts come through here */ \ 328 SET_SCRATCH0(r13); /* save r13 */ \ 329 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 330 EXC_STD, KVMTEST_PR, vec) 331 332 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 333 . = loc; \ 334 .globl label##_relon_hv; \ 335 label##_relon_hv: \ 336 HMT_MEDIUM; \ 337 /* No guest interrupts come through here */ \ 338 SET_SCRATCH0(r13); /* save r13 */ \ 339 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 340 EXC_HV, KVMTEST, vec) 341 342 /* This associate vector numbers with bits in paca->irq_happened */ 343 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 344 #define SOFTEN_VALUE_0x502 PACA_IRQ_EE 345 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 346 #define SOFTEN_VALUE_0x982 PACA_IRQ_DEC 347 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 348 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 349 #define SOFTEN_VALUE_0xe82 PACA_IRQ_DBELL 350 351 #define __SOFTEN_TEST(h, vec) \ 352 lbz r10,PACASOFTIRQEN(r13); \ 353 cmpwi r10,0; \ 354 li r10,SOFTEN_VALUE_##vec; \ 355 beq masked_##h##interrupt 356 #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec) 357 358 #define SOFTEN_TEST_PR(vec) \ 359 KVMTEST_PR(vec); \ 360 _SOFTEN_TEST(EXC_STD, vec) 361 362 #define SOFTEN_TEST_HV(vec) \ 363 KVMTEST(vec); \ 364 _SOFTEN_TEST(EXC_HV, vec) 365 366 #define SOFTEN_TEST_HV_201(vec) \ 367 KVMTEST(vec); \ 368 _SOFTEN_TEST(EXC_STD, vec) 369 370 #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec) 371 #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) 372 373 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 374 HMT_MEDIUM; \ 375 SET_SCRATCH0(r13); /* save r13 */ \ 376 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 377 EXCEPTION_PROLOG_PSERIES_1(label##_common, h); 378 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 379 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) 380 381 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \ 382 . = loc; \ 383 .globl label##_pSeries; \ 384 label##_pSeries: \ 385 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 386 EXC_STD, SOFTEN_TEST_PR) 387 388 #define MASKABLE_EXCEPTION_HV(loc, vec, label) \ 389 . = loc; \ 390 .globl label##_hv; \ 391 label##_hv: \ 392 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 393 EXC_HV, SOFTEN_TEST_HV) 394 395 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 396 HMT_MEDIUM; \ 397 SET_SCRATCH0(r13); /* save r13 */ \ 398 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 399 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, h); 400 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 401 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) 402 403 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 404 . = loc; \ 405 .globl label##_relon_pSeries; \ 406 label##_relon_pSeries: \ 407 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 408 EXC_STD, SOFTEN_NOTEST_PR) 409 410 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \ 411 . = loc; \ 412 .globl label##_relon_hv; \ 413 label##_relon_hv: \ 414 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 415 EXC_HV, SOFTEN_NOTEST_HV) 416 417 /* 418 * Our exception common code can be passed various "additions" 419 * to specify the behaviour of interrupts, whether to kick the 420 * runlatch, etc... 421 */ 422 423 /* Exception addition: Hard disable interrupts */ 424 #define DISABLE_INTS SOFT_DISABLE_INTS(r10,r11) 425 426 #define ADD_NVGPRS \ 427 bl .save_nvgprs 428 429 #define RUNLATCH_ON \ 430 BEGIN_FTR_SECTION \ 431 CURRENT_THREAD_INFO(r3, r1); \ 432 ld r4,TI_LOCAL_FLAGS(r3); \ 433 andi. r0,r4,_TLF_RUNLATCH; \ 434 beql ppc64_runlatch_on_trampoline; \ 435 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 436 437 #define EXCEPTION_COMMON(trap, label, hdlr, ret, additions) \ 438 .align 7; \ 439 .globl label##_common; \ 440 label##_common: \ 441 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 442 additions; \ 443 addi r3,r1,STACK_FRAME_OVERHEAD; \ 444 bl hdlr; \ 445 b ret 446 447 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 448 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except, \ 449 ADD_NVGPRS;DISABLE_INTS) 450 451 /* 452 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 453 * in the idle task and therefore need the special idle handling 454 * (finish nap and runlatch) 455 */ 456 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 457 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \ 458 FINISH_NAP;RUNLATCH_ON;DISABLE_INTS) 459 460 /* 461 * When the idle code in power4_idle puts the CPU into NAP mode, 462 * it has to do so in a loop, and relies on the external interrupt 463 * and decrementer interrupt entry code to get it out of the loop. 464 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 465 * to signal that it is in the loop and needs help to get out. 466 */ 467 #ifdef CONFIG_PPC_970_NAP 468 #define FINISH_NAP \ 469 BEGIN_FTR_SECTION \ 470 CURRENT_THREAD_INFO(r11, r1); \ 471 ld r9,TI_LOCAL_FLAGS(r11); \ 472 andi. r10,r9,_TLF_NAPPING; \ 473 bnel power4_fixup_nap; \ 474 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 475 #else 476 #define FINISH_NAP 477 #endif 478 479 #endif /* _ASM_POWERPC_EXCEPTION_H */ 480