1 /* 2 * linux/arch/mips/txx9/pci.c 3 * 4 * Based on linux/arch/mips/txx9/rbtx4927/setup.c, 5 * linux/arch/mips/txx9/rbtx4938/setup.c, 6 * and RBTX49xx patch from CELF patch archive. 7 * 8 * Copyright 2001-2005 MontaVista Software Inc. 9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) 10 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file "COPYING" in the main directory of this archive 14 * for more details. 15 */ 16 #include <linux/delay.h> 17 #include <linux/jiffies.h> 18 #include <linux/io.h> 19 #include <asm/txx9/generic.h> 20 #include <asm/txx9/pci.h> 21 #ifdef CONFIG_TOSHIBA_FPCIB0 22 #include <linux/interrupt.h> 23 #include <asm/i8259.h> 24 #include <asm/txx9/smsc_fdc37m81x.h> 25 #endif 26 27 static int __init 28 early_read_config_word(struct pci_controller *hose, 29 int top_bus, int bus, int devfn, int offset, u16 *value) 30 { 31 struct pci_dev fake_dev; 32 struct pci_bus fake_bus; 33 34 fake_dev.bus = &fake_bus; 35 fake_dev.sysdata = hose; 36 fake_dev.devfn = devfn; 37 fake_bus.number = bus; 38 fake_bus.sysdata = hose; 39 fake_bus.ops = hose->pci_ops; 40 41 if (bus != top_bus) 42 /* Fake a parent bus structure. */ 43 fake_bus.parent = &fake_bus; 44 else 45 fake_bus.parent = NULL; 46 47 return pci_read_config_word(&fake_dev, offset, value); 48 } 49 50 int __init txx9_pci66_check(struct pci_controller *hose, int top_bus, 51 int current_bus) 52 { 53 u32 pci_devfn; 54 unsigned short vid; 55 int cap66 = -1; 56 u16 stat; 57 58 /* It seems SLC90E66 needs some time after PCI reset... */ 59 mdelay(80); 60 61 printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); 62 63 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 64 if (PCI_FUNC(pci_devfn)) 65 continue; 66 if (early_read_config_word(hose, top_bus, current_bus, 67 pci_devfn, PCI_VENDOR_ID, &vid) != 68 PCIBIOS_SUCCESSFUL) 69 continue; 70 if (vid == 0xffff) 71 continue; 72 73 /* check 66MHz capability */ 74 if (cap66 < 0) 75 cap66 = 1; 76 if (cap66) { 77 early_read_config_word(hose, top_bus, current_bus, 78 pci_devfn, PCI_STATUS, &stat); 79 if (!(stat & PCI_STATUS_66MHZ)) { 80 printk(KERN_DEBUG 81 "PCI: %02x:%02x not 66MHz capable.\n", 82 current_bus, pci_devfn); 83 cap66 = 0; 84 break; 85 } 86 } 87 } 88 return cap66 > 0; 89 } 90 91 static struct resource primary_pci_mem_res[2] = { 92 { .name = "PCI MEM" }, 93 { .name = "PCI MMIO" }, 94 }; 95 static struct resource primary_pci_io_res = { .name = "PCI IO" }; 96 struct pci_controller txx9_primary_pcic = { 97 .mem_resource = &primary_pci_mem_res[0], 98 .io_resource = &primary_pci_io_res, 99 }; 100 101 #ifdef CONFIG_64BIT 102 int txx9_pci_mem_high __initdata = 1; 103 #else 104 int txx9_pci_mem_high __initdata; 105 #endif 106 107 /* 108 * allocate pci_controller and resources. 109 * mem_base, io_base: physical addresss. 0 for auto assignment. 110 * mem_size and io_size means max size on auto assignment. 111 * pcic must be &txx9_primary_pcic or NULL. 112 */ 113 struct pci_controller *__init 114 txx9_alloc_pci_controller(struct pci_controller *pcic, 115 unsigned long mem_base, unsigned long mem_size, 116 unsigned long io_base, unsigned long io_size) 117 { 118 struct pcic { 119 struct pci_controller c; 120 struct resource r_mem[2]; 121 struct resource r_io; 122 } *new = NULL; 123 int min_size = 0x10000; 124 125 if (!pcic) { 126 new = kzalloc(sizeof(*new), GFP_KERNEL); 127 if (!new) 128 return NULL; 129 new->r_mem[0].name = "PCI mem"; 130 new->r_mem[1].name = "PCI mmio"; 131 new->r_io.name = "PCI io"; 132 new->c.mem_resource = new->r_mem; 133 new->c.io_resource = &new->r_io; 134 pcic = &new->c; 135 } else 136 BUG_ON(pcic != &txx9_primary_pcic); 137 pcic->io_resource->flags = IORESOURCE_IO; 138 139 /* 140 * for auto assignment, first search a (big) region for PCI 141 * MEM, then search a region for PCI IO. 142 */ 143 if (mem_base) { 144 pcic->mem_resource[0].start = mem_base; 145 pcic->mem_resource[0].end = mem_base + mem_size - 1; 146 if (request_resource(&iomem_resource, &pcic->mem_resource[0])) 147 goto free_and_exit; 148 } else { 149 unsigned long min = 0, max = 0x20000000; /* low 512MB */ 150 if (!mem_size) { 151 /* default size for auto assignment */ 152 if (txx9_pci_mem_high) 153 mem_size = 0x20000000; /* mem:512M(max) */ 154 else 155 mem_size = 0x08000000; /* mem:128M(max) */ 156 } 157 if (txx9_pci_mem_high) { 158 min = 0x20000000; 159 max = 0xe0000000; 160 } 161 /* search free region for PCI MEM */ 162 for (; mem_size >= min_size; mem_size /= 2) { 163 if (allocate_resource(&iomem_resource, 164 &pcic->mem_resource[0], 165 mem_size, min, max, 166 mem_size, NULL, NULL) == 0) 167 break; 168 } 169 if (mem_size < min_size) 170 goto free_and_exit; 171 } 172 173 pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY; 174 if (io_base) { 175 pcic->mem_resource[1].start = io_base; 176 pcic->mem_resource[1].end = io_base + io_size - 1; 177 if (request_resource(&iomem_resource, &pcic->mem_resource[1])) 178 goto release_and_exit; 179 } else { 180 if (!io_size) 181 /* default size for auto assignment */ 182 io_size = 0x01000000; /* io:16M(max) */ 183 /* search free region for PCI IO in low 512MB */ 184 for (; io_size >= min_size; io_size /= 2) { 185 if (allocate_resource(&iomem_resource, 186 &pcic->mem_resource[1], 187 io_size, 0, 0x20000000, 188 io_size, NULL, NULL) == 0) 189 break; 190 } 191 if (io_size < min_size) 192 goto release_and_exit; 193 io_base = pcic->mem_resource[1].start; 194 } 195 196 pcic->mem_resource[0].flags = IORESOURCE_MEM; 197 if (pcic == &txx9_primary_pcic && 198 mips_io_port_base == (unsigned long)-1) { 199 /* map ioport 0 to PCI I/O space address 0 */ 200 set_io_port_base(IO_BASE + pcic->mem_resource[1].start); 201 pcic->io_resource->start = 0; 202 pcic->io_offset = 0; /* busaddr == ioaddr */ 203 pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start; 204 } else { 205 /* physaddr to ioaddr */ 206 pcic->io_resource->start = 207 io_base - (mips_io_port_base - IO_BASE); 208 pcic->io_offset = io_base - (mips_io_port_base - IO_BASE); 209 pcic->io_map_base = mips_io_port_base; 210 } 211 pcic->io_resource->end = pcic->io_resource->start + io_size - 1; 212 213 pcic->mem_offset = 0; /* busaddr == physaddr */ 214 215 printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n", 216 (unsigned long long)pcic->mem_resource[1].start, 217 (unsigned long long)pcic->mem_resource[1].end, 218 (unsigned long long)pcic->mem_resource[0].start, 219 (unsigned long long)pcic->mem_resource[0].end); 220 221 /* register_pci_controller() will request MEM resource */ 222 release_resource(&pcic->mem_resource[0]); 223 return pcic; 224 release_and_exit: 225 release_resource(&pcic->mem_resource[0]); 226 free_and_exit: 227 kfree(new); 228 printk(KERN_ERR "PCI: Failed to allocate resources.\n"); 229 return NULL; 230 } 231 232 static int __init 233 txx9_arch_pci_init(void) 234 { 235 PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */ 236 return 0; 237 } 238 arch_initcall(txx9_arch_pci_init); 239 240 /* IRQ/IDSEL mapping */ 241 int txx9_pci_option = 242 #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT 243 TXX9_PCI_OPT_PICMG | 244 #endif 245 TXX9_PCI_OPT_CLK_AUTO; 246 247 enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT; 248 249 #ifdef CONFIG_TOSHIBA_FPCIB0 250 static irqreturn_t i8259_interrupt(int irq, void *dev_id) 251 { 252 int isairq; 253 254 isairq = i8259_irq(); 255 if (unlikely(isairq <= I8259A_IRQ_BASE)) 256 return IRQ_NONE; 257 generic_handle_irq(isairq); 258 return IRQ_HANDLED; 259 } 260 261 static int __init 262 txx9_i8259_irq_setup(int irq) 263 { 264 int err; 265 266 init_i8259_irqs(); 267 err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED, 268 "cascade(i8259)", (void *)(long)irq); 269 if (!err) 270 printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); 271 return err; 272 } 273 274 static void __init quirk_slc90e66_bridge(struct pci_dev *dev) 275 { 276 int irq; /* PCI/ISA Bridge interrupt */ 277 u8 reg_64; 278 u32 reg_b0; 279 u8 reg_e1; 280 irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */ 281 if (!irq) 282 return; 283 txx9_i8259_irq_setup(irq); 284 pci_read_config_byte(dev, 0x64, ®_64); 285 pci_read_config_dword(dev, 0xb0, ®_b0); 286 pci_read_config_byte(dev, 0xe1, ®_e1); 287 /* serial irq control */ 288 reg_64 = 0xd0; 289 /* serial irq pin */ 290 reg_b0 |= 0x00010000; 291 /* ide irq on isa14 */ 292 reg_e1 &= 0xf0; 293 reg_e1 |= 0x0d; 294 pci_write_config_byte(dev, 0x64, reg_64); 295 pci_write_config_dword(dev, 0xb0, reg_b0); 296 pci_write_config_byte(dev, 0xe1, reg_e1); 297 298 smsc_fdc37m81x_init(0x3f0); 299 smsc_fdc37m81x_config_beg(); 300 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, 301 SMSC_FDC37M81X_KBD); 302 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); 303 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); 304 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, 305 1); 306 smsc_fdc37m81x_config_end(); 307 } 308 309 static void quirk_slc90e66_ide(struct pci_dev *dev) 310 { 311 unsigned char dat; 312 int regs[2] = {0x41, 0x43}; 313 int i; 314 315 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ 316 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14); 317 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat); 318 printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat); 319 /* enable SMSC SLC90E66 IDE */ 320 for (i = 0; i < ARRAY_SIZE(regs); i++) { 321 pci_read_config_byte(dev, regs[i], &dat); 322 pci_write_config_byte(dev, regs[i], dat | 0x80); 323 pci_read_config_byte(dev, regs[i], &dat); 324 printk(KERN_CONT " IDETIM%d %02x", i, dat); 325 } 326 pci_read_config_byte(dev, 0x5c, &dat); 327 /* 328 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! 329 * 330 * This line of code is intended to provide the user with a work 331 * around solution to the anomalies cited in SMSC's anomaly sheet 332 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". 333 * 334 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! 335 */ 336 dat |= 0x01; 337 pci_write_config_byte(dev, regs[i], dat); 338 pci_read_config_byte(dev, 0x5c, &dat); 339 printk(KERN_CONT " REG5C %02x", dat); 340 printk(KERN_CONT "\n"); 341 } 342 #endif /* CONFIG_TOSHIBA_FPCIB0 */ 343 344 static void final_fixup(struct pci_dev *dev) 345 { 346 unsigned char bist; 347 348 /* Do build-in self test */ 349 if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL && 350 (bist & PCI_BIST_CAPABLE)) { 351 unsigned long timeout; 352 pci_set_power_state(dev, PCI_D0); 353 printk(KERN_INFO "PCI: %s BIST...", pci_name(dev)); 354 pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START); 355 timeout = jiffies + HZ * 2; /* timeout after 2 sec */ 356 do { 357 pci_read_config_byte(dev, PCI_BIST, &bist); 358 if (time_after(jiffies, timeout)) 359 break; 360 } while (bist & PCI_BIST_START); 361 if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START)) 362 printk(KERN_CONT "failed. (0x%x)\n", bist); 363 else 364 printk(KERN_CONT "OK.\n"); 365 } 366 } 367 368 #ifdef CONFIG_TOSHIBA_FPCIB0 369 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, 371 quirk_slc90e66_bridge); 372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, 373 quirk_slc90e66_ide); 374 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, 375 quirk_slc90e66_ide); 376 #endif 377 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup); 378 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup); 379 380 int pcibios_plat_dev_init(struct pci_dev *dev) 381 { 382 return 0; 383 } 384 385 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 386 { 387 return txx9_board_vec->pci_map_irq(dev, slot, pin); 388 } 389