xref: /openbmc/linux/arch/mips/txx9/generic/pci.c (revision e7513ecc)
1 /*
2  * linux/arch/mips/txx9/pci.c
3  *
4  * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
5  *	    linux/arch/mips/txx9/rbtx4938/setup.c,
6  *	    and RBTX49xx patch from CELF patch archive.
7  *
8  * Copyright 2001-2005 MontaVista Software Inc.
9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
10  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file "COPYING" in the main directory of this archive
14  * for more details.
15  */
16 #include <linux/delay.h>
17 #include <linux/jiffies.h>
18 #include <linux/io.h>
19 #include <asm/txx9/generic.h>
20 #include <asm/txx9/pci.h>
21 #ifdef CONFIG_TOSHIBA_FPCIB0
22 #include <linux/interrupt.h>
23 #include <linux/slab.h>
24 #include <asm/i8259.h>
25 #include <asm/txx9/smsc_fdc37m81x.h>
26 #endif
27 
28 static int __init
early_read_config_word(struct pci_controller * hose,int top_bus,int bus,int devfn,int offset,u16 * value)29 early_read_config_word(struct pci_controller *hose,
30 		       int top_bus, int bus, int devfn, int offset, u16 *value)
31 {
32 	struct pci_bus fake_bus;
33 
34 	fake_bus.number = bus;
35 	fake_bus.sysdata = hose;
36 	fake_bus.ops = hose->pci_ops;
37 
38 	if (bus != top_bus)
39 		/* Fake a parent bus structure. */
40 		fake_bus.parent = &fake_bus;
41 	else
42 		fake_bus.parent = NULL;
43 
44 	return pci_bus_read_config_word(&fake_bus, devfn, offset, value);
45 }
46 
txx9_pci66_check(struct pci_controller * hose,int top_bus,int current_bus)47 int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
48 			    int current_bus)
49 {
50 	u32 pci_devfn;
51 	unsigned short vid;
52 	int cap66 = -1;
53 	u16 stat;
54 	int ret;
55 
56 	/* It seems SLC90E66 needs some time after PCI reset... */
57 	mdelay(80);
58 
59 	pr_info("PCI: Checking 66MHz capabilities...\n");
60 
61 	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
62 		if (PCI_FUNC(pci_devfn))
63 			continue;
64 		ret = early_read_config_word(hose, top_bus, current_bus,
65 					     pci_devfn, PCI_VENDOR_ID, &vid);
66 		if (ret != PCIBIOS_SUCCESSFUL)
67 			continue;
68 		if (vid == 0xffff)
69 			continue;
70 
71 		/* check 66MHz capability */
72 		if (cap66 < 0)
73 			cap66 = 1;
74 		if (cap66) {
75 			early_read_config_word(hose, top_bus, current_bus,
76 					       pci_devfn, PCI_STATUS, &stat);
77 			if (!(stat & PCI_STATUS_66MHZ)) {
78 				pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
79 					 current_bus, pci_devfn);
80 				cap66 = 0;
81 				break;
82 			}
83 		}
84 	}
85 	return cap66 > 0;
86 }
87 
88 static struct resource primary_pci_mem_res[2] = {
89 	{ .name = "PCI MEM" },
90 	{ .name = "PCI MMIO" },
91 };
92 static struct resource primary_pci_io_res = { .name = "PCI IO" };
93 struct pci_controller txx9_primary_pcic = {
94 	.mem_resource = &primary_pci_mem_res[0],
95 	.io_resource = &primary_pci_io_res,
96 };
97 
98 #ifdef CONFIG_64BIT
99 int txx9_pci_mem_high __initdata = 1;
100 #else
101 int txx9_pci_mem_high __initdata;
102 #endif
103 
104 /*
105  * allocate pci_controller and resources.
106  * mem_base, io_base: physical address.	 0 for auto assignment.
107  * mem_size and io_size means max size on auto assignment.
108  * pcic must be &txx9_primary_pcic or NULL.
109  */
110 struct pci_controller *__init
txx9_alloc_pci_controller(struct pci_controller * pcic,unsigned long mem_base,unsigned long mem_size,unsigned long io_base,unsigned long io_size)111 txx9_alloc_pci_controller(struct pci_controller *pcic,
112 			  unsigned long mem_base, unsigned long mem_size,
113 			  unsigned long io_base, unsigned long io_size)
114 {
115 	struct pcic {
116 		struct pci_controller c;
117 		struct resource r_mem[2];
118 		struct resource r_io;
119 	} *new = NULL;
120 	int min_size = 0x10000;
121 
122 	if (!pcic) {
123 		new = kzalloc(sizeof(*new), GFP_KERNEL);
124 		if (!new)
125 			return NULL;
126 		new->r_mem[0].name = "PCI mem";
127 		new->r_mem[1].name = "PCI mmio";
128 		new->r_io.name = "PCI io";
129 		new->c.mem_resource = new->r_mem;
130 		new->c.io_resource = &new->r_io;
131 		pcic = &new->c;
132 	} else
133 		BUG_ON(pcic != &txx9_primary_pcic);
134 	pcic->io_resource->flags = IORESOURCE_IO;
135 
136 	/*
137 	 * for auto assignment, first search a (big) region for PCI
138 	 * MEM, then search a region for PCI IO.
139 	 */
140 	if (mem_base) {
141 		pcic->mem_resource[0].start = mem_base;
142 		pcic->mem_resource[0].end = mem_base + mem_size - 1;
143 		if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
144 			goto free_and_exit;
145 	} else {
146 		unsigned long min = 0, max = 0x20000000; /* low 512MB */
147 		if (!mem_size) {
148 			/* default size for auto assignment */
149 			if (txx9_pci_mem_high)
150 				mem_size = 0x20000000;	/* mem:512M(max) */
151 			else
152 				mem_size = 0x08000000;	/* mem:128M(max) */
153 		}
154 		if (txx9_pci_mem_high) {
155 			min = 0x20000000;
156 			max = 0xe0000000;
157 		}
158 		/* search free region for PCI MEM */
159 		for (; mem_size >= min_size; mem_size /= 2) {
160 			if (allocate_resource(&iomem_resource,
161 					      &pcic->mem_resource[0],
162 					      mem_size, min, max,
163 					      mem_size, NULL, NULL) == 0)
164 				break;
165 		}
166 		if (mem_size < min_size)
167 			goto free_and_exit;
168 	}
169 
170 	pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
171 	if (io_base) {
172 		pcic->mem_resource[1].start = io_base;
173 		pcic->mem_resource[1].end = io_base + io_size - 1;
174 		if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
175 			goto release_and_exit;
176 	} else {
177 		if (!io_size)
178 			/* default size for auto assignment */
179 			io_size = 0x01000000;	/* io:16M(max) */
180 		/* search free region for PCI IO in low 512MB */
181 		for (; io_size >= min_size; io_size /= 2) {
182 			if (allocate_resource(&iomem_resource,
183 					      &pcic->mem_resource[1],
184 					      io_size, 0, 0x20000000,
185 					      io_size, NULL, NULL) == 0)
186 				break;
187 		}
188 		if (io_size < min_size)
189 			goto release_and_exit;
190 		io_base = pcic->mem_resource[1].start;
191 	}
192 
193 	pcic->mem_resource[0].flags = IORESOURCE_MEM;
194 	if (pcic == &txx9_primary_pcic &&
195 	    mips_io_port_base == (unsigned long)-1) {
196 		/* map ioport 0 to PCI I/O space address 0 */
197 		set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
198 		pcic->io_resource->start = 0;
199 		pcic->io_offset = 0;	/* busaddr == ioaddr */
200 		pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
201 	} else {
202 		/* physaddr to ioaddr */
203 		pcic->io_resource->start =
204 			io_base - (mips_io_port_base - IO_BASE);
205 		pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
206 		pcic->io_map_base = mips_io_port_base;
207 	}
208 	pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
209 
210 	pcic->mem_offset = 0;	/* busaddr == physaddr */
211 
212 	pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
213 		&pcic->mem_resource[0]);
214 
215 	/* register_pci_controller() will request MEM resource */
216 	release_resource(&pcic->mem_resource[0]);
217 	return pcic;
218  release_and_exit:
219 	release_resource(&pcic->mem_resource[0]);
220  free_and_exit:
221 	kfree(new);
222 	pr_err("PCI: Failed to allocate resources.\n");
223 	return NULL;
224 }
225 
226 static int __init
txx9_arch_pci_init(void)227 txx9_arch_pci_init(void)
228 {
229 	PCIBIOS_MIN_IO = 0x8000;	/* reserve legacy I/O space */
230 	return 0;
231 }
232 arch_initcall(txx9_arch_pci_init);
233 
234 /* IRQ/IDSEL mapping */
235 int txx9_pci_option =
236 #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
237 	TXX9_PCI_OPT_PICMG |
238 #endif
239 	TXX9_PCI_OPT_CLK_AUTO;
240 
241 enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
242 
243 #ifdef CONFIG_TOSHIBA_FPCIB0
i8259_interrupt(int irq,void * dev_id)244 static irqreturn_t i8259_interrupt(int irq, void *dev_id)
245 {
246 	int isairq;
247 
248 	isairq = i8259_irq();
249 	if (unlikely(isairq <= I8259A_IRQ_BASE))
250 		return IRQ_NONE;
251 	generic_handle_irq(isairq);
252 	return IRQ_HANDLED;
253 }
254 
txx9_i8259_irq_setup(int irq)255 static int txx9_i8259_irq_setup(int irq)
256 {
257 	int err;
258 
259 	init_i8259_irqs();
260 	err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
261 			  "cascade(i8259)", (void *)(long)irq);
262 	if (!err)
263 		pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
264 	return err;
265 }
266 
quirk_slc90e66_bridge(struct pci_dev * dev)267 static void __ref quirk_slc90e66_bridge(struct pci_dev *dev)
268 {
269 	int irq;	/* PCI/ISA Bridge interrupt */
270 	u8 reg_64;
271 	u32 reg_b0;
272 	u8 reg_e1;
273 	irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
274 	if (!irq)
275 		return;
276 	txx9_i8259_irq_setup(irq);
277 	pci_read_config_byte(dev, 0x64, &reg_64);
278 	pci_read_config_dword(dev, 0xb0, &reg_b0);
279 	pci_read_config_byte(dev, 0xe1, &reg_e1);
280 	/* serial irq control */
281 	reg_64 = 0xd0;
282 	/* serial irq pin */
283 	reg_b0 |= 0x00010000;
284 	/* ide irq on isa14 */
285 	reg_e1 &= 0xf0;
286 	reg_e1 |= 0x0d;
287 	pci_write_config_byte(dev, 0x64, reg_64);
288 	pci_write_config_dword(dev, 0xb0, reg_b0);
289 	pci_write_config_byte(dev, 0xe1, reg_e1);
290 
291 	smsc_fdc37m81x_init(0x3f0);
292 	smsc_fdc37m81x_config_beg();
293 	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
294 				  SMSC_FDC37M81X_KBD);
295 	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
296 	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
297 	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
298 				  1);
299 	smsc_fdc37m81x_config_end();
300 }
301 
quirk_slc90e66_ide(struct pci_dev * dev)302 static void quirk_slc90e66_ide(struct pci_dev *dev)
303 {
304 	unsigned char dat;
305 	int regs[2] = {0x41, 0x43};
306 	int i;
307 
308 	/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
309 	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
310 	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
311 	pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
312 	/* enable SMSC SLC90E66 IDE */
313 	for (i = 0; i < ARRAY_SIZE(regs); i++) {
314 		pci_read_config_byte(dev, regs[i], &dat);
315 		pci_write_config_byte(dev, regs[i], dat | 0x80);
316 		pci_read_config_byte(dev, regs[i], &dat);
317 		pr_cont(" IDETIM%d %02x", i, dat);
318 	}
319 	pci_read_config_byte(dev, 0x5c, &dat);
320 	/*
321 	 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
322 	 *
323 	 * This line of code is intended to provide the user with a work
324 	 * around solution to the anomalies cited in SMSC's anomaly sheet
325 	 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
326 	 *
327 	 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
328 	 */
329 	dat |= 0x01;
330 	pci_write_config_byte(dev, 0x5c, dat);
331 	pci_read_config_byte(dev, 0x5c, &dat);
332 	pr_cont(" REG5C %02x\n", dat);
333 }
334 #endif /* CONFIG_TOSHIBA_FPCIB0 */
335 
tc35815_fixup(struct pci_dev * dev)336 static void tc35815_fixup(struct pci_dev *dev)
337 {
338 	/* This device may have PM registers but not they are not supported. */
339 	if (dev->pm_cap) {
340 		dev_info(&dev->dev, "PM disabled\n");
341 		dev->pm_cap = 0;
342 	}
343 }
344 
final_fixup(struct pci_dev * dev)345 static void final_fixup(struct pci_dev *dev)
346 {
347 	unsigned long timeout;
348 	unsigned char bist;
349 	int ret;
350 
351 	/* Do build-in self test */
352 	ret = pci_read_config_byte(dev, PCI_BIST, &bist);
353 	if ((ret != PCIBIOS_SUCCESSFUL) || !(bist & PCI_BIST_CAPABLE))
354 		return;
355 
356 	pci_set_power_state(dev, PCI_D0);
357 	pr_info("PCI: %s BIST...", pci_name(dev));
358 	pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
359 	timeout = jiffies + HZ * 2;	/* timeout after 2 sec */
360 	do {
361 		pci_read_config_byte(dev, PCI_BIST, &bist);
362 		if (time_after(jiffies, timeout))
363 			break;
364 	} while (bist & PCI_BIST_START);
365 	if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
366 		pr_cont("failed. (0x%x)\n", bist);
367 	else
368 		pr_cont("OK.\n");
369 }
370 
371 #ifdef CONFIG_TOSHIBA_FPCIB0
372 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
374 	quirk_slc90e66_bridge);
375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
376 	quirk_slc90e66_ide);
377 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
378 	quirk_slc90e66_ide);
379 #endif
380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
381 			PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
383 			PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
384 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
385 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
386 
pcibios_plat_dev_init(struct pci_dev * dev)387 int pcibios_plat_dev_init(struct pci_dev *dev)
388 {
389 	return 0;
390 }
391 
392 static int (*txx9_pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)393 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
394 {
395 	return txx9_pci_map_irq(dev, slot, pin);
396 }
397 
398 char * (*txx9_board_pcibios_setup)(char *str) __initdata;
399 
txx9_pcibios_setup(char * str)400 char *__init txx9_pcibios_setup(char *str)
401 {
402 	if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
403 		return NULL;
404 	if (!strcmp(str, "picmg")) {
405 		/* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
406 		   (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
407 		txx9_pci_option |= TXX9_PCI_OPT_PICMG;
408 		return NULL;
409 	} else if (!strcmp(str, "nopicmg")) {
410 		/* non-PICMG compliant backplane (TOSHIBA
411 		   RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
412 		txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
413 		return NULL;
414 	} else if (!strncmp(str, "clk=", 4)) {
415 		char *val = str + 4;
416 		txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
417 		if (strcmp(val, "33") == 0)
418 			txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
419 		else if (strcmp(val, "66") == 0)
420 			txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
421 		else /* "auto" */
422 			txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
423 		return NULL;
424 	} else if (!strncmp(str, "err=", 4)) {
425 		if (!strcmp(str + 4, "panic"))
426 			txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
427 		else if (!strcmp(str + 4, "ignore"))
428 			txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
429 		return NULL;
430 	}
431 
432 	txx9_pci_map_irq = txx9_board_vec->pci_map_irq;
433 
434 	return str;
435 }
436