1 /* 2 * linux/arch/mips/txx9/pci.c 3 * 4 * Based on linux/arch/mips/txx9/rbtx4927/setup.c, 5 * linux/arch/mips/txx9/rbtx4938/setup.c, 6 * and RBTX49xx patch from CELF patch archive. 7 * 8 * Copyright 2001-2005 MontaVista Software Inc. 9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) 10 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file "COPYING" in the main directory of this archive 14 * for more details. 15 */ 16 #include <linux/delay.h> 17 #include <linux/jiffies.h> 18 #include <linux/io.h> 19 #include <asm/txx9/pci.h> 20 #ifdef CONFIG_TOSHIBA_FPCIB0 21 #include <linux/interrupt.h> 22 #include <asm/i8259.h> 23 #include <asm/txx9/smsc_fdc37m81x.h> 24 #endif 25 26 static int __init 27 early_read_config_word(struct pci_controller *hose, 28 int top_bus, int bus, int devfn, int offset, u16 *value) 29 { 30 struct pci_dev fake_dev; 31 struct pci_bus fake_bus; 32 33 fake_dev.bus = &fake_bus; 34 fake_dev.sysdata = hose; 35 fake_dev.devfn = devfn; 36 fake_bus.number = bus; 37 fake_bus.sysdata = hose; 38 fake_bus.ops = hose->pci_ops; 39 40 if (bus != top_bus) 41 /* Fake a parent bus structure. */ 42 fake_bus.parent = &fake_bus; 43 else 44 fake_bus.parent = NULL; 45 46 return pci_read_config_word(&fake_dev, offset, value); 47 } 48 49 int __init txx9_pci66_check(struct pci_controller *hose, int top_bus, 50 int current_bus) 51 { 52 u32 pci_devfn; 53 unsigned short vid; 54 int cap66 = -1; 55 u16 stat; 56 57 /* It seems SLC90E66 needs some time after PCI reset... */ 58 mdelay(80); 59 60 printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); 61 62 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 63 if (PCI_FUNC(pci_devfn)) 64 continue; 65 if (early_read_config_word(hose, top_bus, current_bus, 66 pci_devfn, PCI_VENDOR_ID, &vid) != 67 PCIBIOS_SUCCESSFUL) 68 continue; 69 if (vid == 0xffff) 70 continue; 71 72 /* check 66MHz capability */ 73 if (cap66 < 0) 74 cap66 = 1; 75 if (cap66) { 76 early_read_config_word(hose, top_bus, current_bus, 77 pci_devfn, PCI_STATUS, &stat); 78 if (!(stat & PCI_STATUS_66MHZ)) { 79 printk(KERN_DEBUG 80 "PCI: %02x:%02x not 66MHz capable.\n", 81 current_bus, pci_devfn); 82 cap66 = 0; 83 break; 84 } 85 } 86 } 87 return cap66 > 0; 88 } 89 90 static struct resource primary_pci_mem_res[2] = { 91 { .name = "PCI MEM" }, 92 { .name = "PCI MMIO" }, 93 }; 94 static struct resource primary_pci_io_res = { .name = "PCI IO" }; 95 struct pci_controller txx9_primary_pcic = { 96 .mem_resource = &primary_pci_mem_res[0], 97 .io_resource = &primary_pci_io_res, 98 }; 99 100 #ifdef CONFIG_64BIT 101 int txx9_pci_mem_high __initdata = 1; 102 #else 103 int txx9_pci_mem_high __initdata; 104 #endif 105 106 /* 107 * allocate pci_controller and resources. 108 * mem_base, io_base: physical addresss. 0 for auto assignment. 109 * mem_size and io_size means max size on auto assignment. 110 * pcic must be &txx9_primary_pcic or NULL. 111 */ 112 struct pci_controller *__init 113 txx9_alloc_pci_controller(struct pci_controller *pcic, 114 unsigned long mem_base, unsigned long mem_size, 115 unsigned long io_base, unsigned long io_size) 116 { 117 struct pcic { 118 struct pci_controller c; 119 struct resource r_mem[2]; 120 struct resource r_io; 121 } *new = NULL; 122 int min_size = 0x10000; 123 124 if (!pcic) { 125 new = kzalloc(sizeof(*new), GFP_KERNEL); 126 if (!new) 127 return NULL; 128 new->r_mem[0].name = "PCI mem"; 129 new->r_mem[1].name = "PCI mmio"; 130 new->r_io.name = "PCI io"; 131 new->c.mem_resource = new->r_mem; 132 new->c.io_resource = &new->r_io; 133 pcic = &new->c; 134 } else 135 BUG_ON(pcic != &txx9_primary_pcic); 136 pcic->io_resource->flags = IORESOURCE_IO; 137 138 /* 139 * for auto assignment, first search a (big) region for PCI 140 * MEM, then search a region for PCI IO. 141 */ 142 if (mem_base) { 143 pcic->mem_resource[0].start = mem_base; 144 pcic->mem_resource[0].end = mem_base + mem_size - 1; 145 if (request_resource(&iomem_resource, &pcic->mem_resource[0])) 146 goto free_and_exit; 147 } else { 148 unsigned long min = 0, max = 0x20000000; /* low 512MB */ 149 if (!mem_size) { 150 /* default size for auto assignment */ 151 if (txx9_pci_mem_high) 152 mem_size = 0x20000000; /* mem:512M(max) */ 153 else 154 mem_size = 0x08000000; /* mem:128M(max) */ 155 } 156 if (txx9_pci_mem_high) { 157 min = 0x20000000; 158 max = 0xe0000000; 159 } 160 /* search free region for PCI MEM */ 161 for (; mem_size >= min_size; mem_size /= 2) { 162 if (allocate_resource(&iomem_resource, 163 &pcic->mem_resource[0], 164 mem_size, min, max, 165 mem_size, NULL, NULL) == 0) 166 break; 167 } 168 if (mem_size < min_size) 169 goto free_and_exit; 170 } 171 172 pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY; 173 if (io_base) { 174 pcic->mem_resource[1].start = io_base; 175 pcic->mem_resource[1].end = io_base + io_size - 1; 176 if (request_resource(&iomem_resource, &pcic->mem_resource[1])) 177 goto release_and_exit; 178 } else { 179 if (!io_size) 180 /* default size for auto assignment */ 181 io_size = 0x01000000; /* io:16M(max) */ 182 /* search free region for PCI IO in low 512MB */ 183 for (; io_size >= min_size; io_size /= 2) { 184 if (allocate_resource(&iomem_resource, 185 &pcic->mem_resource[1], 186 io_size, 0, 0x20000000, 187 io_size, NULL, NULL) == 0) 188 break; 189 } 190 if (io_size < min_size) 191 goto release_and_exit; 192 io_base = pcic->mem_resource[1].start; 193 } 194 195 pcic->mem_resource[0].flags = IORESOURCE_MEM; 196 if (pcic == &txx9_primary_pcic && 197 mips_io_port_base == (unsigned long)-1) { 198 /* map ioport 0 to PCI I/O space address 0 */ 199 set_io_port_base(IO_BASE + pcic->mem_resource[1].start); 200 pcic->io_resource->start = 0; 201 pcic->io_offset = 0; /* busaddr == ioaddr */ 202 pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start; 203 } else { 204 /* physaddr to ioaddr */ 205 pcic->io_resource->start = 206 io_base - (mips_io_port_base - IO_BASE); 207 pcic->io_offset = io_base - (mips_io_port_base - IO_BASE); 208 pcic->io_map_base = mips_io_port_base; 209 } 210 pcic->io_resource->end = pcic->io_resource->start + io_size - 1; 211 212 pcic->mem_offset = 0; /* busaddr == physaddr */ 213 214 printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n", 215 (unsigned long long)pcic->mem_resource[1].start, 216 (unsigned long long)pcic->mem_resource[1].end, 217 (unsigned long long)pcic->mem_resource[0].start, 218 (unsigned long long)pcic->mem_resource[0].end); 219 220 /* register_pci_controller() will request MEM resource */ 221 release_resource(&pcic->mem_resource[0]); 222 return pcic; 223 release_and_exit: 224 release_resource(&pcic->mem_resource[0]); 225 free_and_exit: 226 kfree(new); 227 printk(KERN_ERR "PCI: Failed to allocate resources.\n"); 228 return NULL; 229 } 230 231 static int __init 232 txx9_arch_pci_init(void) 233 { 234 PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */ 235 return 0; 236 } 237 arch_initcall(txx9_arch_pci_init); 238 239 /* IRQ/IDSEL mapping */ 240 int txx9_pci_option = 241 #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT 242 TXX9_PCI_OPT_PICMG | 243 #endif 244 TXX9_PCI_OPT_CLK_AUTO; 245 246 enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT; 247 248 #ifdef CONFIG_TOSHIBA_FPCIB0 249 static irqreturn_t i8259_interrupt(int irq, void *dev_id) 250 { 251 int isairq; 252 253 isairq = i8259_irq(); 254 if (unlikely(isairq <= I8259A_IRQ_BASE)) 255 return IRQ_NONE; 256 generic_handle_irq(isairq); 257 return IRQ_HANDLED; 258 } 259 260 static int __init 261 txx9_i8259_irq_setup(int irq) 262 { 263 int err; 264 265 init_i8259_irqs(); 266 err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED, 267 "cascade(i8259)", (void *)(long)irq); 268 if (!err) 269 printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); 270 return err; 271 } 272 273 static void __init quirk_slc90e66_bridge(struct pci_dev *dev) 274 { 275 int irq; /* PCI/ISA Bridge interrupt */ 276 u8 reg_64; 277 u32 reg_b0; 278 u8 reg_e1; 279 irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */ 280 if (!irq) 281 return; 282 txx9_i8259_irq_setup(irq); 283 pci_read_config_byte(dev, 0x64, ®_64); 284 pci_read_config_dword(dev, 0xb0, ®_b0); 285 pci_read_config_byte(dev, 0xe1, ®_e1); 286 /* serial irq control */ 287 reg_64 = 0xd0; 288 /* serial irq pin */ 289 reg_b0 |= 0x00010000; 290 /* ide irq on isa14 */ 291 reg_e1 &= 0xf0; 292 reg_e1 |= 0x0d; 293 pci_write_config_byte(dev, 0x64, reg_64); 294 pci_write_config_dword(dev, 0xb0, reg_b0); 295 pci_write_config_byte(dev, 0xe1, reg_e1); 296 297 smsc_fdc37m81x_init(0x3f0); 298 smsc_fdc37m81x_config_beg(); 299 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, 300 SMSC_FDC37M81X_KBD); 301 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); 302 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); 303 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, 304 1); 305 smsc_fdc37m81x_config_end(); 306 } 307 308 static void quirk_slc90e66_ide(struct pci_dev *dev) 309 { 310 unsigned char dat; 311 int regs[2] = {0x41, 0x43}; 312 int i; 313 314 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ 315 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14); 316 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat); 317 printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat); 318 /* enable SMSC SLC90E66 IDE */ 319 for (i = 0; i < ARRAY_SIZE(regs); i++) { 320 pci_read_config_byte(dev, regs[i], &dat); 321 pci_write_config_byte(dev, regs[i], dat | 0x80); 322 pci_read_config_byte(dev, regs[i], &dat); 323 printk(KERN_CONT " IDETIM%d %02x", i, dat); 324 } 325 pci_read_config_byte(dev, 0x5c, &dat); 326 /* 327 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! 328 * 329 * This line of code is intended to provide the user with a work 330 * around solution to the anomalies cited in SMSC's anomaly sheet 331 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". 332 * 333 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! 334 */ 335 dat |= 0x01; 336 pci_write_config_byte(dev, regs[i], dat); 337 pci_read_config_byte(dev, 0x5c, &dat); 338 printk(KERN_CONT " REG5C %02x", dat); 339 printk(KERN_CONT "\n"); 340 } 341 #endif /* CONFIG_TOSHIBA_FPCIB0 */ 342 343 static void final_fixup(struct pci_dev *dev) 344 { 345 unsigned char bist; 346 347 /* Do build-in self test */ 348 if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL && 349 (bist & PCI_BIST_CAPABLE)) { 350 unsigned long timeout; 351 pci_set_power_state(dev, PCI_D0); 352 printk(KERN_INFO "PCI: %s BIST...", pci_name(dev)); 353 pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START); 354 timeout = jiffies + HZ * 2; /* timeout after 2 sec */ 355 do { 356 pci_read_config_byte(dev, PCI_BIST, &bist); 357 if (time_after(jiffies, timeout)) 358 break; 359 } while (bist & PCI_BIST_START); 360 if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START)) 361 printk(KERN_CONT "failed. (0x%x)\n", bist); 362 else 363 printk(KERN_CONT "OK.\n"); 364 } 365 } 366 367 #ifdef CONFIG_TOSHIBA_FPCIB0 368 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, 370 quirk_slc90e66_bridge); 371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, 372 quirk_slc90e66_ide); 373 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, 374 quirk_slc90e66_ide); 375 #endif 376 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup); 377 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup); 378