1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 */
9 #ifndef _ASM_PGTABLE_32_H
10 #define _ASM_PGTABLE_32_H
11
12 #include <asm/addrspace.h>
13 #include <asm/page.h>
14
15 #include <linux/linkage.h>
16 #include <asm/cachectl.h>
17 #include <asm/fixmap.h>
18
19 #include <asm-generic/pgtable-nopmd.h>
20
21 #ifdef CONFIG_HIGHMEM
22 #include <asm/highmem.h>
23 #endif
24
25 /*
26 * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
27 *
28 * We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
29 * our 2-level table layout would normally have a PGD entry cover a contiguous
30 * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
31 * pointers, each pointing to a 4KB physical page). The problem is that 4MB,
32 * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page
33 * support, not one of the standard supported sizes (1MB,4MB,16MB,...).
34 * To correct for this, when huge pages are enabled, we halve the number of
35 * pointers a PTE page holds, making its last half go to waste. Correspondingly,
36 * we double the number of PGD pages. Overall, page table memory overhead
37 * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
38 *
39 * NOTE: We don't yet support huge pages if extended-addressing is enabled
40 * (i.e. EVA, XPA, 36-bit Alchemy/Netlogic).
41 */
42
43 extern int temp_tlb_entry;
44
45 /*
46 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
47 * starting at the top and working down. This is for populating the
48 * TLB before trap_init() puts the TLB miss handler in place. It
49 * should be used only for entries matching the actual page tables,
50 * to prevent inconsistencies.
51 */
52 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
53 unsigned long entryhi, unsigned long pagemask);
54
55 /*
56 * Basically we have the same two-level (which is the logical three level
57 * Linux page table layout folded) page tables as the i386. Some day
58 * when we have proper page coloring support we can have a 1% quicker
59 * tlb refill handling mechanism, but for now it is a bit slower but
60 * works even with the cache aliasing problem the R4k and above have.
61 */
62
63 /* PGDIR_SHIFT determines what a third-level page table entry can map */
64 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
65 # define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2 - 1)
66 #else
67 # define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2)
68 #endif
69
70 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
71 #define PGDIR_MASK (~(PGDIR_SIZE-1))
72
73 /*
74 * Entries per page directory level: we use two-level, so
75 * we don't really have any PUD/PMD directory physically.
76 */
77 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
78 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
79 #else
80 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
81 #endif
82
83 #define PGD_TABLE_ORDER (__PGD_TABLE_ORDER >= 0 ? __PGD_TABLE_ORDER : 0)
84 #define PUD_TABLE_ORDER aieeee_attempt_to_allocate_pud
85 #define PMD_TABLE_ORDER aieeee_attempt_to_allocate_pmd
86
87 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
88 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
89 # define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t) / 2)
90 #else
91 # define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t))
92 #endif
93
94 #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
95
96 #define VMALLOC_START MAP_BASE
97
98 #define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
99 #define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
100
101 #ifdef CONFIG_HIGHMEM
102 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
103 #else
104 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
105 #endif
106
107 #ifdef CONFIG_PHYS_ADDR_T_64BIT
108 #define pte_ERROR(e) \
109 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
110 #else
111 #define pte_ERROR(e) \
112 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
113 #endif
114 #define pgd_ERROR(e) \
115 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
116
117 extern void load_pgd(unsigned long pg_dir);
118
119 extern pte_t invalid_pte_table[PTRS_PER_PTE];
120
121 /*
122 * Empty pgd/pmd entries point to the invalid_pte_table.
123 */
pmd_none(pmd_t pmd)124 static inline int pmd_none(pmd_t pmd)
125 {
126 return pmd_val(pmd) == (unsigned long) invalid_pte_table;
127 }
128
pmd_bad(pmd_t pmd)129 static inline int pmd_bad(pmd_t pmd)
130 {
131 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
132 /* pmd_huge(pmd) but inline */
133 if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
134 return 0;
135 #endif
136
137 if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
138 return 1;
139
140 return 0;
141 }
142
pmd_present(pmd_t pmd)143 static inline int pmd_present(pmd_t pmd)
144 {
145 return pmd_val(pmd) != (unsigned long) invalid_pte_table;
146 }
147
pmd_clear(pmd_t * pmdp)148 static inline void pmd_clear(pmd_t *pmdp)
149 {
150 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
151 }
152
153 #if defined(CONFIG_XPA)
154
155 #define MAX_POSSIBLE_PHYSMEM_BITS 40
156 #define pte_pfn(x) (((unsigned long)((x).pte_high >> PFN_PTE_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
157 static inline pte_t
pfn_pte(unsigned long pfn,pgprot_t prot)158 pfn_pte(unsigned long pfn, pgprot_t prot)
159 {
160 pte_t pte;
161
162 pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
163 (pgprot_val(prot) & ~_PFNX_MASK);
164 pte.pte_high = (pfn << PFN_PTE_SHIFT) |
165 (pgprot_val(prot) & ~_PFN_MASK);
166 return pte;
167 }
168
169 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
170
171 #define MAX_POSSIBLE_PHYSMEM_BITS 36
172 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
173
pfn_pte(unsigned long pfn,pgprot_t prot)174 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
175 {
176 pte_t pte;
177
178 pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
179 pte.pte_low = pgprot_val(prot);
180
181 return pte;
182 }
183
184 #else
185
186 #define MAX_POSSIBLE_PHYSMEM_BITS 32
187 #define pte_pfn(x) ((unsigned long)((x).pte >> PFN_PTE_SHIFT))
188 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))
189 #define pfn_pmd(pfn, prot) __pmd(((unsigned long long)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))
190 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
191
192 #define pte_page(x) pfn_to_page(pte_pfn(x))
193
194 /*
195 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
196 * are !pte_none() && !pte_present().
197 */
198 #if defined(CONFIG_CPU_R3K_TLB)
199
200 /*
201 * Format of swap PTEs:
202 *
203 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
204 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
205 * <----------- offset ------------> < type -> V G E 0 0 0 0 0 0 P
206 *
207 * E is the exclusive marker that is not stored in swap entries.
208 * _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain
209 * unused.
210 */
211 #define __swp_type(x) (((x).val >> 10) & 0x1f)
212 #define __swp_offset(x) ((x).val >> 15)
213 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 10) | ((offset) << 15) })
214 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
215 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
216
217 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */
218 #define _PAGE_SWP_EXCLUSIVE (1 << 7)
219
220 #else
221
222 #if defined(CONFIG_XPA)
223
224 /*
225 * Format of swap PTEs:
226 *
227 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
228 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
229 * 0 0 0 0 0 0 E P <------------------ zeroes ------------------->
230 *
231 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
232 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
233 * <----------------- offset ------------------> < type -> V G 0 0
234 *
235 * E is the exclusive marker that is not stored in swap entries.
236 * _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain
237 * unused.
238 */
239 #define __swp_type(x) (((x).val >> 4) & 0x1f)
240 #define __swp_offset(x) ((x).val >> 9)
241 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 4) | ((offset) << 9) })
242 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
243 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
244
245 /*
246 * We borrow bit 57 (bit 25 in the low PTE) to store the exclusive marker in
247 * swap PTEs.
248 */
249 #define _PAGE_SWP_EXCLUSIVE (1 << 25)
250
251 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
252
253 /*
254 * Format of swap PTEs:
255 *
256 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
257 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
258 * <------------------ zeroes -------------------> E P 0 0 0 0 0 0
259 *
260 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
261 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
262 * <------------------- offset --------------------> < type -> V G
263 *
264 * E is the exclusive marker that is not stored in swap entries.
265 * _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain
266 * unused.
267 */
268 #define __swp_type(x) (((x).val >> 2) & 0x1f)
269 #define __swp_offset(x) ((x).val >> 7)
270 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 2) | ((offset) << 7) })
271 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
272 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
273
274 /*
275 * We borrow bit 39 (bit 7 in the low PTE) to store the exclusive marker in swap
276 * PTEs.
277 */
278 #define _PAGE_SWP_EXCLUSIVE (1 << 7)
279
280 #else
281 /*
282 * Format of swap PTEs:
283 *
284 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
285 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
286 * <------------- offset --------------> < type -> 0 0 0 0 0 0 E P
287 *
288 * E is the exclusive marker that is not stored in swap entries.
289 * _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain
290 * unused. The location of V and G varies.
291 */
292 #define __swp_type(x) (((x).val >> 8) & 0x1f)
293 #define __swp_offset(x) ((x).val >> 13)
294 #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
295 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
296 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
297
298 /* We borrow bit 1 to store the exclusive marker in swap PTEs. */
299 #define _PAGE_SWP_EXCLUSIVE (1 << 1)
300
301 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
302
303 #endif /* defined(CONFIG_CPU_R3K_TLB) */
304
305 #endif /* _ASM_PGTABLE_32_H */
306