1 /* 2 * Copyright (C) 2013 Imagination Technologies 3 * Author: Paul Burton <paul.burton@imgtec.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #ifndef __MIPS_ASM_MIPS_CPC_H__ 12 #define __MIPS_ASM_MIPS_CPC_H__ 13 14 #include <linux/io.h> 15 #include <linux/types.h> 16 17 /* The base address of the CPC registers */ 18 extern void __iomem *mips_cpc_base; 19 20 /** 21 * mips_cpc_default_phys_base - retrieve the default physical base address of 22 * the CPC 23 * 24 * Returns the default physical base address of the Cluster Power Controller 25 * memory mapped registers. This is platform dependant & must therefore be 26 * implemented per-platform. 27 */ 28 extern phys_addr_t mips_cpc_default_phys_base(void); 29 30 /** 31 * mips_cpc_probe - probe for a Cluster Power Controller 32 * 33 * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if 34 * a CPC is successfully detected, else -errno. 35 */ 36 #ifdef CONFIG_MIPS_CPC 37 extern int mips_cpc_probe(void); 38 #else 39 static inline int mips_cpc_probe(void) 40 { 41 return -ENODEV; 42 } 43 #endif 44 45 /** 46 * mips_cpc_present - determine whether a Cluster Power Controller is present 47 * 48 * Returns true if a CPC is present in the system, else false. 49 */ 50 static inline bool mips_cpc_present(void) 51 { 52 #ifdef CONFIG_MIPS_CPC 53 return mips_cpc_base != NULL; 54 #else 55 return false; 56 #endif 57 } 58 59 /* Offsets from the CPC base address to various control blocks */ 60 #define MIPS_CPC_GCB_OFS 0x0000 61 #define MIPS_CPC_CLCB_OFS 0x2000 62 #define MIPS_CPC_COCB_OFS 0x4000 63 64 /* Macros to ease the creation of register access functions */ 65 #define BUILD_CPC_R_(name, off) \ 66 static inline u32 *addr_cpc_##name(void) \ 67 { \ 68 return (u32 *)(mips_cpc_base + (off)); \ 69 } \ 70 \ 71 static inline u32 read_cpc_##name(void) \ 72 { \ 73 return __raw_readl(mips_cpc_base + (off)); \ 74 } 75 76 #define BUILD_CPC__W(name, off) \ 77 static inline void write_cpc_##name(u32 value) \ 78 { \ 79 __raw_writel(value, mips_cpc_base + (off)); \ 80 } 81 82 #define BUILD_CPC_RW(name, off) \ 83 BUILD_CPC_R_(name, off) \ 84 BUILD_CPC__W(name, off) 85 86 #define BUILD_CPC_Cx_R_(name, off) \ 87 BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \ 88 BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off)) 89 90 #define BUILD_CPC_Cx__W(name, off) \ 91 BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \ 92 BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off)) 93 94 #define BUILD_CPC_Cx_RW(name, off) \ 95 BUILD_CPC_Cx_R_(name, off) \ 96 BUILD_CPC_Cx__W(name, off) 97 98 /* GCB register accessor functions */ 99 BUILD_CPC_RW(access, MIPS_CPC_GCB_OFS + 0x00) 100 BUILD_CPC_RW(seqdel, MIPS_CPC_GCB_OFS + 0x08) 101 BUILD_CPC_RW(rail, MIPS_CPC_GCB_OFS + 0x10) 102 BUILD_CPC_RW(resetlen, MIPS_CPC_GCB_OFS + 0x18) 103 BUILD_CPC_R_(revision, MIPS_CPC_GCB_OFS + 0x20) 104 105 /* Core Local & Core Other accessor functions */ 106 BUILD_CPC_Cx_RW(cmd, 0x00) 107 BUILD_CPC_Cx_RW(stat_conf, 0x08) 108 BUILD_CPC_Cx_RW(other, 0x10) 109 BUILD_CPC_Cx_RW(vp_stop, 0x20) 110 BUILD_CPC_Cx_RW(vp_run, 0x28) 111 BUILD_CPC_Cx_RW(vp_running, 0x30) 112 113 /* CPC_Cx_CMD register fields */ 114 #define CPC_Cx_CMD_SHF 0 115 #define CPC_Cx_CMD_MSK (_ULCAST_(0xf) << 0) 116 #define CPC_Cx_CMD_CLOCKOFF (_ULCAST_(0x1) << 0) 117 #define CPC_Cx_CMD_PWRDOWN (_ULCAST_(0x2) << 0) 118 #define CPC_Cx_CMD_PWRUP (_ULCAST_(0x3) << 0) 119 #define CPC_Cx_CMD_RESET (_ULCAST_(0x4) << 0) 120 121 /* CPC_Cx_STAT_CONF register fields */ 122 #define CPC_Cx_STAT_CONF_PWRUPE_SHF 23 123 #define CPC_Cx_STAT_CONF_PWRUPE_MSK (_ULCAST_(0x1) << 23) 124 #define CPC_Cx_STAT_CONF_SEQSTATE_SHF 19 125 #define CPC_Cx_STAT_CONF_SEQSTATE_MSK (_ULCAST_(0xf) << 19) 126 #define CPC_Cx_STAT_CONF_SEQSTATE_D0 (_ULCAST_(0x0) << 19) 127 #define CPC_Cx_STAT_CONF_SEQSTATE_U0 (_ULCAST_(0x1) << 19) 128 #define CPC_Cx_STAT_CONF_SEQSTATE_U1 (_ULCAST_(0x2) << 19) 129 #define CPC_Cx_STAT_CONF_SEQSTATE_U2 (_ULCAST_(0x3) << 19) 130 #define CPC_Cx_STAT_CONF_SEQSTATE_U3 (_ULCAST_(0x4) << 19) 131 #define CPC_Cx_STAT_CONF_SEQSTATE_U4 (_ULCAST_(0x5) << 19) 132 #define CPC_Cx_STAT_CONF_SEQSTATE_U5 (_ULCAST_(0x6) << 19) 133 #define CPC_Cx_STAT_CONF_SEQSTATE_U6 (_ULCAST_(0x7) << 19) 134 #define CPC_Cx_STAT_CONF_SEQSTATE_D1 (_ULCAST_(0x8) << 19) 135 #define CPC_Cx_STAT_CONF_SEQSTATE_D3 (_ULCAST_(0x9) << 19) 136 #define CPC_Cx_STAT_CONF_SEQSTATE_D2 (_ULCAST_(0xa) << 19) 137 #define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF 17 138 #define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK (_ULCAST_(0x1) << 17) 139 #define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF 16 140 #define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK (_ULCAST_(0x1) << 16) 141 #define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF 15 142 #define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK (_ULCAST_(0x1) << 15) 143 144 /* CPC_Cx_OTHER register fields */ 145 #define CPC_Cx_OTHER_CORENUM_SHF 16 146 #define CPC_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xff) << 16) 147 148 #ifdef CONFIG_MIPS_CPC 149 150 /** 151 * mips_cpc_lock_other - lock access to another core 152 * core: the other core to be accessed 153 * 154 * Call before operating upon a core via the 'other' register region in 155 * order to prevent the region being moved during access. Must be called 156 * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed 157 * by a call to mips_cpc_unlock_other. 158 */ 159 extern void mips_cpc_lock_other(unsigned int core); 160 161 /** 162 * mips_cpc_unlock_other - unlock access to another core 163 * 164 * Call after operating upon another core via the 'other' register region. 165 * Must be called after mips_cpc_lock_other. 166 */ 167 extern void mips_cpc_unlock_other(void); 168 169 #else /* !CONFIG_MIPS_CPC */ 170 171 static inline void mips_cpc_lock_other(unsigned int core) { } 172 static inline void mips_cpc_unlock_other(void) { } 173 174 #endif /* !CONFIG_MIPS_CPC */ 175 176 #endif /* __MIPS_ASM_MIPS_CPC_H__ */ 177