1 /* 2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2008-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #ifndef _ASM_MICROBLAZE_PGTABLE_H 12 #define _ASM_MICROBLAZE_PGTABLE_H 13 14 #include <asm/setup.h> 15 16 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 17 remap_pfn_range(vma, vaddr, pfn, size, prot) 18 19 #ifndef __ASSEMBLY__ 20 extern int mem_init_done; 21 #endif 22 23 #ifndef CONFIG_MMU 24 25 #define pgd_present(pgd) (1) /* pages are always present on non MMU */ 26 #define pgd_none(pgd) (0) 27 #define pgd_bad(pgd) (0) 28 #define pgd_clear(pgdp) 29 #define kern_addr_valid(addr) (1) 30 #define pmd_offset(a, b) ((void *) 0) 31 32 #define PAGE_NONE __pgprot(0) /* these mean nothing to non MMU */ 33 #define PAGE_SHARED __pgprot(0) /* these mean nothing to non MMU */ 34 #define PAGE_COPY __pgprot(0) /* these mean nothing to non MMU */ 35 #define PAGE_READONLY __pgprot(0) /* these mean nothing to non MMU */ 36 #define PAGE_KERNEL __pgprot(0) /* these mean nothing to non MMU */ 37 38 #define pgprot_noncached(x) (x) 39 40 #define __swp_type(x) (0) 41 #define __swp_offset(x) (0) 42 #define __swp_entry(typ, off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) 43 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 44 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 45 46 #ifndef __ASSEMBLY__ 47 static inline int pte_file(pte_t pte) { return 0; } 48 #endif /* __ASSEMBLY__ */ 49 50 #define ZERO_PAGE(vaddr) ({ BUG(); NULL; }) 51 52 #define swapper_pg_dir ((pgd_t *) NULL) 53 54 #define pgtable_cache_init() do {} while (0) 55 56 #define arch_enter_lazy_cpu_mode() do {} while (0) 57 58 #define pgprot_noncached_wc(prot) prot 59 60 /* 61 * All 32bit addresses are effectively valid for vmalloc... 62 * Sort of meaningless for non-VM targets. 63 */ 64 #define VMALLOC_START 0 65 #define VMALLOC_END 0xffffffff 66 67 #else /* CONFIG_MMU */ 68 69 #include <asm-generic/4level-fixup.h> 70 71 #ifdef __KERNEL__ 72 #ifndef __ASSEMBLY__ 73 74 #include <linux/sched.h> 75 #include <linux/threads.h> 76 #include <asm/processor.h> /* For TASK_SIZE */ 77 #include <asm/mmu.h> 78 #include <asm/page.h> 79 80 #define FIRST_USER_ADDRESS 0 81 82 extern unsigned long va_to_phys(unsigned long address); 83 extern pte_t *va_to_pte(unsigned long address); 84 85 /* 86 * The following only work if pte_present() is true. 87 * Undefined behaviour if not.. 88 */ 89 90 static inline int pte_special(pte_t pte) { return 0; } 91 92 static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 93 94 /* Start and end of the vmalloc area. */ 95 /* Make sure to map the vmalloc area above the pinned kernel memory area 96 of 32Mb. */ 97 #define VMALLOC_START (CONFIG_KERNEL_START + \ 98 max(32 * 1024 * 1024UL, memory_size)) 99 #define VMALLOC_END ioremap_bot 100 101 #endif /* __ASSEMBLY__ */ 102 103 /* 104 * Macro to mark a page protection value as "uncacheable". 105 */ 106 107 #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \ 108 _PAGE_WRITETHRU) 109 110 #define pgprot_noncached(prot) \ 111 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 112 _PAGE_NO_CACHE | _PAGE_GUARDED)) 113 114 #define pgprot_noncached_wc(prot) \ 115 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 116 _PAGE_NO_CACHE)) 117 118 /* 119 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 120 * table containing PTEs, together with a set of 16 segment registers, to 121 * define the virtual to physical address mapping. 122 * 123 * We use the hash table as an extended TLB, i.e. a cache of currently 124 * active mappings. We maintain a two-level page table tree, much 125 * like that used by the i386, for the sake of the Linux memory 126 * management code. Low-level assembler code in hashtable.S 127 * (procedure hash_page) is responsible for extracting ptes from the 128 * tree and putting them into the hash table when necessary, and 129 * updating the accessed and modified bits in the page table tree. 130 */ 131 132 /* 133 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 134 * instruction and data sides share a unified, 64-entry, semi-associative 135 * TLB which is maintained totally under software control. In addition, the 136 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative 137 * TLB which serves as a first level to the shared TLB. These two TLBs are 138 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions). 139 */ 140 141 /* 142 * The normal case is that PTEs are 32-bits and we have a 1-page 143 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 144 * 145 */ 146 147 /* PMD_SHIFT determines the size of the area mapped by the PTE pages */ 148 #define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT) 149 #define PMD_SIZE (1UL << PMD_SHIFT) 150 #define PMD_MASK (~(PMD_SIZE-1)) 151 152 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 153 #define PGDIR_SHIFT PMD_SHIFT 154 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 155 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 156 157 /* 158 * entries per page directory level: our page-table tree is two-level, so 159 * we don't really have any PMD directory. 160 */ 161 #define PTRS_PER_PTE (1 << PTE_SHIFT) 162 #define PTRS_PER_PMD 1 163 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) 164 165 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 166 #define FIRST_USER_PGD_NR 0 167 168 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) 169 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) 170 171 #define pte_ERROR(e) \ 172 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \ 173 __FILE__, __LINE__, pte_val(e)) 174 #define pmd_ERROR(e) \ 175 printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \ 176 __FILE__, __LINE__, pmd_val(e)) 177 #define pgd_ERROR(e) \ 178 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ 179 __FILE__, __LINE__, pgd_val(e)) 180 181 /* 182 * Bits in a linux-style PTE. These match the bits in the 183 * (hardware-defined) PTE as closely as possible. 184 */ 185 186 /* There are several potential gotchas here. The hardware TLBLO 187 * field looks like this: 188 * 189 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 190 * RPN..................... 0 0 EX WR ZSEL....... W I M G 191 * 192 * Where possible we make the Linux PTE bits match up with this 193 * 194 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can 195 * support down to 1k pages), this is done in the TLBMiss exception 196 * handler. 197 * - We use only zones 0 (for kernel pages) and 1 (for user pages) 198 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB 199 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct 200 * zone. 201 * - PRESENT *must* be in the bottom two bits because swap cache 202 * entries use the top 30 bits. Because 4xx doesn't support SMP 203 * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 204 * is cleared in the TLB miss handler before the TLB entry is loaded. 205 * - All other bits of the PTE are loaded into TLBLO without 206 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for 207 * software PTE bits. We actually use use bits 21, 24, 25, and 208 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and 209 * PRESENT. 210 */ 211 212 /* Definitions for MicroBlaze. */ 213 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ 214 #define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */ 215 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ 216 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ 217 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ 218 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ 219 #define _PAGE_RW 0x040 /* software: Writes permitted */ 220 #define _PAGE_DIRTY 0x080 /* software: dirty page */ 221 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ 222 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ 223 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ 224 #define _PMD_PRESENT PAGE_MASK 225 226 /* 227 * Some bits are unused... 228 */ 229 #ifndef _PAGE_HASHPTE 230 #define _PAGE_HASHPTE 0 231 #endif 232 #ifndef _PTE_NONE_MASK 233 #define _PTE_NONE_MASK 0 234 #endif 235 #ifndef _PAGE_SHARED 236 #define _PAGE_SHARED 0 237 #endif 238 #ifndef _PAGE_HWWRITE 239 #define _PAGE_HWWRITE 0 240 #endif 241 #ifndef _PAGE_HWEXEC 242 #define _PAGE_HWEXEC 0 243 #endif 244 #ifndef _PAGE_EXEC 245 #define _PAGE_EXEC 0 246 #endif 247 248 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 249 250 /* 251 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware 252 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need 253 * to have it in the Linux PTE, and in fact the bit could be reused for 254 * another purpose. -- paulus. 255 */ 256 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) 257 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) 258 259 #define _PAGE_KERNEL \ 260 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC) 261 262 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) 263 264 #define PAGE_NONE __pgprot(_PAGE_BASE) 265 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 266 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 267 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 268 #define PAGE_SHARED_X \ 269 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 270 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 271 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 272 273 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 274 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED) 275 #define PAGE_KERNEL_CI __pgprot(_PAGE_IO) 276 277 /* 278 * We consider execute permission the same as read. 279 * Also, write permissions imply read permissions. 280 */ 281 #define __P000 PAGE_NONE 282 #define __P001 PAGE_READONLY_X 283 #define __P010 PAGE_COPY 284 #define __P011 PAGE_COPY_X 285 #define __P100 PAGE_READONLY 286 #define __P101 PAGE_READONLY_X 287 #define __P110 PAGE_COPY 288 #define __P111 PAGE_COPY_X 289 290 #define __S000 PAGE_NONE 291 #define __S001 PAGE_READONLY_X 292 #define __S010 PAGE_SHARED 293 #define __S011 PAGE_SHARED_X 294 #define __S100 PAGE_READONLY 295 #define __S101 PAGE_READONLY_X 296 #define __S110 PAGE_SHARED 297 #define __S111 PAGE_SHARED_X 298 299 #ifndef __ASSEMBLY__ 300 /* 301 * ZERO_PAGE is a global shared page that is always zero: used 302 * for zero-mapped memory areas etc.. 303 */ 304 extern unsigned long empty_zero_page[1024]; 305 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 306 307 #endif /* __ASSEMBLY__ */ 308 309 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) 310 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 311 #define pte_clear(mm, addr, ptep) \ 312 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) 313 314 #define pmd_none(pmd) (!pmd_val(pmd)) 315 #define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0) 316 #define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0) 317 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) 318 319 #define pte_page(x) (mem_map + (unsigned long) \ 320 ((pte_val(x) - memory_start) >> PAGE_SHIFT)) 321 #define PFN_SHIFT_OFFSET (PAGE_SHIFT) 322 323 #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) 324 325 #define pfn_pte(pfn, prot) \ 326 __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot)) 327 328 #ifndef __ASSEMBLY__ 329 /* 330 * The "pgd_xxx()" functions here are trivial for a folded two-level 331 * setup: the pgd is never bad, and a pmd always exists (as it's folded 332 * into the pgd entry) 333 */ 334 static inline int pgd_none(pgd_t pgd) { return 0; } 335 static inline int pgd_bad(pgd_t pgd) { return 0; } 336 static inline int pgd_present(pgd_t pgd) { return 1; } 337 #define pgd_clear(xp) do { } while (0) 338 #define pgd_page(pgd) \ 339 ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) 340 341 /* 342 * The following only work if pte_present() is true. 343 * Undefined behaviour if not.. 344 */ 345 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } 346 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } 347 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 348 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 349 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 350 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } 351 352 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } 353 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } 354 355 static inline pte_t pte_rdprotect(pte_t pte) \ 356 { pte_val(pte) &= ~_PAGE_USER; return pte; } 357 static inline pte_t pte_wrprotect(pte_t pte) \ 358 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } 359 static inline pte_t pte_exprotect(pte_t pte) \ 360 { pte_val(pte) &= ~_PAGE_EXEC; return pte; } 361 static inline pte_t pte_mkclean(pte_t pte) \ 362 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } 363 static inline pte_t pte_mkold(pte_t pte) \ 364 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 365 366 static inline pte_t pte_mkread(pte_t pte) \ 367 { pte_val(pte) |= _PAGE_USER; return pte; } 368 static inline pte_t pte_mkexec(pte_t pte) \ 369 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } 370 static inline pte_t pte_mkwrite(pte_t pte) \ 371 { pte_val(pte) |= _PAGE_RW; return pte; } 372 static inline pte_t pte_mkdirty(pte_t pte) \ 373 { pte_val(pte) |= _PAGE_DIRTY; return pte; } 374 static inline pte_t pte_mkyoung(pte_t pte) \ 375 { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 376 377 /* 378 * Conversion functions: convert a page and protection to a page entry, 379 * and a page entry and page directory to the page they refer to. 380 */ 381 382 static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot) 383 { 384 pte_t pte; 385 pte_val(pte) = physpage | pgprot_val(pgprot); 386 return pte; 387 } 388 389 #define mk_pte(page, pgprot) \ 390 ({ \ 391 pte_t pte; \ 392 pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \ 393 pgprot_val(pgprot); \ 394 pte; \ 395 }) 396 397 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 398 { 399 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); 400 return pte; 401 } 402 403 /* 404 * Atomic PTE updates. 405 * 406 * pte_update clears and sets bit atomically, and returns 407 * the old pte value. 408 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant 409 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits. 410 */ 411 static inline unsigned long pte_update(pte_t *p, unsigned long clr, 412 unsigned long set) 413 { 414 unsigned long flags, old, tmp; 415 416 raw_local_irq_save(flags); 417 418 __asm__ __volatile__( "lw %0, %2, r0 \n" 419 "andn %1, %0, %3 \n" 420 "or %1, %1, %4 \n" 421 "sw %1, %2, r0 \n" 422 : "=&r" (old), "=&r" (tmp) 423 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set) 424 : "cc"); 425 426 raw_local_irq_restore(flags); 427 428 return old; 429 } 430 431 /* 432 * set_pte stores a linux PTE into the linux page table. 433 */ 434 static inline void set_pte(struct mm_struct *mm, unsigned long addr, 435 pte_t *ptep, pte_t pte) 436 { 437 *ptep = pte; 438 } 439 440 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 441 pte_t *ptep, pte_t pte) 442 { 443 *ptep = pte; 444 } 445 446 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 447 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 448 unsigned long address, pte_t *ptep) 449 { 450 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; 451 } 452 453 static inline int ptep_test_and_clear_dirty(struct mm_struct *mm, 454 unsigned long addr, pte_t *ptep) 455 { 456 return (pte_update(ptep, \ 457 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; 458 } 459 460 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 461 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 462 unsigned long addr, pte_t *ptep) 463 { 464 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); 465 } 466 467 /*static inline void ptep_set_wrprotect(struct mm_struct *mm, 468 unsigned long addr, pte_t *ptep) 469 { 470 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); 471 }*/ 472 473 static inline void ptep_mkdirty(struct mm_struct *mm, 474 unsigned long addr, pte_t *ptep) 475 { 476 pte_update(ptep, 0, _PAGE_DIRTY); 477 } 478 479 /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/ 480 481 /* Convert pmd entry to page */ 482 /* our pmd entry is an effective address of pte table*/ 483 /* returns effective address of the pmd entry*/ 484 #define pmd_page_kernel(pmd) ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) 485 486 /* returns struct *page of the pmd entry*/ 487 #define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT)) 488 489 /* to find an entry in a kernel page-table-directory */ 490 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 491 492 /* to find an entry in a page-table-directory */ 493 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 494 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 495 496 /* Find an entry in the second-level page table.. */ 497 static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) 498 { 499 return (pmd_t *) dir; 500 } 501 502 /* Find an entry in the third-level page table.. */ 503 #define pte_index(address) \ 504 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 505 #define pte_offset_kernel(dir, addr) \ 506 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr)) 507 #define pte_offset_map(dir, addr) \ 508 ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr)) 509 510 #define pte_unmap(pte) kunmap_atomic(pte) 511 512 /* Encode and decode a nonlinear file mapping entry */ 513 #define PTE_FILE_MAX_BITS 29 514 #define pte_to_pgoff(pte) (pte_val(pte) >> 3) 515 #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) 516 517 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 518 519 /* 520 * Encode and decode a swap entry. 521 * Note that the bits we use in a PTE for representing a swap entry 522 * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit 523 * (if used). -- paulus 524 */ 525 #define __swp_type(entry) ((entry).val & 0x3f) 526 #define __swp_offset(entry) ((entry).val >> 6) 527 #define __swp_entry(type, offset) \ 528 ((swp_entry_t) { (type) | ((offset) << 6) }) 529 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 }) 530 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 }) 531 532 extern unsigned long iopa(unsigned long addr); 533 534 /* Values for nocacheflag and cmode */ 535 /* These are not used by the APUS kernel_map, but prevents 536 * compilation errors. 537 */ 538 #define IOMAP_FULL_CACHING 0 539 #define IOMAP_NOCACHE_SER 1 540 #define IOMAP_NOCACHE_NONSER 2 541 #define IOMAP_NO_COPYBACK 3 542 543 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 544 #define kern_addr_valid(addr) (1) 545 546 #define io_remap_page_range remap_page_range 547 548 /* 549 * No page table caches to initialise 550 */ 551 #define pgtable_cache_init() do { } while (0) 552 553 void do_page_fault(struct pt_regs *regs, unsigned long address, 554 unsigned long error_code); 555 556 void mapin_ram(void); 557 int map_page(unsigned long va, phys_addr_t pa, int flags); 558 559 extern int mem_init_done; 560 561 asmlinkage void __init mmu_init(void); 562 563 void __init *early_get_page(void); 564 565 #endif /* __ASSEMBLY__ */ 566 #endif /* __KERNEL__ */ 567 568 #endif /* CONFIG_MMU */ 569 570 #ifndef __ASSEMBLY__ 571 #include <asm-generic/pgtable.h> 572 573 extern unsigned long ioremap_bot, ioremap_base; 574 575 void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle); 576 void consistent_free(size_t size, void *vaddr); 577 void consistent_sync(void *vaddr, size_t size, int direction); 578 void consistent_sync_page(struct page *page, unsigned long offset, 579 size_t size, int direction); 580 581 void setup_memory(void); 582 #endif /* __ASSEMBLY__ */ 583 584 #endif /* _ASM_MICROBLAZE_PGTABLE_H */ 585