1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2008-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 */ 7 8 #ifndef _ASM_MICROBLAZE_PGTABLE_H 9 #define _ASM_MICROBLAZE_PGTABLE_H 10 11 #include <asm/setup.h> 12 13 #ifndef __ASSEMBLY__ 14 extern int mem_init_done; 15 #endif 16 17 #include <asm-generic/pgtable-nopmd.h> 18 19 #ifdef __KERNEL__ 20 #ifndef __ASSEMBLY__ 21 22 #include <linux/sched.h> 23 #include <linux/threads.h> 24 #include <asm/processor.h> /* For TASK_SIZE */ 25 #include <asm/mmu.h> 26 #include <asm/page.h> 27 28 extern unsigned long va_to_phys(unsigned long address); 29 extern pte_t *va_to_pte(unsigned long address); 30 31 /* 32 * The following only work if pte_present() is true. 33 * Undefined behaviour if not.. 34 */ 35 36 /* Start and end of the vmalloc area. */ 37 /* Make sure to map the vmalloc area above the pinned kernel memory area 38 of 32Mb. */ 39 #define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE) 40 #define VMALLOC_END ioremap_bot 41 42 #endif /* __ASSEMBLY__ */ 43 44 /* 45 * Macro to mark a page protection value as "uncacheable". 46 */ 47 48 #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \ 49 _PAGE_WRITETHRU) 50 51 #define pgprot_noncached(prot) \ 52 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 53 _PAGE_NO_CACHE | _PAGE_GUARDED)) 54 55 #define pgprot_noncached_wc(prot) \ 56 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 57 _PAGE_NO_CACHE)) 58 59 /* 60 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 61 * table containing PTEs, together with a set of 16 segment registers, to 62 * define the virtual to physical address mapping. 63 * 64 * We use the hash table as an extended TLB, i.e. a cache of currently 65 * active mappings. We maintain a two-level page table tree, much 66 * like that used by the i386, for the sake of the Linux memory 67 * management code. Low-level assembler code in hashtable.S 68 * (procedure hash_page) is responsible for extracting ptes from the 69 * tree and putting them into the hash table when necessary, and 70 * updating the accessed and modified bits in the page table tree. 71 */ 72 73 /* 74 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 75 * instruction and data sides share a unified, 64-entry, semi-associative 76 * TLB which is maintained totally under software control. In addition, the 77 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative 78 * TLB which serves as a first level to the shared TLB. These two TLBs are 79 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions). 80 */ 81 82 /* 83 * The normal case is that PTEs are 32-bits and we have a 1-page 84 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 85 * 86 */ 87 88 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 89 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT) 90 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 91 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 92 93 /* 94 * entries per page directory level: our page-table tree is two-level, so 95 * we don't really have any PMD directory. 96 */ 97 #define PTRS_PER_PTE (1 << PTE_SHIFT) 98 #define PTRS_PER_PMD 1 99 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) 100 101 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 102 #define FIRST_USER_PGD_NR 0 103 104 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) 105 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) 106 107 #define pte_ERROR(e) \ 108 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \ 109 __FILE__, __LINE__, pte_val(e)) 110 #define pgd_ERROR(e) \ 111 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ 112 __FILE__, __LINE__, pgd_val(e)) 113 114 /* 115 * Bits in a linux-style PTE. These match the bits in the 116 * (hardware-defined) PTE as closely as possible. 117 */ 118 119 /* There are several potential gotchas here. The hardware TLBLO 120 * field looks like this: 121 * 122 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 123 * RPN..................... 0 0 EX WR ZSEL....... W I M G 124 * 125 * Where possible we make the Linux PTE bits match up with this 126 * 127 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can 128 * support down to 1k pages), this is done in the TLBMiss exception 129 * handler. 130 * - We use only zones 0 (for kernel pages) and 1 (for user pages) 131 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB 132 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct 133 * zone. 134 * - PRESENT *must* be in the bottom two bits because swap PTEs use the top 135 * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we 136 * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler 137 * before the TLB entry is loaded. 138 * - All other bits of the PTE are loaded into TLBLO without 139 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for 140 * software PTE bits. We actually use bits 21, 24, 25, and 141 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and 142 * PRESENT. 143 */ 144 145 /* Definitions for MicroBlaze. */ 146 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ 147 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ 148 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ 149 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ 150 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ 151 #define _PAGE_RW 0x040 /* software: Writes permitted */ 152 #define _PAGE_DIRTY 0x080 /* software: dirty page */ 153 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ 154 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ 155 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ 156 #define _PMD_PRESENT PAGE_MASK 157 158 /* We borrow bit 24 to store the exclusive marker in swap PTEs. */ 159 #define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY 160 161 /* 162 * Some bits are unused... 163 */ 164 #ifndef _PAGE_HASHPTE 165 #define _PAGE_HASHPTE 0 166 #endif 167 #ifndef _PTE_NONE_MASK 168 #define _PTE_NONE_MASK 0 169 #endif 170 #ifndef _PAGE_SHARED 171 #define _PAGE_SHARED 0 172 #endif 173 #ifndef _PAGE_EXEC 174 #define _PAGE_EXEC 0 175 #endif 176 177 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 178 179 /* 180 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware 181 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need 182 * to have it in the Linux PTE, and in fact the bit could be reused for 183 * another purpose. -- paulus. 184 */ 185 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) 186 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) 187 188 #define _PAGE_KERNEL \ 189 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC) 190 191 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) 192 193 #define PAGE_NONE __pgprot(_PAGE_BASE) 194 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 195 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 196 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 197 #define PAGE_SHARED_X \ 198 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 199 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 200 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 201 202 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 203 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED) 204 #define PAGE_KERNEL_CI __pgprot(_PAGE_IO) 205 206 /* 207 * We consider execute permission the same as read. 208 * Also, write permissions imply read permissions. 209 */ 210 211 #ifndef __ASSEMBLY__ 212 /* 213 * ZERO_PAGE is a global shared page that is always zero: used 214 * for zero-mapped memory areas etc.. 215 */ 216 extern unsigned long empty_zero_page[1024]; 217 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 218 219 #endif /* __ASSEMBLY__ */ 220 221 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) 222 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 223 #define pte_clear(mm, addr, ptep) \ 224 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) 225 226 #define pmd_none(pmd) (!pmd_val(pmd)) 227 #define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0) 228 #define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0) 229 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) 230 231 #define pte_page(x) (mem_map + (unsigned long) \ 232 ((pte_val(x) - memory_start) >> PAGE_SHIFT)) 233 #define PFN_PTE_SHIFT PAGE_SHIFT 234 235 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT) 236 237 #define pfn_pte(pfn, prot) \ 238 __pte(((pte_basic_t)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot)) 239 240 #ifndef __ASSEMBLY__ 241 /* 242 * The following only work if pte_present() is true. 243 * Undefined behaviour if not.. 244 */ 245 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } 246 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } 247 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 248 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 249 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 250 251 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } 252 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } 253 254 static inline pte_t pte_rdprotect(pte_t pte) \ 255 { pte_val(pte) &= ~_PAGE_USER; return pte; } 256 static inline pte_t pte_wrprotect(pte_t pte) \ 257 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } 258 static inline pte_t pte_exprotect(pte_t pte) \ 259 { pte_val(pte) &= ~_PAGE_EXEC; return pte; } 260 static inline pte_t pte_mkclean(pte_t pte) \ 261 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } 262 static inline pte_t pte_mkold(pte_t pte) \ 263 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 264 265 static inline pte_t pte_mkread(pte_t pte) \ 266 { pte_val(pte) |= _PAGE_USER; return pte; } 267 static inline pte_t pte_mkexec(pte_t pte) \ 268 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } 269 static inline pte_t pte_mkwrite_novma(pte_t pte) \ 270 { pte_val(pte) |= _PAGE_RW; return pte; } 271 static inline pte_t pte_mkdirty(pte_t pte) \ 272 { pte_val(pte) |= _PAGE_DIRTY; return pte; } 273 static inline pte_t pte_mkyoung(pte_t pte) \ 274 { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 275 276 /* 277 * Conversion functions: convert a page and protection to a page entry, 278 * and a page entry and page directory to the page they refer to. 279 */ 280 281 static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot) 282 { 283 pte_t pte; 284 pte_val(pte) = physpage | pgprot_val(pgprot); 285 return pte; 286 } 287 288 #define mk_pte(page, pgprot) \ 289 ({ \ 290 pte_t pte; \ 291 pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \ 292 pgprot_val(pgprot); \ 293 pte; \ 294 }) 295 296 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 297 { 298 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); 299 return pte; 300 } 301 302 /* 303 * Atomic PTE updates. 304 * 305 * pte_update clears and sets bit atomically, and returns 306 * the old pte value. 307 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant 308 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits. 309 */ 310 static inline unsigned long pte_update(pte_t *p, unsigned long clr, 311 unsigned long set) 312 { 313 unsigned long flags, old, tmp; 314 315 raw_local_irq_save(flags); 316 317 __asm__ __volatile__( "lw %0, %2, r0 \n" 318 "andn %1, %0, %3 \n" 319 "or %1, %1, %4 \n" 320 "sw %1, %2, r0 \n" 321 : "=&r" (old), "=&r" (tmp) 322 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set) 323 : "cc"); 324 325 raw_local_irq_restore(flags); 326 327 return old; 328 } 329 330 /* 331 * set_pte stores a linux PTE into the linux page table. 332 */ 333 static inline void set_pte(pte_t *ptep, pte_t pte) 334 { 335 *ptep = pte; 336 } 337 338 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 339 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 340 unsigned long address, pte_t *ptep) 341 { 342 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; 343 } 344 345 static inline int ptep_test_and_clear_dirty(struct mm_struct *mm, 346 unsigned long addr, pte_t *ptep) 347 { 348 return (pte_update(ptep, \ 349 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; 350 } 351 352 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 353 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 354 unsigned long addr, pte_t *ptep) 355 { 356 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); 357 } 358 359 /*static inline void ptep_set_wrprotect(struct mm_struct *mm, 360 unsigned long addr, pte_t *ptep) 361 { 362 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); 363 }*/ 364 365 static inline void ptep_mkdirty(struct mm_struct *mm, 366 unsigned long addr, pte_t *ptep) 367 { 368 pte_update(ptep, 0, _PAGE_DIRTY); 369 } 370 371 /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/ 372 373 /* Convert pmd entry to page */ 374 /* our pmd entry is an effective address of pte table*/ 375 /* returns effective address of the pmd entry*/ 376 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 377 { 378 return ((unsigned long) (pmd_val(pmd) & PAGE_MASK)); 379 } 380 381 /* returns pfn of the pmd entry*/ 382 #define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT) 383 384 /* returns struct *page of the pmd entry*/ 385 #define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT)) 386 387 /* Find an entry in the third-level page table.. */ 388 389 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 390 391 /* 392 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 393 * are !pte_none() && !pte_present(). 394 * 395 * 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 396 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 397 * <------------------ offset -------------------> E < type -> 0 0 398 * 399 * E is the exclusive marker that is not stored in swap entries. 400 */ 401 #define __swp_type(entry) ((entry).val & 0x1f) 402 #define __swp_offset(entry) ((entry).val >> 6) 403 #define __swp_entry(type, offset) \ 404 ((swp_entry_t) { ((type) & 0x1f) | ((offset) << 6) }) 405 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 }) 406 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 }) 407 408 static inline int pte_swp_exclusive(pte_t pte) 409 { 410 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 411 } 412 413 static inline pte_t pte_swp_mkexclusive(pte_t pte) 414 { 415 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; 416 return pte; 417 } 418 419 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 420 { 421 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE; 422 return pte; 423 } 424 425 extern unsigned long iopa(unsigned long addr); 426 427 /* Values for nocacheflag and cmode */ 428 /* These are not used by the APUS kernel_map, but prevents 429 * compilation errors. 430 */ 431 #define IOMAP_FULL_CACHING 0 432 #define IOMAP_NOCACHE_SER 1 433 #define IOMAP_NOCACHE_NONSER 2 434 #define IOMAP_NO_COPYBACK 3 435 436 void do_page_fault(struct pt_regs *regs, unsigned long address, 437 unsigned long error_code); 438 439 void mapin_ram(void); 440 int map_page(unsigned long va, phys_addr_t pa, int flags); 441 442 extern int mem_init_done; 443 444 asmlinkage void __init mmu_init(void); 445 446 #endif /* __ASSEMBLY__ */ 447 #endif /* __KERNEL__ */ 448 449 #ifndef __ASSEMBLY__ 450 extern unsigned long ioremap_bot, ioremap_base; 451 452 void setup_memory(void); 453 #endif /* __ASSEMBLY__ */ 454 455 #endif /* _ASM_MICROBLAZE_PGTABLE_H */ 456