1a12cf0a8SGreg Ungerer /****************************************************************************/ 2a12cf0a8SGreg Ungerer 3a12cf0a8SGreg Ungerer /* 4a12cf0a8SGreg Ungerer * m52xxacr.h -- ColdFire version 2 core cache support 5a12cf0a8SGreg Ungerer * 6a12cf0a8SGreg Ungerer * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> 7a12cf0a8SGreg Ungerer */ 8a12cf0a8SGreg Ungerer 9a12cf0a8SGreg Ungerer /****************************************************************************/ 10a12cf0a8SGreg Ungerer #ifndef m52xxacr_h 11a12cf0a8SGreg Ungerer #define m52xxacr_h 12a12cf0a8SGreg Ungerer /****************************************************************************/ 13a12cf0a8SGreg Ungerer 14a12cf0a8SGreg Ungerer /* 15a12cf0a8SGreg Ungerer * All varients of the ColdFire using version 2 cores have a similar 16a12cf0a8SGreg Ungerer * cache setup. Although not absolutely identical the cache register 17a12cf0a8SGreg Ungerer * definitions are compatible for all of them. Mostly they support a 18a12cf0a8SGreg Ungerer * configurable cache memory that can be instruction only, data only, 19a12cf0a8SGreg Ungerer * or split instruction and data. The exception is the very old version 2 20a12cf0a8SGreg Ungerer * core based parts, like the 5206(e), 5249 and 5272, which are instruction 21a12cf0a8SGreg Ungerer * cache only. Cache size varies from 2k up to 16k. 22a12cf0a8SGreg Ungerer */ 23a12cf0a8SGreg Ungerer 24a12cf0a8SGreg Ungerer /* 25a12cf0a8SGreg Ungerer * Define the Cache Control register flags. 26a12cf0a8SGreg Ungerer */ 27a12cf0a8SGreg Ungerer #define CACR_CENB 0x80000000 /* Enable cache */ 28a12cf0a8SGreg Ungerer #define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */ 29a12cf0a8SGreg Ungerer #define CACR_CFRZ 0x08000000 /* Cache freeze mode */ 30a12cf0a8SGreg Ungerer #define CACR_CINV 0x01000000 /* Invalidate cache */ 31a12cf0a8SGreg Ungerer #define CACR_DISI 0x00800000 /* Disable instruction cache */ 32a12cf0a8SGreg Ungerer #define CACR_DISD 0x00400000 /* Disable data cache */ 33a12cf0a8SGreg Ungerer #define CACR_INVI 0x00200000 /* Invalidate instruction cache */ 34a12cf0a8SGreg Ungerer #define CACR_INVD 0x00100000 /* Invalidate data cache */ 35a12cf0a8SGreg Ungerer #define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */ 36a12cf0a8SGreg Ungerer #define CACR_DCM 0x00000200 /* Default cache mode */ 37a12cf0a8SGreg Ungerer #define CACR_DBWE 0x00000100 /* Buffered write enable */ 38a12cf0a8SGreg Ungerer #define CACR_DWP 0x00000020 /* Write protection */ 39a12cf0a8SGreg Ungerer #define CACR_EUSP 0x00000010 /* Enable separate user a7 */ 40a12cf0a8SGreg Ungerer 41a12cf0a8SGreg Ungerer /* 42a12cf0a8SGreg Ungerer * Define the Access Control register flags. 43a12cf0a8SGreg Ungerer */ 44a12cf0a8SGreg Ungerer #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ 45a12cf0a8SGreg Ungerer #define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ 46a12cf0a8SGreg Ungerer #define ACR_ENABLE 0x00008000 /* Enable this ACR */ 47a12cf0a8SGreg Ungerer #define ACR_USER 0x00000000 /* Allow only user accesses */ 48a12cf0a8SGreg Ungerer #define ACR_SUPER 0x00002000 /* Allow supervisor access only */ 49a12cf0a8SGreg Ungerer #define ACR_ANY 0x00004000 /* Allow any access type */ 50a12cf0a8SGreg Ungerer #define ACR_CENB 0x00000000 /* Caching of region enabled */ 51a12cf0a8SGreg Ungerer #define ACR_CDIS 0x00000040 /* Caching of region disabled */ 52a12cf0a8SGreg Ungerer #define ACR_BWE 0x00000020 /* Write buffer enabled */ 53a12cf0a8SGreg Ungerer #define ACR_WPROTECT 0x00000004 /* Write protect region */ 54a12cf0a8SGreg Ungerer 55a12cf0a8SGreg Ungerer /****************************************************************************/ 56a12cf0a8SGreg Ungerer #endif /* m52xxsim_h */ 57