1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU106 4 * 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU106 RevA"; 21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 nvmem0 = &eeprom; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &dcc; 33 }; 34 35 chosen { 36 bootargs = "earlycon"; 37 stdout-path = "serial0:115200n8"; 38 }; 39 40 memory@0 { 41 device_type = "memory"; 42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 autorepeat; 48 sw19 { 49 label = "sw19"; 50 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 51 linux,code = <KEY_DOWN>; 52 wakeup-source; 53 autorepeat; 54 }; 55 }; 56 57 leds { 58 compatible = "gpio-leds"; 59 heartbeat-led { 60 label = "heartbeat"; 61 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 62 linux,default-trigger = "heartbeat"; 63 }; 64 }; 65 66 ina226-u76 { 67 compatible = "iio-hwmon"; 68 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 69 }; 70 ina226-u77 { 71 compatible = "iio-hwmon"; 72 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 73 }; 74 ina226-u78 { 75 compatible = "iio-hwmon"; 76 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 77 }; 78 ina226-u87 { 79 compatible = "iio-hwmon"; 80 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 81 }; 82 ina226-u85 { 83 compatible = "iio-hwmon"; 84 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 85 }; 86 ina226-u86 { 87 compatible = "iio-hwmon"; 88 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 89 }; 90 ina226-u93 { 91 compatible = "iio-hwmon"; 92 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 93 }; 94 ina226-u88 { 95 compatible = "iio-hwmon"; 96 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 97 }; 98 ina226-u15 { 99 compatible = "iio-hwmon"; 100 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 101 }; 102 ina226-u92 { 103 compatible = "iio-hwmon"; 104 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 105 }; 106 ina226-u79 { 107 compatible = "iio-hwmon"; 108 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 109 }; 110 ina226-u81 { 111 compatible = "iio-hwmon"; 112 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 113 }; 114 ina226-u80 { 115 compatible = "iio-hwmon"; 116 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 117 }; 118 ina226-u84 { 119 compatible = "iio-hwmon"; 120 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 121 }; 122 ina226-u16 { 123 compatible = "iio-hwmon"; 124 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 125 }; 126 ina226-u65 { 127 compatible = "iio-hwmon"; 128 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 129 }; 130 ina226-u74 { 131 compatible = "iio-hwmon"; 132 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 133 }; 134 ina226-u75 { 135 compatible = "iio-hwmon"; 136 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 137 }; 138 139 /* 48MHz reference crystal */ 140 ref48: ref48M { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <48000000>; 144 }; 145 146 refhdmi: refhdmi { 147 compatible = "fixed-clock"; 148 #clock-cells = <0>; 149 clock-frequency = <114285000>; 150 }; 151}; 152 153&can1 { 154 status = "okay"; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_can1_default>; 157}; 158 159&dcc { 160 status = "okay"; 161}; 162 163&fpd_dma_chan1 { 164 status = "okay"; 165}; 166 167&fpd_dma_chan2 { 168 status = "okay"; 169}; 170 171&fpd_dma_chan3 { 172 status = "okay"; 173}; 174 175&fpd_dma_chan4 { 176 status = "okay"; 177}; 178 179&fpd_dma_chan5 { 180 status = "okay"; 181}; 182 183&fpd_dma_chan6 { 184 status = "okay"; 185}; 186 187&fpd_dma_chan7 { 188 status = "okay"; 189}; 190 191&fpd_dma_chan8 { 192 status = "okay"; 193}; 194 195&gem3 { 196 status = "okay"; 197 phy-handle = <&phy0>; 198 phy-mode = "rgmii-id"; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_gem3_default>; 201 phy0: ethernet-phy@c { 202 reg = <0xc>; 203 ti,rx-internal-delay = <0x8>; 204 ti,tx-internal-delay = <0xa>; 205 ti,fifo-depth = <0x1>; 206 ti,dp83867-rxctrl-strap-quirk; 207 }; 208}; 209 210&gpio { 211 status = "okay"; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_gpio_default>; 214}; 215 216&i2c0 { 217 status = "okay"; 218 clock-frequency = <400000>; 219 pinctrl-names = "default", "gpio"; 220 pinctrl-0 = <&pinctrl_i2c0_default>; 221 pinctrl-1 = <&pinctrl_i2c0_gpio>; 222 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 223 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 224 225 tca6416_u97: gpio@20 { 226 compatible = "ti,tca6416"; 227 reg = <0x20>; 228 gpio-controller; /* interrupt not connected */ 229 #gpio-cells = <2>; 230 /* 231 * IRQ not connected 232 * Lines: 233 * 0 - SFP_SI5328_INT_ALM 234 * 1 - HDMI_SI5328_INT_ALM 235 * 5 - IIC_MUX_RESET_B 236 * 6 - GEM3_EXP_RESET_B 237 * 10 - FMC_HPC0_PRSNT_M2C_B 238 * 11 - FMC_HPC1_PRSNT_M2C_B 239 * 2-4, 7, 12-17 - not connected 240 */ 241 }; 242 243 tca6416_u61: gpio@21 { 244 compatible = "ti,tca6416"; 245 reg = <0x21>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 /* 249 * IRQ not connected 250 * Lines: 251 * 0 - VCCPSPLL_EN 252 * 1 - MGTRAVCC_EN 253 * 2 - MGTRAVTT_EN 254 * 3 - VCCPSDDRPLL_EN 255 * 4 - MIO26_PMU_INPUT_LS 256 * 5 - PL_PMBUS_ALERT 257 * 6 - PS_PMBUS_ALERT 258 * 7 - MAXIM_PMBUS_ALERT 259 * 10 - PL_DDR4_VTERM_EN 260 * 11 - PL_DDR4_VPP_2V5_EN 261 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON 262 * 13 - PS_DIMM_SUSPEND_EN 263 * 14 - PS_DDR4_VTERM_EN 264 * 15 - PS_DDR4_VPP_2V5_EN 265 * 16 - 17 - not connected 266 */ 267 }; 268 269 i2c-mux@75 { /* u60 */ 270 compatible = "nxp,pca9544"; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 reg = <0x75>; 274 i2c@0 { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 reg = <0>; 278 /* PS_PMBUS */ 279 u76: ina226@40 { /* u76 */ 280 compatible = "ti,ina226"; 281 #io-channel-cells = <1>; 282 label = "ina226-u76"; 283 reg = <0x40>; 284 shunt-resistor = <5000>; 285 }; 286 u77: ina226@41 { /* u77 */ 287 compatible = "ti,ina226"; 288 #io-channel-cells = <1>; 289 label = "ina226-u77"; 290 reg = <0x41>; 291 shunt-resistor = <5000>; 292 }; 293 u78: ina226@42 { /* u78 */ 294 compatible = "ti,ina226"; 295 #io-channel-cells = <1>; 296 label = "ina226-u78"; 297 reg = <0x42>; 298 shunt-resistor = <5000>; 299 }; 300 u87: ina226@43 { /* u87 */ 301 compatible = "ti,ina226"; 302 #io-channel-cells = <1>; 303 label = "ina226-u87"; 304 reg = <0x43>; 305 shunt-resistor = <5000>; 306 }; 307 u85: ina226@44 { /* u85 */ 308 compatible = "ti,ina226"; 309 #io-channel-cells = <1>; 310 label = "ina226-u85"; 311 reg = <0x44>; 312 shunt-resistor = <5000>; 313 }; 314 u86: ina226@45 { /* u86 */ 315 compatible = "ti,ina226"; 316 #io-channel-cells = <1>; 317 label = "ina226-u86"; 318 reg = <0x45>; 319 shunt-resistor = <5000>; 320 }; 321 u93: ina226@46 { /* u93 */ 322 compatible = "ti,ina226"; 323 #io-channel-cells = <1>; 324 label = "ina226-u93"; 325 reg = <0x46>; 326 shunt-resistor = <5000>; 327 }; 328 u88: ina226@47 { /* u88 */ 329 compatible = "ti,ina226"; 330 #io-channel-cells = <1>; 331 label = "ina226-u88"; 332 reg = <0x47>; 333 shunt-resistor = <5000>; 334 }; 335 u15: ina226@4a { /* u15 */ 336 compatible = "ti,ina226"; 337 #io-channel-cells = <1>; 338 label = "ina226-u15"; 339 reg = <0x4a>; 340 shunt-resistor = <5000>; 341 }; 342 u92: ina226@4b { /* u92 */ 343 compatible = "ti,ina226"; 344 #io-channel-cells = <1>; 345 label = "ina226-u92"; 346 reg = <0x4b>; 347 shunt-resistor = <5000>; 348 }; 349 }; 350 i2c@1 { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 reg = <1>; 354 /* PL_PMBUS */ 355 u79: ina226@40 { /* u79 */ 356 compatible = "ti,ina226"; 357 #io-channel-cells = <1>; 358 label = "ina226-u79"; 359 reg = <0x40>; 360 shunt-resistor = <2000>; 361 }; 362 u81: ina226@41 { /* u81 */ 363 compatible = "ti,ina226"; 364 #io-channel-cells = <1>; 365 label = "ina226-u81"; 366 reg = <0x41>; 367 shunt-resistor = <5000>; 368 }; 369 u80: ina226@42 { /* u80 */ 370 compatible = "ti,ina226"; 371 #io-channel-cells = <1>; 372 label = "ina226-u80"; 373 reg = <0x42>; 374 shunt-resistor = <5000>; 375 }; 376 u84: ina226@43 { /* u84 */ 377 compatible = "ti,ina226"; 378 #io-channel-cells = <1>; 379 label = "ina226-u84"; 380 reg = <0x43>; 381 shunt-resistor = <5000>; 382 }; 383 u16: ina226@44 { /* u16 */ 384 compatible = "ti,ina226"; 385 #io-channel-cells = <1>; 386 label = "ina226-u16"; 387 reg = <0x44>; 388 shunt-resistor = <5000>; 389 }; 390 u65: ina226@45 { /* u65 */ 391 compatible = "ti,ina226"; 392 #io-channel-cells = <1>; 393 label = "ina226-u65"; 394 reg = <0x45>; 395 shunt-resistor = <5000>; 396 }; 397 u74: ina226@46 { /* u74 */ 398 compatible = "ti,ina226"; 399 #io-channel-cells = <1>; 400 label = "ina226-u74"; 401 reg = <0x46>; 402 shunt-resistor = <5000>; 403 }; 404 u75: ina226@47 { /* u75 */ 405 compatible = "ti,ina226"; 406 #io-channel-cells = <1>; 407 label = "ina226-u75"; 408 reg = <0x47>; 409 shunt-resistor = <5000>; 410 }; 411 }; 412 i2c@2 { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <2>; 416 /* MAXIM_PMBUS - 00 */ 417 max15301@a { /* u46 */ 418 compatible = "maxim,max15301"; 419 reg = <0xa>; 420 }; 421 max15303@b { /* u4 */ 422 compatible = "maxim,max15303"; 423 reg = <0xb>; 424 }; 425 max15303@10 { /* u13 */ 426 compatible = "maxim,max15303"; 427 reg = <0x10>; 428 }; 429 max15301@13 { /* u47 */ 430 compatible = "maxim,max15301"; 431 reg = <0x13>; 432 }; 433 max15303@14 { /* u7 */ 434 compatible = "maxim,max15303"; 435 reg = <0x14>; 436 }; 437 max15303@15 { /* u6 */ 438 compatible = "maxim,max15303"; 439 reg = <0x15>; 440 }; 441 max15303@16 { /* u10 */ 442 compatible = "maxim,max15303"; 443 reg = <0x16>; 444 }; 445 max15303@17 { /* u9 */ 446 compatible = "maxim,max15303"; 447 reg = <0x17>; 448 }; 449 max15301@18 { /* u63 */ 450 compatible = "maxim,max15301"; 451 reg = <0x18>; 452 }; 453 max15303@1a { /* u49 */ 454 compatible = "maxim,max15303"; 455 reg = <0x1a>; 456 }; 457 max15303@1b { /* u8 */ 458 compatible = "maxim,max15303"; 459 reg = <0x1b>; 460 }; 461 max15303@1d { /* u18 */ 462 compatible = "maxim,max15303"; 463 reg = <0x1d>; 464 }; 465 466 max20751@72 { /* u95 */ 467 compatible = "maxim,max20751"; 468 reg = <0x72>; 469 }; 470 max20751@73 { /* u96 */ 471 compatible = "maxim,max20751"; 472 reg = <0x73>; 473 }; 474 }; 475 /* Bus 3 is not connected */ 476 }; 477}; 478 479&i2c1 { 480 status = "okay"; 481 clock-frequency = <400000>; 482 pinctrl-names = "default", "gpio"; 483 pinctrl-0 = <&pinctrl_i2c1_default>; 484 pinctrl-1 = <&pinctrl_i2c1_gpio>; 485 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 486 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 487 488 /* PL i2c via PCA9306 - u45 */ 489 i2c-mux@74 { /* u34 */ 490 compatible = "nxp,pca9548"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <0x74>; 494 i2c@0 { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 reg = <0>; 498 /* 499 * IIC_EEPROM 1kB memory which uses 256B blocks 500 * where every block has different address. 501 * 0 - 256B address 0x54 502 * 256B - 512B address 0x55 503 * 512B - 768B address 0x56 504 * 768B - 1024B address 0x57 505 */ 506 eeprom: eeprom@54 { /* u23 */ 507 compatible = "atmel,24c08"; 508 reg = <0x54>; 509 }; 510 }; 511 i2c@1 { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 reg = <1>; 515 si5341: clock-generator@36 { /* SI5341 - u69 */ 516 compatible = "silabs,si5341"; 517 reg = <0x36>; 518 #clock-cells = <2>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 clocks = <&ref48>; 522 clock-names = "xtal"; 523 clock-output-names = "si5341"; 524 525 si5341_0: out@0 { 526 /* refclk0 for PS-GT, used for DP */ 527 reg = <0>; 528 always-on; 529 }; 530 si5341_2: out@2 { 531 /* refclk2 for PS-GT, used for USB3 */ 532 reg = <2>; 533 always-on; 534 }; 535 si5341_3: out@3 { 536 /* refclk3 for PS-GT, used for SATA */ 537 reg = <3>; 538 always-on; 539 }; 540 si5341_6: out@6 { 541 /* refclk6 PL CLK125 */ 542 reg = <6>; 543 always-on; 544 }; 545 si5341_7: out@7 { 546 /* refclk7 PL CLK74 */ 547 reg = <7>; 548 always-on; 549 }; 550 si5341_9: out@9 { 551 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 552 reg = <9>; 553 always-on; 554 }; 555 }; 556 557 }; 558 i2c@2 { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 reg = <2>; 562 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 563 #clock-cells = <0>; 564 compatible = "silabs,si570"; 565 reg = <0x5d>; 566 temperature-stability = <50>; 567 factory-fout = <300000000>; 568 clock-frequency = <300000000>; 569 clock-output-names = "si570_user"; 570 }; 571 }; 572 i2c@3 { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 reg = <3>; 576 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 577 #clock-cells = <0>; 578 compatible = "silabs,si570"; 579 reg = <0x5d>; 580 temperature-stability = <50>; /* copy from zc702 */ 581 factory-fout = <156250000>; 582 clock-frequency = <148500000>; 583 clock-output-names = "si570_mgt"; 584 }; 585 }; 586 i2c@4 { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 reg = <4>; 590 /* SI5328 - u20 */ 591 }; 592 i2c@5 { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 reg = <5>; /* FAN controller */ 596 temp@4c {/* lm96163 - u128 */ 597 compatible = "national,lm96163"; 598 reg = <0x4c>; 599 }; 600 }; 601 /* 6 - 7 unconnected */ 602 }; 603 604 i2c-mux@75 { 605 compatible = "nxp,pca9548"; /* u135 */ 606 #address-cells = <1>; 607 #size-cells = <0>; 608 reg = <0x75>; 609 610 i2c@0 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 reg = <0>; 614 /* HPC0_IIC */ 615 }; 616 i2c@1 { 617 #address-cells = <1>; 618 #size-cells = <0>; 619 reg = <1>; 620 /* HPC1_IIC */ 621 }; 622 i2c@2 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 reg = <2>; 626 /* SYSMON */ 627 }; 628 i2c@3 { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 reg = <3>; 632 /* DDR4 SODIMM */ 633 }; 634 i2c@4 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 reg = <4>; 638 /* SEP 3 */ 639 }; 640 i2c@5 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 reg = <5>; 644 /* SEP 2 */ 645 }; 646 i2c@6 { 647 #address-cells = <1>; 648 #size-cells = <0>; 649 reg = <6>; 650 /* SEP 1 */ 651 }; 652 i2c@7 { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 reg = <7>; 656 /* SEP 0 */ 657 }; 658 }; 659}; 660 661&pinctrl0 { 662 status = "okay"; 663 pinctrl_i2c0_default: i2c0-default { 664 mux { 665 groups = "i2c0_3_grp"; 666 function = "i2c0"; 667 }; 668 669 conf { 670 groups = "i2c0_3_grp"; 671 bias-pull-up; 672 slew-rate = <SLEW_RATE_SLOW>; 673 power-source = <IO_STANDARD_LVCMOS18>; 674 }; 675 }; 676 677 pinctrl_i2c0_gpio: i2c0-gpio { 678 mux { 679 groups = "gpio0_14_grp", "gpio0_15_grp"; 680 function = "gpio0"; 681 }; 682 683 conf { 684 groups = "gpio0_14_grp", "gpio0_15_grp"; 685 slew-rate = <SLEW_RATE_SLOW>; 686 power-source = <IO_STANDARD_LVCMOS18>; 687 }; 688 }; 689 690 pinctrl_i2c1_default: i2c1-default { 691 mux { 692 groups = "i2c1_4_grp"; 693 function = "i2c1"; 694 }; 695 696 conf { 697 groups = "i2c1_4_grp"; 698 bias-pull-up; 699 slew-rate = <SLEW_RATE_SLOW>; 700 power-source = <IO_STANDARD_LVCMOS18>; 701 }; 702 }; 703 704 pinctrl_i2c1_gpio: i2c1-gpio { 705 mux { 706 groups = "gpio0_16_grp", "gpio0_17_grp"; 707 function = "gpio0"; 708 }; 709 710 conf { 711 groups = "gpio0_16_grp", "gpio0_17_grp"; 712 slew-rate = <SLEW_RATE_SLOW>; 713 power-source = <IO_STANDARD_LVCMOS18>; 714 }; 715 }; 716 717 pinctrl_uart0_default: uart0-default { 718 mux { 719 groups = "uart0_4_grp"; 720 function = "uart0"; 721 }; 722 723 conf { 724 groups = "uart0_4_grp"; 725 slew-rate = <SLEW_RATE_SLOW>; 726 power-source = <IO_STANDARD_LVCMOS18>; 727 }; 728 729 conf-rx { 730 pins = "MIO18"; 731 bias-high-impedance; 732 }; 733 734 conf-tx { 735 pins = "MIO19"; 736 bias-disable; 737 }; 738 }; 739 740 pinctrl_uart1_default: uart1-default { 741 mux { 742 groups = "uart1_5_grp"; 743 function = "uart1"; 744 }; 745 746 conf { 747 groups = "uart1_5_grp"; 748 slew-rate = <SLEW_RATE_SLOW>; 749 power-source = <IO_STANDARD_LVCMOS18>; 750 }; 751 752 conf-rx { 753 pins = "MIO21"; 754 bias-high-impedance; 755 }; 756 757 conf-tx { 758 pins = "MIO20"; 759 bias-disable; 760 }; 761 }; 762 763 pinctrl_usb0_default: usb0-default { 764 mux { 765 groups = "usb0_0_grp"; 766 function = "usb0"; 767 }; 768 769 conf { 770 groups = "usb0_0_grp"; 771 slew-rate = <SLEW_RATE_SLOW>; 772 power-source = <IO_STANDARD_LVCMOS18>; 773 }; 774 775 conf-rx { 776 pins = "MIO52", "MIO53", "MIO55"; 777 bias-high-impedance; 778 }; 779 780 conf-tx { 781 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 782 "MIO60", "MIO61", "MIO62", "MIO63"; 783 bias-disable; 784 }; 785 }; 786 787 pinctrl_gem3_default: gem3-default { 788 mux { 789 function = "ethernet3"; 790 groups = "ethernet3_0_grp"; 791 }; 792 793 conf { 794 groups = "ethernet3_0_grp"; 795 slew-rate = <SLEW_RATE_SLOW>; 796 power-source = <IO_STANDARD_LVCMOS18>; 797 }; 798 799 conf-rx { 800 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 801 "MIO75"; 802 bias-high-impedance; 803 low-power-disable; 804 }; 805 806 conf-tx { 807 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 808 "MIO69"; 809 bias-disable; 810 low-power-enable; 811 }; 812 813 mux-mdio { 814 function = "mdio3"; 815 groups = "mdio3_0_grp"; 816 }; 817 818 conf-mdio { 819 groups = "mdio3_0_grp"; 820 slew-rate = <SLEW_RATE_SLOW>; 821 power-source = <IO_STANDARD_LVCMOS18>; 822 bias-disable; 823 }; 824 }; 825 826 pinctrl_can1_default: can1-default { 827 mux { 828 function = "can1"; 829 groups = "can1_6_grp"; 830 }; 831 832 conf { 833 groups = "can1_6_grp"; 834 slew-rate = <SLEW_RATE_SLOW>; 835 power-source = <IO_STANDARD_LVCMOS18>; 836 }; 837 838 conf-rx { 839 pins = "MIO25"; 840 bias-high-impedance; 841 }; 842 843 conf-tx { 844 pins = "MIO24"; 845 bias-disable; 846 }; 847 }; 848 849 pinctrl_sdhci1_default: sdhci1-default { 850 mux { 851 groups = "sdio1_0_grp"; 852 function = "sdio1"; 853 }; 854 855 conf { 856 groups = "sdio1_0_grp"; 857 slew-rate = <SLEW_RATE_SLOW>; 858 power-source = <IO_STANDARD_LVCMOS18>; 859 bias-disable; 860 }; 861 862 mux-cd { 863 groups = "sdio1_cd_0_grp"; 864 function = "sdio1_cd"; 865 }; 866 867 conf-cd { 868 groups = "sdio1_cd_0_grp"; 869 bias-high-impedance; 870 bias-pull-up; 871 slew-rate = <SLEW_RATE_SLOW>; 872 power-source = <IO_STANDARD_LVCMOS18>; 873 }; 874 875 mux-wp { 876 groups = "sdio1_wp_0_grp"; 877 function = "sdio1_wp"; 878 }; 879 880 conf-wp { 881 groups = "sdio1_wp_0_grp"; 882 bias-high-impedance; 883 bias-pull-up; 884 slew-rate = <SLEW_RATE_SLOW>; 885 power-source = <IO_STANDARD_LVCMOS18>; 886 }; 887 }; 888 889 pinctrl_gpio_default: gpio-default { 890 mux { 891 function = "gpio0"; 892 groups = "gpio0_22_grp", "gpio0_23_grp"; 893 }; 894 895 conf { 896 groups = "gpio0_22_grp", "gpio0_23_grp"; 897 slew-rate = <SLEW_RATE_SLOW>; 898 power-source = <IO_STANDARD_LVCMOS18>; 899 }; 900 901 mux-msp { 902 function = "gpio0"; 903 groups = "gpio0_13_grp", "gpio0_38_grp"; 904 }; 905 906 conf-msp { 907 groups = "gpio0_13_grp", "gpio0_38_grp"; 908 slew-rate = <SLEW_RATE_SLOW>; 909 power-source = <IO_STANDARD_LVCMOS18>; 910 }; 911 912 conf-pull-up { 913 pins = "MIO22"; 914 bias-pull-up; 915 }; 916 917 conf-pull-none { 918 pins = "MIO13", "MIO23", "MIO38"; 919 bias-disable; 920 }; 921 }; 922}; 923 924&psgtr { 925 status = "okay"; 926 /* nc, sata, usb3, dp */ 927 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 928 clock-names = "ref1", "ref2", "ref3"; 929}; 930 931&rtc { 932 status = "okay"; 933}; 934 935&sata { 936 status = "okay"; 937 /* SATA OOB timing settings */ 938 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 939 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 940 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 941 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 942 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 943 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 944 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 945 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 946 phy-names = "sata-phy"; 947 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 948}; 949 950/* SD1 with level shifter */ 951&sdhci1 { 952 status = "okay"; 953 /* 954 * This property should be removed for supporting UHS mode 955 */ 956 no-1-8-v; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&pinctrl_sdhci1_default>; 959 xlnx,mio-bank = <1>; 960}; 961 962&uart0 { 963 status = "okay"; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&pinctrl_uart0_default>; 966}; 967 968&uart1 { 969 status = "okay"; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&pinctrl_uart1_default>; 972}; 973 974/* ULPI SMSC USB3320 */ 975&usb0 { 976 status = "okay"; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&pinctrl_usb0_default>; 979 dr_mode = "host"; 980 phy-names = "usb3-phy"; 981 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 982 maximum-speed = "super-speed"; 983}; 984 985&watchdog0 { 986 status = "okay"; 987}; 988 989&zynqmp_dpdma { 990 status = "okay"; 991}; 992 993&zynqmp_dpsub { 994 status = "okay"; 995 phy-names = "dp-phy0", "dp-phy1"; 996 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 997 <&psgtr 0 PHY_TYPE_DP 1 3>; 998}; 999