1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16
17/ {
18	model = "ZynqMP ZCU106 RevA";
19	compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem3;
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		mmc0 = &sdhci1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		serial1 = &uart1;
29		serial2 = &dcc;
30	};
31
32	chosen {
33		bootargs = "earlycon";
34		stdout-path = "serial0:115200n8";
35	};
36
37	memory@0 {
38		device_type = "memory";
39		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44		autorepeat;
45		sw19 {
46			label = "sw19";
47			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
48			linux,code = <KEY_DOWN>;
49			wakeup-source;
50			autorepeat;
51		};
52	};
53
54	leds {
55		compatible = "gpio-leds";
56		heartbeat-led {
57			label = "heartbeat";
58			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
59			linux,default-trigger = "heartbeat";
60		};
61	};
62
63	ina226-u76 {
64		compatible = "iio-hwmon";
65		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
66	};
67	ina226-u77 {
68		compatible = "iio-hwmon";
69		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
70	};
71	ina226-u78 {
72		compatible = "iio-hwmon";
73		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
74	};
75	ina226-u87 {
76		compatible = "iio-hwmon";
77		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
78	};
79	ina226-u85 {
80		compatible = "iio-hwmon";
81		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
82	};
83	ina226-u86 {
84		compatible = "iio-hwmon";
85		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
86	};
87	ina226-u93 {
88		compatible = "iio-hwmon";
89		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
90	};
91	ina226-u88 {
92		compatible = "iio-hwmon";
93		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
94	};
95	ina226-u15 {
96		compatible = "iio-hwmon";
97		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
98	};
99	ina226-u92 {
100		compatible = "iio-hwmon";
101		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
102	};
103	ina226-u79 {
104		compatible = "iio-hwmon";
105		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
106	};
107	ina226-u81 {
108		compatible = "iio-hwmon";
109		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
110	};
111	ina226-u80 {
112		compatible = "iio-hwmon";
113		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
114	};
115	ina226-u84 {
116		compatible = "iio-hwmon";
117		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
118	};
119	ina226-u16 {
120		compatible = "iio-hwmon";
121		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
122	};
123	ina226-u65 {
124		compatible = "iio-hwmon";
125		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
126	};
127	ina226-u74 {
128		compatible = "iio-hwmon";
129		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
130	};
131	ina226-u75 {
132		compatible = "iio-hwmon";
133		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
134	};
135};
136
137&can1 {
138	status = "okay";
139};
140
141&dcc {
142	status = "okay";
143};
144
145/* fpd_dma clk 667MHz, lpd_dma 500MHz */
146&fpd_dma_chan1 {
147	status = "okay";
148};
149
150&fpd_dma_chan2 {
151	status = "okay";
152};
153
154&fpd_dma_chan3 {
155	status = "okay";
156};
157
158&fpd_dma_chan4 {
159	status = "okay";
160};
161
162&fpd_dma_chan5 {
163	status = "okay";
164};
165
166&fpd_dma_chan6 {
167	status = "okay";
168};
169
170&fpd_dma_chan7 {
171	status = "okay";
172};
173
174&fpd_dma_chan8 {
175	status = "okay";
176};
177
178&gem3 {
179	status = "okay";
180	phy-handle = <&phy0>;
181	phy-mode = "rgmii-id";
182	phy0: ethernet-phy@c {
183		reg = <0xc>;
184		ti,rx-internal-delay = <0x8>;
185		ti,tx-internal-delay = <0xa>;
186		ti,fifo-depth = <0x1>;
187		ti,dp83867-rxctrl-strap-quirk;
188	};
189};
190
191&gpio {
192	status = "okay";
193};
194
195&i2c0 {
196	status = "okay";
197	clock-frequency = <400000>;
198
199	tca6416_u97: gpio@20 {
200		compatible = "ti,tca6416";
201		reg = <0x20>;
202		gpio-controller; /* interrupt not connected */
203		#gpio-cells = <2>;
204		/*
205		 * IRQ not connected
206		 * Lines:
207		 * 0 - SFP_SI5328_INT_ALM
208		 * 1 - HDMI_SI5328_INT_ALM
209		 * 5 - IIC_MUX_RESET_B
210		 * 6 - GEM3_EXP_RESET_B
211		 * 10 - FMC_HPC0_PRSNT_M2C_B
212		 * 11 - FMC_HPC1_PRSNT_M2C_B
213		 * 2-4, 7, 12-17 - not connected
214		 */
215	};
216
217	tca6416_u61: gpio@21 {
218		compatible = "ti,tca6416";
219		reg = <0x21>;
220		gpio-controller;
221		#gpio-cells = <2>;
222		/*
223		 * IRQ not connected
224		 * Lines:
225		 * 0 - VCCPSPLL_EN
226		 * 1 - MGTRAVCC_EN
227		 * 2 - MGTRAVTT_EN
228		 * 3 - VCCPSDDRPLL_EN
229		 * 4 - MIO26_PMU_INPUT_LS
230		 * 5 - PL_PMBUS_ALERT
231		 * 6 - PS_PMBUS_ALERT
232		 * 7 - MAXIM_PMBUS_ALERT
233		 * 10 - PL_DDR4_VTERM_EN
234		 * 11 - PL_DDR4_VPP_2V5_EN
235		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
236		 * 13 - PS_DIMM_SUSPEND_EN
237		 * 14 - PS_DDR4_VTERM_EN
238		 * 15 - PS_DDR4_VPP_2V5_EN
239		 * 16 - 17 - not connected
240		 */
241	};
242
243	i2c-mux@75 { /* u60 */
244		compatible = "nxp,pca9544";
245		#address-cells = <1>;
246		#size-cells = <0>;
247		reg = <0x75>;
248		i2c@0 {
249			#address-cells = <1>;
250			#size-cells = <0>;
251			reg = <0>;
252			/* PS_PMBUS */
253			u76: ina226@40 { /* u76 */
254				compatible = "ti,ina226";
255				#io-channel-cells = <1>;
256				label = "ina226-u76";
257				reg = <0x40>;
258				shunt-resistor = <5000>;
259			};
260			u77: ina226@41 { /* u77 */
261				compatible = "ti,ina226";
262				#io-channel-cells = <1>;
263				label = "ina226-u77";
264				reg = <0x41>;
265				shunt-resistor = <5000>;
266			};
267			u78: ina226@42 { /* u78 */
268				compatible = "ti,ina226";
269				#io-channel-cells = <1>;
270				label = "ina226-u78";
271				reg = <0x42>;
272				shunt-resistor = <5000>;
273			};
274			u87: ina226@43 { /* u87 */
275				compatible = "ti,ina226";
276				#io-channel-cells = <1>;
277				label = "ina226-u87";
278				reg = <0x43>;
279				shunt-resistor = <5000>;
280			};
281			u85: ina226@44 { /* u85 */
282				compatible = "ti,ina226";
283				#io-channel-cells = <1>;
284				label = "ina226-u85";
285				reg = <0x44>;
286				shunt-resistor = <5000>;
287			};
288			u86: ina226@45 { /* u86 */
289				compatible = "ti,ina226";
290				#io-channel-cells = <1>;
291				label = "ina226-u86";
292				reg = <0x45>;
293				shunt-resistor = <5000>;
294			};
295			u93: ina226@46 { /* u93 */
296				compatible = "ti,ina226";
297				#io-channel-cells = <1>;
298				label = "ina226-u93";
299				reg = <0x46>;
300				shunt-resistor = <5000>;
301			};
302			u88: ina226@47 { /* u88 */
303				compatible = "ti,ina226";
304				#io-channel-cells = <1>;
305				label = "ina226-u88";
306				reg = <0x47>;
307				shunt-resistor = <5000>;
308			};
309			u15: ina226@4a { /* u15 */
310				compatible = "ti,ina226";
311				#io-channel-cells = <1>;
312				label = "ina226-u15";
313				reg = <0x4a>;
314				shunt-resistor = <5000>;
315			};
316			u92: ina226@4b { /* u92 */
317				compatible = "ti,ina226";
318				#io-channel-cells = <1>;
319				label = "ina226-u92";
320				reg = <0x4b>;
321				shunt-resistor = <5000>;
322			};
323		};
324		i2c@1 {
325			#address-cells = <1>;
326			#size-cells = <0>;
327			reg = <1>;
328			/* PL_PMBUS */
329			u79: ina226@40 { /* u79 */
330				compatible = "ti,ina226";
331				#io-channel-cells = <1>;
332				label = "ina226-u79";
333				reg = <0x40>;
334				shunt-resistor = <2000>;
335			};
336			u81: ina226@41 { /* u81 */
337				compatible = "ti,ina226";
338				#io-channel-cells = <1>;
339				label = "ina226-u81";
340				reg = <0x41>;
341				shunt-resistor = <5000>;
342			};
343			u80: ina226@42 { /* u80 */
344				compatible = "ti,ina226";
345				#io-channel-cells = <1>;
346				label = "ina226-u80";
347				reg = <0x42>;
348				shunt-resistor = <5000>;
349			};
350			u84: ina226@43 { /* u84 */
351				compatible = "ti,ina226";
352				#io-channel-cells = <1>;
353				label = "ina226-u84";
354				reg = <0x43>;
355				shunt-resistor = <5000>;
356			};
357			u16: ina226@44 { /* u16 */
358				compatible = "ti,ina226";
359				#io-channel-cells = <1>;
360				label = "ina226-u16";
361				reg = <0x44>;
362				shunt-resistor = <5000>;
363			};
364			u65: ina226@45 { /* u65 */
365				compatible = "ti,ina226";
366				#io-channel-cells = <1>;
367				label = "ina226-u65";
368				reg = <0x45>;
369				shunt-resistor = <5000>;
370			};
371			u74: ina226@46 { /* u74 */
372				compatible = "ti,ina226";
373				#io-channel-cells = <1>;
374				label = "ina226-u74";
375				reg = <0x46>;
376				shunt-resistor = <5000>;
377			};
378			u75: ina226@47 { /* u75 */
379				compatible = "ti,ina226";
380				#io-channel-cells = <1>;
381				label = "ina226-u75";
382				reg = <0x47>;
383				shunt-resistor = <5000>;
384			};
385		};
386		i2c@2 {
387			#address-cells = <1>;
388			#size-cells = <0>;
389			reg = <2>;
390			/* MAXIM_PMBUS - 00 */
391			max15301@a { /* u46 */
392				compatible = "maxim,max15301";
393				reg = <0xa>;
394			};
395			max15303@b { /* u4 */
396				compatible = "maxim,max15303";
397				reg = <0xb>;
398			};
399			max15303@10 { /* u13 */
400				compatible = "maxim,max15303";
401				reg = <0x10>;
402			};
403			max15301@13 { /* u47 */
404				compatible = "maxim,max15301";
405				reg = <0x13>;
406			};
407			max15303@14 { /* u7 */
408				compatible = "maxim,max15303";
409				reg = <0x14>;
410			};
411			max15303@15 { /* u6 */
412				compatible = "maxim,max15303";
413				reg = <0x15>;
414			};
415			max15303@16 { /* u10 */
416				compatible = "maxim,max15303";
417				reg = <0x16>;
418			};
419			max15303@17 { /* u9 */
420				compatible = "maxim,max15303";
421				reg = <0x17>;
422			};
423			max15301@18 { /* u63 */
424				compatible = "maxim,max15301";
425				reg = <0x18>;
426			};
427			max15303@1a { /* u49 */
428				compatible = "maxim,max15303";
429				reg = <0x1a>;
430			};
431			max15303@1b { /* u8 */
432				compatible = "maxim,max15303";
433				reg = <0x1b>;
434			};
435			max15303@1d { /* u18 */
436				compatible = "maxim,max15303";
437				reg = <0x1d>;
438			};
439
440			max20751@72 { /* u95 */
441				compatible = "maxim,max20751";
442				reg = <0x72>;
443			};
444			max20751@73 { /* u96 */
445				compatible = "maxim,max20751";
446				reg = <0x73>;
447			};
448		};
449		/* Bus 3 is not connected */
450	};
451};
452
453&i2c1 {
454	status = "okay";
455	clock-frequency = <400000>;
456
457	/* PL i2c via PCA9306 - u45 */
458	i2c-mux@74 { /* u34 */
459		compatible = "nxp,pca9548";
460		#address-cells = <1>;
461		#size-cells = <0>;
462		reg = <0x74>;
463		i2c@0 {
464			#address-cells = <1>;
465			#size-cells = <0>;
466			reg = <0>;
467			/*
468			 * IIC_EEPROM 1kB memory which uses 256B blocks
469			 * where every block has different address.
470			 *    0 - 256B address 0x54
471			 * 256B - 512B address 0x55
472			 * 512B - 768B address 0x56
473			 * 768B - 1024B address 0x57
474			 */
475			eeprom: eeprom@54 { /* u23 */
476				compatible = "atmel,24c08";
477				reg = <0x54>;
478			};
479		};
480		i2c@1 {
481			#address-cells = <1>;
482			#size-cells = <0>;
483			reg = <1>;
484			si5341: clock-generator@36 { /* SI5341 - u69 */
485				reg = <0x36>;
486			};
487
488		};
489		i2c@2 {
490			#address-cells = <1>;
491			#size-cells = <0>;
492			reg = <2>;
493			si570_1: clock-generator@5d { /* USER SI570 - u42 */
494				#clock-cells = <0>;
495				compatible = "silabs,si570";
496				reg = <0x5d>;
497				temperature-stability = <50>;
498				factory-fout = <300000000>;
499				clock-frequency = <300000000>;
500				clock-output-names = "si570_user";
501			};
502		};
503		i2c@3 {
504			#address-cells = <1>;
505			#size-cells = <0>;
506			reg = <3>;
507			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
508				#clock-cells = <0>;
509				compatible = "silabs,si570";
510				reg = <0x5d>;
511				temperature-stability = <50>; /* copy from zc702 */
512				factory-fout = <156250000>;
513				clock-frequency = <148500000>;
514				clock-output-names = "si570_mgt";
515			};
516		};
517		i2c@4 {
518			#address-cells = <1>;
519			#size-cells = <0>;
520			reg = <4>;
521			si5328: clock-generator@69 {/* SI5328 - u20 */
522				reg = <0x69>;
523			};
524		};
525		i2c@5 {
526			#address-cells = <1>;
527			#size-cells = <0>;
528			reg = <5>; /* FAN controller */
529			temp@4c {/* lm96163 - u128 */
530				compatible = "national,lm96163";
531				reg = <0x4c>;
532			};
533		};
534		/* 6 - 7 unconnected */
535	};
536
537	i2c-mux@75 {
538		compatible = "nxp,pca9548"; /* u135 */
539		#address-cells = <1>;
540		#size-cells = <0>;
541		reg = <0x75>;
542
543		i2c@0 {
544			#address-cells = <1>;
545			#size-cells = <0>;
546			reg = <0>;
547			/* HPC0_IIC */
548		};
549		i2c@1 {
550			#address-cells = <1>;
551			#size-cells = <0>;
552			reg = <1>;
553			/* HPC1_IIC */
554		};
555		i2c@2 {
556			#address-cells = <1>;
557			#size-cells = <0>;
558			reg = <2>;
559			/* SYSMON */
560		};
561		i2c@3 {
562			#address-cells = <1>;
563			#size-cells = <0>;
564			reg = <3>;
565			/* DDR4 SODIMM */
566		};
567		i2c@4 {
568			#address-cells = <1>;
569			#size-cells = <0>;
570			reg = <4>;
571			/* SEP 3 */
572		};
573		i2c@5 {
574			#address-cells = <1>;
575			#size-cells = <0>;
576			reg = <5>;
577			/* SEP 2 */
578		};
579		i2c@6 {
580			#address-cells = <1>;
581			#size-cells = <0>;
582			reg = <6>;
583			/* SEP 1 */
584		};
585		i2c@7 {
586			#address-cells = <1>;
587			#size-cells = <0>;
588			reg = <7>;
589			/* SEP 0 */
590		};
591	};
592};
593
594&rtc {
595	status = "okay";
596};
597
598&sata {
599	status = "okay";
600	/* SATA OOB timing settings */
601	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
602	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
603	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
604	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
605	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
606	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
607	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
608	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
609};
610
611/* SD1 with level shifter */
612&sdhci1 {
613	status = "okay";
614	no-1-8-v;
615};
616
617&uart0 {
618	status = "okay";
619};
620
621&uart1 {
622	status = "okay";
623};
624
625/* ULPI SMSC USB3320 */
626&usb0 {
627	status = "okay";
628	dr_mode = "host";
629};
630
631&watchdog0 {
632	status = "okay";
633};
634