1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU106 4 * 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU106 RevA"; 21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 rtc0 = &rtc; 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &dcc; 32 }; 33 34 chosen { 35 bootargs = "earlycon"; 36 stdout-path = "serial0:115200n8"; 37 }; 38 39 memory@0 { 40 device_type = "memory"; 41 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 42 }; 43 44 gpio-keys { 45 compatible = "gpio-keys"; 46 autorepeat; 47 sw19 { 48 label = "sw19"; 49 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 50 linux,code = <KEY_DOWN>; 51 wakeup-source; 52 autorepeat; 53 }; 54 }; 55 56 leds { 57 compatible = "gpio-leds"; 58 heartbeat-led { 59 label = "heartbeat"; 60 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 61 linux,default-trigger = "heartbeat"; 62 }; 63 }; 64 65 ina226-u76 { 66 compatible = "iio-hwmon"; 67 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 68 }; 69 ina226-u77 { 70 compatible = "iio-hwmon"; 71 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 72 }; 73 ina226-u78 { 74 compatible = "iio-hwmon"; 75 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 76 }; 77 ina226-u87 { 78 compatible = "iio-hwmon"; 79 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 80 }; 81 ina226-u85 { 82 compatible = "iio-hwmon"; 83 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 84 }; 85 ina226-u86 { 86 compatible = "iio-hwmon"; 87 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 88 }; 89 ina226-u93 { 90 compatible = "iio-hwmon"; 91 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 92 }; 93 ina226-u88 { 94 compatible = "iio-hwmon"; 95 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 96 }; 97 ina226-u15 { 98 compatible = "iio-hwmon"; 99 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 100 }; 101 ina226-u92 { 102 compatible = "iio-hwmon"; 103 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 104 }; 105 ina226-u79 { 106 compatible = "iio-hwmon"; 107 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 108 }; 109 ina226-u81 { 110 compatible = "iio-hwmon"; 111 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 112 }; 113 ina226-u80 { 114 compatible = "iio-hwmon"; 115 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 116 }; 117 ina226-u84 { 118 compatible = "iio-hwmon"; 119 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 120 }; 121 ina226-u16 { 122 compatible = "iio-hwmon"; 123 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 124 }; 125 ina226-u65 { 126 compatible = "iio-hwmon"; 127 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 128 }; 129 ina226-u74 { 130 compatible = "iio-hwmon"; 131 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 132 }; 133 ina226-u75 { 134 compatible = "iio-hwmon"; 135 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 136 }; 137 138 /* 48MHz reference crystal */ 139 ref48: ref48M { 140 compatible = "fixed-clock"; 141 #clock-cells = <0>; 142 clock-frequency = <48000000>; 143 }; 144 145 refhdmi: refhdmi { 146 compatible = "fixed-clock"; 147 #clock-cells = <0>; 148 clock-frequency = <114285000>; 149 }; 150}; 151 152&can1 { 153 status = "okay"; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_can1_default>; 156}; 157 158&dcc { 159 status = "okay"; 160}; 161 162&zynqmp_dpdma { 163 status = "okay"; 164}; 165 166&zynqmp_dpsub { 167 status = "okay"; 168 phy-names = "dp-phy0", "dp-phy1"; 169 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 170 <&psgtr 0 PHY_TYPE_DP 1 3>; 171}; 172 173/* fpd_dma clk 667MHz, lpd_dma 500MHz */ 174&fpd_dma_chan1 { 175 status = "okay"; 176}; 177 178&fpd_dma_chan2 { 179 status = "okay"; 180}; 181 182&fpd_dma_chan3 { 183 status = "okay"; 184}; 185 186&fpd_dma_chan4 { 187 status = "okay"; 188}; 189 190&fpd_dma_chan5 { 191 status = "okay"; 192}; 193 194&fpd_dma_chan6 { 195 status = "okay"; 196}; 197 198&fpd_dma_chan7 { 199 status = "okay"; 200}; 201 202&fpd_dma_chan8 { 203 status = "okay"; 204}; 205 206&gem3 { 207 status = "okay"; 208 phy-handle = <&phy0>; 209 phy-mode = "rgmii-id"; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_gem3_default>; 212 phy0: ethernet-phy@c { 213 reg = <0xc>; 214 ti,rx-internal-delay = <0x8>; 215 ti,tx-internal-delay = <0xa>; 216 ti,fifo-depth = <0x1>; 217 ti,dp83867-rxctrl-strap-quirk; 218 }; 219}; 220 221&gpio { 222 status = "okay"; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_gpio_default>; 225}; 226 227&i2c0 { 228 status = "okay"; 229 clock-frequency = <400000>; 230 pinctrl-names = "default", "gpio"; 231 pinctrl-0 = <&pinctrl_i2c0_default>; 232 pinctrl-1 = <&pinctrl_i2c0_gpio>; 233 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 234 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 235 236 tca6416_u97: gpio@20 { 237 compatible = "ti,tca6416"; 238 reg = <0x20>; 239 gpio-controller; /* interrupt not connected */ 240 #gpio-cells = <2>; 241 /* 242 * IRQ not connected 243 * Lines: 244 * 0 - SFP_SI5328_INT_ALM 245 * 1 - HDMI_SI5328_INT_ALM 246 * 5 - IIC_MUX_RESET_B 247 * 6 - GEM3_EXP_RESET_B 248 * 10 - FMC_HPC0_PRSNT_M2C_B 249 * 11 - FMC_HPC1_PRSNT_M2C_B 250 * 2-4, 7, 12-17 - not connected 251 */ 252 }; 253 254 tca6416_u61: gpio@21 { 255 compatible = "ti,tca6416"; 256 reg = <0x21>; 257 gpio-controller; 258 #gpio-cells = <2>; 259 /* 260 * IRQ not connected 261 * Lines: 262 * 0 - VCCPSPLL_EN 263 * 1 - MGTRAVCC_EN 264 * 2 - MGTRAVTT_EN 265 * 3 - VCCPSDDRPLL_EN 266 * 4 - MIO26_PMU_INPUT_LS 267 * 5 - PL_PMBUS_ALERT 268 * 6 - PS_PMBUS_ALERT 269 * 7 - MAXIM_PMBUS_ALERT 270 * 10 - PL_DDR4_VTERM_EN 271 * 11 - PL_DDR4_VPP_2V5_EN 272 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON 273 * 13 - PS_DIMM_SUSPEND_EN 274 * 14 - PS_DDR4_VTERM_EN 275 * 15 - PS_DDR4_VPP_2V5_EN 276 * 16 - 17 - not connected 277 */ 278 }; 279 280 i2c-mux@75 { /* u60 */ 281 compatible = "nxp,pca9544"; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 reg = <0x75>; 285 i2c@0 { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 reg = <0>; 289 /* PS_PMBUS */ 290 u76: ina226@40 { /* u76 */ 291 compatible = "ti,ina226"; 292 #io-channel-cells = <1>; 293 label = "ina226-u76"; 294 reg = <0x40>; 295 shunt-resistor = <5000>; 296 }; 297 u77: ina226@41 { /* u77 */ 298 compatible = "ti,ina226"; 299 #io-channel-cells = <1>; 300 label = "ina226-u77"; 301 reg = <0x41>; 302 shunt-resistor = <5000>; 303 }; 304 u78: ina226@42 { /* u78 */ 305 compatible = "ti,ina226"; 306 #io-channel-cells = <1>; 307 label = "ina226-u78"; 308 reg = <0x42>; 309 shunt-resistor = <5000>; 310 }; 311 u87: ina226@43 { /* u87 */ 312 compatible = "ti,ina226"; 313 #io-channel-cells = <1>; 314 label = "ina226-u87"; 315 reg = <0x43>; 316 shunt-resistor = <5000>; 317 }; 318 u85: ina226@44 { /* u85 */ 319 compatible = "ti,ina226"; 320 #io-channel-cells = <1>; 321 label = "ina226-u85"; 322 reg = <0x44>; 323 shunt-resistor = <5000>; 324 }; 325 u86: ina226@45 { /* u86 */ 326 compatible = "ti,ina226"; 327 #io-channel-cells = <1>; 328 label = "ina226-u86"; 329 reg = <0x45>; 330 shunt-resistor = <5000>; 331 }; 332 u93: ina226@46 { /* u93 */ 333 compatible = "ti,ina226"; 334 #io-channel-cells = <1>; 335 label = "ina226-u93"; 336 reg = <0x46>; 337 shunt-resistor = <5000>; 338 }; 339 u88: ina226@47 { /* u88 */ 340 compatible = "ti,ina226"; 341 #io-channel-cells = <1>; 342 label = "ina226-u88"; 343 reg = <0x47>; 344 shunt-resistor = <5000>; 345 }; 346 u15: ina226@4a { /* u15 */ 347 compatible = "ti,ina226"; 348 #io-channel-cells = <1>; 349 label = "ina226-u15"; 350 reg = <0x4a>; 351 shunt-resistor = <5000>; 352 }; 353 u92: ina226@4b { /* u92 */ 354 compatible = "ti,ina226"; 355 #io-channel-cells = <1>; 356 label = "ina226-u92"; 357 reg = <0x4b>; 358 shunt-resistor = <5000>; 359 }; 360 }; 361 i2c@1 { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 reg = <1>; 365 /* PL_PMBUS */ 366 u79: ina226@40 { /* u79 */ 367 compatible = "ti,ina226"; 368 #io-channel-cells = <1>; 369 label = "ina226-u79"; 370 reg = <0x40>; 371 shunt-resistor = <2000>; 372 }; 373 u81: ina226@41 { /* u81 */ 374 compatible = "ti,ina226"; 375 #io-channel-cells = <1>; 376 label = "ina226-u81"; 377 reg = <0x41>; 378 shunt-resistor = <5000>; 379 }; 380 u80: ina226@42 { /* u80 */ 381 compatible = "ti,ina226"; 382 #io-channel-cells = <1>; 383 label = "ina226-u80"; 384 reg = <0x42>; 385 shunt-resistor = <5000>; 386 }; 387 u84: ina226@43 { /* u84 */ 388 compatible = "ti,ina226"; 389 #io-channel-cells = <1>; 390 label = "ina226-u84"; 391 reg = <0x43>; 392 shunt-resistor = <5000>; 393 }; 394 u16: ina226@44 { /* u16 */ 395 compatible = "ti,ina226"; 396 #io-channel-cells = <1>; 397 label = "ina226-u16"; 398 reg = <0x44>; 399 shunt-resistor = <5000>; 400 }; 401 u65: ina226@45 { /* u65 */ 402 compatible = "ti,ina226"; 403 #io-channel-cells = <1>; 404 label = "ina226-u65"; 405 reg = <0x45>; 406 shunt-resistor = <5000>; 407 }; 408 u74: ina226@46 { /* u74 */ 409 compatible = "ti,ina226"; 410 #io-channel-cells = <1>; 411 label = "ina226-u74"; 412 reg = <0x46>; 413 shunt-resistor = <5000>; 414 }; 415 u75: ina226@47 { /* u75 */ 416 compatible = "ti,ina226"; 417 #io-channel-cells = <1>; 418 label = "ina226-u75"; 419 reg = <0x47>; 420 shunt-resistor = <5000>; 421 }; 422 }; 423 i2c@2 { 424 #address-cells = <1>; 425 #size-cells = <0>; 426 reg = <2>; 427 /* MAXIM_PMBUS - 00 */ 428 max15301@a { /* u46 */ 429 compatible = "maxim,max15301"; 430 reg = <0xa>; 431 }; 432 max15303@b { /* u4 */ 433 compatible = "maxim,max15303"; 434 reg = <0xb>; 435 }; 436 max15303@10 { /* u13 */ 437 compatible = "maxim,max15303"; 438 reg = <0x10>; 439 }; 440 max15301@13 { /* u47 */ 441 compatible = "maxim,max15301"; 442 reg = <0x13>; 443 }; 444 max15303@14 { /* u7 */ 445 compatible = "maxim,max15303"; 446 reg = <0x14>; 447 }; 448 max15303@15 { /* u6 */ 449 compatible = "maxim,max15303"; 450 reg = <0x15>; 451 }; 452 max15303@16 { /* u10 */ 453 compatible = "maxim,max15303"; 454 reg = <0x16>; 455 }; 456 max15303@17 { /* u9 */ 457 compatible = "maxim,max15303"; 458 reg = <0x17>; 459 }; 460 max15301@18 { /* u63 */ 461 compatible = "maxim,max15301"; 462 reg = <0x18>; 463 }; 464 max15303@1a { /* u49 */ 465 compatible = "maxim,max15303"; 466 reg = <0x1a>; 467 }; 468 max15303@1b { /* u8 */ 469 compatible = "maxim,max15303"; 470 reg = <0x1b>; 471 }; 472 max15303@1d { /* u18 */ 473 compatible = "maxim,max15303"; 474 reg = <0x1d>; 475 }; 476 477 max20751@72 { /* u95 */ 478 compatible = "maxim,max20751"; 479 reg = <0x72>; 480 }; 481 max20751@73 { /* u96 */ 482 compatible = "maxim,max20751"; 483 reg = <0x73>; 484 }; 485 }; 486 /* Bus 3 is not connected */ 487 }; 488}; 489 490&i2c1 { 491 status = "okay"; 492 clock-frequency = <400000>; 493 pinctrl-names = "default", "gpio"; 494 pinctrl-0 = <&pinctrl_i2c1_default>; 495 pinctrl-1 = <&pinctrl_i2c1_gpio>; 496 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 497 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 498 499 /* PL i2c via PCA9306 - u45 */ 500 i2c-mux@74 { /* u34 */ 501 compatible = "nxp,pca9548"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 reg = <0x74>; 505 i2c@0 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <0>; 509 /* 510 * IIC_EEPROM 1kB memory which uses 256B blocks 511 * where every block has different address. 512 * 0 - 256B address 0x54 513 * 256B - 512B address 0x55 514 * 512B - 768B address 0x56 515 * 768B - 1024B address 0x57 516 */ 517 eeprom: eeprom@54 { /* u23 */ 518 compatible = "atmel,24c08"; 519 reg = <0x54>; 520 }; 521 }; 522 i2c@1 { 523 #address-cells = <1>; 524 #size-cells = <0>; 525 reg = <1>; 526 si5341: clock-generator@36 { /* SI5341 - u69 */ 527 compatible = "silabs,si5341"; 528 reg = <0x36>; 529 #clock-cells = <2>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 clocks = <&ref48>; 533 clock-names = "xtal"; 534 clock-output-names = "si5341"; 535 536 si5341_0: out@0 { 537 /* refclk0 for PS-GT, used for DP */ 538 reg = <0>; 539 always-on; 540 }; 541 si5341_2: out@2 { 542 /* refclk2 for PS-GT, used for USB3 */ 543 reg = <2>; 544 always-on; 545 }; 546 si5341_3: out@3 { 547 /* refclk3 for PS-GT, used for SATA */ 548 reg = <3>; 549 always-on; 550 }; 551 si5341_6: out@6 { 552 /* refclk6 PL CLK125 */ 553 reg = <6>; 554 always-on; 555 }; 556 si5341_7: out@7 { 557 /* refclk7 PL CLK74 */ 558 reg = <7>; 559 always-on; 560 }; 561 si5341_9: out@9 { 562 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 563 reg = <9>; 564 always-on; 565 }; 566 }; 567 568 }; 569 i2c@2 { 570 #address-cells = <1>; 571 #size-cells = <0>; 572 reg = <2>; 573 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 574 #clock-cells = <0>; 575 compatible = "silabs,si570"; 576 reg = <0x5d>; 577 temperature-stability = <50>; 578 factory-fout = <300000000>; 579 clock-frequency = <300000000>; 580 clock-output-names = "si570_user"; 581 }; 582 }; 583 i2c@3 { 584 #address-cells = <1>; 585 #size-cells = <0>; 586 reg = <3>; 587 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 588 #clock-cells = <0>; 589 compatible = "silabs,si570"; 590 reg = <0x5d>; 591 temperature-stability = <50>; /* copy from zc702 */ 592 factory-fout = <156250000>; 593 clock-frequency = <148500000>; 594 clock-output-names = "si570_mgt"; 595 }; 596 }; 597 i2c@4 { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 reg = <4>; 601 /* SI5328 - u20 */ 602 }; 603 i2c@5 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 reg = <5>; /* FAN controller */ 607 temp@4c {/* lm96163 - u128 */ 608 compatible = "national,lm96163"; 609 reg = <0x4c>; 610 }; 611 }; 612 /* 6 - 7 unconnected */ 613 }; 614 615 i2c-mux@75 { 616 compatible = "nxp,pca9548"; /* u135 */ 617 #address-cells = <1>; 618 #size-cells = <0>; 619 reg = <0x75>; 620 621 i2c@0 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 reg = <0>; 625 /* HPC0_IIC */ 626 }; 627 i2c@1 { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 reg = <1>; 631 /* HPC1_IIC */ 632 }; 633 i2c@2 { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 reg = <2>; 637 /* SYSMON */ 638 }; 639 i2c@3 { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 reg = <3>; 643 /* DDR4 SODIMM */ 644 }; 645 i2c@4 { 646 #address-cells = <1>; 647 #size-cells = <0>; 648 reg = <4>; 649 /* SEP 3 */ 650 }; 651 i2c@5 { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 reg = <5>; 655 /* SEP 2 */ 656 }; 657 i2c@6 { 658 #address-cells = <1>; 659 #size-cells = <0>; 660 reg = <6>; 661 /* SEP 1 */ 662 }; 663 i2c@7 { 664 #address-cells = <1>; 665 #size-cells = <0>; 666 reg = <7>; 667 /* SEP 0 */ 668 }; 669 }; 670}; 671 672&pinctrl0 { 673 status = "okay"; 674 pinctrl_i2c0_default: i2c0-default { 675 mux { 676 groups = "i2c0_3_grp"; 677 function = "i2c0"; 678 }; 679 680 conf { 681 groups = "i2c0_3_grp"; 682 bias-pull-up; 683 slew-rate = <SLEW_RATE_SLOW>; 684 power-source = <IO_STANDARD_LVCMOS18>; 685 }; 686 }; 687 688 pinctrl_i2c0_gpio: i2c0-gpio { 689 mux { 690 groups = "gpio0_14_grp", "gpio0_15_grp"; 691 function = "gpio0"; 692 }; 693 694 conf { 695 groups = "gpio0_14_grp", "gpio0_15_grp"; 696 slew-rate = <SLEW_RATE_SLOW>; 697 power-source = <IO_STANDARD_LVCMOS18>; 698 }; 699 }; 700 701 pinctrl_i2c1_default: i2c1-default { 702 mux { 703 groups = "i2c1_4_grp"; 704 function = "i2c1"; 705 }; 706 707 conf { 708 groups = "i2c1_4_grp"; 709 bias-pull-up; 710 slew-rate = <SLEW_RATE_SLOW>; 711 power-source = <IO_STANDARD_LVCMOS18>; 712 }; 713 }; 714 715 pinctrl_i2c1_gpio: i2c1-gpio { 716 mux { 717 groups = "gpio0_16_grp", "gpio0_17_grp"; 718 function = "gpio0"; 719 }; 720 721 conf { 722 groups = "gpio0_16_grp", "gpio0_17_grp"; 723 slew-rate = <SLEW_RATE_SLOW>; 724 power-source = <IO_STANDARD_LVCMOS18>; 725 }; 726 }; 727 728 pinctrl_uart0_default: uart0-default { 729 mux { 730 groups = "uart0_4_grp"; 731 function = "uart0"; 732 }; 733 734 conf { 735 groups = "uart0_4_grp"; 736 slew-rate = <SLEW_RATE_SLOW>; 737 power-source = <IO_STANDARD_LVCMOS18>; 738 }; 739 740 conf-rx { 741 pins = "MIO18"; 742 bias-high-impedance; 743 }; 744 745 conf-tx { 746 pins = "MIO19"; 747 bias-disable; 748 }; 749 }; 750 751 pinctrl_uart1_default: uart1-default { 752 mux { 753 groups = "uart1_5_grp"; 754 function = "uart1"; 755 }; 756 757 conf { 758 groups = "uart1_5_grp"; 759 slew-rate = <SLEW_RATE_SLOW>; 760 power-source = <IO_STANDARD_LVCMOS18>; 761 }; 762 763 conf-rx { 764 pins = "MIO21"; 765 bias-high-impedance; 766 }; 767 768 conf-tx { 769 pins = "MIO20"; 770 bias-disable; 771 }; 772 }; 773 774 pinctrl_usb0_default: usb0-default { 775 mux { 776 groups = "usb0_0_grp"; 777 function = "usb0"; 778 }; 779 780 conf { 781 groups = "usb0_0_grp"; 782 slew-rate = <SLEW_RATE_SLOW>; 783 power-source = <IO_STANDARD_LVCMOS18>; 784 }; 785 786 conf-rx { 787 pins = "MIO52", "MIO53", "MIO55"; 788 bias-high-impedance; 789 }; 790 791 conf-tx { 792 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 793 "MIO60", "MIO61", "MIO62", "MIO63"; 794 bias-disable; 795 }; 796 }; 797 798 pinctrl_gem3_default: gem3-default { 799 mux { 800 function = "ethernet3"; 801 groups = "ethernet3_0_grp"; 802 }; 803 804 conf { 805 groups = "ethernet3_0_grp"; 806 slew-rate = <SLEW_RATE_SLOW>; 807 power-source = <IO_STANDARD_LVCMOS18>; 808 }; 809 810 conf-rx { 811 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 812 "MIO75"; 813 bias-high-impedance; 814 low-power-disable; 815 }; 816 817 conf-tx { 818 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 819 "MIO69"; 820 bias-disable; 821 low-power-enable; 822 }; 823 824 mux-mdio { 825 function = "mdio3"; 826 groups = "mdio3_0_grp"; 827 }; 828 829 conf-mdio { 830 groups = "mdio3_0_grp"; 831 slew-rate = <SLEW_RATE_SLOW>; 832 power-source = <IO_STANDARD_LVCMOS18>; 833 bias-disable; 834 }; 835 }; 836 837 pinctrl_can1_default: can1-default { 838 mux { 839 function = "can1"; 840 groups = "can1_6_grp"; 841 }; 842 843 conf { 844 groups = "can1_6_grp"; 845 slew-rate = <SLEW_RATE_SLOW>; 846 power-source = <IO_STANDARD_LVCMOS18>; 847 }; 848 849 conf-rx { 850 pins = "MIO25"; 851 bias-high-impedance; 852 }; 853 854 conf-tx { 855 pins = "MIO24"; 856 bias-disable; 857 }; 858 }; 859 860 pinctrl_sdhci1_default: sdhci1-default { 861 mux { 862 groups = "sdio1_0_grp"; 863 function = "sdio1"; 864 }; 865 866 conf { 867 groups = "sdio1_0_grp"; 868 slew-rate = <SLEW_RATE_SLOW>; 869 power-source = <IO_STANDARD_LVCMOS18>; 870 bias-disable; 871 }; 872 873 mux-cd { 874 groups = "sdio1_cd_0_grp"; 875 function = "sdio1_cd"; 876 }; 877 878 conf-cd { 879 groups = "sdio1_cd_0_grp"; 880 bias-high-impedance; 881 bias-pull-up; 882 slew-rate = <SLEW_RATE_SLOW>; 883 power-source = <IO_STANDARD_LVCMOS18>; 884 }; 885 886 mux-wp { 887 groups = "sdio1_wp_0_grp"; 888 function = "sdio1_wp"; 889 }; 890 891 conf-wp { 892 groups = "sdio1_wp_0_grp"; 893 bias-high-impedance; 894 bias-pull-up; 895 slew-rate = <SLEW_RATE_SLOW>; 896 power-source = <IO_STANDARD_LVCMOS18>; 897 }; 898 }; 899 900 pinctrl_gpio_default: gpio-default { 901 mux { 902 function = "gpio0"; 903 groups = "gpio0_22_grp", "gpio0_23_grp"; 904 }; 905 906 conf { 907 groups = "gpio0_22_grp", "gpio0_23_grp"; 908 slew-rate = <SLEW_RATE_SLOW>; 909 power-source = <IO_STANDARD_LVCMOS18>; 910 }; 911 912 mux-msp { 913 function = "gpio0"; 914 groups = "gpio0_13_grp", "gpio0_38_grp"; 915 }; 916 917 conf-msp { 918 groups = "gpio0_13_grp", "gpio0_38_grp"; 919 slew-rate = <SLEW_RATE_SLOW>; 920 power-source = <IO_STANDARD_LVCMOS18>; 921 }; 922 923 conf-pull-up { 924 pins = "MIO22"; 925 bias-pull-up; 926 }; 927 928 conf-pull-none { 929 pins = "MIO13", "MIO23", "MIO38"; 930 bias-disable; 931 }; 932 }; 933}; 934 935&psgtr { 936 status = "okay"; 937 /* nc, sata, usb3, dp */ 938 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 939 clock-names = "ref1", "ref2", "ref3"; 940}; 941 942&rtc { 943 status = "okay"; 944}; 945 946&sata { 947 status = "okay"; 948 /* SATA OOB timing settings */ 949 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 950 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 951 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 952 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 953 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 954 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 955 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 956 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 957 phy-names = "sata-phy"; 958 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 959}; 960 961/* SD1 with level shifter */ 962&sdhci1 { 963 status = "okay"; 964 no-1-8-v; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&pinctrl_sdhci1_default>; 967 xlnx,mio-bank = <1>; 968}; 969 970&uart0 { 971 status = "okay"; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&pinctrl_uart0_default>; 974}; 975 976&uart1 { 977 status = "okay"; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&pinctrl_uart1_default>; 980}; 981 982/* ULPI SMSC USB3320 */ 983&usb0 { 984 status = "okay"; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&pinctrl_usb0_default>; 987 dr_mode = "host"; 988 phy-names = "usb3-phy"; 989 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 990 maximum-speed = "super-speed"; 991}; 992 993&watchdog0 { 994 status = "okay"; 995}; 996