1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU106 4 * 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU106 RevA"; 21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 nvmem0 = &eeprom; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &dcc; 33 spi0 = &qspi; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 }; 40 41 memory@0 { 42 device_type = "memory"; 43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 44 }; 45 46 gpio-keys { 47 compatible = "gpio-keys"; 48 autorepeat; 49 sw19 { 50 label = "sw19"; 51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 52 linux,code = <KEY_DOWN>; 53 wakeup-source; 54 autorepeat; 55 }; 56 }; 57 58 leds { 59 compatible = "gpio-leds"; 60 heartbeat-led { 61 label = "heartbeat"; 62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 63 linux,default-trigger = "heartbeat"; 64 }; 65 }; 66 67 ina226-u76 { 68 compatible = "iio-hwmon"; 69 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 70 }; 71 ina226-u77 { 72 compatible = "iio-hwmon"; 73 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 74 }; 75 ina226-u78 { 76 compatible = "iio-hwmon"; 77 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 78 }; 79 ina226-u87 { 80 compatible = "iio-hwmon"; 81 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 82 }; 83 ina226-u85 { 84 compatible = "iio-hwmon"; 85 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 86 }; 87 ina226-u86 { 88 compatible = "iio-hwmon"; 89 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 90 }; 91 ina226-u93 { 92 compatible = "iio-hwmon"; 93 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 94 }; 95 ina226-u88 { 96 compatible = "iio-hwmon"; 97 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 98 }; 99 ina226-u15 { 100 compatible = "iio-hwmon"; 101 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 102 }; 103 ina226-u92 { 104 compatible = "iio-hwmon"; 105 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 106 }; 107 ina226-u79 { 108 compatible = "iio-hwmon"; 109 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 110 }; 111 ina226-u81 { 112 compatible = "iio-hwmon"; 113 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 114 }; 115 ina226-u80 { 116 compatible = "iio-hwmon"; 117 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 118 }; 119 ina226-u84 { 120 compatible = "iio-hwmon"; 121 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 122 }; 123 ina226-u16 { 124 compatible = "iio-hwmon"; 125 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 126 }; 127 ina226-u65 { 128 compatible = "iio-hwmon"; 129 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 130 }; 131 ina226-u74 { 132 compatible = "iio-hwmon"; 133 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 134 }; 135 ina226-u75 { 136 compatible = "iio-hwmon"; 137 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 138 }; 139 140 /* 48MHz reference crystal */ 141 ref48: ref48M { 142 compatible = "fixed-clock"; 143 #clock-cells = <0>; 144 clock-frequency = <48000000>; 145 }; 146 147 refhdmi: refhdmi { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <114285000>; 151 }; 152}; 153 154&can1 { 155 status = "okay"; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_can1_default>; 158}; 159 160&dcc { 161 status = "okay"; 162}; 163 164&fpd_dma_chan1 { 165 status = "okay"; 166}; 167 168&fpd_dma_chan2 { 169 status = "okay"; 170}; 171 172&fpd_dma_chan3 { 173 status = "okay"; 174}; 175 176&fpd_dma_chan4 { 177 status = "okay"; 178}; 179 180&fpd_dma_chan5 { 181 status = "okay"; 182}; 183 184&fpd_dma_chan6 { 185 status = "okay"; 186}; 187 188&fpd_dma_chan7 { 189 status = "okay"; 190}; 191 192&fpd_dma_chan8 { 193 status = "okay"; 194}; 195 196&gem3 { 197 status = "okay"; 198 phy-handle = <&phy0>; 199 phy-mode = "rgmii-id"; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_gem3_default>; 202 phy0: ethernet-phy@c { 203 reg = <0xc>; 204 ti,rx-internal-delay = <0x8>; 205 ti,tx-internal-delay = <0xa>; 206 ti,fifo-depth = <0x1>; 207 ti,dp83867-rxctrl-strap-quirk; 208 }; 209}; 210 211&gpio { 212 status = "okay"; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_gpio_default>; 215}; 216 217&i2c0 { 218 status = "okay"; 219 clock-frequency = <400000>; 220 pinctrl-names = "default", "gpio"; 221 pinctrl-0 = <&pinctrl_i2c0_default>; 222 pinctrl-1 = <&pinctrl_i2c0_gpio>; 223 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 224 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 225 226 tca6416_u97: gpio@20 { 227 compatible = "ti,tca6416"; 228 reg = <0x20>; 229 gpio-controller; /* interrupt not connected */ 230 #gpio-cells = <2>; 231 /* 232 * IRQ not connected 233 * Lines: 234 * 0 - SFP_SI5328_INT_ALM 235 * 1 - HDMI_SI5328_INT_ALM 236 * 5 - IIC_MUX_RESET_B 237 * 6 - GEM3_EXP_RESET_B 238 * 10 - FMC_HPC0_PRSNT_M2C_B 239 * 11 - FMC_HPC1_PRSNT_M2C_B 240 * 2-4, 7, 12-17 - not connected 241 */ 242 }; 243 244 tca6416_u61: gpio@21 { 245 compatible = "ti,tca6416"; 246 reg = <0x21>; 247 gpio-controller; 248 #gpio-cells = <2>; 249 /* 250 * IRQ not connected 251 * Lines: 252 * 0 - VCCPSPLL_EN 253 * 1 - MGTRAVCC_EN 254 * 2 - MGTRAVTT_EN 255 * 3 - VCCPSDDRPLL_EN 256 * 4 - MIO26_PMU_INPUT_LS 257 * 5 - PL_PMBUS_ALERT 258 * 6 - PS_PMBUS_ALERT 259 * 7 - MAXIM_PMBUS_ALERT 260 * 10 - PL_DDR4_VTERM_EN 261 * 11 - PL_DDR4_VPP_2V5_EN 262 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON 263 * 13 - PS_DIMM_SUSPEND_EN 264 * 14 - PS_DDR4_VTERM_EN 265 * 15 - PS_DDR4_VPP_2V5_EN 266 * 16 - 17 - not connected 267 */ 268 }; 269 270 i2c-mux@75 { /* u60 */ 271 compatible = "nxp,pca9544"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 reg = <0x75>; 275 i2c@0 { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <0>; 279 /* PS_PMBUS */ 280 u76: ina226@40 { /* u76 */ 281 compatible = "ti,ina226"; 282 #io-channel-cells = <1>; 283 label = "ina226-u76"; 284 reg = <0x40>; 285 shunt-resistor = <5000>; 286 }; 287 u77: ina226@41 { /* u77 */ 288 compatible = "ti,ina226"; 289 #io-channel-cells = <1>; 290 label = "ina226-u77"; 291 reg = <0x41>; 292 shunt-resistor = <5000>; 293 }; 294 u78: ina226@42 { /* u78 */ 295 compatible = "ti,ina226"; 296 #io-channel-cells = <1>; 297 label = "ina226-u78"; 298 reg = <0x42>; 299 shunt-resistor = <5000>; 300 }; 301 u87: ina226@43 { /* u87 */ 302 compatible = "ti,ina226"; 303 #io-channel-cells = <1>; 304 label = "ina226-u87"; 305 reg = <0x43>; 306 shunt-resistor = <5000>; 307 }; 308 u85: ina226@44 { /* u85 */ 309 compatible = "ti,ina226"; 310 #io-channel-cells = <1>; 311 label = "ina226-u85"; 312 reg = <0x44>; 313 shunt-resistor = <5000>; 314 }; 315 u86: ina226@45 { /* u86 */ 316 compatible = "ti,ina226"; 317 #io-channel-cells = <1>; 318 label = "ina226-u86"; 319 reg = <0x45>; 320 shunt-resistor = <5000>; 321 }; 322 u93: ina226@46 { /* u93 */ 323 compatible = "ti,ina226"; 324 #io-channel-cells = <1>; 325 label = "ina226-u93"; 326 reg = <0x46>; 327 shunt-resistor = <5000>; 328 }; 329 u88: ina226@47 { /* u88 */ 330 compatible = "ti,ina226"; 331 #io-channel-cells = <1>; 332 label = "ina226-u88"; 333 reg = <0x47>; 334 shunt-resistor = <5000>; 335 }; 336 u15: ina226@4a { /* u15 */ 337 compatible = "ti,ina226"; 338 #io-channel-cells = <1>; 339 label = "ina226-u15"; 340 reg = <0x4a>; 341 shunt-resistor = <5000>; 342 }; 343 u92: ina226@4b { /* u92 */ 344 compatible = "ti,ina226"; 345 #io-channel-cells = <1>; 346 label = "ina226-u92"; 347 reg = <0x4b>; 348 shunt-resistor = <5000>; 349 }; 350 }; 351 i2c@1 { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 reg = <1>; 355 /* PL_PMBUS */ 356 u79: ina226@40 { /* u79 */ 357 compatible = "ti,ina226"; 358 #io-channel-cells = <1>; 359 label = "ina226-u79"; 360 reg = <0x40>; 361 shunt-resistor = <2000>; 362 }; 363 u81: ina226@41 { /* u81 */ 364 compatible = "ti,ina226"; 365 #io-channel-cells = <1>; 366 label = "ina226-u81"; 367 reg = <0x41>; 368 shunt-resistor = <5000>; 369 }; 370 u80: ina226@42 { /* u80 */ 371 compatible = "ti,ina226"; 372 #io-channel-cells = <1>; 373 label = "ina226-u80"; 374 reg = <0x42>; 375 shunt-resistor = <5000>; 376 }; 377 u84: ina226@43 { /* u84 */ 378 compatible = "ti,ina226"; 379 #io-channel-cells = <1>; 380 label = "ina226-u84"; 381 reg = <0x43>; 382 shunt-resistor = <5000>; 383 }; 384 u16: ina226@44 { /* u16 */ 385 compatible = "ti,ina226"; 386 #io-channel-cells = <1>; 387 label = "ina226-u16"; 388 reg = <0x44>; 389 shunt-resistor = <5000>; 390 }; 391 u65: ina226@45 { /* u65 */ 392 compatible = "ti,ina226"; 393 #io-channel-cells = <1>; 394 label = "ina226-u65"; 395 reg = <0x45>; 396 shunt-resistor = <5000>; 397 }; 398 u74: ina226@46 { /* u74 */ 399 compatible = "ti,ina226"; 400 #io-channel-cells = <1>; 401 label = "ina226-u74"; 402 reg = <0x46>; 403 shunt-resistor = <5000>; 404 }; 405 u75: ina226@47 { /* u75 */ 406 compatible = "ti,ina226"; 407 #io-channel-cells = <1>; 408 label = "ina226-u75"; 409 reg = <0x47>; 410 shunt-resistor = <5000>; 411 }; 412 }; 413 i2c@2 { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 reg = <2>; 417 /* MAXIM_PMBUS - 00 */ 418 max15301@a { /* u46 */ 419 compatible = "maxim,max15301"; 420 reg = <0xa>; 421 }; 422 max15303@b { /* u4 */ 423 compatible = "maxim,max15303"; 424 reg = <0xb>; 425 }; 426 max15303@10 { /* u13 */ 427 compatible = "maxim,max15303"; 428 reg = <0x10>; 429 }; 430 max15301@13 { /* u47 */ 431 compatible = "maxim,max15301"; 432 reg = <0x13>; 433 }; 434 max15303@14 { /* u7 */ 435 compatible = "maxim,max15303"; 436 reg = <0x14>; 437 }; 438 max15303@15 { /* u6 */ 439 compatible = "maxim,max15303"; 440 reg = <0x15>; 441 }; 442 max15303@16 { /* u10 */ 443 compatible = "maxim,max15303"; 444 reg = <0x16>; 445 }; 446 max15303@17 { /* u9 */ 447 compatible = "maxim,max15303"; 448 reg = <0x17>; 449 }; 450 max15301@18 { /* u63 */ 451 compatible = "maxim,max15301"; 452 reg = <0x18>; 453 }; 454 max15303@1a { /* u49 */ 455 compatible = "maxim,max15303"; 456 reg = <0x1a>; 457 }; 458 max15303@1b { /* u8 */ 459 compatible = "maxim,max15303"; 460 reg = <0x1b>; 461 }; 462 max15303@1d { /* u18 */ 463 compatible = "maxim,max15303"; 464 reg = <0x1d>; 465 }; 466 467 max20751@72 { /* u95 */ 468 compatible = "maxim,max20751"; 469 reg = <0x72>; 470 }; 471 max20751@73 { /* u96 */ 472 compatible = "maxim,max20751"; 473 reg = <0x73>; 474 }; 475 }; 476 /* Bus 3 is not connected */ 477 }; 478}; 479 480&i2c1 { 481 status = "okay"; 482 clock-frequency = <400000>; 483 pinctrl-names = "default", "gpio"; 484 pinctrl-0 = <&pinctrl_i2c1_default>; 485 pinctrl-1 = <&pinctrl_i2c1_gpio>; 486 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 487 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 488 489 /* PL i2c via PCA9306 - u45 */ 490 i2c-mux@74 { /* u34 */ 491 compatible = "nxp,pca9548"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 reg = <0x74>; 495 i2c@0 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 reg = <0>; 499 /* 500 * IIC_EEPROM 1kB memory which uses 256B blocks 501 * where every block has different address. 502 * 0 - 256B address 0x54 503 * 256B - 512B address 0x55 504 * 512B - 768B address 0x56 505 * 768B - 1024B address 0x57 506 */ 507 eeprom: eeprom@54 { /* u23 */ 508 compatible = "atmel,24c08"; 509 reg = <0x54>; 510 }; 511 }; 512 i2c@1 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <1>; 516 si5341: clock-generator@36 { /* SI5341 - u69 */ 517 compatible = "silabs,si5341"; 518 reg = <0x36>; 519 #clock-cells = <2>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 clocks = <&ref48>; 523 clock-names = "xtal"; 524 clock-output-names = "si5341"; 525 526 si5341_0: out@0 { 527 /* refclk0 for PS-GT, used for DP */ 528 reg = <0>; 529 always-on; 530 }; 531 si5341_2: out@2 { 532 /* refclk2 for PS-GT, used for USB3 */ 533 reg = <2>; 534 always-on; 535 }; 536 si5341_3: out@3 { 537 /* refclk3 for PS-GT, used for SATA */ 538 reg = <3>; 539 always-on; 540 }; 541 si5341_6: out@6 { 542 /* refclk6 PL CLK125 */ 543 reg = <6>; 544 always-on; 545 }; 546 si5341_7: out@7 { 547 /* refclk7 PL CLK74 */ 548 reg = <7>; 549 always-on; 550 }; 551 si5341_9: out@9 { 552 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 553 reg = <9>; 554 always-on; 555 }; 556 }; 557 558 }; 559 i2c@2 { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 reg = <2>; 563 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 564 #clock-cells = <0>; 565 compatible = "silabs,si570"; 566 reg = <0x5d>; 567 temperature-stability = <50>; 568 factory-fout = <300000000>; 569 clock-frequency = <300000000>; 570 clock-output-names = "si570_user"; 571 }; 572 }; 573 i2c@3 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 reg = <3>; 577 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 578 #clock-cells = <0>; 579 compatible = "silabs,si570"; 580 reg = <0x5d>; 581 temperature-stability = <50>; /* copy from zc702 */ 582 factory-fout = <156250000>; 583 clock-frequency = <148500000>; 584 clock-output-names = "si570_mgt"; 585 }; 586 }; 587 i2c@4 { 588 #address-cells = <1>; 589 #size-cells = <0>; 590 reg = <4>; 591 /* SI5328 - u20 */ 592 }; 593 i2c@5 { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 reg = <5>; /* FAN controller */ 597 temp@4c {/* lm96163 - u128 */ 598 compatible = "national,lm96163"; 599 reg = <0x4c>; 600 }; 601 }; 602 /* 6 - 7 unconnected */ 603 }; 604 605 i2c-mux@75 { 606 compatible = "nxp,pca9548"; /* u135 */ 607 #address-cells = <1>; 608 #size-cells = <0>; 609 reg = <0x75>; 610 611 i2c@0 { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 reg = <0>; 615 /* HPC0_IIC */ 616 }; 617 i2c@1 { 618 #address-cells = <1>; 619 #size-cells = <0>; 620 reg = <1>; 621 /* HPC1_IIC */ 622 }; 623 i2c@2 { 624 #address-cells = <1>; 625 #size-cells = <0>; 626 reg = <2>; 627 /* SYSMON */ 628 }; 629 i2c@3 { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 reg = <3>; 633 /* DDR4 SODIMM */ 634 }; 635 i2c@4 { 636 #address-cells = <1>; 637 #size-cells = <0>; 638 reg = <4>; 639 /* SEP 3 */ 640 }; 641 i2c@5 { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 reg = <5>; 645 /* SEP 2 */ 646 }; 647 i2c@6 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 reg = <6>; 651 /* SEP 1 */ 652 }; 653 i2c@7 { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 reg = <7>; 657 /* SEP 0 */ 658 }; 659 }; 660}; 661 662&pinctrl0 { 663 status = "okay"; 664 pinctrl_i2c0_default: i2c0-default { 665 mux { 666 groups = "i2c0_3_grp"; 667 function = "i2c0"; 668 }; 669 670 conf { 671 groups = "i2c0_3_grp"; 672 bias-pull-up; 673 slew-rate = <SLEW_RATE_SLOW>; 674 power-source = <IO_STANDARD_LVCMOS18>; 675 }; 676 }; 677 678 pinctrl_i2c0_gpio: i2c0-gpio { 679 mux { 680 groups = "gpio0_14_grp", "gpio0_15_grp"; 681 function = "gpio0"; 682 }; 683 684 conf { 685 groups = "gpio0_14_grp", "gpio0_15_grp"; 686 slew-rate = <SLEW_RATE_SLOW>; 687 power-source = <IO_STANDARD_LVCMOS18>; 688 }; 689 }; 690 691 pinctrl_i2c1_default: i2c1-default { 692 mux { 693 groups = "i2c1_4_grp"; 694 function = "i2c1"; 695 }; 696 697 conf { 698 groups = "i2c1_4_grp"; 699 bias-pull-up; 700 slew-rate = <SLEW_RATE_SLOW>; 701 power-source = <IO_STANDARD_LVCMOS18>; 702 }; 703 }; 704 705 pinctrl_i2c1_gpio: i2c1-gpio { 706 mux { 707 groups = "gpio0_16_grp", "gpio0_17_grp"; 708 function = "gpio0"; 709 }; 710 711 conf { 712 groups = "gpio0_16_grp", "gpio0_17_grp"; 713 slew-rate = <SLEW_RATE_SLOW>; 714 power-source = <IO_STANDARD_LVCMOS18>; 715 }; 716 }; 717 718 pinctrl_uart0_default: uart0-default { 719 mux { 720 groups = "uart0_4_grp"; 721 function = "uart0"; 722 }; 723 724 conf { 725 groups = "uart0_4_grp"; 726 slew-rate = <SLEW_RATE_SLOW>; 727 power-source = <IO_STANDARD_LVCMOS18>; 728 }; 729 730 conf-rx { 731 pins = "MIO18"; 732 bias-high-impedance; 733 }; 734 735 conf-tx { 736 pins = "MIO19"; 737 bias-disable; 738 }; 739 }; 740 741 pinctrl_uart1_default: uart1-default { 742 mux { 743 groups = "uart1_5_grp"; 744 function = "uart1"; 745 }; 746 747 conf { 748 groups = "uart1_5_grp"; 749 slew-rate = <SLEW_RATE_SLOW>; 750 power-source = <IO_STANDARD_LVCMOS18>; 751 }; 752 753 conf-rx { 754 pins = "MIO21"; 755 bias-high-impedance; 756 }; 757 758 conf-tx { 759 pins = "MIO20"; 760 bias-disable; 761 }; 762 }; 763 764 pinctrl_usb0_default: usb0-default { 765 mux { 766 groups = "usb0_0_grp"; 767 function = "usb0"; 768 }; 769 770 conf { 771 groups = "usb0_0_grp"; 772 slew-rate = <SLEW_RATE_SLOW>; 773 power-source = <IO_STANDARD_LVCMOS18>; 774 }; 775 776 conf-rx { 777 pins = "MIO52", "MIO53", "MIO55"; 778 bias-high-impedance; 779 }; 780 781 conf-tx { 782 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 783 "MIO60", "MIO61", "MIO62", "MIO63"; 784 bias-disable; 785 }; 786 }; 787 788 pinctrl_gem3_default: gem3-default { 789 mux { 790 function = "ethernet3"; 791 groups = "ethernet3_0_grp"; 792 }; 793 794 conf { 795 groups = "ethernet3_0_grp"; 796 slew-rate = <SLEW_RATE_SLOW>; 797 power-source = <IO_STANDARD_LVCMOS18>; 798 }; 799 800 conf-rx { 801 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 802 "MIO75"; 803 bias-high-impedance; 804 low-power-disable; 805 }; 806 807 conf-tx { 808 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 809 "MIO69"; 810 bias-disable; 811 low-power-enable; 812 }; 813 814 mux-mdio { 815 function = "mdio3"; 816 groups = "mdio3_0_grp"; 817 }; 818 819 conf-mdio { 820 groups = "mdio3_0_grp"; 821 slew-rate = <SLEW_RATE_SLOW>; 822 power-source = <IO_STANDARD_LVCMOS18>; 823 bias-disable; 824 }; 825 }; 826 827 pinctrl_can1_default: can1-default { 828 mux { 829 function = "can1"; 830 groups = "can1_6_grp"; 831 }; 832 833 conf { 834 groups = "can1_6_grp"; 835 slew-rate = <SLEW_RATE_SLOW>; 836 power-source = <IO_STANDARD_LVCMOS18>; 837 }; 838 839 conf-rx { 840 pins = "MIO25"; 841 bias-high-impedance; 842 }; 843 844 conf-tx { 845 pins = "MIO24"; 846 bias-disable; 847 }; 848 }; 849 850 pinctrl_sdhci1_default: sdhci1-default { 851 mux { 852 groups = "sdio1_0_grp"; 853 function = "sdio1"; 854 }; 855 856 conf { 857 groups = "sdio1_0_grp"; 858 slew-rate = <SLEW_RATE_SLOW>; 859 power-source = <IO_STANDARD_LVCMOS18>; 860 bias-disable; 861 }; 862 863 mux-cd { 864 groups = "sdio1_cd_0_grp"; 865 function = "sdio1_cd"; 866 }; 867 868 conf-cd { 869 groups = "sdio1_cd_0_grp"; 870 bias-high-impedance; 871 bias-pull-up; 872 slew-rate = <SLEW_RATE_SLOW>; 873 power-source = <IO_STANDARD_LVCMOS18>; 874 }; 875 876 mux-wp { 877 groups = "sdio1_wp_0_grp"; 878 function = "sdio1_wp"; 879 }; 880 881 conf-wp { 882 groups = "sdio1_wp_0_grp"; 883 bias-high-impedance; 884 bias-pull-up; 885 slew-rate = <SLEW_RATE_SLOW>; 886 power-source = <IO_STANDARD_LVCMOS18>; 887 }; 888 }; 889 890 pinctrl_gpio_default: gpio-default { 891 mux { 892 function = "gpio0"; 893 groups = "gpio0_22_grp", "gpio0_23_grp"; 894 }; 895 896 conf { 897 groups = "gpio0_22_grp", "gpio0_23_grp"; 898 slew-rate = <SLEW_RATE_SLOW>; 899 power-source = <IO_STANDARD_LVCMOS18>; 900 }; 901 902 mux-msp { 903 function = "gpio0"; 904 groups = "gpio0_13_grp", "gpio0_38_grp"; 905 }; 906 907 conf-msp { 908 groups = "gpio0_13_grp", "gpio0_38_grp"; 909 slew-rate = <SLEW_RATE_SLOW>; 910 power-source = <IO_STANDARD_LVCMOS18>; 911 }; 912 913 conf-pull-up { 914 pins = "MIO22"; 915 bias-pull-up; 916 }; 917 918 conf-pull-none { 919 pins = "MIO13", "MIO23", "MIO38"; 920 bias-disable; 921 }; 922 }; 923}; 924 925&psgtr { 926 status = "okay"; 927 /* nc, sata, usb3, dp */ 928 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 929 clock-names = "ref1", "ref2", "ref3"; 930}; 931 932&qspi { 933 status = "okay"; 934 is-dual = <1>; 935 flash@0 { 936 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 937 #address-cells = <1>; 938 #size-cells = <1>; 939 reg = <0x0>; 940 spi-tx-bus-width = <1>; 941 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 942 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 943 }; 944}; 945 946&rtc { 947 status = "okay"; 948}; 949 950&sata { 951 status = "okay"; 952 /* SATA OOB timing settings */ 953 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 954 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 955 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 956 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 957 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 958 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 959 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 960 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 961 phy-names = "sata-phy"; 962 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 963}; 964 965/* SD1 with level shifter */ 966&sdhci1 { 967 status = "okay"; 968 /* 969 * This property should be removed for supporting UHS mode 970 */ 971 no-1-8-v; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&pinctrl_sdhci1_default>; 974 xlnx,mio-bank = <1>; 975}; 976 977&uart0 { 978 status = "okay"; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&pinctrl_uart0_default>; 981}; 982 983&uart1 { 984 status = "okay"; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&pinctrl_uart1_default>; 987}; 988 989/* ULPI SMSC USB3320 */ 990&usb0 { 991 status = "okay"; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&pinctrl_usb0_default>; 994 dr_mode = "host"; 995 phy-names = "usb3-phy"; 996 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 997 maximum-speed = "super-speed"; 998}; 999 1000&watchdog0 { 1001 status = "okay"; 1002}; 1003 1004&zynqmp_dpdma { 1005 status = "okay"; 1006}; 1007 1008&zynqmp_dpsub { 1009 status = "okay"; 1010 phy-names = "dp-phy0", "dp-phy1"; 1011 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 1012 <&psgtr 0 PHY_TYPE_DP 1 3>; 1013}; 1014