1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU106 4 * 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU106 RevA"; 21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 nvmem0 = &eeprom; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &dcc; 33 spi0 = &qspi; 34 usb0 = &usb0; 35 }; 36 37 chosen { 38 bootargs = "earlycon"; 39 stdout-path = "serial0:115200n8"; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 autorepeat; 50 switch-19 { 51 label = "sw19"; 52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 53 linux,code = <KEY_DOWN>; 54 wakeup-source; 55 autorepeat; 56 }; 57 }; 58 59 leds { 60 compatible = "gpio-leds"; 61 heartbeat-led { 62 label = "heartbeat"; 63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 64 linux,default-trigger = "heartbeat"; 65 }; 66 }; 67 68 ina226-u76 { 69 compatible = "iio-hwmon"; 70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 71 }; 72 ina226-u77 { 73 compatible = "iio-hwmon"; 74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 75 }; 76 ina226-u78 { 77 compatible = "iio-hwmon"; 78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 79 }; 80 ina226-u87 { 81 compatible = "iio-hwmon"; 82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 83 }; 84 ina226-u85 { 85 compatible = "iio-hwmon"; 86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 87 }; 88 ina226-u86 { 89 compatible = "iio-hwmon"; 90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 91 }; 92 ina226-u93 { 93 compatible = "iio-hwmon"; 94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 95 }; 96 ina226-u88 { 97 compatible = "iio-hwmon"; 98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 99 }; 100 ina226-u15 { 101 compatible = "iio-hwmon"; 102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 103 }; 104 ina226-u92 { 105 compatible = "iio-hwmon"; 106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 107 }; 108 ina226-u79 { 109 compatible = "iio-hwmon"; 110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 111 }; 112 ina226-u81 { 113 compatible = "iio-hwmon"; 114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 115 }; 116 ina226-u80 { 117 compatible = "iio-hwmon"; 118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 119 }; 120 ina226-u84 { 121 compatible = "iio-hwmon"; 122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 123 }; 124 ina226-u16 { 125 compatible = "iio-hwmon"; 126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 127 }; 128 ina226-u65 { 129 compatible = "iio-hwmon"; 130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 131 }; 132 ina226-u74 { 133 compatible = "iio-hwmon"; 134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 135 }; 136 ina226-u75 { 137 compatible = "iio-hwmon"; 138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 139 }; 140 141 /* 48MHz reference crystal */ 142 ref48: ref48M { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 clock-frequency = <48000000>; 146 }; 147 148 refhdmi: refhdmi { 149 compatible = "fixed-clock"; 150 #clock-cells = <0>; 151 clock-frequency = <114285000>; 152 }; 153 154 dpcon { 155 compatible = "dp-connector"; 156 label = "P11"; 157 type = "full-size"; 158 159 port { 160 dpcon_in: endpoint { 161 remote-endpoint = <&dpsub_dp_out>; 162 }; 163 }; 164 }; 165}; 166 167&can1 { 168 status = "okay"; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_can1_default>; 171}; 172 173&dcc { 174 status = "okay"; 175}; 176 177&fpd_dma_chan1 { 178 status = "okay"; 179}; 180 181&fpd_dma_chan2 { 182 status = "okay"; 183}; 184 185&fpd_dma_chan3 { 186 status = "okay"; 187}; 188 189&fpd_dma_chan4 { 190 status = "okay"; 191}; 192 193&fpd_dma_chan5 { 194 status = "okay"; 195}; 196 197&fpd_dma_chan6 { 198 status = "okay"; 199}; 200 201&fpd_dma_chan7 { 202 status = "okay"; 203}; 204 205&fpd_dma_chan8 { 206 status = "okay"; 207}; 208 209&gem3 { 210 status = "okay"; 211 phy-handle = <&phy0>; 212 phy-mode = "rgmii-id"; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_gem3_default>; 215 phy0: ethernet-phy@c { 216 reg = <0xc>; 217 ti,rx-internal-delay = <0x8>; 218 ti,tx-internal-delay = <0xa>; 219 ti,fifo-depth = <0x1>; 220 ti,dp83867-rxctrl-strap-quirk; 221 }; 222}; 223 224&gpio { 225 status = "okay"; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_gpio_default>; 228}; 229 230&i2c0 { 231 status = "okay"; 232 clock-frequency = <400000>; 233 pinctrl-names = "default", "gpio"; 234 pinctrl-0 = <&pinctrl_i2c0_default>; 235 pinctrl-1 = <&pinctrl_i2c0_gpio>; 236 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 237 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 238 239 tca6416_u97: gpio@20 { 240 compatible = "ti,tca6416"; 241 reg = <0x20>; 242 gpio-controller; /* interrupt not connected */ 243 #gpio-cells = <2>; 244 /* 245 * IRQ not connected 246 * Lines: 247 * 0 - SFP_SI5328_INT_ALM 248 * 1 - HDMI_SI5328_INT_ALM 249 * 5 - IIC_MUX_RESET_B 250 * 6 - GEM3_EXP_RESET_B 251 * 10 - FMC_HPC0_PRSNT_M2C_B 252 * 11 - FMC_HPC1_PRSNT_M2C_B 253 * 2-4, 7, 12-17 - not connected 254 */ 255 }; 256 257 tca6416_u61: gpio@21 { 258 compatible = "ti,tca6416"; 259 reg = <0x21>; 260 gpio-controller; 261 #gpio-cells = <2>; 262 /* 263 * IRQ not connected 264 * Lines: 265 * 0 - VCCPSPLL_EN 266 * 1 - MGTRAVCC_EN 267 * 2 - MGTRAVTT_EN 268 * 3 - VCCPSDDRPLL_EN 269 * 4 - MIO26_PMU_INPUT_LS 270 * 5 - PL_PMBUS_ALERT 271 * 6 - PS_PMBUS_ALERT 272 * 7 - MAXIM_PMBUS_ALERT 273 * 10 - PL_DDR4_VTERM_EN 274 * 11 - PL_DDR4_VPP_2V5_EN 275 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON 276 * 13 - PS_DIMM_SUSPEND_EN 277 * 14 - PS_DDR4_VTERM_EN 278 * 15 - PS_DDR4_VPP_2V5_EN 279 * 16 - 17 - not connected 280 */ 281 }; 282 283 i2c-mux@75 { /* u60 */ 284 compatible = "nxp,pca9544"; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <0x75>; 288 i2c@0 { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 reg = <0>; 292 /* PS_PMBUS */ 293 u76: ina226@40 { /* u76 */ 294 compatible = "ti,ina226"; 295 #io-channel-cells = <1>; 296 label = "ina226-u76"; 297 reg = <0x40>; 298 shunt-resistor = <5000>; 299 }; 300 u77: ina226@41 { /* u77 */ 301 compatible = "ti,ina226"; 302 #io-channel-cells = <1>; 303 label = "ina226-u77"; 304 reg = <0x41>; 305 shunt-resistor = <5000>; 306 }; 307 u78: ina226@42 { /* u78 */ 308 compatible = "ti,ina226"; 309 #io-channel-cells = <1>; 310 label = "ina226-u78"; 311 reg = <0x42>; 312 shunt-resistor = <5000>; 313 }; 314 u87: ina226@43 { /* u87 */ 315 compatible = "ti,ina226"; 316 #io-channel-cells = <1>; 317 label = "ina226-u87"; 318 reg = <0x43>; 319 shunt-resistor = <5000>; 320 }; 321 u85: ina226@44 { /* u85 */ 322 compatible = "ti,ina226"; 323 #io-channel-cells = <1>; 324 label = "ina226-u85"; 325 reg = <0x44>; 326 shunt-resistor = <5000>; 327 }; 328 u86: ina226@45 { /* u86 */ 329 compatible = "ti,ina226"; 330 #io-channel-cells = <1>; 331 label = "ina226-u86"; 332 reg = <0x45>; 333 shunt-resistor = <5000>; 334 }; 335 u93: ina226@46 { /* u93 */ 336 compatible = "ti,ina226"; 337 #io-channel-cells = <1>; 338 label = "ina226-u93"; 339 reg = <0x46>; 340 shunt-resistor = <5000>; 341 }; 342 u88: ina226@47 { /* u88 */ 343 compatible = "ti,ina226"; 344 #io-channel-cells = <1>; 345 label = "ina226-u88"; 346 reg = <0x47>; 347 shunt-resistor = <5000>; 348 }; 349 u15: ina226@4a { /* u15 */ 350 compatible = "ti,ina226"; 351 #io-channel-cells = <1>; 352 label = "ina226-u15"; 353 reg = <0x4a>; 354 shunt-resistor = <5000>; 355 }; 356 u92: ina226@4b { /* u92 */ 357 compatible = "ti,ina226"; 358 #io-channel-cells = <1>; 359 label = "ina226-u92"; 360 reg = <0x4b>; 361 shunt-resistor = <5000>; 362 }; 363 }; 364 i2c@1 { 365 #address-cells = <1>; 366 #size-cells = <0>; 367 reg = <1>; 368 /* PL_PMBUS */ 369 u79: ina226@40 { /* u79 */ 370 compatible = "ti,ina226"; 371 #io-channel-cells = <1>; 372 label = "ina226-u79"; 373 reg = <0x40>; 374 shunt-resistor = <2000>; 375 }; 376 u81: ina226@41 { /* u81 */ 377 compatible = "ti,ina226"; 378 #io-channel-cells = <1>; 379 label = "ina226-u81"; 380 reg = <0x41>; 381 shunt-resistor = <5000>; 382 }; 383 u80: ina226@42 { /* u80 */ 384 compatible = "ti,ina226"; 385 #io-channel-cells = <1>; 386 label = "ina226-u80"; 387 reg = <0x42>; 388 shunt-resistor = <5000>; 389 }; 390 u84: ina226@43 { /* u84 */ 391 compatible = "ti,ina226"; 392 #io-channel-cells = <1>; 393 label = "ina226-u84"; 394 reg = <0x43>; 395 shunt-resistor = <5000>; 396 }; 397 u16: ina226@44 { /* u16 */ 398 compatible = "ti,ina226"; 399 #io-channel-cells = <1>; 400 label = "ina226-u16"; 401 reg = <0x44>; 402 shunt-resistor = <5000>; 403 }; 404 u65: ina226@45 { /* u65 */ 405 compatible = "ti,ina226"; 406 #io-channel-cells = <1>; 407 label = "ina226-u65"; 408 reg = <0x45>; 409 shunt-resistor = <5000>; 410 }; 411 u74: ina226@46 { /* u74 */ 412 compatible = "ti,ina226"; 413 #io-channel-cells = <1>; 414 label = "ina226-u74"; 415 reg = <0x46>; 416 shunt-resistor = <5000>; 417 }; 418 u75: ina226@47 { /* u75 */ 419 compatible = "ti,ina226"; 420 #io-channel-cells = <1>; 421 label = "ina226-u75"; 422 reg = <0x47>; 423 shunt-resistor = <5000>; 424 }; 425 }; 426 i2c@2 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 reg = <2>; 430 /* MAXIM_PMBUS - 00 */ 431 max15301@a { /* u46 */ 432 compatible = "maxim,max15301"; 433 reg = <0xa>; 434 }; 435 max15303@b { /* u4 */ 436 compatible = "maxim,max15303"; 437 reg = <0xb>; 438 }; 439 max15303@10 { /* u13 */ 440 compatible = "maxim,max15303"; 441 reg = <0x10>; 442 }; 443 max15301@13 { /* u47 */ 444 compatible = "maxim,max15301"; 445 reg = <0x13>; 446 }; 447 max15303@14 { /* u7 */ 448 compatible = "maxim,max15303"; 449 reg = <0x14>; 450 }; 451 max15303@15 { /* u6 */ 452 compatible = "maxim,max15303"; 453 reg = <0x15>; 454 }; 455 max15303@16 { /* u10 */ 456 compatible = "maxim,max15303"; 457 reg = <0x16>; 458 }; 459 max15303@17 { /* u9 */ 460 compatible = "maxim,max15303"; 461 reg = <0x17>; 462 }; 463 max15301@18 { /* u63 */ 464 compatible = "maxim,max15301"; 465 reg = <0x18>; 466 }; 467 max15303@1a { /* u49 */ 468 compatible = "maxim,max15303"; 469 reg = <0x1a>; 470 }; 471 max15303@1b { /* u8 */ 472 compatible = "maxim,max15303"; 473 reg = <0x1b>; 474 }; 475 max15303@1d { /* u18 */ 476 compatible = "maxim,max15303"; 477 reg = <0x1d>; 478 }; 479 480 max20751@72 { /* u95 */ 481 compatible = "maxim,max20751"; 482 reg = <0x72>; 483 }; 484 max20751@73 { /* u96 */ 485 compatible = "maxim,max20751"; 486 reg = <0x73>; 487 }; 488 }; 489 /* Bus 3 is not connected */ 490 }; 491}; 492 493&i2c1 { 494 status = "okay"; 495 clock-frequency = <400000>; 496 pinctrl-names = "default", "gpio"; 497 pinctrl-0 = <&pinctrl_i2c1_default>; 498 pinctrl-1 = <&pinctrl_i2c1_gpio>; 499 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 500 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 501 502 /* PL i2c via PCA9306 - u45 */ 503 i2c-mux@74 { /* u34 */ 504 compatible = "nxp,pca9548"; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 reg = <0x74>; 508 i2c@0 { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <0>; 512 /* 513 * IIC_EEPROM 1kB memory which uses 256B blocks 514 * where every block has different address. 515 * 0 - 256B address 0x54 516 * 256B - 512B address 0x55 517 * 512B - 768B address 0x56 518 * 768B - 1024B address 0x57 519 */ 520 eeprom: eeprom@54 { /* u23 */ 521 compatible = "atmel,24c08"; 522 reg = <0x54>; 523 }; 524 }; 525 i2c@1 { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 reg = <1>; 529 si5341: clock-generator@36 { /* SI5341 - u69 */ 530 compatible = "silabs,si5341"; 531 reg = <0x36>; 532 #clock-cells = <2>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 clocks = <&ref48>; 536 clock-names = "xtal"; 537 clock-output-names = "si5341"; 538 539 si5341_0: out@0 { 540 /* refclk0 for PS-GT, used for DP */ 541 reg = <0>; 542 always-on; 543 }; 544 si5341_2: out@2 { 545 /* refclk2 for PS-GT, used for USB3 */ 546 reg = <2>; 547 always-on; 548 }; 549 si5341_3: out@3 { 550 /* refclk3 for PS-GT, used for SATA */ 551 reg = <3>; 552 always-on; 553 }; 554 si5341_6: out@6 { 555 /* refclk6 PL CLK125 */ 556 reg = <6>; 557 always-on; 558 }; 559 si5341_7: out@7 { 560 /* refclk7 PL CLK74 */ 561 reg = <7>; 562 always-on; 563 }; 564 si5341_9: out@9 { 565 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 566 reg = <9>; 567 always-on; 568 }; 569 }; 570 571 }; 572 i2c@2 { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 reg = <2>; 576 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 577 #clock-cells = <0>; 578 compatible = "silabs,si570"; 579 reg = <0x5d>; 580 temperature-stability = <50>; 581 factory-fout = <300000000>; 582 clock-frequency = <300000000>; 583 clock-output-names = "si570_user"; 584 }; 585 }; 586 i2c@3 { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 reg = <3>; 590 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 591 #clock-cells = <0>; 592 compatible = "silabs,si570"; 593 reg = <0x5d>; 594 temperature-stability = <50>; /* copy from zc702 */ 595 factory-fout = <156250000>; 596 clock-frequency = <148500000>; 597 clock-output-names = "si570_mgt"; 598 }; 599 }; 600 i2c@4 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 reg = <4>; 604 /* SI5328 - u20 */ 605 }; 606 i2c@5 { 607 #address-cells = <1>; 608 #size-cells = <0>; 609 reg = <5>; /* FAN controller */ 610 temp@4c {/* lm96163 - u128 */ 611 compatible = "national,lm96163"; 612 reg = <0x4c>; 613 }; 614 }; 615 /* 6 - 7 unconnected */ 616 }; 617 618 i2c-mux@75 { 619 compatible = "nxp,pca9548"; /* u135 */ 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0x75>; 623 624 i2c@0 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 reg = <0>; 628 /* HPC0_IIC */ 629 }; 630 i2c@1 { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 reg = <1>; 634 /* HPC1_IIC */ 635 }; 636 i2c@2 { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 reg = <2>; 640 /* SYSMON */ 641 }; 642 i2c@3 { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 reg = <3>; 646 /* DDR4 SODIMM */ 647 }; 648 i2c@4 { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 reg = <4>; 652 /* SEP 3 */ 653 }; 654 i2c@5 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 reg = <5>; 658 /* SEP 2 */ 659 }; 660 i2c@6 { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 reg = <6>; 664 /* SEP 1 */ 665 }; 666 i2c@7 { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 reg = <7>; 670 /* SEP 0 */ 671 }; 672 }; 673}; 674 675&pinctrl0 { 676 status = "okay"; 677 pinctrl_i2c0_default: i2c0-default { 678 mux { 679 groups = "i2c0_3_grp"; 680 function = "i2c0"; 681 }; 682 683 conf { 684 groups = "i2c0_3_grp"; 685 bias-pull-up; 686 slew-rate = <SLEW_RATE_SLOW>; 687 power-source = <IO_STANDARD_LVCMOS18>; 688 }; 689 }; 690 691 pinctrl_i2c0_gpio: i2c0-gpio { 692 mux { 693 groups = "gpio0_14_grp", "gpio0_15_grp"; 694 function = "gpio0"; 695 }; 696 697 conf { 698 groups = "gpio0_14_grp", "gpio0_15_grp"; 699 slew-rate = <SLEW_RATE_SLOW>; 700 power-source = <IO_STANDARD_LVCMOS18>; 701 }; 702 }; 703 704 pinctrl_i2c1_default: i2c1-default { 705 mux { 706 groups = "i2c1_4_grp"; 707 function = "i2c1"; 708 }; 709 710 conf { 711 groups = "i2c1_4_grp"; 712 bias-pull-up; 713 slew-rate = <SLEW_RATE_SLOW>; 714 power-source = <IO_STANDARD_LVCMOS18>; 715 }; 716 }; 717 718 pinctrl_i2c1_gpio: i2c1-gpio { 719 mux { 720 groups = "gpio0_16_grp", "gpio0_17_grp"; 721 function = "gpio0"; 722 }; 723 724 conf { 725 groups = "gpio0_16_grp", "gpio0_17_grp"; 726 slew-rate = <SLEW_RATE_SLOW>; 727 power-source = <IO_STANDARD_LVCMOS18>; 728 }; 729 }; 730 731 pinctrl_uart0_default: uart0-default { 732 mux { 733 groups = "uart0_4_grp"; 734 function = "uart0"; 735 }; 736 737 conf { 738 groups = "uart0_4_grp"; 739 slew-rate = <SLEW_RATE_SLOW>; 740 power-source = <IO_STANDARD_LVCMOS18>; 741 }; 742 743 conf-rx { 744 pins = "MIO18"; 745 bias-high-impedance; 746 }; 747 748 conf-tx { 749 pins = "MIO19"; 750 bias-disable; 751 }; 752 }; 753 754 pinctrl_uart1_default: uart1-default { 755 mux { 756 groups = "uart1_5_grp"; 757 function = "uart1"; 758 }; 759 760 conf { 761 groups = "uart1_5_grp"; 762 slew-rate = <SLEW_RATE_SLOW>; 763 power-source = <IO_STANDARD_LVCMOS18>; 764 }; 765 766 conf-rx { 767 pins = "MIO21"; 768 bias-high-impedance; 769 }; 770 771 conf-tx { 772 pins = "MIO20"; 773 bias-disable; 774 }; 775 }; 776 777 pinctrl_usb0_default: usb0-default { 778 mux { 779 groups = "usb0_0_grp"; 780 function = "usb0"; 781 }; 782 783 conf { 784 groups = "usb0_0_grp"; 785 slew-rate = <SLEW_RATE_SLOW>; 786 power-source = <IO_STANDARD_LVCMOS18>; 787 }; 788 789 conf-rx { 790 pins = "MIO52", "MIO53", "MIO55"; 791 bias-high-impedance; 792 }; 793 794 conf-tx { 795 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 796 "MIO60", "MIO61", "MIO62", "MIO63"; 797 bias-disable; 798 }; 799 }; 800 801 pinctrl_gem3_default: gem3-default { 802 mux { 803 function = "ethernet3"; 804 groups = "ethernet3_0_grp"; 805 }; 806 807 conf { 808 groups = "ethernet3_0_grp"; 809 slew-rate = <SLEW_RATE_SLOW>; 810 power-source = <IO_STANDARD_LVCMOS18>; 811 }; 812 813 conf-rx { 814 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 815 "MIO75"; 816 bias-high-impedance; 817 low-power-disable; 818 }; 819 820 conf-tx { 821 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 822 "MIO69"; 823 bias-disable; 824 low-power-enable; 825 }; 826 827 mux-mdio { 828 function = "mdio3"; 829 groups = "mdio3_0_grp"; 830 }; 831 832 conf-mdio { 833 groups = "mdio3_0_grp"; 834 slew-rate = <SLEW_RATE_SLOW>; 835 power-source = <IO_STANDARD_LVCMOS18>; 836 bias-disable; 837 }; 838 }; 839 840 pinctrl_can1_default: can1-default { 841 mux { 842 function = "can1"; 843 groups = "can1_6_grp"; 844 }; 845 846 conf { 847 groups = "can1_6_grp"; 848 slew-rate = <SLEW_RATE_SLOW>; 849 power-source = <IO_STANDARD_LVCMOS18>; 850 }; 851 852 conf-rx { 853 pins = "MIO25"; 854 bias-high-impedance; 855 }; 856 857 conf-tx { 858 pins = "MIO24"; 859 bias-disable; 860 }; 861 }; 862 863 pinctrl_sdhci1_default: sdhci1-default { 864 mux { 865 groups = "sdio1_0_grp"; 866 function = "sdio1"; 867 }; 868 869 conf { 870 groups = "sdio1_0_grp"; 871 slew-rate = <SLEW_RATE_SLOW>; 872 power-source = <IO_STANDARD_LVCMOS18>; 873 bias-disable; 874 }; 875 876 mux-cd { 877 groups = "sdio1_cd_0_grp"; 878 function = "sdio1_cd"; 879 }; 880 881 conf-cd { 882 groups = "sdio1_cd_0_grp"; 883 bias-high-impedance; 884 bias-pull-up; 885 slew-rate = <SLEW_RATE_SLOW>; 886 power-source = <IO_STANDARD_LVCMOS18>; 887 }; 888 889 mux-wp { 890 groups = "sdio1_wp_0_grp"; 891 function = "sdio1_wp"; 892 }; 893 894 conf-wp { 895 groups = "sdio1_wp_0_grp"; 896 bias-high-impedance; 897 bias-pull-up; 898 slew-rate = <SLEW_RATE_SLOW>; 899 power-source = <IO_STANDARD_LVCMOS18>; 900 }; 901 }; 902 903 pinctrl_gpio_default: gpio-default { 904 mux { 905 function = "gpio0"; 906 groups = "gpio0_22_grp", "gpio0_23_grp"; 907 }; 908 909 conf { 910 groups = "gpio0_22_grp", "gpio0_23_grp"; 911 slew-rate = <SLEW_RATE_SLOW>; 912 power-source = <IO_STANDARD_LVCMOS18>; 913 }; 914 915 mux-msp { 916 function = "gpio0"; 917 groups = "gpio0_13_grp", "gpio0_38_grp"; 918 }; 919 920 conf-msp { 921 groups = "gpio0_13_grp", "gpio0_38_grp"; 922 slew-rate = <SLEW_RATE_SLOW>; 923 power-source = <IO_STANDARD_LVCMOS18>; 924 }; 925 926 conf-pull-up { 927 pins = "MIO22"; 928 bias-pull-up; 929 }; 930 931 conf-pull-none { 932 pins = "MIO13", "MIO23", "MIO38"; 933 bias-disable; 934 }; 935 }; 936}; 937 938&psgtr { 939 status = "okay"; 940 /* nc, sata, usb3, dp */ 941 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 942 clock-names = "ref1", "ref2", "ref3"; 943}; 944 945&qspi { 946 status = "okay"; 947 flash@0 { 948 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ 949 #address-cells = <1>; 950 #size-cells = <1>; 951 reg = <0x0>; 952 spi-tx-bus-width = <1>; 953 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 954 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 955 }; 956}; 957 958&rtc { 959 status = "okay"; 960}; 961 962&sata { 963 status = "okay"; 964 /* SATA OOB timing settings */ 965 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 966 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 967 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 968 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 969 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 970 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 971 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 972 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 973 phy-names = "sata-phy"; 974 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 975}; 976 977/* SD1 with level shifter */ 978&sdhci1 { 979 status = "okay"; 980 /* 981 * This property should be removed for supporting UHS mode 982 */ 983 no-1-8-v; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&pinctrl_sdhci1_default>; 986 xlnx,mio-bank = <1>; 987}; 988 989&uart0 { 990 status = "okay"; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&pinctrl_uart0_default>; 993}; 994 995&uart1 { 996 status = "okay"; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&pinctrl_uart1_default>; 999}; 1000 1001/* ULPI SMSC USB3320 */ 1002&usb0 { 1003 status = "okay"; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&pinctrl_usb0_default>; 1006 phy-names = "usb3-phy"; 1007 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 1008}; 1009 1010&dwc3_0 { 1011 status = "okay"; 1012 dr_mode = "host"; 1013 snps,usb3_lpm_capable; 1014 maximum-speed = "super-speed"; 1015}; 1016 1017&watchdog0 { 1018 status = "okay"; 1019}; 1020 1021&zynqmp_dpdma { 1022 status = "okay"; 1023}; 1024 1025&zynqmp_dpsub { 1026 status = "okay"; 1027 phy-names = "dp-phy0", "dp-phy1"; 1028 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 1029 <&psgtr 0 PHY_TYPE_DP 1 3>; 1030 1031 ports { 1032 port@5 { 1033 dpsub_dp_out: endpoint { 1034 remote-endpoint = <&dpcon_in>; 1035 }; 1036 }; 1037 }; 1038}; 1039