1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU102 RevA 4 * 5 * (C) Copyright 2015 - 2018, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16 17/ { 18 model = "ZynqMP ZCU102 RevA"; 19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 20 21 aliases { 22 ethernet0 = &gem3; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 mmc0 = &sdhci1; 26 rtc0 = &rtc; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &dcc; 30 }; 31 32 chosen { 33 bootargs = "earlycon"; 34 stdout-path = "serial0:115200n8"; 35 }; 36 37 memory@0 { 38 device_type = "memory"; 39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 40 }; 41 42 gpio-keys { 43 compatible = "gpio-keys"; 44 autorepeat; 45 sw19 { 46 label = "sw19"; 47 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 48 linux,code = <KEY_DOWN>; 49 gpio-key,wakeup; 50 autorepeat; 51 }; 52 }; 53 54 leds { 55 compatible = "gpio-leds"; 56 heartbeat_led { 57 label = "heartbeat"; 58 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 59 linux,default-trigger = "heartbeat"; 60 }; 61 }; 62}; 63 64&can1 { 65 status = "okay"; 66}; 67 68&dcc { 69 status = "okay"; 70}; 71 72&fpd_dma_chan1 { 73 status = "okay"; 74}; 75 76&fpd_dma_chan2 { 77 status = "okay"; 78}; 79 80&fpd_dma_chan3 { 81 status = "okay"; 82}; 83 84&fpd_dma_chan4 { 85 status = "okay"; 86}; 87 88&fpd_dma_chan5 { 89 status = "okay"; 90}; 91 92&fpd_dma_chan6 { 93 status = "okay"; 94}; 95 96&fpd_dma_chan7 { 97 status = "okay"; 98}; 99 100&fpd_dma_chan8 { 101 status = "okay"; 102}; 103 104&gem3 { 105 status = "okay"; 106 phy-handle = <&phy0>; 107 phy-mode = "rgmii-id"; 108 phy0: phy@21 { 109 reg = <21>; 110 ti,rx-internal-delay = <0x8>; 111 ti,tx-internal-delay = <0xa>; 112 ti,fifo-depth = <0x1>; 113 }; 114}; 115 116&gpio { 117 status = "okay"; 118}; 119 120&i2c0 { 121 status = "okay"; 122 clock-frequency = <400000>; 123 124 tca6416_u97: gpio@20 { 125 compatible = "ti,tca6416"; 126 reg = <0x20>; 127 gpio-controller; 128 #gpio-cells = <2>; 129 /* 130 * IRQ not connected 131 * Lines: 132 * 0 - PS_GTR_LAN_SEL0 133 * 1 - PS_GTR_LAN_SEL1 134 * 2 - PS_GTR_LAN_SEL2 135 * 3 - PS_GTR_LAN_SEL3 136 * 4 - PCI_CLK_DIR_SEL 137 * 5 - IIC_MUX_RESET_B 138 * 6 - GEM3_EXP_RESET_B 139 * 7, 10 - 17 - not connected 140 */ 141 142 gtr_sel0 { 143 gpio-hog; 144 gpios = <0 0>; 145 output-low; /* PCIE = 0, DP = 1 */ 146 line-name = "sel0"; 147 }; 148 gtr_sel1 { 149 gpio-hog; 150 gpios = <1 0>; 151 output-high; /* PCIE = 0, DP = 1 */ 152 line-name = "sel1"; 153 }; 154 gtr_sel2 { 155 gpio-hog; 156 gpios = <2 0>; 157 output-high; /* PCIE = 0, USB0 = 1 */ 158 line-name = "sel2"; 159 }; 160 gtr_sel3 { 161 gpio-hog; 162 gpios = <3 0>; 163 output-high; /* PCIE = 0, SATA = 1 */ 164 line-name = "sel3"; 165 }; 166 }; 167 168 tca6416_u61: gpio@21 { 169 compatible = "ti,tca6416"; 170 reg = <0x21>; 171 gpio-controller; 172 #gpio-cells = <2>; 173 /* 174 * IRQ not connected 175 * Lines: 176 * 0 - VCCPSPLL_EN 177 * 1 - MGTRAVCC_EN 178 * 2 - MGTRAVTT_EN 179 * 3 - VCCPSDDRPLL_EN 180 * 4 - MIO26_PMU_INPUT_LS 181 * 5 - PL_PMBUS_ALERT 182 * 6 - PS_PMBUS_ALERT 183 * 7 - MAXIM_PMBUS_ALERT 184 * 10 - PL_DDR4_VTERM_EN 185 * 11 - PL_DDR4_VPP_2V5_EN 186 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON 187 * 13 - PS_DIMM_SUSPEND_EN 188 * 14 - PS_DDR4_VTERM_EN 189 * 15 - PS_DDR4_VPP_2V5_EN 190 * 16 - 17 - not connected 191 */ 192 }; 193 194 i2c-mux@75 { /* u60 */ 195 compatible = "nxp,pca9544"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 reg = <0x75>; 199 i2c@0 { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 reg = <0>; 203 /* PS_PMBUS */ 204 ina226@40 { /* u76 */ 205 compatible = "ti,ina226"; 206 reg = <0x40>; 207 shunt-resistor = <5000>; 208 }; 209 ina226@41 { /* u77 */ 210 compatible = "ti,ina226"; 211 reg = <0x41>; 212 shunt-resistor = <5000>; 213 }; 214 ina226@42 { /* u78 */ 215 compatible = "ti,ina226"; 216 reg = <0x42>; 217 shunt-resistor = <5000>; 218 }; 219 ina226@43 { /* u87 */ 220 compatible = "ti,ina226"; 221 reg = <0x43>; 222 shunt-resistor = <5000>; 223 }; 224 ina226@44 { /* u85 */ 225 compatible = "ti,ina226"; 226 reg = <0x44>; 227 shunt-resistor = <5000>; 228 }; 229 ina226@45 { /* u86 */ 230 compatible = "ti,ina226"; 231 reg = <0x45>; 232 shunt-resistor = <5000>; 233 }; 234 ina226@46 { /* u93 */ 235 compatible = "ti,ina226"; 236 reg = <0x46>; 237 shunt-resistor = <5000>; 238 }; 239 ina226@47 { /* u88 */ 240 compatible = "ti,ina226"; 241 reg = <0x47>; 242 shunt-resistor = <5000>; 243 }; 244 ina226@4a { /* u15 */ 245 compatible = "ti,ina226"; 246 reg = <0x4a>; 247 shunt-resistor = <5000>; 248 }; 249 ina226@4b { /* u92 */ 250 compatible = "ti,ina226"; 251 reg = <0x4b>; 252 shunt-resistor = <5000>; 253 }; 254 }; 255 i2c@1 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <1>; 259 /* PL_PMBUS */ 260 ina226@40 { /* u79 */ 261 compatible = "ti,ina226"; 262 reg = <0x40>; 263 shunt-resistor = <2000>; 264 }; 265 ina226@41 { /* u81 */ 266 compatible = "ti,ina226"; 267 reg = <0x41>; 268 shunt-resistor = <5000>; 269 }; 270 ina226@42 { /* u80 */ 271 compatible = "ti,ina226"; 272 reg = <0x42>; 273 shunt-resistor = <5000>; 274 }; 275 ina226@43 { /* u84 */ 276 compatible = "ti,ina226"; 277 reg = <0x43>; 278 shunt-resistor = <5000>; 279 }; 280 ina226@44 { /* u16 */ 281 compatible = "ti,ina226"; 282 reg = <0x44>; 283 shunt-resistor = <5000>; 284 }; 285 ina226@45 { /* u65 */ 286 compatible = "ti,ina226"; 287 reg = <0x45>; 288 shunt-resistor = <5000>; 289 }; 290 ina226@46 { /* u74 */ 291 compatible = "ti,ina226"; 292 reg = <0x46>; 293 shunt-resistor = <5000>; 294 }; 295 ina226@47 { /* u75 */ 296 compatible = "ti,ina226"; 297 reg = <0x47>; 298 shunt-resistor = <5000>; 299 }; 300 }; 301 i2c@2 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <2>; 305 /* MAXIM_PMBUS - 00 */ 306 max15301@a { /* u46 */ 307 compatible = "maxim,max15301"; 308 reg = <0xa>; 309 }; 310 max15303@b { /* u4 */ 311 compatible = "maxim,max15303"; 312 reg = <0xb>; 313 }; 314 max15303@10 { /* u13 */ 315 compatible = "maxim,max15303"; 316 reg = <0x10>; 317 }; 318 max15301@13 { /* u47 */ 319 compatible = "maxim,max15301"; 320 reg = <0x13>; 321 }; 322 max15303@14 { /* u7 */ 323 compatible = "maxim,max15303"; 324 reg = <0x14>; 325 }; 326 max15303@15 { /* u6 */ 327 compatible = "maxim,max15303"; 328 reg = <0x15>; 329 }; 330 max15303@16 { /* u10 */ 331 compatible = "maxim,max15303"; 332 reg = <0x16>; 333 }; 334 max15303@17 { /* u9 */ 335 compatible = "maxim,max15303"; 336 reg = <0x17>; 337 }; 338 max15301@18 { /* u63 */ 339 compatible = "maxim,max15301"; 340 reg = <0x18>; 341 }; 342 max15303@1a { /* u49 */ 343 compatible = "maxim,max15303"; 344 reg = <0x1a>; 345 }; 346 max15303@1d { /* u18 */ 347 compatible = "maxim,max15303"; 348 reg = <0x1d>; 349 }; 350 max15303@20 { /* u8 */ 351 compatible = "maxim,max15303"; 352 status = "disabled"; /* unreachable */ 353 reg = <0x20>; 354 }; 355 356 max20751@72 { /* u95 */ 357 compatible = "maxim,max20751"; 358 reg = <0x72>; 359 }; 360 max20751@73 { /* u96 */ 361 compatible = "maxim,max20751"; 362 reg = <0x73>; 363 }; 364 }; 365 /* Bus 3 is not connected */ 366 }; 367}; 368 369&i2c1 { 370 status = "okay"; 371 clock-frequency = <400000>; 372 373 /* PL i2c via PCA9306 - u45 */ 374 i2c-mux@74 { /* u34 */ 375 compatible = "nxp,pca9548"; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 reg = <0x74>; 379 i2c@0 { 380 #address-cells = <1>; 381 #size-cells = <0>; 382 reg = <0>; 383 /* 384 * IIC_EEPROM 1kB memory which uses 256B blocks 385 * where every block has different address. 386 * 0 - 256B address 0x54 387 * 256B - 512B address 0x55 388 * 512B - 768B address 0x56 389 * 768B - 1024B address 0x57 390 */ 391 eeprom: eeprom@54 { /* u23 */ 392 compatible = "atmel,24c08"; 393 reg = <0x54>; 394 }; 395 }; 396 i2c@1 { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 reg = <1>; 400 si5341: clock-generator@36 { /* SI5341 - u69 */ 401 reg = <0x36>; 402 }; 403 404 }; 405 i2c@2 { 406 #address-cells = <1>; 407 #size-cells = <0>; 408 reg = <2>; 409 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 410 #clock-cells = <0>; 411 compatible = "silabs,si570"; 412 reg = <0x5d>; 413 temperature-stability = <50>; 414 factory-fout = <300000000>; 415 clock-frequency = <300000000>; 416 }; 417 }; 418 i2c@3 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 reg = <3>; 422 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 423 #clock-cells = <0>; 424 compatible = "silabs,si570"; 425 reg = <0x5d>; 426 temperature-stability = <50>; /* copy from zc702 */ 427 factory-fout = <156250000>; 428 clock-frequency = <148500000>; 429 }; 430 }; 431 i2c@4 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 reg = <4>; 435 si5328: clock-generator@69 {/* SI5328 - u20 */ 436 reg = <0x69>; 437 /* 438 * Chip has interrupt present connected to PL 439 * interrupt-parent = <&>; 440 * interrupts = <>; 441 */ 442 }; 443 }; 444 /* 5 - 7 unconnected */ 445 }; 446 447 i2c-mux@75 { 448 compatible = "nxp,pca9548"; /* u135 */ 449 #address-cells = <1>; 450 #size-cells = <0>; 451 reg = <0x75>; 452 453 i2c@0 { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 reg = <0>; 457 /* HPC0_IIC */ 458 }; 459 i2c@1 { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 reg = <1>; 463 /* HPC1_IIC */ 464 }; 465 i2c@2 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 reg = <2>; 469 /* SYSMON */ 470 }; 471 i2c@3 { 472 #address-cells = <1>; 473 #size-cells = <0>; 474 reg = <3>; 475 /* DDR4 SODIMM */ 476 }; 477 i2c@4 { 478 #address-cells = <1>; 479 #size-cells = <0>; 480 reg = <4>; 481 /* SEP 3 */ 482 }; 483 i2c@5 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 reg = <5>; 487 /* SEP 2 */ 488 }; 489 i2c@6 { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <6>; 493 /* SEP 1 */ 494 }; 495 i2c@7 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 reg = <7>; 499 /* SEP 0 */ 500 }; 501 }; 502}; 503 504&pcie { 505 status = "okay"; 506}; 507 508&rtc { 509 status = "okay"; 510}; 511 512&sata { 513 status = "okay"; 514 /* SATA OOB timing settings */ 515 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 516 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 517 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 518 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 519 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 520 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 521 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 522 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 523}; 524 525/* SD1 with level shifter */ 526&sdhci1 { 527 status = "okay"; 528 no-1-8-v; 529}; 530 531&uart0 { 532 status = "okay"; 533}; 534 535&uart1 { 536 status = "okay"; 537}; 538 539/* ULPI SMSC USB3320 */ 540&usb0 { 541 status = "okay"; 542}; 543 544&watchdog0 { 545 status = "okay"; 546}; 547