1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU102 RevA
4 *
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16
17/ {
18	model = "ZynqMP ZCU102 RevA";
19	compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem3;
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		mmc0 = &sdhci1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		serial1 = &uart1;
29		serial2 = &dcc;
30	};
31
32	chosen {
33		bootargs = "earlycon";
34		stdout-path = "serial0:115200n8";
35	};
36
37	memory@0 {
38		device_type = "memory";
39		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44		#address-cells = <1>;
45		#size-cells = <0>;
46		autorepeat;
47		sw19 {
48			label = "sw19";
49			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
50			linux,code = <KEY_DOWN>;
51			gpio-key,wakeup;
52			autorepeat;
53		};
54	};
55
56	leds {
57		compatible = "gpio-leds";
58		heartbeat_led {
59			label = "heartbeat";
60			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
61			linux,default-trigger = "heartbeat";
62		};
63	};
64};
65
66&can1 {
67	status = "okay";
68};
69
70&dcc {
71	status = "okay";
72};
73
74&fpd_dma_chan1 {
75	status = "okay";
76};
77
78&fpd_dma_chan2 {
79	status = "okay";
80};
81
82&fpd_dma_chan3 {
83	status = "okay";
84};
85
86&fpd_dma_chan4 {
87	status = "okay";
88};
89
90&fpd_dma_chan5 {
91	status = "okay";
92};
93
94&fpd_dma_chan6 {
95	status = "okay";
96};
97
98&fpd_dma_chan7 {
99	status = "okay";
100};
101
102&fpd_dma_chan8 {
103	status = "okay";
104};
105
106&gem3 {
107	status = "okay";
108	phy-handle = <&phy0>;
109	phy-mode = "rgmii-id";
110	phy0: phy@21 {
111		reg = <21>;
112		ti,rx-internal-delay = <0x8>;
113		ti,tx-internal-delay = <0xa>;
114		ti,fifo-depth = <0x1>;
115	};
116};
117
118&gpio {
119	status = "okay";
120};
121
122&i2c0 {
123	status = "okay";
124	clock-frequency = <400000>;
125
126	tca6416_u97: gpio@20 {
127		compatible = "ti,tca6416";
128		reg = <0x20>;
129		gpio-controller;
130		#gpio-cells = <2>;
131		/*
132		 * IRQ not connected
133		 * Lines:
134		 * 0 - PS_GTR_LAN_SEL0
135		 * 1 - PS_GTR_LAN_SEL1
136		 * 2 - PS_GTR_LAN_SEL2
137		 * 3 - PS_GTR_LAN_SEL3
138		 * 4 - PCI_CLK_DIR_SEL
139		 * 5 - IIC_MUX_RESET_B
140		 * 6 - GEM3_EXP_RESET_B
141		 * 7, 10 - 17 - not connected
142		 */
143
144		gtr_sel0 {
145			gpio-hog;
146			gpios = <0 0>;
147			output-low; /* PCIE = 0, DP = 1 */
148			line-name = "sel0";
149		};
150		gtr_sel1 {
151			gpio-hog;
152			gpios = <1 0>;
153			output-high; /* PCIE = 0, DP = 1 */
154			line-name = "sel1";
155		};
156		gtr_sel2 {
157			gpio-hog;
158			gpios = <2 0>;
159			output-high; /* PCIE = 0, USB0 = 1 */
160			line-name = "sel2";
161		};
162		gtr_sel3 {
163			gpio-hog;
164			gpios = <3 0>;
165			output-high; /* PCIE = 0, SATA = 1 */
166			line-name = "sel3";
167		};
168	};
169
170	tca6416_u61: gpio@21 {
171		compatible = "ti,tca6416";
172		reg = <0x21>;
173		gpio-controller;
174		#gpio-cells = <2>;
175		/*
176		 * IRQ not connected
177		 * Lines:
178		 * 0 - VCCPSPLL_EN
179		 * 1 - MGTRAVCC_EN
180		 * 2 - MGTRAVTT_EN
181		 * 3 - VCCPSDDRPLL_EN
182		 * 4 - MIO26_PMU_INPUT_LS
183		 * 5 - PL_PMBUS_ALERT
184		 * 6 - PS_PMBUS_ALERT
185		 * 7 - MAXIM_PMBUS_ALERT
186		 * 10 - PL_DDR4_VTERM_EN
187		 * 11 - PL_DDR4_VPP_2V5_EN
188		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
189		 * 13 - PS_DIMM_SUSPEND_EN
190		 * 14 - PS_DDR4_VTERM_EN
191		 * 15 - PS_DDR4_VPP_2V5_EN
192		 * 16 - 17 - not connected
193		 */
194	};
195
196	i2c-mux@75 { /* u60 */
197		compatible = "nxp,pca9544";
198		#address-cells = <1>;
199		#size-cells = <0>;
200		reg = <0x75>;
201		i2c@0 {
202			#address-cells = <1>;
203			#size-cells = <0>;
204			reg = <0>;
205			/* PS_PMBUS */
206			ina226@40 { /* u76 */
207				compatible = "ti,ina226";
208				reg = <0x40>;
209				shunt-resistor = <5000>;
210			};
211			ina226@41 { /* u77 */
212				compatible = "ti,ina226";
213				reg = <0x41>;
214				shunt-resistor = <5000>;
215			};
216			ina226@42 { /* u78 */
217				compatible = "ti,ina226";
218				reg = <0x42>;
219				shunt-resistor = <5000>;
220			};
221			ina226@43 { /* u87 */
222				compatible = "ti,ina226";
223				reg = <0x43>;
224				shunt-resistor = <5000>;
225			};
226			ina226@44 { /* u85 */
227				compatible = "ti,ina226";
228				reg = <0x44>;
229				shunt-resistor = <5000>;
230			};
231			ina226@45 { /* u86 */
232				compatible = "ti,ina226";
233				reg = <0x45>;
234				shunt-resistor = <5000>;
235			};
236			ina226@46 { /* u93 */
237				compatible = "ti,ina226";
238				reg = <0x46>;
239				shunt-resistor = <5000>;
240			};
241			ina226@47 { /* u88 */
242				compatible = "ti,ina226";
243				reg = <0x47>;
244				shunt-resistor = <5000>;
245			};
246			ina226@4a { /* u15 */
247				compatible = "ti,ina226";
248				reg = <0x4a>;
249				shunt-resistor = <5000>;
250			};
251			ina226@4b { /* u92 */
252				compatible = "ti,ina226";
253				reg = <0x4b>;
254				shunt-resistor = <5000>;
255			};
256		};
257		i2c@1 {
258			#address-cells = <1>;
259			#size-cells = <0>;
260			reg = <1>;
261			/* PL_PMBUS */
262			ina226@40 { /* u79 */
263				compatible = "ti,ina226";
264				reg = <0x40>;
265				shunt-resistor = <2000>;
266			};
267			ina226@41 { /* u81 */
268				compatible = "ti,ina226";
269				reg = <0x41>;
270				shunt-resistor = <5000>;
271			};
272			ina226@42 { /* u80 */
273				compatible = "ti,ina226";
274				reg = <0x42>;
275				shunt-resistor = <5000>;
276			};
277			ina226@43 { /* u84 */
278				compatible = "ti,ina226";
279				reg = <0x43>;
280				shunt-resistor = <5000>;
281			};
282			ina226@44 { /* u16 */
283				compatible = "ti,ina226";
284				reg = <0x44>;
285				shunt-resistor = <5000>;
286			};
287			ina226@45 { /* u65 */
288				compatible = "ti,ina226";
289				reg = <0x45>;
290				shunt-resistor = <5000>;
291			};
292			ina226@46 { /* u74 */
293				compatible = "ti,ina226";
294				reg = <0x46>;
295				shunt-resistor = <5000>;
296			};
297			ina226@47 { /* u75 */
298				compatible = "ti,ina226";
299				reg = <0x47>;
300				shunt-resistor = <5000>;
301			};
302		};
303		i2c@2 {
304			#address-cells = <1>;
305			#size-cells = <0>;
306			reg = <2>;
307			/* MAXIM_PMBUS - 00 */
308			max15301@a { /* u46 */
309				compatible = "maxim,max15301";
310				reg = <0xa>;
311			};
312			max15303@b { /* u4 */
313				compatible = "maxim,max15303";
314				reg = <0xb>;
315			};
316			max15303@10 { /* u13 */
317				compatible = "maxim,max15303";
318				reg = <0x10>;
319			};
320			max15301@13 { /* u47 */
321				compatible = "maxim,max15301";
322				reg = <0x13>;
323			};
324			max15303@14 { /* u7 */
325				compatible = "maxim,max15303";
326				reg = <0x14>;
327			};
328			max15303@15 { /* u6 */
329				compatible = "maxim,max15303";
330				reg = <0x15>;
331			};
332			max15303@16 { /* u10 */
333				compatible = "maxim,max15303";
334				reg = <0x16>;
335			};
336			max15303@17 { /* u9 */
337				compatible = "maxim,max15303";
338				reg = <0x17>;
339			};
340			max15301@18 { /* u63 */
341				compatible = "maxim,max15301";
342				reg = <0x18>;
343			};
344			max15303@1a { /* u49 */
345				compatible = "maxim,max15303";
346				reg = <0x1a>;
347			};
348			max15303@1d { /* u18 */
349				compatible = "maxim,max15303";
350				reg = <0x1d>;
351			};
352			max15303@20 { /* u8 */
353				compatible = "maxim,max15303";
354				status = "disabled"; /* unreachable */
355				reg = <0x20>;
356			};
357
358			max20751@72 { /* u95 */
359				compatible = "maxim,max20751";
360				reg = <0x72>;
361			};
362			max20751@73 { /* u96 */
363				compatible = "maxim,max20751";
364				reg = <0x73>;
365			};
366		};
367		/* Bus 3 is not connected */
368	};
369};
370
371&i2c1 {
372	status = "okay";
373	clock-frequency = <400000>;
374
375	/* PL i2c via PCA9306 - u45 */
376	i2c-mux@74 { /* u34 */
377		compatible = "nxp,pca9548";
378		#address-cells = <1>;
379		#size-cells = <0>;
380		reg = <0x74>;
381		i2c@0 {
382			#address-cells = <1>;
383			#size-cells = <0>;
384			reg = <0>;
385			/*
386			 * IIC_EEPROM 1kB memory which uses 256B blocks
387			 * where every block has different address.
388			 *    0 - 256B address 0x54
389			 * 256B - 512B address 0x55
390			 * 512B - 768B address 0x56
391			 * 768B - 1024B address 0x57
392			 */
393			eeprom: eeprom@54 { /* u23 */
394				compatible = "atmel,24c08";
395				reg = <0x54>;
396			};
397		};
398		i2c@1 {
399			#address-cells = <1>;
400			#size-cells = <0>;
401			reg = <1>;
402			si5341: clock-generator@36 { /* SI5341 - u69 */
403				reg = <0x36>;
404			};
405
406		};
407		i2c@2 {
408			#address-cells = <1>;
409			#size-cells = <0>;
410			reg = <2>;
411			si570_1: clock-generator@5d { /* USER SI570 - u42 */
412				#clock-cells = <0>;
413				compatible = "silabs,si570";
414				reg = <0x5d>;
415				temperature-stability = <50>;
416				factory-fout = <300000000>;
417				clock-frequency = <300000000>;
418			};
419		};
420		i2c@3 {
421			#address-cells = <1>;
422			#size-cells = <0>;
423			reg = <3>;
424			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
425				#clock-cells = <0>;
426				compatible = "silabs,si570";
427				reg = <0x5d>;
428				temperature-stability = <50>; /* copy from zc702 */
429				factory-fout = <156250000>;
430				clock-frequency = <148500000>;
431			};
432		};
433		i2c@4 {
434			#address-cells = <1>;
435			#size-cells = <0>;
436			reg = <4>;
437			si5328: clock-generator@69 {/* SI5328 - u20 */
438				reg = <0x69>;
439				/*
440				 * Chip has interrupt present connected to PL
441				 * interrupt-parent = <&>;
442				 * interrupts = <>;
443				 */
444			};
445		};
446		/* 5 - 7 unconnected */
447	};
448
449	i2c-mux@75 {
450		compatible = "nxp,pca9548"; /* u135 */
451		#address-cells = <1>;
452		#size-cells = <0>;
453		reg = <0x75>;
454
455		i2c@0 {
456			#address-cells = <1>;
457			#size-cells = <0>;
458			reg = <0>;
459			/* HPC0_IIC */
460		};
461		i2c@1 {
462			#address-cells = <1>;
463			#size-cells = <0>;
464			reg = <1>;
465			/* HPC1_IIC */
466		};
467		i2c@2 {
468			#address-cells = <1>;
469			#size-cells = <0>;
470			reg = <2>;
471			/* SYSMON */
472		};
473		i2c@3 {
474			#address-cells = <1>;
475			#size-cells = <0>;
476			reg = <3>;
477			/* DDR4 SODIMM */
478		};
479		i2c@4 {
480			#address-cells = <1>;
481			#size-cells = <0>;
482			reg = <4>;
483			/* SEP 3 */
484		};
485		i2c@5 {
486			#address-cells = <1>;
487			#size-cells = <0>;
488			reg = <5>;
489			/* SEP 2 */
490		};
491		i2c@6 {
492			#address-cells = <1>;
493			#size-cells = <0>;
494			reg = <6>;
495			/* SEP 1 */
496		};
497		i2c@7 {
498			#address-cells = <1>;
499			#size-cells = <0>;
500			reg = <7>;
501			/* SEP 0 */
502		};
503	};
504};
505
506&pcie {
507	status = "okay";
508};
509
510&rtc {
511	status = "okay";
512};
513
514&sata {
515	status = "okay";
516	/* SATA OOB timing settings */
517	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
518	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
519	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
520	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
521	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
522	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
523	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
524	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
525};
526
527/* SD1 with level shifter */
528&sdhci1 {
529	status = "okay";
530	no-1-8-v;
531};
532
533&uart0 {
534	status = "okay";
535};
536
537&uart1 {
538	status = "okay";
539};
540
541/* ULPI SMSC USB3320 */
542&usb0 {
543	status = "okay";
544};
545
546&watchdog0 {
547	status = "okay";
548};
549